diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm index add3d979b..7d444ab57 100644 --- a/src/mem/protocol/RubySlicc_Types.sm +++ b/src/mem/protocol/RubySlicc_Types.sm @@ -146,6 +146,10 @@ structure (CacheMemory, external = "yes") { void setMRU(Address); } +structure (WireBuffer, inport="yes", outport="yes", external = "yes") { + +} + structure (MemoryControl, inport="yes", outport="yes", external = "yes") { } diff --git a/src/mem/ruby/SConscript b/src/mem/ruby/SConscript index 4d8c82cf8..3c9c02fe2 100644 --- a/src/mem/ruby/SConscript +++ b/src/mem/ruby/SConscript @@ -107,6 +107,7 @@ MakeInclude('system/DMASequencer.hh') MakeInclude('system/DirectoryMemory.hh') MakeInclude('system/MachineID.hh') MakeInclude('system/MemoryControl.hh') +MakeInclude('system/WireBuffer.hh') MakeInclude('system/NodeID.hh') MakeInclude('system/PerfectCacheMemory.hh') MakeInclude('system/PersistentTable.hh') diff --git a/src/mem/ruby/system/SConscript b/src/mem/ruby/system/SConscript index edc9d451f..f1e7c425c 100644 --- a/src/mem/ruby/system/SConscript +++ b/src/mem/ruby/system/SConscript @@ -37,6 +37,7 @@ SimObject('Cache.py') SimObject('Sequencer.py') SimObject('DirectoryMemory.py') SimObject('MemoryControl.py') +SimObject('WireBuffer.py') SimObject('RubySystem.py') Source('DMASequencer.cc') @@ -44,6 +45,7 @@ Source('DirectoryMemory.cc') Source('SparseMemory.cc') Source('CacheMemory.cc') Source('MemoryControl.cc') +Source('WireBuffer.cc') Source('MemoryNode.cc') Source('PersistentTable.cc') Source('RubyPort.cc') diff --git a/src/mem/ruby/system/WireBuffer.cc b/src/mem/ruby/system/WireBuffer.cc new file mode 100644 index 000000000..bab935c5d --- /dev/null +++ b/src/mem/ruby/system/WireBuffer.cc @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2010 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lisa Hsu + * + */ + +#include +#include + +#include "base/cprintf.hh" +#include "base/stl_helpers.hh" +#include "mem/ruby/system/WireBuffer.hh" + +using namespace std; + +class Consumer; + + +// Output operator definition + +ostream& +operator<<(ostream& out, const WireBuffer& obj) +{ + obj.print(out); + out << flush; + return out; +} + + +// **************************************************************** + +// CONSTRUCTOR +WireBuffer::WireBuffer(const Params *p) + : SimObject(p) +{ + m_msg_counter = 0; +} + +void +WireBuffer::init() +{ +} + +WireBuffer::~WireBuffer() +{ +} + +void +WireBuffer::enqueue(MsgPtr message, int latency) +{ + m_msg_counter++; + Time current_time = g_eventQueue_ptr->getTime(); + Time arrival_time = current_time + latency; + assert(arrival_time > current_time); + MessageBufferNode thisNode(arrival_time, m_msg_counter, message); + m_message_queue.push_back(thisNode); + if (m_consumer_ptr != NULL) { + g_eventQueue_ptr->scheduleEventAbsolute(m_consumer_ptr, arrival_time); + } else { + panic("No Consumer for WireBuffer! %s\n", *this); + } +} + +void +WireBuffer::dequeue() +{ + assert(isReady()); + pop_heap(m_message_queue.begin(), m_message_queue.end(), + greater()); + m_message_queue.pop_back(); +} + +const Message* +WireBuffer::peek() +{ + MessageBufferNode node = peekNode(); + Message* msg_ptr = node.m_msgptr.get(); + assert(msg_ptr != NULL); + return msg_ptr; +} + +MessageBufferNode +WireBuffer::peekNode() +{ + assert(isReady()); + MessageBufferNode req = m_message_queue.front(); + return req; +} + +void +WireBuffer::recycle() +{ + // Because you don't want anything reordered, make sure the recycle latency + // is just 1 cycle. As a result, you really want to use this only in + // Wire-like situations because you don't want to deadlock as a result of + // being stuck behind something if you're not actually supposed to. + assert(isReady()); + MessageBufferNode node = m_message_queue.front(); + pop_heap(m_message_queue.begin(), m_message_queue.end(), + greater()); + node.m_time = g_eventQueue_ptr->getTime() + 1; + m_message_queue.back() = node; + push_heap(m_message_queue.begin(), m_message_queue.end(), + greater()); + g_eventQueue_ptr->scheduleEventAbsolute(m_consumer_ptr, + g_eventQueue_ptr->getTime() + 1); +} + +bool +WireBuffer::isReady() +{ + return ((!m_message_queue.empty()) && + (m_message_queue.front().m_time <= g_eventQueue_ptr->getTime())); +} + +void +WireBuffer::print(ostream& out) const +{ +} + +void +WireBuffer::printConfig(ostream& out) +{ +} + +void +WireBuffer::clearStats() const +{ +} + +void +WireBuffer::printStats(ostream& out) const +{ +} + +void +WireBuffer::wakeup() +{ +} + +WireBuffer * +RubyWireBufferParams::create() +{ + return new WireBuffer(this); +} + diff --git a/src/mem/ruby/system/WireBuffer.hh b/src/mem/ruby/system/WireBuffer.hh new file mode 100644 index 000000000..1404f5561 --- /dev/null +++ b/src/mem/ruby/system/WireBuffer.hh @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2010 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lisa Hsu + * + */ + +#ifndef __MEM_RUBY_SYSTEM_WIREBUFFER_HH__ +#define __MEM_RUBY_SYSTEM_WIREBUFFER_HH__ + +#include +#include +#include + +#include "mem/ruby/buffers/MessageBufferNode.hh" +#include "mem/ruby/common/Global.hh" +#include "mem/ruby/eventqueue/RubyEventQueue.hh" +#include "params/RubyWireBuffer.hh" +#include "sim/sim_object.hh" + + +////////////////////////////////////////////////////////////////////////////// +// This object was written to literally mimic a Wire in Ruby, in the sense +// that there is no way for messages to get reordered en route on the WireBuffer. +// With Message Buffers, even if randomization is off and ordered is on, +// messages can arrive in different orders than they were sent because of +// network issues. This mimics a Wire, such that that is not possible. This can +// allow for messages between closely coupled controllers that are not actually +// separated by a network in real systems to simplify coherence. +///////////////////////////////////////////////////////////////////////////// + +class Consumer; +class Message; // I added this and removed Message.hh + +class WireBuffer : public SimObject +{ + public: + typedef RubyWireBufferParams Params; + WireBuffer(const Params *p); + void init(); + + ~WireBuffer(); + + void wakeup(); + + void setConsumer(Consumer* consumer_ptr) + { + m_consumer_ptr = consumer_ptr; + } + Consumer* getConsumer() { return m_consumer_ptr; }; + void setDescription(const std::string& name) { m_description = name; }; + std::string getDescription() { return m_description; }; + + void enqueue(MsgPtr message, int latency ); + void dequeue(); + const Message* peek(); + MessageBufferNode peekNode(); + void recycle(); + bool isReady(); + bool areNSlotsAvailable(int n) { return true; }; // infinite queue length + + void printConfig(std::ostream& out); + void print(std::ostream& out) const; + void clearStats() const; + void printStats(std::ostream& out) const; + +// int m_dummy; + uint64_t m_msg_counter; + + private: + // Private copy constructor and assignment operator + WireBuffer (const WireBuffer& obj); + WireBuffer& operator=(const WireBuffer& obj); + + // data members + Consumer* m_consumer_ptr; // Consumer to signal a wakeup() + std::string m_description; + + // queues where memory requests live + std::vector m_message_queue; + +}; + +#endif // __MEM_RUBY_SYSTEM_WireBuffer_HH__ diff --git a/src/mem/ruby/system/WireBuffer.py b/src/mem/ruby/system/WireBuffer.py new file mode 100644 index 000000000..0bcc291bb --- /dev/null +++ b/src/mem/ruby/system/WireBuffer.py @@ -0,0 +1,35 @@ +# Copyright (c) 2010 Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Author: Lisa Hsu + +from m5.params import * +from m5.SimObject import SimObject +#from Controller import RubyController + +class RubyWireBuffer(SimObject): + type = 'RubyWireBuffer' + cxx_class = 'WireBuffer' diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py index 71b786616..90b7bfbd8 100644 --- a/src/mem/slicc/symbols/StateMachine.py +++ b/src/mem/slicc/symbols/StateMachine.py @@ -36,6 +36,7 @@ python_class_map = {"int": "Int", "std::string": "String", "bool": "Bool", "CacheMemory": "RubyCache", + "WireBuffer": "RubyWireBuffer", "Sequencer": "RubySequencer", "DirectoryMemory": "RubyDirectoryMemory", "MemoryControl": "RubyMemoryControl",