sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

ruby: mesi three level: slight naming changes.

Browse source
This commit is contained in:
Nilay Vaish 2014-09-01 16:55:44 -05:00
parent 557200725c
commit 3202ec98e7
2 changed files with 18 additions and 18 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
src/mem/protocol/MESI_Three_Level-L0cache.sm
View file

@ -36,10 +36,10 @@ machine(L0Cache, "MESI Directory L0 Cache")
{ {
// NODE L0 CACHE // NODE L0 CACHE
// From this node's L0 cache to the network // From this node's L0 cache to the network
MessageBuffer bufferFromCache, network="To", physical_network="0", ordered="true"; MessageBuffer bufferToL1, network="To", physical_network="0", ordered="true";
// To this node's L0 cache FROM the network // To this node's L0 cache FROM the network
MessageBuffer bufferToCache, network="From", physical_network="0", ordered="true"; MessageBuffer bufferFromL1, network="From", physical_network="0", ordered="true";
// Message queue between this controller and the processor // Message queue between this controller and the processor
MessageBuffer mandatoryQueue, ordered="false"; MessageBuffer mandatoryQueue, ordered="false";
@ -237,10 +237,10 @@ machine(L0Cache, "MESI Directory L0 Cache")
return tbe.pendingAcks; return tbe.pendingAcks;
} }
out_port(requestNetwork_out, CoherenceMsg, bufferFromCache); out_port(requestNetwork_out, CoherenceMsg, bufferToL1);
// Messages for this L0 cache from the L1 cache // Messages for this L0 cache from the L1 cache
in_port(messgeBuffer_in, CoherenceMsg, bufferToCache, rank = 1) { in_port(messgeBuffer_in, CoherenceMsg, bufferFromL1, rank = 1) {
if (messgeBuffer_in.isReady()) { if (messgeBuffer_in.isReady()) {
peek(messgeBuffer_in, CoherenceMsg, block_on="Addr") { peek(messgeBuffer_in, CoherenceMsg, block_on="Addr") {
assert(in_msg.Destination == machineID); assert(in_msg.Destination == machineID);

28
src/mem/protocol/MESI_Three_Level-L1cache.sm
View file

@ -35,23 +35,23 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
{ {
// From this node's L1 cache TO the network // From this node's L1 cache TO the network
// a local L1 -> this L2 bank, currently ordered with directory forwarded requests // a local L1 -> this L2 bank, currently ordered with directory forwarded requests
MessageBuffer requestFromCache, network="To", virtual_network="0", ordered="false", vnet_type="request"; MessageBuffer requestToL2, network="To", virtual_network="0", ordered="false", vnet_type="request";
// a local L1 -> this L2 bank // a local L1 -> this L2 bank
MessageBuffer responseFromCache, network="To", virtual_network="1", ordered="false", vnet_type="response"; MessageBuffer responseToL2, network="To", virtual_network="1", ordered="false", vnet_type="response";
MessageBuffer unblockFromCache, network="To", virtual_network="2", ordered="false", vnet_type="unblock"; MessageBuffer unblockToL2, network="To", virtual_network="2", ordered="false", vnet_type="unblock";
// To this node's L1 cache FROM the network // To this node's L1 cache FROM the network
// a L2 bank -> this L1 // a L2 bank -> this L1
MessageBuffer requestToCache, network="From", virtual_network="0", ordered="false", vnet_type="request"; MessageBuffer requestFromL2, network="From", virtual_network="0", ordered="false", vnet_type="request";
// a L2 bank -> this L1 // a L2 bank -> this L1
MessageBuffer responseToCache, network="From", virtual_network="1", ordered="false", vnet_type="response"; MessageBuffer responseFromL2, network="From", virtual_network="1", ordered="false", vnet_type="response";
// Message Buffers between the L1 and the L0 Cache // Message Buffers between the L1 and the L0 Cache
// From the L1 cache to the L0 cache // From the L1 cache to the L0 cache
MessageBuffer bufferFromL1ToL0, network="To", physical_network="0", ordered="true"; MessageBuffer bufferToL0, network="To", physical_network="0", ordered="true";
// From the L0 cache to the L1 cache // From the L0 cache to the L1 cache
MessageBuffer bufferToL1FromL0, network="From", physical_network="0", ordered="true"; MessageBuffer bufferFromL0, network="From", physical_network="0", ordered="true";
// STATES // STATES
state_declaration(State, desc="Cache states", default="L1Cache_State_I") { state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
@ -244,13 +244,13 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
return false; return false;
} }
out_port(requestNetwork_out, RequestMsg, requestFromCache); out_port(requestNetwork_out, RequestMsg, requestToL2);
out_port(responseNetwork_out, ResponseMsg, responseFromCache); out_port(responseNetwork_out, ResponseMsg, responseToL2);
out_port(unblockNetwork_out, ResponseMsg, unblockFromCache); out_port(unblockNetwork_out, ResponseMsg, unblockToL2);
out_port(bufferToL0_out, CoherenceMsg, bufferFromL1ToL0); out_port(bufferToL0_out, CoherenceMsg, bufferToL0);
// Response From the L2 Cache to this L1 cache // Response From the L2 Cache to this L1 cache
in_port(responseNetwork_in, ResponseMsg, responseToCache, rank = 3) { in_port(responseNetwork_in, ResponseMsg, responseFromL2, rank = 3) {
if (responseNetwork_in.isReady()) { if (responseNetwork_in.isReady()) {
peek(responseNetwork_in, ResponseMsg) { peek(responseNetwork_in, ResponseMsg) {
assert(in_msg.Destination.isElement(machineID)); assert(in_msg.Destination.isElement(machineID));
@ -288,7 +288,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
} }
// Request to this L1 cache from the shared L2 // Request to this L1 cache from the shared L2
in_port(requestNetwork_in, RequestMsg, requestToCache, rank = 2) { in_port(requestNetwork_in, RequestMsg, requestFromL2, rank = 2) {
if(requestNetwork_in.isReady()) { if(requestNetwork_in.isReady()) {
peek(requestNetwork_in, RequestMsg) { peek(requestNetwork_in, RequestMsg) {
assert(in_msg.Destination.isElement(machineID)); assert(in_msg.Destination.isElement(machineID));
@ -325,7 +325,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
} }
// Requests to this L1 cache from the L0 cache. // Requests to this L1 cache from the L0 cache.
in_port(messageBufferFromL0_in, CoherenceMsg, bufferToL1FromL0, rank = 0) { in_port(messageBufferFromL0_in, CoherenceMsg, bufferFromL0, rank = 0) {
if (messageBufferFromL0_in.isReady()) { if (messageBufferFromL0_in.isReady()) {
peek(messageBufferFromL0_in, CoherenceMsg) { peek(messageBufferFromL0_in, CoherenceMsg) {
Entry cache_entry := getCacheEntry(in_msg.Addr); Entry cache_entry := getCacheEntry(in_msg.Addr);