Include option for disabling PC symbols.
cpu/inst_seq.hh: cpu/o3/cpu.cc: cpu/ozone/cpu_builder.cc: cpu/ozone/thread_state.hh: SE build fixes. --HG-- extra : convert_revision : a4df6128533105f849b5469f62d83dffe299b7df
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4 changed files with 15 additions and 14 deletions
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@ -29,6 +29,8 @@
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#ifndef __STD_TYPES_HH__
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#ifndef __STD_TYPES_HH__
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#define __STD_TYPES_HH__
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#define __STD_TYPES_HH__
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#include <stdint.h>
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// inst sequence type, used to order instructions in the ready list,
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// inst sequence type, used to order instructions in the ready list,
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// if this rolls over the ready list order temporarily will get messed
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// if this rolls over the ready list order temporarily will get messed
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// up, but execution will continue and complete correctly
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// up, but execution will continue and complete correctly
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@ -123,7 +123,7 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
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physmem(system->physmem),
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physmem(system->physmem),
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mem(params->mem),
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mem(params->mem),
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#else
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#else
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pTable(params->pTable),
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// pTable(params->pTable),
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#endif // FULL_SYSTEM
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#endif // FULL_SYSTEM
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icacheInterface(params->icacheInterface),
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icacheInterface(params->icacheInterface),
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@ -238,8 +238,8 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
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// Setup the page table for whichever stages need it.
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// Setup the page table for whichever stages need it.
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#if !FULL_SYSTEM
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#if !FULL_SYSTEM
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fetch.setPageTable(pTable);
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// fetch.setPageTable(pTable);
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iew.setPageTable(pTable);
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// iew.setPageTable(pTable);
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#endif
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#endif
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// Setup the ROB for whichever stages need it.
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// Setup the ROB for whichever stages need it.
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@ -885,11 +885,9 @@ template <class Impl>
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void
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void
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FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
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FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
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{
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{
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unsigned tid = inst->threadNumber;
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DPRINTF(FullCPU, "FullCPU: Removing committed instruction [tid:%i] PC %#x "
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DPRINTF(FullCPU, "FullCPU: Removing committed instruction [tid:%i] PC %#x "
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"[sn:%lli]\n",
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"[sn:%lli]\n",
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tid, inst->readPC(), inst->seqNum);
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inst->threadNumber, inst->readPC(), inst->seqNum);
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removeInstsThisCycle = true;
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removeInstsThisCycle = true;
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@ -45,7 +45,7 @@ SimObjectParam<AlphaITB *> itb;
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SimObjectParam<AlphaDTB *> dtb;
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SimObjectParam<AlphaDTB *> dtb;
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#else
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#else
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SimObjectVectorParam<Process *> workload;
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SimObjectVectorParam<Process *> workload;
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SimObjectParam<PageTable *> page_table;
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//SimObjectParam<PageTable *> page_table;
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#endif // FULL_SYSTEM
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#endif // FULL_SYSTEM
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SimObjectParam<FunctionalMemory *> mem;
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SimObjectParam<FunctionalMemory *> mem;
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@ -159,7 +159,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
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INIT_PARAM(dtb, "Data translation buffer"),
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INIT_PARAM(dtb, "Data translation buffer"),
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#else
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#else
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INIT_PARAM(workload, "Processes to run"),
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INIT_PARAM(workload, "Processes to run"),
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INIT_PARAM(page_table, "Page table"),
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// INIT_PARAM(page_table, "Page table"),
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#endif // FULL_SYSTEM
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#endif // FULL_SYSTEM
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INIT_PARAM_DFLT(mem, "Memory", NULL),
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INIT_PARAM_DFLT(mem, "Memory", NULL),
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@ -310,7 +310,7 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
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params->dtb = dtb;
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params->dtb = dtb;
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#else
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#else
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params->workload = workload;
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params->workload = workload;
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params->pTable = page_table;
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// params->pTable = page_table;
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#endif // FULL_SYSTEM
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#endif // FULL_SYSTEM
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params->mem = mem;
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params->mem = mem;
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@ -440,7 +440,7 @@ SimObjectParam<AlphaITB *> itb;
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SimObjectParam<AlphaDTB *> dtb;
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SimObjectParam<AlphaDTB *> dtb;
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#else
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#else
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SimObjectVectorParam<Process *> workload;
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SimObjectVectorParam<Process *> workload;
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SimObjectParam<PageTable *> page_table;
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//SimObjectParam<PageTable *> page_table;
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#endif // FULL_SYSTEM
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#endif // FULL_SYSTEM
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SimObjectParam<FunctionalMemory *> mem;
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SimObjectParam<FunctionalMemory *> mem;
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@ -554,7 +554,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
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INIT_PARAM(dtb, "Data translation buffer"),
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INIT_PARAM(dtb, "Data translation buffer"),
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#else
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#else
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INIT_PARAM(workload, "Processes to run"),
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INIT_PARAM(workload, "Processes to run"),
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INIT_PARAM(page_table, "Page table"),
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// INIT_PARAM(page_table, "Page table"),
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#endif // FULL_SYSTEM
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#endif // FULL_SYSTEM
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INIT_PARAM_DFLT(mem, "Memory", NULL),
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INIT_PARAM_DFLT(mem, "Memory", NULL),
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@ -705,7 +705,7 @@ CREATE_SIM_OBJECT(SimpleOzoneCPU)
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params->dtb = dtb;
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params->dtb = dtb;
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#else
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#else
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params->workload = workload;
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params->workload = workload;
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params->pTable = page_table;
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// params->pTable = page_table;
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#endif // FULL_SYSTEM
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#endif // FULL_SYSTEM
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params->mem = mem;
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params->mem = mem;
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@ -6,9 +6,10 @@
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#include "arch/isa_traits.hh"
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#include "arch/isa_traits.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/thread_state.hh"
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#include "cpu/thread_state.hh"
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#include "sim/process.hh"
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class Event;
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class Event;
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class Process;
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//class Process;
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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class EndQuiesceEvent;
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class EndQuiesceEvent;
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@ -40,7 +41,7 @@ struct OzoneThreadState : public ThreadState {
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}
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}
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#else
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#else
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OzoneThreadState(FullCPU *_cpu, int _thread_num, Process *_process, int _asid)
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OzoneThreadState(FullCPU *_cpu, int _thread_num, Process *_process, int _asid)
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: ThreadState(-1, _thread_num, NULL, _process, _asid),
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: ThreadState(-1, _thread_num, _process->getMemory(), _process, _asid),
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cpu(_cpu), inSyscall(0), trapPending(0)
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cpu(_cpu), inSyscall(0), trapPending(0)
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{
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{
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memset(®s, 0, sizeof(TheISA::RegFile));
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memset(®s, 0, sizeof(TheISA::RegFile));
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