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Make the fsr a serializing register. Other control registers probably need this as well.

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--HG--
extra : convert_revision : edd3f9a83cc2722b6e0eff0eff4a8e034b0f6ec6
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Gabe Black 2007-04-14 17:07:24 +00:00
parent e9c6012acf
commit 3140dd88bc
1 changed files with 1 additions and 1 deletions
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2
src/arch/sparc/isa/operands.isa
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@ -187,7 +187,7 @@ def operands {{
'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75),
'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 80),
'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80),
# Mem gets a large number so it's always last
'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)