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config: move ruby objects under ruby_system in obj hierarchy

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This patch moves the contollers to be children of the ruby_system instead of
'system' under the python object hierarchy. This is so that these objects
can inherit some of the ruby_system's parameter values without resorting to
calling a global system pointer during run-time.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
This commit is contained in:
Malek Musleh 2013-01-14 10:05:14 -06:00
parent 1abf950f3c
commit 3137557cad
6 changed files with 25 additions and 25 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
configs/ruby/MESI_CMP_directory.py
View file

@ -110,7 +110,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
if piobus != None:
cpu_seq.pio_port = piobus.slave
exec("system.l1_cntrl%d = l1_cntrl" % i)
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
@ -135,7 +135,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
L2cacheMemory = l2_cache,
ruby_system = ruby_system)
exec("system.l2_cntrl%d = l2_cntrl" % i)
exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
l2_cntrl_nodes.append(l2_cntrl)
cntrl_count += 1
@ -165,7 +165,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
memBuffer = mem_cntrl,
ruby_system = ruby_system)
exec("system.dir_cntrl%d = dir_cntrl" % i)
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
cntrl_count += 1
@ -182,8 +182,8 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
dma_sequencer = dma_seq,
ruby_system = ruby_system)
exec("system.dma_cntrl%d = dma_cntrl" % i)
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
cntrl_count += 1

8
configs/ruby/MI_example.py
View file

@ -96,7 +96,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
if piobus != None:
cpu_seq.pio_port = piobus.slave
exec("system.l1_cntrl%d = l1_cntrl" % i)
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
#
@ -132,7 +132,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
memBuffer = mem_cntrl,
ruby_system = ruby_system)
exec("system.dir_cntrl%d = dir_cntrl" % i)
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
cntrl_count += 1
@ -149,8 +149,8 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
dma_sequencer = dma_seq,
ruby_system = ruby_system)
exec("system.dma_cntrl%d = dma_cntrl" % i)
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
cntrl_count += 1

10
configs/ruby/MOESI_CMP_directory.py
View file

@ -106,7 +106,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
if piobus != None:
cpu_seq.pio_port = piobus.slave
exec("system.l1_cntrl%d = l1_cntrl" % i)
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
#
@ -130,7 +130,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
L2cacheMemory = l2_cache,
ruby_system = ruby_system)
exec("system.l2_cntrl%d = l2_cntrl" % i)
exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
l2_cntrl_nodes.append(l2_cntrl)
cntrl_count += 1
@ -158,7 +158,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
memBuffer = mem_cntrl,
ruby_system = ruby_system)
exec("system.dir_cntrl%d = dir_cntrl" % i)
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
cntrl_count += 1
@ -175,8 +175,8 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
dma_sequencer = dma_seq,
ruby_system = ruby_system)
exec("system.dma_cntrl%d = dma_cntrl" % i)
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
cntrl_count += 1

10
configs/ruby/MOESI_CMP_token.py
View file

@ -126,7 +126,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
if piobus != None:
cpu_seq.pio_port = piobus.slave
exec("system.l1_cntrl%d = l1_cntrl" % i)
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
#
@ -151,7 +151,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
N_tokens = n_tokens,
ruby_system = ruby_system)
exec("system.l2_cntrl%d = l2_cntrl" % i)
exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
l2_cntrl_nodes.append(l2_cntrl)
cntrl_count += 1
@ -180,7 +180,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
l2_select_num_bits = l2_bits,
ruby_system = ruby_system)
exec("system.dir_cntrl%d = dir_cntrl" % i)
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
cntrl_count += 1
@ -197,8 +197,8 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
dma_sequencer = dma_seq,
ruby_system = ruby_system)
exec("system.dma_cntrl%d = dma_cntrl" % i)
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
cntrl_count += 1

8
configs/ruby/MOESI_hammer.py
View file

@ -122,7 +122,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
if options.recycle_latency:
l1_cntrl.recycle_latency = options.recycle_latency
exec("system.l1_cntrl%d = l1_cntrl" % i)
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
#
@ -192,7 +192,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
if options.recycle_latency:
dir_cntrl.recycle_latency = options.recycle_latency
exec("system.dir_cntrl%d = dir_cntrl" % i)
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
cntrl_count += 1
@ -209,8 +209,8 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
dma_sequencer = dma_seq,
ruby_system = ruby_system)
exec("system.dma_cntrl%d = dma_cntrl" % i)
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
if options.recycle_latency:

4
configs/ruby/Network_test.py
View file

@ -97,7 +97,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
if piobus != None:
cpu_seq.pio_port = piobus.slave
exec("system.l1_cntrl%d = l1_cntrl" % i)
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
#
@ -129,7 +129,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
memBuffer = mem_cntrl,
ruby_system = ruby_system)
exec("system.dir_cntrl%d = dir_cntrl" % i)
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
cntrl_count += 1