request: rename INST_READ to INST_FETCH.
This commit is contained in:
parent
7f8ea68a30
commit
3083268d60
6 changed files with 14 additions and 13 deletions
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@ -211,7 +211,7 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
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memReq->cmd = Read;
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memReq->cmd = Read;
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memReq->completionEvent = NULL;
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memReq->completionEvent = NULL;
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memReq->time = curTick;
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memReq->time = curTick;
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memReq->flags &= ~INST_READ;
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memReq->flags &= ~INST_FETCH;
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MemAccessResult result = dcacheInterface->access(memReq);
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MemAccessResult result = dcacheInterface->access(memReq);
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// Ugly hack to get an event scheduled *only* if the access is
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// Ugly hack to get an event scheduled *only* if the access is
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@ -252,7 +252,7 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
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// memcpy(memReq->data,(uint8_t *)&data,memReq->size);
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// memcpy(memReq->data,(uint8_t *)&data,memReq->size);
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memReq->completionEvent = NULL;
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memReq->completionEvent = NULL;
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memReq->time = curTick;
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memReq->time = curTick;
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memReq->flags &= ~INST_READ;
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memReq->flags &= ~INST_FETCH;
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MemAccessResult result = dcacheInterface->access(memReq);
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MemAccessResult result = dcacheInterface->access(memReq);
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// Ugly hack to get an event scheduled *only* if the access is
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// Ugly hack to get an event scheduled *only* if the access is
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@ -293,7 +293,7 @@ InorderBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx)
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req->time = curTick;
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req->time = curTick;
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assert(!req->data);
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assert(!req->data);
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req->data = new uint8_t[64];
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req->data = new uint8_t[64];
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req->flags &= ~INST_READ;
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req->flags &= ~INST_FETCH;
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Fault fault = cpu->read(req, data);
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Fault fault = cpu->read(req, data);
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memcpy(req->data, &data, sizeof(T));
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memcpy(req->data, &data, sizeof(T));
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@ -363,7 +363,7 @@ InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
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memcpy(req->data,(uint8_t *)&data,req->size);
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memcpy(req->data,(uint8_t *)&data,req->size);
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req->completionEvent = NULL;
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req->completionEvent = NULL;
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req->time = curTick;
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req->time = curTick;
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req->flags &= ~INST_READ;
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req->flags &= ~INST_FETCH;
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MemAccessResult result = dcacheInterface->access(req);
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MemAccessResult result = dcacheInterface->access(req);
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// Ugly hack to get an event scheduled *only* if the access is
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// Ugly hack to get an event scheduled *only* if the access is
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@ -48,6 +48,7 @@
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#include "cpu/static_inst.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/thread_context.hh"
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#include "mem/packet.hh"
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#include "mem/packet.hh"
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#include "mem/request.hh"
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#include "sim/byteswap.hh"
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#include "sim/byteswap.hh"
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#include "sim/debug.hh"
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#include "sim/debug.hh"
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#include "sim/host.hh"
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#include "sim/host.hh"
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@ -280,7 +281,7 @@ BaseSimpleCPU::copy(Addr dest)
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memReq->dest = dest_addr;
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memReq->dest = dest_addr;
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memReq->size = 64;
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memReq->size = 64;
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memReq->time = curTick;
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memReq->time = curTick;
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memReq->flags &= ~INST_READ;
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memReq->flags &= ~INST_FETCH;
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dcacheInterface->access(memReq);
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dcacheInterface->access(memReq);
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}
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}
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}
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}
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@ -346,7 +347,7 @@ BaseSimpleCPU::setupFetchRequest(Request *req)
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#endif
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#endif
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Addr fetchPC = (threadPC & PCMask) + fetchOffset;
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Addr fetchPC = (threadPC & PCMask) + fetchOffset;
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req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC);
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req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, threadPC);
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}
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}
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@ -168,7 +168,7 @@ ITXReader::getNextReq(MemReqPtr &req)
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break;
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break;
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case ITXCode:
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case ITXCode:
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tmp_req->cmd = Read;
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tmp_req->cmd = Read;
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tmp_req->flags |= INST_READ;
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tmp_req->flags |= INST_FETCH;
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break;
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break;
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default:
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default:
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fatal("Unknown ITX type");
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fatal("Unknown ITX type");
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@ -68,7 +68,7 @@ TraceCPU::tick()
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while (nextReq && curTick >= nextCycle) {
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while (nextReq && curTick >= nextCycle) {
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assert(nextReq->thread_num < 4 && "Not enough threads");
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assert(nextReq->thread_num < 4 && "Not enough threads");
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if (nextReq->isInstRead() && icacheInterface) {
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if (nextReq->isInstFetch() && icacheInterface) {
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if (icacheInterface->isBlocked())
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if (icacheInterface->isBlocked())
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break;
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break;
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2
src/mem/cache/prefetch/base.cc
vendored
2
src/mem/cache/prefetch/base.cc
vendored
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@ -170,7 +170,7 @@ BasePrefetcher::getPacket()
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Tick
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Tick
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BasePrefetcher::notify(PacketPtr &pkt, Tick time)
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BasePrefetcher::notify(PacketPtr &pkt, Tick time)
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{
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{
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if (!pkt->req->isUncacheable() && !(pkt->req->isInstRead() && onlyData)) {
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if (!pkt->req->isUncacheable() && !(pkt->req->isInstFetch() && onlyData)) {
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// Calculate the blk address
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// Calculate the blk address
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Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1);
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Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1);
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@ -86,8 +86,8 @@ class Request : public FastAlloc
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static const FlagsType EVICT_NEXT = 0x00020000;
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static const FlagsType EVICT_NEXT = 0x00020000;
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/** The request should ignore unaligned access faults */
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/** The request should ignore unaligned access faults */
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static const FlagsType NO_ALIGN_FAULT = 0x00040000;
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static const FlagsType NO_ALIGN_FAULT = 0x00040000;
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/** The request was an instruction read. */
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/** The request was an instruction fetch. */
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static const FlagsType INST_READ = 0x00080000;
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static const FlagsType INST_FETCH = 0x00080000;
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/** This request is for a memory swap. */
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/** This request is for a memory swap. */
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static const FlagsType MEM_SWAP = 0x00100000;
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static const FlagsType MEM_SWAP = 0x00100000;
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static const FlagsType MEM_SWAP_COND = 0x00200000;
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static const FlagsType MEM_SWAP_COND = 0x00200000;
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@ -98,7 +98,7 @@ class Request : public FastAlloc
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/** These flags are *not* cleared when a Request object is reused
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/** These flags are *not* cleared when a Request object is reused
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(assigned a new address). */
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(assigned a new address). */
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static const FlagsType STICKY_FLAGS = INST_READ;
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static const FlagsType STICKY_FLAGS = INST_FETCH;
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private:
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private:
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typedef uint8_t PrivateFlagsType;
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typedef uint8_t PrivateFlagsType;
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@ -430,7 +430,7 @@ class Request : public FastAlloc
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/** Accessor Function to Check Cacheability. */
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/** Accessor Function to Check Cacheability. */
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bool isUncacheable() const { return flags.isSet(UNCACHEABLE); }
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bool isUncacheable() const { return flags.isSet(UNCACHEABLE); }
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bool isInstRead() const { return flags.isSet(INST_READ); }
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bool isInstFetch() const { return flags.isSet(INST_FETCH); }
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bool isLLSC() const { return flags.isSet(LLSC); }
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bool isLLSC() const { return flags.isSet(LLSC); }
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bool isLocked() const { return flags.isSet(LOCKED); }
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bool isLocked() const { return flags.isSet(LOCKED); }
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bool isSwap() const { return flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
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bool isSwap() const { return flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
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