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O3/ARM: Update stats for recent changes.

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This commit is contained in:
Ali Saidi 2011-05-04 20:38:27 -05:00
parent 8aff996db1
commit 307f089e7f
22 changed files with 2144 additions and 2143 deletions
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4
tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
View file

@ -11,7 +11,7 @@ children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview t
boot_cpu_frequency=500
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0
init_param=0
kernel=/dist/m5/system/binaries/vmlinux.arm
kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
@ -495,7 +495,7 @@ type=ExeTracer
[system.diskmem]
type=PhysicalMemory
file=/dist/m5/system/disks/ael-arm.ext2
file=/chips/pd/randd/dist/disks/ael-arm.ext2
latency=30000
latency_var=0
null=false

10
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 21 2011 12:05:49
M5 started Apr 21 2011 15:19:16
M5 executing on maize
M5 compiled May 1 2011 21:51:08
M5 started May 1 2011 21:52:01
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 82662490500 because m5_exit instruction encountered
Exiting @ tick 82642207500 because m5_exit instruction encountered

984
tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
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File diff suppressed because it is too large Load diff

2
tests/long/10.linux-boot/ref/arm/linux/realview-o3/status
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@ -1 +1 @@
build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 passed.
build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 FAILED!

BIN
tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
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Binary file not shown.

2
tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
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@ -498,7 +498,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864

8
tests/long/50.vortex/ref/arm/linux/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 21 2011 12:05:01
M5 started Apr 21 2011 14:53:22
M5 executing on maize
M5 compiled May 1 2011 19:23:04
M5 started May 1 2011 19:48:10
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 39891736000 because target called exit()
Exiting @ tick 39989822000 because target called exit()

770
tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,146 +1,146 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 153606 # Simulator instruction rate (inst/s)
host_mem_usage 226292 # Number of bytes of host memory used
host_seconds 655.14 # Real time elapsed on the host
host_tick_rate 60890397 # Simulator tick rate (ticks/s)
host_inst_rate 102961 # Simulator instruction rate (inst/s)
host_mem_usage 269452 # Number of bytes of host memory used
host_seconds 977.39 # Real time elapsed on the host
host_tick_rate 40914717 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 100633305 # Number of instructions simulated
sim_seconds 0.039892 # Number of seconds simulated
sim_ticks 39891736000 # Number of ticks simulated
sim_insts 100633290 # Number of instructions simulated
sim_seconds 0.039990 # Number of seconds simulated
sim_ticks 39989822000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 9865367 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 15339513 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 176572 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 830445 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 11914381 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 18227498 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 1851553 # Number of times the RAS was used to get a target.
system.cpu.commit.branchMispredicts 800437 # The number of times a branch was mispredicted
system.cpu.commit.branches 13669912 # Number of branches committed
system.cpu.commit.bw_lim_events 2877364 # number cycles where commit BW limit reached
system.cpu.BPredUnit.BTBHits 9867090 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 15337107 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 176470 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 829676 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 11914855 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 18228284 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 1851579 # Number of times the RAS was used to get a target.
system.cpu.commit.branchMispredicts 800204 # The number of times a branch was mispredicted
system.cpu.commit.branches 13669909 # Number of branches committed
system.cpu.commit.bw_lim_events 2821197 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts 100638857 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 700914 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 13588852 # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples 76617428 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.313524 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.896154 # Number of insts commited each cycle
system.cpu.commit.commitCommittedInsts 100638842 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 700911 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 13587653 # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples 76811336 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.310208 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.890150 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 34018334 44.40% 44.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 22269182 29.07% 73.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 6570057 8.58% 82.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 4759391 6.21% 88.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 3903161 5.09% 93.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1377879 1.80% 95.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 463983 0.61% 95.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 378077 0.49% 96.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 2877364 3.76% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 34147257 44.46% 44.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 22326004 29.07% 73.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 6547391 8.52% 82.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 4777302 6.22% 88.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 3867270 5.03% 93.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1481997 1.93% 95.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 462917 0.60% 95.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 380001 0.49% 96.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 2821197 3.67% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 76617428 # Number of insts commited each cycle
system.cpu.commit.count 100638857 # Number of instructions committed
system.cpu.commit.committed_per_cycle::total 76811336 # Number of insts commited each cycle
system.cpu.commit.count 100638842 # Number of instructions committed
system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
system.cpu.commit.int_insts 91477923 # Number of committed integer instructions.
system.cpu.commit.loads 27308393 # Number of loads committed
system.cpu.commit.int_insts 91477911 # Number of committed integer instructions.
system.cpu.commit.loads 27308390 # Number of loads committed
system.cpu.commit.membars 15920 # Number of memory barriers committed
system.cpu.commit.refs 47865415 # Number of memory references committed
system.cpu.commit.refs 47865409 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 100633305 # Number of Instructions Simulated
system.cpu.committedInsts_total 100633305 # Number of Instructions Simulated
system.cpu.cpi 0.792814 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.792814 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 18795 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency 13515.151515 # average LoadLockedReq miss latency
system.cpu.committedInsts 100633290 # Number of Instructions Simulated
system.cpu.committedInsts_total 100633290 # Number of Instructions Simulated
system.cpu.cpi 0.794763 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.794763 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 18794 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency 13530.303030 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_hits 18762 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency 446000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_hits 18761 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency 446500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate 0.001756 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses 33 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_hits 32 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.000053 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.ReadReq_accesses 26949457 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 22750.430442 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18884.806074 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 26845494 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 2365203000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.003858 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 103963 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 49303 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1032243500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002028 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 54660 # number of ReadReq MSHR misses
system.cpu.dcache.StoreCondReq_accesses 17203 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits 17203 # number of StoreCondReq hits
system.cpu.dcache.ReadReq_accesses 26968856 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 22747.311569 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18885.481864 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 26864892 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 2364901500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.003855 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 103964 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 49322 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1031940500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002026 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 54642 # number of ReadReq MSHR misses
system.cpu.dcache.StoreCondReq_accesses 17200 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits 17200 # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 32591.489503 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34153.863424 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 18304057 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 50381358500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.077877 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1545844 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1438944 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 3651048000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_avg_miss_latency 32625.233627 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34171.269142 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 18304166 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 50429965500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.077871 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1545735 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1438836 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 3652874500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005385 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 106900 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 106899 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 22000 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 279.703475 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 279.850161 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 22000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 46799358 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 31971.352710 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 28987.939465 # average overall mshr miss latency
system.cpu.dcache.demand_hits 45149551 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 52746561500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.035253 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1649807 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 1488247 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 4683291500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.003452 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 161560 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 46818757 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 32002.727164 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 29000.779988 # average overall mshr miss latency
system.cpu.dcache.demand_hits 45169058 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 52794867000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.035236 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1649699 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 1488158 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 4684815000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.003450 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 161541 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0 4075.453819 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.994984 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 46799358 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 31971.352710 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 28987.939465 # average overall mshr miss latency
system.cpu.dcache.occ_blocks::0 4075.504214 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.994996 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 46818757 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 32002.727164 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 29000.779988 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 45149551 # number of overall hits
system.cpu.dcache.overall_miss_latency 52746561500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.035253 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1649807 # number of overall misses
system.cpu.dcache.overall_mshr_hits 1488247 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 4683291500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.003452 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 161560 # number of overall MSHR misses
system.cpu.dcache.overall_hits 45169058 # number of overall hits
system.cpu.dcache.overall_miss_latency 52794867000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.035236 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1649699 # number of overall misses
system.cpu.dcache.overall_mshr_hits 1488158 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 4684815000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.003450 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 161541 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 157452 # number of replacements
system.cpu.dcache.sampled_refs 161548 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 157437 # number of replacements
system.cpu.dcache.sampled_refs 161533 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4075.453819 # Cycle average of tags in use
system.cpu.dcache.total_refs 45185537 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 4075.504214 # Cycle average of tags in use
system.cpu.dcache.total_refs 45205036 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 327416000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 123381 # number of writebacks
system.cpu.decode.BlockedCycles 28767889 # Number of cycles decode is blocked
system.cpu.decode.BranchMispred 93628 # Number of times decode detected a branch misprediction
system.cpu.decode.BranchResolved 3727749 # Number of times decode resolved a branch
system.cpu.decode.DecodedInsts 120621461 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 25476849 # Number of cycles decode is idle
system.cpu.decode.RunCycles 21756774 # Number of cycles decode is running
system.cpu.decode.SquashCycles 2130394 # Number of cycles decode is squashing
system.cpu.decode.SquashedInsts 323992 # Number of squashed instructions handled by decode
system.cpu.decode.UnblockCycles 615915 # Number of cycles decode is unblocking
system.cpu.dcache.writebacks 123374 # number of writebacks
system.cpu.decode.BlockedCycles 28971891 # Number of cycles decode is blocked
system.cpu.decode.BranchMispred 93075 # Number of times decode detected a branch misprediction
system.cpu.decode.BranchResolved 3727390 # Number of times decode resolved a branch
system.cpu.decode.DecodedInsts 120629333 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 25465357 # Number of cycles decode is idle
system.cpu.decode.RunCycles 21763410 # Number of cycles decode is running
system.cpu.decode.SquashCycles 2130818 # Number of cycles decode is squashing
system.cpu.decode.SquashedInsts 323625 # Number of squashed instructions handled by decode
system.cpu.decode.UnblockCycles 610677 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
@ -162,243 +162,243 @@ system.cpu.dtb.read_misses 0 # DT
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.fetch.Branches 18227498 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 11770565 # Number of cache lines fetched
system.cpu.fetch.Cycles 22825886 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 173702 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 89192210 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 72 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 899278 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.228462 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 11770565 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 11716920 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.117928 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 78747821 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.567287 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.842624 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.Branches 18228284 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 11769962 # Number of cache lines fetched
system.cpu.fetch.Cycles 22827336 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 173608 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 89202846 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 75 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 898458 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.227912 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 11769962 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 11718669 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.115319 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 78942153 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.563587 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.840250 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 55936810 71.03% 71.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2349634 2.98% 74.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 2668515 3.39% 77.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2236984 2.84% 80.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1645406 2.09% 82.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1774436 2.25% 84.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 998371 1.27% 85.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1522539 1.93% 87.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 9615126 12.21% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 56129596 71.10% 71.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2349851 2.98% 74.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 2666538 3.38% 77.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2237184 2.83% 80.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1644999 2.08% 82.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1777059 2.25% 84.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 999675 1.27% 85.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1522909 1.93% 87.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 9614342 12.18% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 78747821 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 78942153 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 90 # number of floating regfile reads
system.cpu.fp_regfile_writes 71 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 11770565 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 12757.129371 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 9282.013745 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 11745142 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 324324500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.002160 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 25423 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 832 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 228254000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.002089 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 24591 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_accesses 11769962 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 12766.812347 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 9293.910530 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 11744564 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 324251500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.002158 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 25398 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 831 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 228323500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.002087 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 24567 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 477.833279 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 478.218331 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 11770565 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 12757.129371 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 9282.013745 # average overall mshr miss latency
system.cpu.icache.demand_hits 11745142 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 324324500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.002160 # miss rate for demand accesses
system.cpu.icache.demand_misses 25423 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 832 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 228254000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.002089 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 24591 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_accesses 11769962 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 12766.812347 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 9293.910530 # average overall mshr miss latency
system.cpu.icache.demand_hits 11744564 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 324251500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.002158 # miss rate for demand accesses
system.cpu.icache.demand_misses 25398 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 831 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 228323500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.002087 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 24567 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_blocks::0 1793.424749 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.875696 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 11770565 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 12757.129371 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 9282.013745 # average overall mshr miss latency
system.cpu.icache.occ_blocks::0 1794.323879 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.876135 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 11769962 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 12766.812347 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 9293.910530 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 11745142 # number of overall hits
system.cpu.icache.overall_miss_latency 324324500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.002160 # miss rate for overall accesses
system.cpu.icache.overall_misses 25423 # number of overall misses
system.cpu.icache.overall_mshr_hits 832 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 228254000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.002089 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 24591 # number of overall MSHR misses
system.cpu.icache.overall_hits 11744564 # number of overall hits
system.cpu.icache.overall_miss_latency 324251500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.002158 # miss rate for overall accesses
system.cpu.icache.overall_misses 25398 # number of overall misses
system.cpu.icache.overall_mshr_hits 831 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 228323500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.002087 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 24567 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 22549 # number of replacements
system.cpu.icache.sampled_refs 24580 # Sample count of references to valid blocks.
system.cpu.icache.replacements 22528 # number of replacements
system.cpu.icache.sampled_refs 24559 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1793.424749 # Cycle average of tags in use
system.cpu.icache.total_refs 11745142 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1794.323879 # Cycle average of tags in use
system.cpu.icache.total_refs 11744564 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 1035652 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.branchMispredicts 874742 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 14732348 # Number of branches executed
system.cpu.iew.exec_nop 77233 # number of nop insts executed
system.cpu.iew.exec_rate 1.323750 # Inst execution rate
system.cpu.iew.exec_refs 49299625 # number of memory reference insts executed
system.cpu.iew.exec_stores 21011299 # Number of stores executed
system.cpu.idleCycles 1037492 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.branchMispredicts 874393 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 14730992 # Number of branches executed
system.cpu.iew.exec_nop 77229 # number of nop insts executed
system.cpu.iew.exec_rate 1.320506 # Inst execution rate
system.cpu.iew.exec_refs 49310444 # number of memory reference insts executed
system.cpu.iew.exec_stores 21021544 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 976865 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 29744817 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 738677 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 687790 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 22207815 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 114301833 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 28288326 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 931089 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 105613393 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 6026 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewBlockCycles 976883 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 29736331 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 738487 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 690502 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 22216200 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 114300611 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 28288900 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 942660 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 105613612 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 6120 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 6915 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 2130394 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 55938 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 6972 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 2130818 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 56086 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.forwLoads 1108085 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.ignoredResponses 2818 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.forwLoads 1088745 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.ignoredResponses 2833 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.memOrderViolation 8523 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.memOrderViolation 8497 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.rescheduledLoads 41 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.squashedLoads 2436412 # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedStores 1650781 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 8523 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 227397 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 647345 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 107738460 # num instructions consuming a value
system.cpu.iew.wb_count 105037825 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.490563 # average fanout of values written-back
system.cpu.iew.lsq.thread0.squashedLoads 2427929 # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedStores 1659169 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 8497 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 227081 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 647312 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 107769064 # num instructions consuming a value
system.cpu.iew.wb_count 105038909 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.490744 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 52852456 # num instructions producing a value
system.cpu.iew.wb_rate 1.316536 # insts written-back per cycle
system.cpu.iew.wb_sent 105209239 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 252839831 # number of integer regfile reads
system.cpu.int_regfile_writes 78127703 # number of integer regfile writes
system.cpu.ipc 1.261330 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.261330 # IPC: Total IPC of All Threads
system.cpu.iew.wb_producers 52886985 # num instructions producing a value
system.cpu.iew.wb_rate 1.313321 # insts written-back per cycle
system.cpu.iew.wb_sent 105210613 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 252852862 # number of integer regfile reads
system.cpu.int_regfile_writes 78118633 # number of integer regfile writes
system.cpu.ipc 1.258236 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.258236 # IPC: Total IPC of All Threads
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 56712642 53.23% 53.23% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 95301 0.09% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 11 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 1 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 8 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 28583241 26.83% 80.15% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 21153285 19.85% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 56704676 53.22% 53.22% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 95260 0.09% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 10 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 1 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 8 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.31% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 28589913 26.83% 80.14% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 21166411 19.86% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 106544489 # Type of FU issued
system.cpu.iq.fp_alu_accesses 82 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 160 # Number of floating instruction queue reads
system.cpu.iq.FU_type_0::total 106556279 # Type of FU issued
system.cpu.iq.fp_alu_accesses 81 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 158 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 68 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 144 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 1792992 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.016829 # FU busy rate (busy events/executed inst)
system.cpu.iq.fp_inst_queue_writes 142 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 1839661 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.017265 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 49061 2.74% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.74% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1439096 80.26% 83.00% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 304835 17.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 48521 2.64% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.64% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1487460 80.86% 83.49% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 303680 16.51% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 108337399 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 293735316 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 105037757 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 127630070 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 113468820 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 106544489 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 755780 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 13400232 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 105692 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 54866 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 21923544 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::samples 78747821 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.352983 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.550711 # Number of insts issued each cycle
system.cpu.iq.int_alu_accesses 108395859 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 294001111 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 105038841 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 127626959 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 113467798 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 106556279 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 755584 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 13398397 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 106904 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 54673 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 21906182 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::samples 78942153 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.349802 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.549470 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 30449549 38.67% 38.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 20272773 25.74% 64.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 12837785 16.30% 80.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 6496976 8.25% 88.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 4874072 6.19% 95.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2197331 2.79% 97.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 925872 1.18% 99.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 480661 0.61% 99.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 212802 0.27% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 30593123 38.75% 38.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 20374659 25.81% 64.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 12756017 16.16% 80.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 6534002 8.28% 89.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 4851612 6.15% 95.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2240036 2.84% 97.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 902250 1.14% 99.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 476180 0.60% 99.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 214274 0.27% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 78747821 # Number of insts issued each cycle
system.cpu.iq.rate 1.335421 # Inst issue rate
system.cpu.iq.issued_per_cycle::total 78942153 # Number of insts issued each cycle
system.cpu.iq.rate 1.332292 # Inst issue rate
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
@ -420,115 +420,115 @@ system.cpu.itb.read_misses 0 # DT
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 106889 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34386.744639 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31232.309942 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 4289 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 3528080000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.959874 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 102600 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3204435000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959874 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 102600 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 79238 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34336.176999 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31108.810299 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 46944 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1108852500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.407557 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_accesses 106892 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34401.384977 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31241.713044 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 4291 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 3529616500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.959857 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 102601 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3205431000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959857 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 102601 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 79200 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34336.641481 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31108.469055 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 46906 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1108867500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.407753 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 32294 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits 59 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_miss_latency 1002792500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.406812 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1002781500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.407008 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 32235 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 12 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 8 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_hits 4 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_miss_rate 0.666667 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 8 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.666667 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 8 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 123381 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 123381 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_miss_rate 0.500000 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 4 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 124000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.500000 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 4 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 123374 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 123374 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.515289 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.514918 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 186127 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34374.638605 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31202.784885 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 51233 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 4636932500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.724742 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 134894 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 186092 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34385.885318 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31209.858643 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 51197 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 4638484000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.724883 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 134895 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 59 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 4207227500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.724425 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 134835 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 4208212500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.724566 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 134836 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_blocks::0 2296.436358 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16005.968558 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.070082 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.488463 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 186127 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34374.638605 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31202.784885 # average overall mshr miss latency
system.cpu.l2cache.occ_blocks::0 2298.143473 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16005.861783 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.070134 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.488460 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 186092 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34385.885318 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31209.858643 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 51233 # number of overall hits
system.cpu.l2cache.overall_miss_latency 4636932500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.724742 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 134894 # number of overall misses
system.cpu.l2cache.overall_hits 51197 # number of overall hits
system.cpu.l2cache.overall_miss_latency 4638484000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.724883 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 134895 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 59 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 4207227500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.724425 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 134835 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 4208212500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.724566 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 134836 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 114581 # number of replacements
system.cpu.l2cache.sampled_refs 133428 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 114587 # number of replacements
system.cpu.l2cache.sampled_refs 133431 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 18302.404916 # Cycle average of tags in use
system.cpu.l2cache.total_refs 68754 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 18304.005255 # Cycle average of tags in use
system.cpu.l2cache.total_refs 68706 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 88457 # number of writebacks
system.cpu.memDep0.conflictingLoads 15454792 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 13946617 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 29744817 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 22207815 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 146355254 # number of misc regfile reads
system.cpu.misc_regfile_writes 34408 # number of misc regfile writes
system.cpu.numCycles 79783473 # number of cpu cycles simulated
system.cpu.l2cache.writebacks 88458 # number of writebacks
system.cpu.memDep0.conflictingLoads 15829057 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 13995589 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 29736331 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 22216200 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 146370110 # number of misc regfile reads
system.cpu.misc_regfile_writes 34402 # number of misc regfile writes
system.cpu.numCycles 79979645 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.BlockCycles 2921057 # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps 75878617 # Number of HB maps that are committed
system.cpu.rename.IQFullEvents 205954 # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles 27124909 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 2993782 # Number of times rename has blocked due to LSQ full
system.cpu.rename.BlockCycles 2934776 # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps 75878602 # Number of HB maps that are committed
system.cpu.rename.IQFullEvents 208173 # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles 27131253 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 3054544 # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
system.cpu.rename.RenameLookups 315599119 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 118180992 # Number of instructions processed by rename
system.cpu.rename.RenamedOperands 90551096 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 20607135 # Number of cycles rename is running
system.cpu.rename.SquashCycles 2130394 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 4279204 # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps 14672443 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 83429 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 315515690 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 21685122 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 759000 # count of serializing insts renamed
system.cpu.rename.skidInsts 12013897 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 759711 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 187942474 # The number of ROB reads
system.cpu.rob.rob_writes 230588533 # The number of ROB writes
system.cpu.timesIdled 60808 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RenameLookups 315617756 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 118187842 # Number of instructions processed by rename
system.cpu.rename.RenamedOperands 90561212 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 20595374 # Number of cycles rename is running
system.cpu.rename.SquashCycles 2130818 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 4332267 # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps 14682574 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 83434 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 315534322 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 21817665 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 758712 # count of serializing insts renamed
system.cpu.rename.skidInsts 12129084 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 759493 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 188191335 # The number of ROB reads
system.cpu.rob.rob_writes 230586603 # The number of ROB writes
system.cpu.timesIdled 60768 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.num_syscalls 1946 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
View file

@ -498,7 +498,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
executable=/chips/pd/randd/dist/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864

8
tests/long/70.twolf/ref/x86/linux/o3-timing/simout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 21 2011 13:30:37
M5 started Apr 21 2011 13:53:57
M5 executing on maize
M5 compiled May 1 2011 16:48:51
M5 started May 1 2011 16:48:54
M5 executing on u200439-lin.austin.arm.com
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sav
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sv2
@ -28,4 +28,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 106785381000 because target called exit()
122 123 124 Exiting @ tick 106659390000 because target called exit()

669
tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,45 +1,45 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 120975 # Simulator instruction rate (inst/s)
host_mem_usage 223752 # Number of bytes of host memory used
host_seconds 1829.83 # Real time elapsed on the host
host_tick_rate 58358040 # Simulator tick rate (ticks/s)
host_inst_rate 88999 # Simulator instruction rate (inst/s)
host_mem_usage 265284 # Number of bytes of host memory used
host_seconds 2487.25 # Real time elapsed on the host
host_tick_rate 42882469 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 221363017 # Number of instructions simulated
sim_seconds 0.106785 # Number of seconds simulated
sim_ticks 106785381000 # Number of ticks simulated
sim_seconds 0.106659 # Number of seconds simulated
sim_ticks 106659390000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 19602584 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 22433110 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 19559071 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 22388883 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 3071588 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 25075434 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 25075434 # Number of BP lookups
system.cpu.BPredUnit.condIncorrect 3071862 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 25034838 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 25034838 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.branchMispredicts 3071621 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 3071894 # The number of times a branch was mispredicted
system.cpu.commit.branches 12326943 # Number of branches committed
system.cpu.commit.bw_lim_events 2318001 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 2350531 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 174370767 # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples 190318905 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.163116 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.516800 # Number of insts commited each cycle
system.cpu.commit.commitSquashedInsts 173965235 # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples 190108496 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.164404 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.519902 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 74095187 38.93% 38.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 71171116 37.40% 76.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 18278998 9.60% 85.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 12739096 6.69% 92.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 5868968 3.08% 95.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 2789277 1.47% 97.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1957482 1.03% 98.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1100780 0.58% 98.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 2318001 1.22% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 74006380 38.93% 38.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 71095556 37.40% 76.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 18250817 9.60% 85.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 12666090 6.66% 92.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 5885570 3.10% 95.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 2802504 1.47% 97.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1948827 1.03% 98.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1102221 0.58% 98.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 2350531 1.24% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 190318905 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 190108496 # Number of insts commited each cycle
system.cpu.commit.count 221363017 # Number of instructions committed
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
@ -50,337 +50,337 @@ system.cpu.commit.refs 77165306 # Nu
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 221363017 # Number of Instructions Simulated
system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated
system.cpu.cpi 0.964799 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.964799 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 50490336 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 33183.118741 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34227.979275 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 50489637 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 23195000 # number of ReadReq miss cycles
system.cpu.cpi 0.963660 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.963660 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 50560876 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 33172.166428 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34228.682171 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 50560179 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 23121000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 699 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 313 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 13212000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_misses 697 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 310 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 13246500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 386 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses 387 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 26460.898971 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35474.187380 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 26488.657179 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35473.248408 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 20508633 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 187793000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 187990000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000346 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 7097 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 5528 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 55659000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000076 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1569 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_hits 5527 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 55693000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1570 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 36353.441884 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 36352.334527 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 71006066 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 27063.622370 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35228.132992 # average overall mshr miss latency
system.cpu.dcache.demand_hits 70998270 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 210988000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_accesses 71076606 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 27086.348473 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35227.133367 # average overall mshr miss latency
system.cpu.dcache.demand_hits 71068812 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 211111000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000110 # miss rate for demand accesses
system.cpu.dcache.demand_misses 7796 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 5841 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 68871000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_misses 7794 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 5837 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 68939500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1955 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses 1957 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0 1398.546932 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.341442 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 71006066 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 27063.622370 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35228.132992 # average overall mshr miss latency
system.cpu.dcache.occ_blocks::0 1400.398145 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.341894 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 71076606 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 27086.348473 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35227.133367 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 70998270 # number of overall hits
system.cpu.dcache.overall_miss_latency 210988000 # number of overall miss cycles
system.cpu.dcache.overall_hits 71068812 # number of overall hits
system.cpu.dcache.overall_miss_latency 211111000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000110 # miss rate for overall accesses
system.cpu.dcache.overall_misses 7796 # number of overall misses
system.cpu.dcache.overall_mshr_hits 5841 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 68871000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_misses 7794 # number of overall misses
system.cpu.dcache.overall_mshr_hits 5837 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 68939500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1955 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses 1957 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 48 # number of replacements
system.cpu.dcache.sampled_refs 1953 # Sample count of references to valid blocks.
system.cpu.dcache.sampled_refs 1955 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 1398.546932 # Cycle average of tags in use
system.cpu.dcache.total_refs 70998272 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 1400.398145 # Cycle average of tags in use
system.cpu.dcache.total_refs 71068814 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 10 # number of writebacks
system.cpu.decode.BlockedCycles 57112679 # Number of cycles decode is blocked
system.cpu.decode.DecodedInsts 420105654 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 67048451 # Number of cycles decode is idle
system.cpu.decode.RunCycles 60385094 # Number of cycles decode is running
system.cpu.decode.SquashCycles 23161998 # Number of cycles decode is squashing
system.cpu.decode.UnblockCycles 5772681 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 25075434 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 27531173 # Number of cache lines fetched
system.cpu.fetch.Cycles 69569563 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 448608 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 261554963 # Number of instructions fetch has processed
system.cpu.decode.BlockedCycles 57002752 # Number of cycles decode is blocked
system.cpu.decode.DecodedInsts 419872535 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 66995296 # Number of cycles decode is idle
system.cpu.decode.RunCycles 60323444 # Number of cycles decode is running
system.cpu.decode.SquashCycles 23120513 # Number of cycles decode is squashing
system.cpu.decode.UnblockCycles 5787004 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 25034838 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 27511716 # Number of cache lines fetched
system.cpu.fetch.Cycles 69512577 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 449654 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 261443886 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 62 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 3099299 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.117410 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 27531173 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 19602584 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.224676 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 213480903 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.014170 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.226415 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.SquashCycles 3099669 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.117359 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 27511716 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 19559071 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.225602 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 213229009 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.015146 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.226933 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 145760613 68.28% 68.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 3769966 1.77% 70.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 3155448 1.48% 71.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4279066 2.00% 73.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4652490 2.18% 75.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 4411215 2.07% 77.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 5002306 2.34% 80.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3209548 1.50% 81.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 39240251 18.38% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 145563800 68.27% 68.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 3763912 1.77% 70.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 3143749 1.47% 71.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4274487 2.00% 73.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4655568 2.18% 75.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 4407393 2.07% 77.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 4998818 2.34% 80.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3209647 1.51% 81.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 39211635 18.39% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 213480903 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 3511578 # number of floating regfile reads
system.cpu.fp_regfile_writes 2187329 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 27531173 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 25557.221784 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22462.481426 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 27524838 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 161905000 # number of ReadReq miss cycles
system.cpu.fetch.rateDist::total 213229009 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 3514377 # number of floating regfile reads
system.cpu.fp_regfile_writes 2187528 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 27511716 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 25569.940006 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22464.790041 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 27505382 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 161960000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000230 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 6335 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 951 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 120938000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_misses 6334 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 952 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 120905500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000196 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 5384 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses 5382 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 5114.239688 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 5112.524535 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 27531173 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 25557.221784 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 22462.481426 # average overall mshr miss latency
system.cpu.icache.demand_hits 27524838 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 161905000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_accesses 27511716 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 25569.940006 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 22464.790041 # average overall mshr miss latency
system.cpu.icache.demand_hits 27505382 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 161960000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000230 # miss rate for demand accesses
system.cpu.icache.demand_misses 6335 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 951 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 120938000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_misses 6334 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 952 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 120905500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000196 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 5384 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses 5382 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_blocks::0 1605.721886 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.784044 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 27531173 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 25557.221784 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 22462.481426 # average overall mshr miss latency
system.cpu.icache.occ_blocks::0 1605.599338 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.783984 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 27511716 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 25569.940006 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 22464.790041 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 27524838 # number of overall hits
system.cpu.icache.overall_miss_latency 161905000 # number of overall miss cycles
system.cpu.icache.overall_hits 27505382 # number of overall hits
system.cpu.icache.overall_miss_latency 161960000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000230 # miss rate for overall accesses
system.cpu.icache.overall_misses 6335 # number of overall misses
system.cpu.icache.overall_mshr_hits 951 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 120938000 # number of overall MSHR miss cycles
system.cpu.icache.overall_misses 6334 # number of overall misses
system.cpu.icache.overall_mshr_hits 952 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 120905500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000196 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 5384 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses 5382 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 3426 # number of replacements
system.cpu.icache.sampled_refs 5382 # Sample count of references to valid blocks.
system.cpu.icache.replacements 3421 # number of replacements
system.cpu.icache.sampled_refs 5380 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1605.721886 # Cycle average of tags in use
system.cpu.icache.total_refs 27524838 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1605.599338 # Cycle average of tags in use
system.cpu.icache.total_refs 27505382 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 89860 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.branchMispredicts 3274274 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 15858881 # Number of branches executed
system.cpu.idleCycles 89772 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.branchMispredicts 3285583 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 15876599 # Number of branches executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_rate 1.303230 # Inst execution rate
system.cpu.iew.exec_refs 90240962 # number of memory reference insts executed
system.cpu.iew.exec_stores 23196856 # Number of stores executed
system.cpu.iew.exec_rate 1.304758 # Inst execution rate
system.cpu.iew.exec_refs 90277406 # number of memory reference insts executed
system.cpu.iew.exec_stores 23169669 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 536838 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 104995800 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 1427 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 231101 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 37116725 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 395719031 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 67044106 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 3514925 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 278331746 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 453294 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewBlockCycles 535171 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 104943598 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 1424 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 227523 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 37082263 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 395310289 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 67107737 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 3518032 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 278329468 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 451527 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 13026 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 23161998 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 523918 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 13065 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 23120513 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 520097 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.forwLoads 16343714 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.ignoredResponses 20445 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.forwLoads 16336525 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.ignoredResponses 15761 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.memOrderViolation 35659 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.rescheduledLoads 45746 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.squashedLoads 48346210 # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedStores 16601009 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 35659 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 741660 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 2532614 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 371845968 # num instructions consuming a value
system.cpu.iew.wb_count 275965139 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.599241 # average fanout of values written-back
system.cpu.iew.lsq.thread0.memOrderViolation 34193 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.rescheduledLoads 46033 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.squashedLoads 48294008 # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedStores 16566547 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 34193 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 745041 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 2540542 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 371832293 # num instructions consuming a value
system.cpu.iew.wb_count 275994943 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.599268 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 222825226 # num instructions producing a value
system.cpu.iew.wb_rate 1.292148 # insts written-back per cycle
system.cpu.iew.wb_sent 277010234 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 516469209 # number of integer regfile reads
system.cpu.int_regfile_writes 283974364 # number of integer regfile writes
system.cpu.ipc 1.036486 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.036486 # IPC: Total IPC of All Threads
system.cpu.iq.FU_type_0::No_OpClass 1200408 0.43% 0.43% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 187079024 66.38% 66.80% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.80% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 1589764 0.56% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.37% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 68461114 24.29% 91.66% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 23516361 8.34% 100.00% # Type of FU issued
system.cpu.iew.wb_producers 222827233 # num instructions producing a value
system.cpu.iew.wb_rate 1.293815 # insts written-back per cycle
system.cpu.iew.wb_sent 277038754 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 516581259 # number of integer regfile reads
system.cpu.int_regfile_writes 284038520 # number of integer regfile writes
system.cpu.ipc 1.037710 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.037710 # IPC: Total IPC of All Threads
system.cpu.iq.FU_type_0::No_OpClass 1197054 0.42% 0.42% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 187021337 66.36% 66.78% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.78% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.78% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 1590291 0.56% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.34% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 68531630 24.32% 91.66% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 23507188 8.34% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 281846671 # Type of FU issued
system.cpu.iq.fp_alu_accesses 2636909 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 5233833 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 2531388 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 5663526 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 2813875 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.009984 # FU busy rate (busy events/executed inst)
system.cpu.iq.FU_type_0::total 281847500 # Type of FU issued
system.cpu.iq.fp_alu_accesses 2638444 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 5236518 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 2534154 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 5693561 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 2791850 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.009906 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 68222 2.42% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.42% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2379596 84.57% 86.99% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 366057 13.01% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 67290 2.41% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.41% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2359047 84.50% 86.91% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 365513 13.09% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 280823229 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 774810101 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 273433751 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 564126820 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 395717604 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 281846671 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 1427 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 174039946 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 55814 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 181 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 358439815 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::samples 213480903 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.320243 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.372505 # Number of insts issued each cycle
system.cpu.iq.int_alu_accesses 280803852 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 774570053 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 273460789 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 563268520 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 395308865 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 281847500 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 1424 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 173620640 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 90712 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 357064626 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::samples 213229009 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.321807 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.374231 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 72600816 34.01% 34.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 65586069 30.72% 64.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 36613512 17.15% 81.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 20576315 9.64% 91.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 12054901 5.65% 97.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 3944773 1.85% 99.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1483005 0.69% 99.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 508962 0.24% 99.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 112550 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 72462076 33.98% 33.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 65441995 30.69% 64.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 36667606 17.20% 81.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 20567003 9.65% 91.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 11965683 5.61% 97.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 3990809 1.87% 99.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1502036 0.70% 99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 514117 0.24% 99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 117684 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 213480903 # Number of insts issued each cycle
system.cpu.iq.rate 1.319688 # Inst issue rate
system.cpu.l2cache.ReadExReq_accesses 1567 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34548.046124 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31351.697630 # average ReadExReq mshr miss latency
system.cpu.iq.issued_per_cycle::total 213229009 # Number of insts issued each cycle
system.cpu.iq.rate 1.321250 # Inst issue rate
system.cpu.l2cache.ReadExReq_accesses 1568 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.695262 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31351.472471 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 6 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 53929500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.996171 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1561 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 48940000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996171 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1561 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 5768 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34292.872747 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31042.872747 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2106 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 125580500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.634882 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_latency 53963500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.996173 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1562 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 48971000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996173 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1562 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 5767 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34290.551611 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31042.326597 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2105 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 125572000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.634992 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 3662 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 113679000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.634882 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_latency 113677000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.634992 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3662 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
@ -393,81 +393,82 @@ system.cpu.l2cache.Writeback_accesses 10 # nu
system.cpu.l2cache.Writeback_hits 10 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.574468 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.574195 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 7335 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34369.136512 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31135.171357 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2112 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 179510000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.712065 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 5223 # number of demand (read+write) misses
system.cpu.l2cache.demand_avg_miss_latency 34367.438744 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31134.762634 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2111 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 179535500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.712202 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 5224 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 162619000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.712065 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 5223 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 162648000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.712202 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 5224 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_blocks::0 2429.985932 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 1.014854 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.074157 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 2429.722700 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 1.014710 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.074149 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.000031 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 7335 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34369.136512 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31135.171357 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_miss_latency 34367.438744 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31134.762634 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2112 # number of overall hits
system.cpu.l2cache.overall_miss_latency 179510000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.712065 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 5223 # number of overall misses
system.cpu.l2cache.overall_hits 2111 # number of overall hits
system.cpu.l2cache.overall_miss_latency 179535500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.712202 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 5224 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 162619000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.712065 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 5223 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 162648000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.712202 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 5224 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 3666 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 2431.000786 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2106 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 2430.737411 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2105 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 90499072 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 30541649 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 104995800 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 37116725 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 145140832 # number of misc regfile reads
system.cpu.memDep0.conflictingLoads 90595235 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 30370608 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 104943598 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 37082263 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 145181965 # number of misc regfile reads
system.cpu.misc_regfile_writes 844 # number of misc regfile writes
system.cpu.numCycles 213570763 # number of cpu cycles simulated
system.cpu.numCycles 213318781 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.BlockCycles 18060003 # Number of cycles rename is blocking
system.cpu.rename.BlockCycles 18031749 # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed
system.cpu.rename.IQFullEvents 21564374 # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles 74887260 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 16382604 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenameLookups 1054491347 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 409882715 # Number of instructions processed by rename
system.cpu.rename.RenamedOperands 430914543 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 57380379 # Number of cycles rename is running
system.cpu.rename.SquashCycles 23161998 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 39968831 # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps 196551134 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 11087102 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 1043404245 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 22432 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 1444 # count of serializing insts renamed
system.cpu.rename.skidInsts 83221554 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 1312 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 583734688 # The number of ROB reads
system.cpu.rob.rob_writes 814640460 # The number of ROB writes
system.cpu.timesIdled 1934 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.IQFullEvents 21548402 # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles 74813235 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 16345466 # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full
system.cpu.rename.RenameLookups 1053910938 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 409668647 # Number of instructions processed by rename
system.cpu.rename.RenamedOperands 430592677 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 57355298 # Number of cycles rename is running
system.cpu.rename.SquashCycles 23120513 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 39885814 # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps 196229268 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 11151271 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 1042759667 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 22400 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 1440 # count of serializing insts renamed
system.cpu.rename.skidInsts 83004304 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 1309 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 583086217 # The number of ROB reads
system.cpu.rob.rob_writes 813789002 # The number of ROB writes
system.cpu.timesIdled 1930 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.num_syscalls 400 # Number of system calls
---------- End Simulation Statistics ----------

4
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
View file

@ -11,7 +11,7 @@ children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview t
boot_cpu_frequency=500
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0
init_param=0
kernel=/dist/m5/system/binaries/vmlinux.arm
kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=atomic
@ -169,7 +169,7 @@ type=ExeTracer
[system.diskmem]
type=PhysicalMemory
file=/dist/m5/system/disks/ael-arm.ext2
file=/chips/pd/randd/dist/disks/ael-arm.ext2
latency=30000
latency_var=0
null=false

10
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 19 2011 13:41:05
M5 started Apr 19 2011 13:41:08
M5 executing on maize
M5 compiled May 1 2011 21:51:08
M5 started May 1 2011 21:51:14
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 26405524500 because m5_exit instruction encountered
Exiting @ tick 26341084000 because m5_exit instruction encountered

362
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
View file

@ -1,63 +1,63 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3981428 # Simulator instruction rate (inst/s)
host_mem_usage 333640 # Number of bytes of host memory used
host_seconds 13.09 # Real time elapsed on the host
host_tick_rate 2017840381 # Simulator tick rate (ticks/s)
host_inst_rate 1460315 # Simulator instruction rate (inst/s)
host_mem_usage 380976 # Number of bytes of host memory used
host_seconds 35.59 # Real time elapsed on the host
host_tick_rate 740141754 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 52100192 # Number of instructions simulated
sim_seconds 0.026406 # Number of seconds simulated
sim_ticks 26405524500 # Number of ticks simulated
system.cpu.dcache.LoadLockedReq_accesses::0 100461 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 100461 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits::0 95296 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 95296 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_rate::0 0.051413 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses::0 5165 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 5165 # number of LoadLockedReq misses
system.cpu.dcache.ReadReq_accesses::0 7831528 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 7831528 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_hits::0 7594963 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7594963 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_rate::0 0.030207 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses::0 236565 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 236565 # number of ReadReq misses
system.cpu.dcache.StoreCondReq_accesses::0 100460 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 100460 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits::0 100460 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 100460 # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses::0 6676897 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6676897 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_hits::0 6504656 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 6504656 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_rate::0 0.025797 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses::0 172241 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 172241 # number of WriteReq misses
sim_insts 51971087 # Number of instructions simulated
sim_seconds 0.026341 # Number of seconds simulated
sim_ticks 26341084000 # Number of ticks simulated
system.cpu.dcache.LoadLockedReq_accesses::0 100443 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 100443 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits::0 95328 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 95328 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_rate::0 0.050924 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses::0 5115 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 5115 # number of LoadLockedReq misses
system.cpu.dcache.ReadReq_accesses::0 7807332 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 7807332 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_hits::0 7570991 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7570991 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_rate::0 0.030272 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses::0 236341 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 236341 # number of ReadReq misses
system.cpu.dcache.StoreCondReq_accesses::0 100442 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 100442 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits::0 100442 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 100442 # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses::0 6662917 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6662917 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_hits::0 6490820 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 6490820 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_rate::0 0.025829 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses::0 172097 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 172097 # number of WriteReq misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 34.690601 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 34.634545 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses::0 14508425 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::0 14470249 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 14508425 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 14470249 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu.dcache.demand_hits::0 14099619 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::0 14061811 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 14099619 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 14061811 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate::0 0.028177 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::0 0.028226 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
system.cpu.dcache.demand_misses::0 408806 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::0 408438 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 408806 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 408438 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
@ -67,26 +67,26 @@ system.cpu.dcache.demand_mshr_misses 0 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0 511.737186 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999487 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses::0 14508425 # number of overall (read+write) accesses
system.cpu.dcache.occ_blocks::0 511.736543 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999485 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses::0 14470249 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 14508425 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 14470249 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits::0 14099619 # number of overall hits
system.cpu.dcache.overall_hits::0 14061811 # number of overall hits
system.cpu.dcache.overall_hits::1 0 # number of overall hits
system.cpu.dcache.overall_hits::total 14099619 # number of overall hits
system.cpu.dcache.overall_hits::total 14061811 # number of overall hits
system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate::0 0.028177 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::0 0.028226 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
system.cpu.dcache.overall_misses::0 408806 # number of overall misses
system.cpu.dcache.overall_misses::0 408438 # number of overall misses
system.cpu.dcache.overall_misses::1 0 # number of overall misses
system.cpu.dcache.overall_misses::total 408806 # number of overall misses
system.cpu.dcache.overall_misses::total 408438 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
@ -95,66 +95,66 @@ system.cpu.dcache.overall_mshr_miss_rate::total no_value
system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 411623 # number of replacements
system.cpu.dcache.sampled_refs 412135 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 411199 # number of replacements
system.cpu.dcache.sampled_refs 411711 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 511.737186 # Cycle average of tags in use
system.cpu.dcache.total_refs 14297211 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 511.736543 # Cycle average of tags in use
system.cpu.dcache.total_refs 14259423 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 21760500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 381909 # number of writebacks
system.cpu.dtb.accesses 15532989 # DTB accesses
system.cpu.dcache.writebacks 380342 # number of writebacks
system.cpu.dtb.accesses 15494791 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 2238 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_entries 2239 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 15527459 # DTB hits
system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 15489154 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 5530 # DTB misses
system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 767 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 8743878 # DTB read accesses
system.cpu.dtb.read_hits 8739345 # DTB read hits
system.cpu.dtb.read_misses 4533 # DTB read misses
system.cpu.dtb.write_accesses 6789111 # DTB write accesses
system.cpu.dtb.write_hits 6788114 # DTB write hits
system.cpu.dtb.write_misses 997 # DTB write misses
system.cpu.icache.ReadReq_accesses::0 41566870 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 41566870 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_hits::0 41133444 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 41133444 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_rate::0 0.010427 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses::0 433426 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 433426 # number of ReadReq misses
system.cpu.dtb.misses 5637 # DTB misses
system.cpu.dtb.perms_faults 263 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 787 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 8719654 # DTB read accesses
system.cpu.dtb.read_hits 8715002 # DTB read hits
system.cpu.dtb.read_misses 4652 # DTB read misses
system.cpu.dtb.write_accesses 6775137 # DTB write accesses
system.cpu.dtb.write_hits 6774152 # DTB write hits
system.cpu.dtb.write_misses 985 # DTB write misses
system.cpu.icache.ReadReq_accesses::0 41451981 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 41451981 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_hits::0 41019813 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 41019813 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_rate::0 0.010426 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses::0 432168 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 432168 # number of ReadReq misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 94.903257 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 94.916579 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses::0 41566870 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::0 41451981 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 41566870 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 41451981 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu.icache.demand_hits::0 41133444 # number of demand (read+write) hits
system.cpu.icache.demand_hits::0 41019813 # number of demand (read+write) hits
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 41133444 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 41019813 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate::0 0.010427 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::0 0.010426 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
system.cpu.icache.demand_misses::0 433426 # number of demand (read+write) misses
system.cpu.icache.demand_misses::0 432168 # number of demand (read+write) misses
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 433426 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 432168 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
@ -164,26 +164,26 @@ system.cpu.icache.demand_mshr_misses 0 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_blocks::0 476.427204 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.930522 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses::0 41566870 # number of overall (read+write) accesses
system.cpu.icache.occ_blocks::0 476.338478 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.930349 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses::0 41451981 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 41566870 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 41451981 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits::0 41133444 # number of overall hits
system.cpu.icache.overall_hits::0 41019813 # number of overall hits
system.cpu.icache.overall_hits::1 0 # number of overall hits
system.cpu.icache.overall_hits::total 41133444 # number of overall hits
system.cpu.icache.overall_hits::total 41019813 # number of overall hits
system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles
system.cpu.icache.overall_miss_rate::0 0.010427 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::0 0.010426 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
system.cpu.icache.overall_misses::0 433426 # number of overall misses
system.cpu.icache.overall_misses::0 432168 # number of overall misses
system.cpu.icache.overall_misses::1 0 # number of overall misses
system.cpu.icache.overall_misses::total 433426 # number of overall misses
system.cpu.icache.overall_misses::total 432168 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
@ -192,27 +192,27 @@ system.cpu.icache.overall_mshr_miss_rate::total no_value
system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 432913 # number of replacements
system.cpu.icache.sampled_refs 433425 # Sample count of references to valid blocks.
system.cpu.icache.replacements 431655 # number of replacements
system.cpu.icache.sampled_refs 432167 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 476.427204 # Cycle average of tags in use
system.cpu.icache.total_refs 41133444 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 4575402000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 33681 # number of writebacks
system.cpu.icache.tagsinuse 476.338478 # Cycle average of tags in use
system.cpu.icache.total_refs 41019813 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 4572561500 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 33762 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 41567997 # DTB accesses
system.cpu.itb.accesses 41453108 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_entries 1476 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 41565169 # DTB hits
system.cpu.itb.inst_accesses 41567997 # ITB inst accesses
system.cpu.itb.inst_hits 41565169 # ITB inst hits
system.cpu.itb.inst_misses 2828 # ITB inst misses
system.cpu.itb.misses 2828 # DTB misses
system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 41450178 # DTB hits
system.cpu.itb.inst_accesses 41453108 # ITB inst accesses
system.cpu.itb.inst_hits 41450178 # ITB inst hits
system.cpu.itb.inst_misses 2930 # ITB inst misses
system.cpu.itb.misses 2930 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
@ -224,25 +224,25 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 52811050 # number of cpu cycles simulated
system.cpu.numCycles 52682169 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 52811050 # Number of busy cycles
system.cpu.num_conditional_control_insts 7028967 # number of instructions that are conditional controls
system.cpu.num_busy_cycles 52682169 # Number of busy cycles
system.cpu.num_conditional_control_insts 7011337 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses
system.cpu.num_fp_insts 6058 # number of float instructions
system.cpu.num_fp_register_reads 4226 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written
system.cpu.num_func_calls 1109362 # number of times a function call or return occured
system.cpu.num_func_calls 1107940 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 52100192 # Number of instructions executed
system.cpu.num_int_alu_accesses 42511691 # Number of integer alu accesses
system.cpu.num_int_insts 42511691 # number of integer instructions
system.cpu.num_int_register_reads 131109932 # number of times the integer registers were read
system.cpu.num_int_register_writes 34554918 # number of times the integer registers were written
system.cpu.num_load_insts 9209160 # Number of load instructions
system.cpu.num_mem_refs 16296226 # number of memory refs
system.cpu.num_store_insts 7087066 # Number of store instructions
system.cpu.num_insts 51971087 # Number of instructions executed
system.cpu.num_int_alu_accesses 42400620 # Number of integer alu accesses
system.cpu.num_int_insts 42400620 # number of integer instructions
system.cpu.num_int_register_reads 130759048 # number of times the integer registers were read
system.cpu.num_int_register_writes 34454879 # number of times the integer registers were written
system.cpu.num_load_insts 9174729 # Number of load instructions
system.cpu.num_mem_refs 16247961 # number of memory refs
system.cpu.num_store_insts 7073232 # Number of store instructions
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.avg_refs no_value # Average number of references to valid blocks.
@ -310,61 +310,61 @@ system.iocache.tagsinuse 0 # Cy
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 0 # number of writebacks
system.l2c.ReadExReq_accesses::0 170405 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 170405 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_hits::0 60553 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 60553 # number of ReadExReq hits
system.l2c.ReadExReq_miss_rate::0 0.644652 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses::0 109852 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 109852 # number of ReadExReq misses
system.l2c.ReadReq_accesses::0 673057 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1 6142 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 679199 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_hits::0 651904 # number of ReadReq hits
system.l2c.ReadReq_hits::1 6117 # number of ReadReq hits
system.l2c.ReadReq_hits::total 658021 # number of ReadReq hits
system.l2c.ReadReq_miss_rate::0 0.031428 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1 0.004070 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.035499 # miss rate for ReadReq accesses
system.l2c.ReadReq_misses::0 21153 # number of ReadReq misses
system.l2c.ReadReq_misses::1 25 # number of ReadReq misses
system.l2c.ReadReq_misses::total 21178 # number of ReadReq misses
system.l2c.UpgradeReq_accesses::0 1836 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 1836 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits
system.l2c.UpgradeReq_miss_rate::0 0.990741 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses::0 1819 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 1819 # number of UpgradeReq misses
system.l2c.Writeback_accesses::0 415590 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 415590 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0 415590 # number of Writeback hits
system.l2c.Writeback_hits::total 415590 # number of Writeback hits
system.l2c.ReadExReq_accesses::0 170255 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 170255 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_hits::0 60589 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 60589 # number of ReadExReq hits
system.l2c.ReadExReq_miss_rate::0 0.644128 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses::0 109666 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 109666 # number of ReadExReq misses
system.l2c.ReadReq_accesses::0 671527 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1 7078 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 678605 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_hits::0 650296 # number of ReadReq hits
system.l2c.ReadReq_hits::1 7047 # number of ReadReq hits
system.l2c.ReadReq_hits::total 657343 # number of ReadReq hits
system.l2c.ReadReq_miss_rate::0 0.031616 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1 0.004380 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.035996 # miss rate for ReadReq accesses
system.l2c.ReadReq_misses::0 21231 # number of ReadReq misses
system.l2c.ReadReq_misses::1 31 # number of ReadReq misses
system.l2c.ReadReq_misses::total 21262 # number of ReadReq misses
system.l2c.UpgradeReq_accesses::0 1842 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 1842 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_hits::0 19 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 19 # number of UpgradeReq hits
system.l2c.UpgradeReq_miss_rate::0 0.989685 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses::0 1823 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 1823 # number of UpgradeReq misses
system.l2c.Writeback_accesses::0 414104 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 414104 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0 414104 # number of Writeback hits
system.l2c.Writeback_hits::total 414104 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.avg_refs 6.746349 # Average number of references to valid blocks.
system.l2c.avg_refs 6.723520 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.demand_accesses::0 843462 # number of demand (read+write) accesses
system.l2c.demand_accesses::1 6142 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 849604 # number of demand (read+write) accesses
system.l2c.demand_accesses::0 841782 # number of demand (read+write) accesses
system.l2c.demand_accesses::1 7078 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 848860 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.l2c.demand_hits::0 712457 # number of demand (read+write) hits
system.l2c.demand_hits::1 6117 # number of demand (read+write) hits
system.l2c.demand_hits::total 718574 # number of demand (read+write) hits
system.l2c.demand_hits::0 710885 # number of demand (read+write) hits
system.l2c.demand_hits::1 7047 # number of demand (read+write) hits
system.l2c.demand_hits::total 717932 # number of demand (read+write) hits
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate::0 0.155318 # miss rate for demand accesses
system.l2c.demand_miss_rate::1 0.004070 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.159389 # miss rate for demand accesses
system.l2c.demand_misses::0 131005 # number of demand (read+write) misses
system.l2c.demand_misses::1 25 # number of demand (read+write) misses
system.l2c.demand_misses::total 131030 # number of demand (read+write) misses
system.l2c.demand_miss_rate::0 0.155500 # miss rate for demand accesses
system.l2c.demand_miss_rate::1 0.004380 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.159880 # miss rate for demand accesses
system.l2c.demand_misses::0 130897 # number of demand (read+write) misses
system.l2c.demand_misses::1 31 # number of demand (read+write) misses
system.l2c.demand_misses::total 130928 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
@ -374,28 +374,28 @@ system.l2c.demand_mshr_misses 0 # nu
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.occ_blocks::0 5042.918302 # Average occupied blocks per context
system.l2c.occ_blocks::1 31264.310783 # Average occupied blocks per context
system.l2c.occ_percent::0 0.076949 # Average percentage of cache occupancy
system.l2c.occ_percent::1 0.477056 # Average percentage of cache occupancy
system.l2c.overall_accesses::0 843462 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 6142 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 849604 # number of overall (read+write) accesses
system.l2c.occ_blocks::0 5062.788087 # Average occupied blocks per context
system.l2c.occ_blocks::1 31189.705520 # Average occupied blocks per context
system.l2c.occ_percent::0 0.077252 # Average percentage of cache occupancy
system.l2c.occ_percent::1 0.475917 # Average percentage of cache occupancy
system.l2c.overall_accesses::0 841782 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 7078 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 848860 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.l2c.overall_hits::0 712457 # number of overall hits
system.l2c.overall_hits::1 6117 # number of overall hits
system.l2c.overall_hits::total 718574 # number of overall hits
system.l2c.overall_hits::0 710885 # number of overall hits
system.l2c.overall_hits::1 7047 # number of overall hits
system.l2c.overall_hits::total 717932 # number of overall hits
system.l2c.overall_miss_latency 0 # number of overall miss cycles
system.l2c.overall_miss_rate::0 0.155318 # miss rate for overall accesses
system.l2c.overall_miss_rate::1 0.004070 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.159389 # miss rate for overall accesses
system.l2c.overall_misses::0 131005 # number of overall misses
system.l2c.overall_misses::1 25 # number of overall misses
system.l2c.overall_misses::total 131030 # number of overall misses
system.l2c.overall_miss_rate::0 0.155500 # miss rate for overall accesses
system.l2c.overall_miss_rate::1 0.004380 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.159880 # miss rate for overall accesses
system.l2c.overall_misses::0 130897 # number of overall misses
system.l2c.overall_misses::1 31 # number of overall misses
system.l2c.overall_misses::total 130928 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
@ -404,12 +404,12 @@ system.l2c.overall_mshr_miss_rate::total 0 # ms
system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.replacements 97025 # number of replacements
system.l2c.sampled_refs 129753 # Sample count of references to valid blocks.
system.l2c.replacements 97110 # number of replacements
system.l2c.sampled_refs 129684 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse 36307.229085 # Cycle average of tags in use
system.l2c.total_refs 875359 # Total number of references to valid blocks.
system.l2c.tagsinuse 36252.493607 # Cycle average of tags in use
system.l2c.total_refs 871933 # Total number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 90930 # number of writebacks
system.l2c.writebacks 91106 # number of writebacks
---------- End Simulation Statistics ----------

BIN
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
View file

Binary file not shown.

4
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
View file

@ -11,7 +11,7 @@ children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview t
boot_cpu_frequency=500
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0
init_param=0
kernel=/dist/m5/system/binaries/vmlinux.arm
kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
@ -166,7 +166,7 @@ type=ExeTracer
[system.diskmem]
type=PhysicalMemory
file=/dist/m5/system/disks/ael-arm.ext2
file=/chips/pd/randd/dist/disks/ael-arm.ext2
latency=30000
latency_var=0
null=false

10
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 19 2011 13:41:05
M5 started Apr 19 2011 13:41:07
M5 executing on maize
M5 compiled May 1 2011 21:51:08
M5 started May 1 2011 21:51:14
M5 executing on u200439-lin.austin.arm.com
command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 114405702000 because m5_exit instruction encountered
Exiting @ tick 114293937000 because m5_exit instruction encountered

548
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
View file

@ -1,264 +1,264 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1969505 # Simulator instruction rate (inst/s)
host_mem_usage 333648 # Number of bytes of host memory used
host_seconds 26.01 # Real time elapsed on the host
host_tick_rate 4398008175 # Simulator tick rate (ticks/s)
host_inst_rate 703032 # Simulator instruction rate (inst/s)
host_mem_usage 381000 # Number of bytes of host memory used
host_seconds 72.76 # Real time elapsed on the host
host_tick_rate 1570917363 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 51232482 # Number of instructions simulated
sim_seconds 0.114406 # Number of seconds simulated
sim_ticks 114405702000 # Number of ticks simulated
system.cpu.dcache.LoadLockedReq_accesses::0 100305 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 100305 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14522.379495 # average LoadLockedReq miss latency
sim_insts 51149744 # Number of instructions simulated
sim_seconds 0.114294 # Number of seconds simulated
sim_ticks 114293937000 # Number of ticks simulated
system.cpu.dcache.LoadLockedReq_accesses::0 100301 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 100301 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14594.610314 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11522.379495 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_hits::0 95077 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 95077 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency 75923000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052121 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses::0 5228 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 5228 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 60239000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.052121 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11594.610314 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_hits::0 95143 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 95143 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency 75279000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate::0 0.051425 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses::0 5158 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 5158 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 59805000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.051425 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_misses 5228 # number of LoadLockedReq MSHR misses
system.cpu.dcache.ReadReq_accesses::0 7829265 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 7829265 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency::0 15673.279330 # average ReadReq miss latency
system.cpu.dcache.LoadLockedReq_mshr_misses 5158 # number of LoadLockedReq MSHR misses
system.cpu.dcache.ReadReq_accesses::0 7812826 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 7812826 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency::0 15651.475503 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12672.933246 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12651.150503 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_hits::0 7590884 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7590884 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 3736212000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate::0 0.030447 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses::0 238381 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 238381 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 3020986500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030447 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_hits::0 7574365 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7574365 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 3732266500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate::0 0.030522 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses::0 238461 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 238461 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 3016806000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030522 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 238381 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38191861000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.StoreCondReq_accesses::0 100304 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 100304 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits::0 100304 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 100304 # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses::0 6674712 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6674712 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency::0 40727.602969 # average WriteReq miss latency
system.cpu.dcache.ReadReq_mshr_misses 238461 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38192110000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.StoreCondReq_accesses::0 100300 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 100300 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits::0 100300 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 100300 # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses::0 6665523 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6665523 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency::0 40729.480776 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37727.353242 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37729.274596 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_hits::0 6502524 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 6502524 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 7012804500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate::0 0.025797 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses::0 172188 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 172188 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 6496197500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025797 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_hits::0 6493343 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 6493343 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 7012802000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate::0 0.025831 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses::0 172180 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 172180 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 6496226500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025831 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 172188 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 927430500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_misses 172180 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 927806000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 34.521241 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 34.459827 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses::0 14503977 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::0 14478349 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 14503977 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency::0 26180.779601 # average overall miss latency
system.cpu.dcache.demand_accesses::total 14478349 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency::0 26166.574940 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 23180.473928 # average overall mshr miss latency
system.cpu.dcache.demand_hits::0 14093408 # number of demand (read+write) hits
system.cpu.dcache.demand_avg_mshr_miss_latency 23166.299761 # average overall mshr miss latency
system.cpu.dcache.demand_hits::0 14067708 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 14093408 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 10749016500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate::0 0.028307 # miss rate for demand accesses
system.cpu.dcache.demand_hits::total 14067708 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 10745068500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate::0 0.028362 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
system.cpu.dcache.demand_misses::0 410569 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::0 410641 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 410569 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 410641 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 9517184000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate::0 0.028307 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_latency 9513032500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate::0 0.028362 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 410569 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses 410641 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0 509.191392 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.994514 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses::0 14503977 # number of overall (read+write) accesses
system.cpu.dcache.occ_blocks::0 509.188646 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.994509 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses::0 14478349 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 14503977 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency::0 26180.779601 # average overall miss latency
system.cpu.dcache.overall_accesses::total 14478349 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency::0 26166.574940 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 23180.473928 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 23166.299761 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits::0 14093408 # number of overall hits
system.cpu.dcache.overall_hits::0 14067708 # number of overall hits
system.cpu.dcache.overall_hits::1 0 # number of overall hits
system.cpu.dcache.overall_hits::total 14093408 # number of overall hits
system.cpu.dcache.overall_miss_latency 10749016500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate::0 0.028307 # miss rate for overall accesses
system.cpu.dcache.overall_hits::total 14067708 # number of overall hits
system.cpu.dcache.overall_miss_latency 10745068500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate::0 0.028362 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
system.cpu.dcache.overall_misses::0 410569 # number of overall misses
system.cpu.dcache.overall_misses::0 410641 # number of overall misses
system.cpu.dcache.overall_misses::1 0 # number of overall misses
system.cpu.dcache.overall_misses::total 410569 # number of overall misses
system.cpu.dcache.overall_misses::total 410641 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 9517184000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate::0 0.028307 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_latency 9513032500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate::0 0.028362 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 410569 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 39119291500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_misses 410641 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 39119916000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 413454 # number of replacements
system.cpu.dcache.sampled_refs 413966 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 413448 # number of replacements
system.cpu.dcache.sampled_refs 413960 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 509.191392 # Cycle average of tags in use
system.cpu.dcache.total_refs 14290620 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 509.188646 # Cycle average of tags in use
system.cpu.dcache.total_refs 14264990 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 658097000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 381963 # number of writebacks
system.cpu.dtb.accesses 15532506 # DTB accesses
system.cpu.dcache.writebacks 382785 # number of writebacks
system.cpu.dtb.accesses 15507021 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 2224 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_entries 2208 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 15526972 # DTB hits
system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 15501368 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 5534 # DTB misses
system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 762 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 8744906 # DTB read accesses
system.cpu.dtb.read_hits 8740351 # DTB read hits
system.cpu.dtb.read_misses 4555 # DTB read misses
system.cpu.dtb.write_accesses 6787600 # DTB write accesses
system.cpu.dtb.write_hits 6786621 # DTB write hits
system.cpu.dtb.write_misses 979 # DTB write misses
system.cpu.icache.ReadReq_accesses::0 41556337 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 41556337 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency::0 14789.924361 # average ReadReq miss latency
system.cpu.dtb.misses 5653 # DTB misses
system.cpu.dtb.perms_faults 263 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 801 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 8728602 # DTB read accesses
system.cpu.dtb.read_hits 8723916 # DTB read hits
system.cpu.dtb.read_misses 4686 # DTB read misses
system.cpu.dtb.write_accesses 6778419 # DTB write accesses
system.cpu.dtb.write_hits 6777452 # DTB write hits
system.cpu.dtb.write_misses 967 # DTB write misses
system.cpu.icache.ReadReq_accesses::0 41474839 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 41474839 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency::0 14791.660330 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11788.627271 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11790.344583 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_hits::0 41121903 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 41121903 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 6425246000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate::0 0.010454 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses::0 434434 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 434434 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 5121380500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010454 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_hits::0 41040865 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 41040865 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 6419196000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate::0 0.010464 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses::0 433974 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 433974 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 5116703000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010464 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 434434 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses 433974 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable_latency 349111000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 94.656272 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 94.569871 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses::0 41556337 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::0 41474839 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 41556337 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency::0 14789.924361 # average overall miss latency
system.cpu.icache.demand_accesses::total 41474839 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency::0 14791.660330 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11788.627271 # average overall mshr miss latency
system.cpu.icache.demand_hits::0 41121903 # number of demand (read+write) hits
system.cpu.icache.demand_avg_mshr_miss_latency 11790.344583 # average overall mshr miss latency
system.cpu.icache.demand_hits::0 41040865 # number of demand (read+write) hits
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 41121903 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 6425246000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate::0 0.010454 # miss rate for demand accesses
system.cpu.icache.demand_hits::total 41040865 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 6419196000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate::0 0.010464 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
system.cpu.icache.demand_misses::0 434434 # number of demand (read+write) misses
system.cpu.icache.demand_misses::0 433974 # number of demand (read+write) misses
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 434434 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 433974 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 5121380500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate::0 0.010454 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_latency 5116703000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate::0 0.010464 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 434434 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses 433974 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_blocks::0 484.333151 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.945963 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses::0 41556337 # number of overall (read+write) accesses
system.cpu.icache.occ_blocks::0 484.306355 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.945911 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses::0 41474839 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 41556337 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency::0 14789.924361 # average overall miss latency
system.cpu.icache.overall_accesses::total 41474839 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency::0 14791.660330 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11788.627271 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11790.344583 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.cpu.icache.overall_hits::0 41121903 # number of overall hits
system.cpu.icache.overall_hits::0 41040865 # number of overall hits
system.cpu.icache.overall_hits::1 0 # number of overall hits
system.cpu.icache.overall_hits::total 41121903 # number of overall hits
system.cpu.icache.overall_miss_latency 6425246000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate::0 0.010454 # miss rate for overall accesses
system.cpu.icache.overall_hits::total 41040865 # number of overall hits
system.cpu.icache.overall_miss_latency 6419196000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate::0 0.010464 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
system.cpu.icache.overall_misses::0 434434 # number of overall misses
system.cpu.icache.overall_misses::0 433974 # number of overall misses
system.cpu.icache.overall_misses::1 0 # number of overall misses
system.cpu.icache.overall_misses::total 434434 # number of overall misses
system.cpu.icache.overall_misses::total 433974 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 5121380500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate::0 0.010454 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_latency 5116703000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate::0 0.010464 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 434434 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses 433974 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 349111000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 433922 # number of replacements
system.cpu.icache.sampled_refs 434434 # Sample count of references to valid blocks.
system.cpu.icache.replacements 433462 # number of replacements
system.cpu.icache.sampled_refs 433974 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 484.333151 # Cycle average of tags in use
system.cpu.icache.total_refs 41121903 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 14253166000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 34027 # number of writebacks
system.cpu.icache.tagsinuse 484.306355 # Cycle average of tags in use
system.cpu.icache.total_refs 41040865 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 14247556000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 34334 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 41559156 # DTB accesses
system.cpu.itb.accesses 41477769 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_entries 1476 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 41556337 # DTB hits
system.cpu.itb.inst_accesses 41559156 # ITB inst accesses
system.cpu.itb.inst_hits 41556337 # ITB inst hits
system.cpu.itb.inst_misses 2819 # ITB inst misses
system.cpu.itb.misses 2819 # DTB misses
system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 41474839 # DTB hits
system.cpu.itb.inst_accesses 41477769 # ITB inst accesses
system.cpu.itb.inst_hits 41474839 # ITB inst hits
system.cpu.itb.inst_misses 2930 # ITB inst misses
system.cpu.itb.misses 2930 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
@ -270,25 +270,25 @@ system.cpu.itb.write_misses 0 # DT
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 228811404 # number of cpu cycles simulated
system.cpu.numCycles 228587874 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 228811404 # Number of busy cycles
system.cpu.num_conditional_control_insts 7027409 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 6059 # Number of float alu accesses
system.cpu.num_fp_insts 6059 # number of float instructions
system.cpu.num_fp_register_reads 4227 # number of times the floating registers were read
system.cpu.num_busy_cycles 228587874 # Number of busy cycles
system.cpu.num_conditional_control_insts 7014796 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses
system.cpu.num_fp_insts 6058 # number of float instructions
system.cpu.num_fp_register_reads 4226 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written
system.cpu.num_func_calls 1109850 # number of times a function call or return occured
system.cpu.num_func_calls 1108768 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 51232482 # Number of instructions executed
system.cpu.num_int_alu_accesses 42503602 # Number of integer alu accesses
system.cpu.num_int_insts 42503602 # number of integer instructions
system.cpu.num_int_register_reads 139360817 # number of times the integer registers were read
system.cpu.num_int_register_writes 34549221 # number of times the integer registers were written
system.cpu.num_load_insts 9206942 # Number of load instructions
system.cpu.num_mem_refs 16291727 # number of memory refs
system.cpu.num_store_insts 7084785 # Number of store instructions
system.cpu.num_insts 51149744 # Number of instructions executed
system.cpu.num_int_alu_accesses 42422684 # Number of integer alu accesses
system.cpu.num_int_insts 42422684 # number of integer instructions
system.cpu.num_int_register_reads 139100376 # number of times the integer registers were read
system.cpu.num_int_register_writes 34478872 # number of times the integer registers were written
system.cpu.num_load_insts 9179491 # Number of load instructions
system.cpu.num_mem_refs 16255504 # number of memory refs
system.cpu.num_store_insts 7076013 # Number of store instructions
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.avg_refs no_value # Average number of references to valid blocks.
@ -356,140 +356,140 @@ system.iocache.tagsinuse 0 # Cy
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 0 # number of writebacks
system.l2c.ReadExReq_accesses::0 170357 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 170357 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::0 170341 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 170341 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_hits::0 62554 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 62554 # number of ReadExReq hits
system.l2c.ReadExReq_miss_latency 5605756000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate::0 0.632806 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses::0 107803 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 107803 # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency 4312120000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate::0 0.632806 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_hits::0 62544 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 62544 # number of ReadExReq hits
system.l2c.ReadExReq_miss_latency 5605444000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate::0 0.632831 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses::0 107797 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 107797 # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency 4311880000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate::0 0.632831 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_misses 107803 # number of ReadExReq MSHR misses
system.l2c.ReadReq_accesses::0 675906 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1 5729 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 681635 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_avg_miss_latency::0 52083.462261 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1 32503672.413793 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 32555755.876054 # average ReadReq miss latency
system.l2c.ReadExReq_mshr_misses 107797 # number of ReadExReq MSHR misses
system.l2c.ReadReq_accesses::0 675421 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1 6188 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 681609 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_avg_miss_latency::0 52063.722222 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1 42597590.909091 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 42649654.631313 # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_hits::0 657808 # number of ReadReq hits
system.l2c.ReadReq_hits::1 5700 # number of ReadReq hits
system.l2c.ReadReq_hits::total 663508 # number of ReadReq hits
system.l2c.ReadReq_miss_latency 942606500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate::0 0.026776 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1 0.005062 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.031838 # miss rate for ReadReq accesses
system.l2c.ReadReq_misses::0 18098 # number of ReadReq misses
system.l2c.ReadReq_misses::1 29 # number of ReadReq misses
system.l2c.ReadReq_misses::total 18127 # number of ReadReq misses
system.l2c.ReadReq_mshr_miss_latency 725080000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::0 0.026819 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1 3.164078 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 3.190896 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses 18127 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_uncacheable_latency 29200537000 # number of ReadReq MSHR uncacheable cycles
system.l2c.UpgradeReq_accesses::0 1831 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 1831 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_avg_miss_latency::0 487.589630 # average UpgradeReq miss latency
system.l2c.ReadReq_hits::0 657421 # number of ReadReq hits
system.l2c.ReadReq_hits::1 6166 # number of ReadReq hits
system.l2c.ReadReq_hits::total 663587 # number of ReadReq hits
system.l2c.ReadReq_miss_latency 937147000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate::0 0.026650 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1 0.003555 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.030205 # miss rate for ReadReq accesses
system.l2c.ReadReq_misses::0 18000 # number of ReadReq misses
system.l2c.ReadReq_misses::1 22 # number of ReadReq misses
system.l2c.ReadReq_misses::total 18022 # number of ReadReq misses
system.l2c.ReadReq_mshr_miss_latency 720880000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::0 0.026683 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1 2.912411 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 2.939094 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses 18022 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_uncacheable_latency 29200759000 # number of ReadReq MSHR uncacheable cycles
system.l2c.UpgradeReq_accesses::0 1839 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 1839 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_avg_miss_latency::0 313.940724 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_hits::0 18 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 18 # number of UpgradeReq hits
system.l2c.UpgradeReq_miss_latency 884000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_rate::0 0.990169 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses::0 1813 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 1813 # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency 72520000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate::0 0.990169 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits
system.l2c.UpgradeReq_miss_latency 572000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_rate::0 0.990756 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses::0 1822 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 1822 # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency 72880000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate::0 0.990756 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses 1813 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses 1822 # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_mshr_uncacheable_latency 740916000 # number of WriteReq MSHR uncacheable cycles
system.l2c.Writeback_accesses::0 415990 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 415990 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0 415990 # number of Writeback hits
system.l2c.Writeback_hits::total 415990 # number of Writeback hits
system.l2c.WriteReq_mshr_uncacheable_latency 741108000 # number of WriteReq MSHR uncacheable cycles
system.l2c.Writeback_accesses::0 417119 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 417119 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0 417119 # number of Writeback hits
system.l2c.Writeback_hits::total 417119 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.avg_refs 7.063302 # Average number of references to valid blocks.
system.l2c.avg_refs 7.066815 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.demand_accesses::0 846263 # number of demand (read+write) accesses
system.l2c.demand_accesses::1 5729 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 851992 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency::0 52011.997522 # average overall miss latency
system.l2c.demand_avg_miss_latency::1 225805603.448276 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 225857615.445798 # average overall miss latency
system.l2c.demand_accesses::0 845762 # number of demand (read+write) accesses
system.l2c.demand_accesses::1 6188 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 851950 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency::0 52009.117864 # average overall miss latency
system.l2c.demand_avg_miss_latency::1 297390500 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 297442509.117864 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.l2c.demand_hits::0 720362 # number of demand (read+write) hits
system.l2c.demand_hits::1 5700 # number of demand (read+write) hits
system.l2c.demand_hits::total 726062 # number of demand (read+write) hits
system.l2c.demand_miss_latency 6548362500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate::0 0.148773 # miss rate for demand accesses
system.l2c.demand_miss_rate::1 0.005062 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.153835 # miss rate for demand accesses
system.l2c.demand_misses::0 125901 # number of demand (read+write) misses
system.l2c.demand_misses::1 29 # number of demand (read+write) misses
system.l2c.demand_misses::total 125930 # number of demand (read+write) misses
system.l2c.demand_hits::0 719965 # number of demand (read+write) hits
system.l2c.demand_hits::1 6166 # number of demand (read+write) hits
system.l2c.demand_hits::total 726131 # number of demand (read+write) hits
system.l2c.demand_miss_latency 6542591000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate::0 0.148738 # miss rate for demand accesses
system.l2c.demand_miss_rate::1 0.003555 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.152293 # miss rate for demand accesses
system.l2c.demand_misses::0 125797 # number of demand (read+write) misses
system.l2c.demand_misses::1 22 # number of demand (read+write) misses
system.l2c.demand_misses::total 125819 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 5037200000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0 0.148807 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1 21.981149 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 22.129956 # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses 125930 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_miss_latency 5032760000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0 0.148764 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1 20.332741 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 20.481505 # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses 125819 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.occ_blocks::0 5334.310202 # Average occupied blocks per context
system.l2c.occ_blocks::1 31332.032709 # Average occupied blocks per context
system.l2c.occ_percent::0 0.081395 # Average percentage of cache occupancy
system.l2c.occ_percent::1 0.478089 # Average percentage of cache occupancy
system.l2c.overall_accesses::0 846263 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 5729 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 851992 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency::0 52011.997522 # average overall miss latency
system.l2c.overall_avg_miss_latency::1 225805603.448276 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 225857615.445798 # average overall miss latency
system.l2c.occ_blocks::0 5338.149518 # Average occupied blocks per context
system.l2c.occ_blocks::1 31318.985652 # Average occupied blocks per context
system.l2c.occ_percent::0 0.081454 # Average percentage of cache occupancy
system.l2c.occ_percent::1 0.477890 # Average percentage of cache occupancy
system.l2c.overall_accesses::0 845762 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 6188 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 851950 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency::0 52009.117864 # average overall miss latency
system.l2c.overall_avg_miss_latency::1 297390500 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 297442509.117864 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.l2c.overall_hits::0 720362 # number of overall hits
system.l2c.overall_hits::1 5700 # number of overall hits
system.l2c.overall_hits::total 726062 # number of overall hits
system.l2c.overall_miss_latency 6548362500 # number of overall miss cycles
system.l2c.overall_miss_rate::0 0.148773 # miss rate for overall accesses
system.l2c.overall_miss_rate::1 0.005062 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.153835 # miss rate for overall accesses
system.l2c.overall_misses::0 125901 # number of overall misses
system.l2c.overall_misses::1 29 # number of overall misses
system.l2c.overall_misses::total 125930 # number of overall misses
system.l2c.overall_hits::0 719965 # number of overall hits
system.l2c.overall_hits::1 6166 # number of overall hits
system.l2c.overall_hits::total 726131 # number of overall hits
system.l2c.overall_miss_latency 6542591000 # number of overall miss cycles
system.l2c.overall_miss_rate::0 0.148738 # miss rate for overall accesses
system.l2c.overall_miss_rate::1 0.003555 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.152293 # miss rate for overall accesses
system.l2c.overall_misses::0 125797 # number of overall misses
system.l2c.overall_misses::1 22 # number of overall misses
system.l2c.overall_misses::total 125819 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 5037200000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0 0.148807 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1 21.981149 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 22.129956 # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 125930 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 29941453000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_miss_latency 5032760000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0 0.148764 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1 20.332741 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 20.481505 # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 125819 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 29941867000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.replacements 93179 # number of replacements
system.l2c.sampled_refs 124640 # Sample count of references to valid blocks.
system.l2c.replacements 93108 # number of replacements
system.l2c.sampled_refs 124568 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse 36666.342911 # Cycle average of tags in use
system.l2c.total_refs 880370 # Total number of references to valid blocks.
system.l2c.tagsinuse 36657.135171 # Cycle average of tags in use
system.l2c.total_refs 880299 # Total number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 87304 # number of writebacks
system.l2c.writebacks 87346 # number of writebacks
---------- End Simulation Statistics ----------

BIN
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
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2
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
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@ -127,7 +127,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
executable=/chips/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
max_stack_size=67108864

8
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
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@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 19 2011 12:19:46
M5 started Apr 19 2011 12:20:58
M5 executing on maize
M5 compiled May 1 2011 16:25:10
M5 started May 1 2011 16:26:16
M5 executing on u200439-lin.austin.arm.com
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -83,4 +83,4 @@ Iteration 9 completed
[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
Iteration 10 completed
PASSED :-)
Exiting @ tick 262295000 because target called exit()
Exiting @ tick 262298000 because target called exit()

880
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
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