From 0b0d5a282a25a936d4aa92ec81ef2bd50141ce03 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 9 Nov 2006 11:33:44 -0500 Subject: [PATCH 1/5] Draining fixes. src/cpu/o3/cpu.cc: Handle draining properly when CPU isn't actually being used. src/cpu/simple/atomic.cc: Be sure to set status properly when draining. src/mem/bus.cc: Fix for draining. --HG-- extra : convert_revision : d9796e6693e974f022159029fc9743c49a970c8f --- src/cpu/o3/cpu.cc | 6 ++++++ src/cpu/simple/atomic.cc | 3 +++ src/mem/bus.cc | 5 ++++- 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index dfe42d882..580816372 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -819,6 +819,12 @@ unsigned int FullO3CPU::drain(Event *drain_event) { DPRINTF(O3CPU, "Switching out\n"); + + // If the CPU isn't doing anything, then return immediately. + if (_status == Idle || _status == SwitchedOut) { + return 0; + } + drainCount = 0; fetch.drain(); decode.drain(); diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 4f68cfd6f..f94ea0917 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -213,6 +213,9 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) break; } } + if (_status != Running) { + _status = Idle; + } } diff --git a/src/mem/bus.cc b/src/mem/bus.cc index 7b65d252b..ae87d8099 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -242,8 +242,11 @@ Bus::recvRetry(int id) } } //If we weren't able to drain before, we might be able to now. - if (drainEvent && retryList.size() == 0 && curTick >= tickNextIdle) + if (drainEvent && retryList.size() == 0 && curTick >= tickNextIdle) { drainEvent->process(); + // Clear the drain event once we're done with it. + drainEvent = NULL; + } } Port * From 21f43bfc4b01051e688a4eec4ce5aef12ad2c951 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 9 Nov 2006 11:37:26 -0500 Subject: [PATCH 2/5] Be sure to populate the packet's finishTime field in the atomic timing case. --HG-- extra : convert_revision : ef34818eb2dea5b3a8e754bf56745a7cd2497bf0 --- src/mem/bus.cc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mem/bus.cc b/src/mem/bus.cc index ae87d8099..8ea67a0e4 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -370,6 +370,10 @@ Bus::recvAtomic(PacketPtr pkt) DPRINTF(Bus, "recvAtomic: packet src %d dest %d addr 0x%x cmd %s\n", pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString()); assert(pkt->getDest() == Packet::Broadcast); + + // Assume one bus cycle in order to get through. This may have + // some clock skew issues yet again... + pkt->finishTime = curTick + clock; Tick snoopTime = atomicSnoop(pkt); if (snoopTime) return snoopTime; //Snoop satisfies it From 0ba2cc6571f80beb3600000649403cbff0b67d8b Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 9 Nov 2006 15:05:13 -0500 Subject: [PATCH 3/5] Clean up config scripts to not have to worry about attaching a cache only to the TimingCPU. Now the Atomic CPU works with caches. configs/common/Simulation.py: Atomic CPU now works properly with caches, so we don't have to do extra parsing to hook up caches only to the timing CPU. However the O3CPU must always use caches, so a check for that must still exist. Also change the switch_cpus to be placed at the system level, now that Steve changed how the IntrController gets its CPU. configs/example/fs.py: configs/example/se.py: Atomic CPU now handles caches. --HG-- extra : convert_revision : 534ded558ef96cafd76b4b5c5317bd8f4d05076e --- configs/common/Simulation.py | 16 ++++------------ configs/example/fs.py | 2 +- configs/example/se.py | 2 +- 3 files changed, 6 insertions(+), 14 deletions(-) diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index d88373d54..f43fa9a6f 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -84,10 +84,6 @@ def run(options, root, testsys, cpu_class): if not m5.build_env['FULL_SYSTEM']: switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus[i].clock = testsys.cpu[0].clock - if options.caches: - switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), - L1Cache(size = '64kB')) - switch_cpus[i].connectMemPorts(testsys.membus) root.switch_cpus = switch_cpus switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] @@ -107,19 +103,15 @@ def run(options, root, testsys, cpu_class): switch_cpus[i].clock = testsys.cpu[0].clock switch_cpus_1[i].clock = testsys.cpu[0].clock - if options.caches: - switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), - L1Cache(size = '64kB')) - switch_cpus[i].connectMemPorts(testsys.membus) - else: + if not options.caches: # O3 CPU must have a cache to work. switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) switch_cpus_1[i].connectMemPorts(testsys.membus) - root.switch_cpus = switch_cpus - root.switch_cpus_1 = switch_cpus_1 + testsys.switch_cpus = switch_cpus + testsys.switch_cpus_1 = switch_cpus_1 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] @@ -222,5 +214,5 @@ def run(options, root, testsys, cpu_class): if exit_cause == '': exit_cause = exit_event.getCause() - print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause + print 'Exiting @ cycle %i because %s' % (m5.curTick(), exit_cause) diff --git a/configs/example/fs.py b/configs/example/fs.py index 180cd2719..a9f1d579a 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -95,7 +95,7 @@ test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) np = options.num_cpus test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] for i in xrange(np): - if options.caches and not options.standard_switch and not FutureClass: + if options.caches: test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) test_sys.cpu[i].connectMemPorts(test_sys.membus) diff --git a/configs/example/se.py b/configs/example/se.py index 0a158244f..0944a030e 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -101,7 +101,7 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], system.physmem.port = system.membus.port for i in xrange(np): - if options.caches and not options.standard_switch and not FutureClass: + if options.caches: system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) system.cpu[i].connectMemPorts(system.membus) From 12e26c68c3e12a17c29b694012819bc7bae7bb5a Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Sun, 12 Nov 2006 20:15:30 -0500 Subject: [PATCH 4/5] Updates to support new interrupt processing and removal of PcPAL. src/arch/alpha/interrupts.hh: No need for this now that the ThreadContext is being used to set these IPRs in interrupts. Also split up the interrupt checking from the updating of the IPL and interrupt summary. src/arch/alpha/tlb.cc: Check the PC for whether or not it's in PAL mode, not the addr. src/cpu/o3/alpha/cpu.hh: Split up getting the interrupt from actually processing the interrupt. src/cpu/o3/alpha/cpu_impl.hh: Splut up the processing of interrupts. src/cpu/o3/commit_impl.hh: Update for ISA-oriented interrupt changes. src/cpu/o3/fetch_impl.hh: Fix broken if statement from PcPAL updates, and properly populate the request fields. Also more debugging output. src/cpu/ozone/cpu_impl.hh: Updates for ISA-oriented interrupt stuff. src/cpu/ozone/front_end_impl.hh: Populate request fields properly. src/cpu/simple/base.cc: Update for interrupt stuff. --HG-- extra : convert_revision : 9bac3f9ffed4948ee788699b2fa8419bc1ca647c --- src/arch/alpha/interrupts.hh | 28 ++++++++++-------- src/arch/alpha/tlb.cc | 2 +- src/cpu/o3/alpha/cpu.hh | 7 +++-- src/cpu/o3/alpha/cpu_impl.hh | 22 +++++++++------ src/cpu/o3/commit_impl.hh | 30 ++++++++++++-------- src/cpu/o3/fetch_impl.hh | 25 +++++++++++++---- src/cpu/ozone/cpu_impl.hh | 50 ++++----------------------------- src/cpu/ozone/front_end_impl.hh | 4 +-- src/cpu/simple/base.cc | 1 + 9 files changed, 82 insertions(+), 87 deletions(-) diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh index 75031ae47..a86fb2d7b 100644 --- a/src/arch/alpha/interrupts.hh +++ b/src/arch/alpha/interrupts.hh @@ -49,6 +49,7 @@ namespace AlphaISA { memset(interrupts, 0, sizeof(interrupts)); intstatus = 0; + newInfoSet = false; } void post(int int_num, int index) @@ -137,18 +138,10 @@ namespace AlphaISA } if (ipl && ipl > tc->readMiscReg(IPR_IPLR)) { - tc->setMiscReg(IPR_ISR, summary); - tc->setMiscReg(IPR_INTID, ipl); - - /* The following needs to be added back in somehow */ - // Checker needs to know these two registers were updated. -/*#if USE_CHECKER - if (this->checker) { - this->checker->threadBase()->setMiscReg(IPR_ISR, summary); - this->checker->threadBase()->setMiscReg(IPR_INTID, ipl); - } -#endif*/ - +// assert(!newInfoSet); + newIpl = ipl; + newSummary = newSummary; + newInfoSet = true; DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", tc->readMiscReg(IPR_IPLR), ipl, summary); @@ -158,7 +151,18 @@ namespace AlphaISA } } + void updateIntrInfo(ThreadContext *tc) + { + assert(newInfoSet); + tc->setMiscReg(IPR_ISR, newSummary); + tc->setMiscReg(IPR_INTID, newIpl); + newInfoSet = false; + } + private: + bool newInfoSet; + int newIpl; + int newSummary; }; } diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index ae302e686..af69e45c0 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -292,7 +292,7 @@ namespace AlphaISA Fault ITB::translate(RequestPtr &req, ThreadContext *tc) const { - if (PcPAL(req->getVaddr())) { + if (PcPAL(req->getPC())) { // strip off PAL PC marker (lsb is 1) req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); hits++; diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh index b62550062..0078db69f 100644 --- a/src/cpu/o3/alpha/cpu.hh +++ b/src/cpu/o3/alpha/cpu.hh @@ -156,8 +156,11 @@ class AlphaO3CPU : public FullO3CPU bool simPalCheck(int palFunc, unsigned tid); - /** Processes any interrupts. */ - void processInterrupts(); + /** Returns the Fault for any valid interrupt. */ + Fault getInterrupts(); + + /** Processes any an interrupt fault. */ + void processInterrupts(Fault interrupt); /** Halts the CPU. */ void halt() { panic("Halt not implemented!\n"); } diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index 04eadfa5a..f5c394826 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -266,9 +266,17 @@ AlphaO3CPU::simPalCheck(int palFunc, unsigned tid) return true; } +template +Fault +AlphaO3CPU::getInterrupts() +{ + // Check if there are any outstanding interrupts + return this->interrupts.getInterrupt(this->threadContexts[0]); +} + template void -AlphaO3CPU::processInterrupts() +AlphaO3CPU::processInterrupts(Fault interrupt) { // Check for interrupts here. For now can copy the code that // exists within isa_fullsys_traits.hh. Also assume that thread 0 @@ -276,14 +284,12 @@ AlphaO3CPU::processInterrupts() // @todo: Possibly consolidate the interrupt checking code. // @todo: Allow other threads to handle interrupts. - // Check if there are any outstanding interrupts - //Handle the interrupts - Fault interrupt = this->interrupts.getInterrupt(this->tcBase(0)); + assert(interrupt != NoFault); + this->interrupts.updateIntrInfo(this->threadContexts[0]); - if (interrupt != NoFault) { - this->checkInterrupts = false; - this->trap(interrupt, 0); - } + DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); + this->checkInterrupts = false; + this->trap(interrupt, 0); } #endif // FULL_SYSTEM diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 30052a148..d8e079a7e 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -640,8 +640,18 @@ DefaultCommit::commit() // @todo: Allow other threads to handle interrupts. if (cpu->checkInterrupts && cpu->check_interrupts(cpu->tcBase(0)) && + commitStatus[0] != TrapPending && !trapSquash[0] && !tcSquash[0]) { + + // Get any interrupt that happened + Fault intr = cpu->getInterrupts(); + + // Exit this if block if there's no fault. + if (intr == NoFault) { + goto commit_insts; + } + // Tell fetch that there is an interrupt pending. This will // make fetch wait until it sees a non PAL-mode PC, at which // point it stops fetching instructions. @@ -650,26 +660,24 @@ DefaultCommit::commit() // Wait until the ROB is empty and all stores have drained in // order to enter the interrupt. if (rob->isEmpty() && !iewStage->hasStoresToWB()) { - // Not sure which thread should be the one to interrupt. For now - // always do thread 0. + // Squash or record that I need to squash this cycle if + // an interrupt needed to be handled. + DPRINTF(Commit, "Interrupt detected.\n"); + assert(!thread[0]->inSyscall); thread[0]->inSyscall = true; - // CPU will handle implementation of the interrupt. - cpu->processInterrupts(); + // CPU will handle interrupt. + cpu->processInterrupts(intr); - // Now squash or record that I need to squash this cycle. - commitStatus[0] = TrapPending; - - // Exit state update mode to avoid accidental updating. thread[0]->inSyscall = false; + commitStatus[0] = TrapPending; + // Generate trap squash event. generateTrapEvent(0); toIEW->commitInfo[0].clearInterrupt = true; - - DPRINTF(Commit, "Interrupt detected.\n"); } else { DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); } @@ -679,7 +687,7 @@ DefaultCommit::commit() //////////////////////////////////// // Check for any possible squashes, handle them first //////////////////////////////////// - + commit_insts: std::list::iterator threads = (*activeThreads).begin(); while (threads != (*activeThreads).end()) { diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 5ef6e27ea..b1fae8cf0 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -559,27 +559,36 @@ DefaultFetch::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid Fault fault = NoFault; //AlphaDep - if (cacheBlocked || isSwitchedOut() || - (interruptPending && (fetch_PC & 0x3))) { + if (cacheBlocked) { + DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n", + tid); + return false; + } else if (isSwitchedOut()) { + DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n", + tid); + return false; + } else if (interruptPending && !(fetch_PC & 0x3)) { // Hold off fetch from getting new instructions when: // Cache is blocked, or // while an interrupt is pending and we're not in PAL mode, or // fetch is switched out. + DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n", + tid); return false; } // Align the fetch PC so it's at the start of a cache block. - fetch_PC = icacheBlockAlignPC(fetch_PC); + Addr block_PC = icacheBlockAlignPC(fetch_PC); // If we've already got the block, no need to try to fetch it again. - if (cacheDataValid[tid] && fetch_PC == cacheDataPC[tid]) { + if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) { return true; } // Setup the memReq to do a read of the first instruction's address. // Set the appropriate read size and flags as well. // Build request here. - RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, 0, + RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0, fetch_PC, cpu->readCpuId(), tid); memReq[tid] = mem_req; @@ -609,7 +618,7 @@ DefaultFetch::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid Packet::ReadReq, Packet::Broadcast); data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]); - cacheDataPC[tid] = fetch_PC; + cacheDataPC[tid] = block_PC; cacheDataValid[tid] = false; DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); @@ -1050,12 +1059,16 @@ DefaultFetch::fetch(bool &status_change) } else { if (fetchStatus[tid] == Idle) { ++fetchIdleCycles; + DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid); } else if (fetchStatus[tid] == Blocked) { ++fetchBlockedCycles; + DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid); } else if (fetchStatus[tid] == Squashing) { ++fetchSquashCycles; + DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid); } else if (fetchStatus[tid] == IcacheWaitResponse) { ++icacheStallCycles; + DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid); } // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index 86c973a0f..accc8d294 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -700,52 +700,12 @@ OzoneCPU::processInterrupts() // Check if there are any outstanding interrupts //Handle the interrupts - int ipl = 0; - int summary = 0; + Fault interrupt = this->interrupts.getInterrupt(thread.getTC()); - checkInterrupts = false; - - if (thread.readMiscReg(IPR_ASTRR)) - panic("asynchronous traps not implemented\n"); - - if (thread.readMiscReg(IPR_SIRR)) { - for (int i = INTLEVEL_SOFTWARE_MIN; - i < INTLEVEL_SOFTWARE_MAX; i++) { - if (thread.readMiscReg(IPR_SIRR) & (ULL(1) << i)) { - // See table 4-19 of the 21164 hardware reference - ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; - summary |= (ULL(1) << i); - } - } - } - - uint64_t interrupts = intr_status(); - - if (interrupts) { - for (int i = INTLEVEL_EXTERNAL_MIN; - i < INTLEVEL_EXTERNAL_MAX; i++) { - if (interrupts & (ULL(1) << i)) { - // See table 4-19 of the 21164 hardware reference - ipl = i; - summary |= (ULL(1) << i); - } - } - } - - if (ipl && ipl > thread.readMiscReg(IPR_IPLR)) { - thread.setMiscReg(IPR_ISR, summary); - thread.setMiscReg(IPR_INTID, ipl); -#if USE_CHECKER - // @todo: Make this more transparent - if (checker) { - checker->threadBase()->setMiscReg(IPR_ISR, summary); - checker->threadBase()->setMiscReg(IPR_INTID, ipl); - } -#endif - Fault fault = new InterruptFault; - fault->invoke(thread.getTC()); - DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", - thread.readMiscReg(IPR_IPLR), ipl, summary); + if (interrupt != NoFault) { + this->interrupts.updateIntrInfo(thread.getTC()); + this->checkInterrupts = false; + interrupt->invoke(thread.getTC()); } } diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh index 73ca6afbe..198ce0308 100644 --- a/src/cpu/ozone/front_end_impl.hh +++ b/src/cpu/ozone/front_end_impl.hh @@ -476,8 +476,8 @@ FrontEnd::fetchCacheLine() // Setup the memReq to do a read of the first isntruction's address. // Set the appropriate read size and flags as well. - memReq = new Request(0, fetch_PC, cacheBlkSize, flags, - fetch_PC, cpu->readCpuId(), 0); + memReq = new Request(0, fetch_PC, cacheBlkSize, 0, + PC, cpu->readCpuId(), 0); // Translate the instruction request. fault = cpu->translateInstReq(memReq, thread); diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index ab438aa77..4e5754bbb 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -315,6 +315,7 @@ BaseSimpleCPU::checkForInterrupts() Fault interrupt = interrupts.getInterrupt(tc); if (interrupt != NoFault) { + interrupts.updateIntrInfo(tc); checkInterrupts = false; interrupt->invoke(tc); } From 437436a2f706477439cfb81d254e8f7b454450a5 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Sun, 12 Nov 2006 21:49:51 -0500 Subject: [PATCH 5/5] Fix for non-FS compile. --HG-- extra : convert_revision : 661b412b0ae670181b89cb7dbc5e9d813804aa7a --- src/cpu/o3/commit_impl.hh | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index d8e079a7e..b394759b9 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -682,12 +682,15 @@ DefaultCommit::commit() DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); } } + + // Label for goto. Not pretty but more readable than really big + // if statement above. + commit_insts: #endif // FULL_SYSTEM //////////////////////////////////// // Check for any possible squashes, handle them first //////////////////////////////////// - commit_insts: std::list::iterator threads = (*activeThreads).begin(); while (threads != (*activeThreads).end()) {