MIPS: Phase out MIPS's int_regfile.hh.
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@ -37,7 +37,6 @@
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#include "arch/mips/types.hh"
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#include "arch/mips/types.hh"
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#include "arch/mips/isa_traits.hh"
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#include "arch/mips/isa_traits.hh"
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#include "arch/mips/mt.hh"
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#include "arch/mips/mt.hh"
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#include "arch/mips/regfile/int_regfile.hh"
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#include "arch/mips/regfile/misc_regfile.hh"
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#include "arch/mips/regfile/misc_regfile.hh"
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#include "sim/faults.hh"
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#include "sim/faults.hh"
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@ -1,70 +0,0 @@
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/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*/
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#ifndef __ARCH_MIPS_REGFILE_INT_REGFILE_HH__
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#define __ARCH_MIPS_REGFILE_INT_REGFILE_HH__
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#include "arch/mips/types.hh"
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#include "arch/mips/isa_traits.hh"
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#include "base/misc.hh"
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#include "base/trace.hh"
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#include "sim/faults.hh"
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class Checkpoint;
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namespace MipsISA
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{
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enum MiscIntRegNums {
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LO = NumIntArchRegs,
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HI,
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DSPACX0,
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DSPLo1,
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DSPHi1,
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DSPACX1,
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DSPLo2,
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DSPHi2,
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DSPACX2,
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DSPLo3,
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DSPHi3,
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DSPACX3,
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DSPControl,
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DSPLo0 = LO,
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DSPHi0 = HI
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};
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//@TODO: Implementing ShadowSets needs to
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//edit this value such that:
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//TotalArchRegs = NumIntArchRegs * ShadowSets
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const int TotalArchRegs = NumIntArchRegs;
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} // namespace MipsISA
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#endif
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@ -35,7 +35,6 @@
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#include "arch/mips/types.hh"
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#include "arch/mips/types.hh"
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#include "arch/mips/isa_traits.hh"
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#include "arch/mips/isa_traits.hh"
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//#include "arch/mips/mt.hh"
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//#include "arch/mips/mt.hh"
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#include "arch/mips/regfile/int_regfile.hh"
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//#include "cpu/base.hh"
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//#include "cpu/base.hh"
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#include "sim/faults.hh"
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#include "sim/faults.hh"
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@ -71,6 +70,30 @@ namespace MipsISA
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Cause_Field = 11
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Cause_Field = 11
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};
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};
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enum MiscIntRegNums {
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LO = NumIntArchRegs,
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HI,
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DSPACX0,
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DSPLo1,
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DSPHi1,
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DSPACX1,
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DSPLo2,
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DSPHi2,
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DSPACX2,
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DSPLo3,
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DSPHi3,
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DSPACX3,
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DSPControl,
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DSPLo0 = LO,
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DSPHi0 = HI
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};
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//@TODO: Implementing ShadowSets needs to
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//edit this value such that:
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//TotalArchRegs = NumIntArchRegs * ShadowSets
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const int TotalArchRegs = NumIntArchRegs;
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class RegFile {
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class RegFile {
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protected:
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protected:
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Addr pc; // program counter
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Addr pc; // program counter
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