From 2f607b882ce3f8e39176983d1bf9c98942ffaa1c Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 19 Apr 2009 04:56:06 -0700
Subject: [PATCH] X86: Implement a locking version of OR.

---
 .../x86/isa/insts/general_purpose/logical.py  | 32 +++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/src/arch/x86/isa/insts/general_purpose/logical.py b/src/arch/x86/isa/insts/general_purpose/logical.py
index a8b7c6a45..ef860215c 100644
--- a/src/arch/x86/isa/insts/general_purpose/logical.py
+++ b/src/arch/x86/isa/insts/general_purpose/logical.py
@@ -76,6 +76,23 @@ def macroop OR_P_I
     st t1, seg, riprel, disp
 };
 
+def macroop OR_LOCKED_M_I
+{
+    limm t2, imm
+    ldstl t1, seg, sib, disp
+    or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
+    stul t1, seg, sib, disp
+};
+
+def macroop OR_LOCKED_P_I
+{
+    limm t2, imm
+    rdip t7
+    ldstl t1, seg, riprel, disp
+    or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
+    stul t1, seg, riprel, disp
+};
+
 def macroop OR_M_R
 {
     ldst t1, seg, sib, disp
@@ -91,6 +108,21 @@ def macroop OR_P_R
     st t1, seg, riprel, disp
 };
 
+def macroop OR_LOCKED_M_R
+{
+    ldstl t1, seg, sib, disp
+    or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
+    stul t1, seg, sib, disp
+};
+
+def macroop OR_LOCKED_P_R
+{
+    rdip t7
+    ldstl t1, seg, riprel, disp
+    or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
+    stul t1, seg, riprel, disp
+};
+
 def macroop OR_R_M
 {
     ld t1, seg, sib, disp