Ruby: Convert AccessModeType to RubyAccessMode
This patch converts AccessModeType to RubyAccessMode so that both the protocol dependent and independent code uses the same access mode.
This commit is contained in:
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dd9083115e
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@ -44,7 +44,7 @@ Check::Check(const Address& address, const Address& pc,
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pickInitiatingNode();
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changeAddress(address);
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m_pc = pc;
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m_access_mode = AccessModeType(random() % AccessModeType_NUM);
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m_access_mode = RubyAccessMode(random() % RubyAccessMode_NUM);
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m_store_count = 0;
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}
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@ -33,7 +33,7 @@
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#include <iostream>
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#include "cpu/testers/rubytest/RubyTester.hh"
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#include "mem/protocol/AccessModeType.hh"
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#include "mem/protocol/RubyAccessMode.hh"
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#include "mem/protocol/TesterStatus.hh"
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/common/Global.hh"
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@ -73,7 +73,7 @@ class Check
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NodeID m_initiatingNode;
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Address m_address;
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Address m_pc;
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AccessModeType m_access_mode;
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RubyAccessMode m_access_mode;
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int m_num_cpu_sequencers;
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RubyTester* m_tester_ptr;
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};
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@ -62,7 +62,7 @@ enumeration(CoherenceResponseType, desc="...") {
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structure(RequestMsg, desc="...", interface="NetworkMessage") {
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Address Address, desc="Physical address for this request";
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CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
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AccessModeType AccessMode, desc="user/supervisor access type";
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RubyAccessMode AccessMode, desc="user/supervisor access type";
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MachineID Requestor , desc="What component request";
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NetDest Destination, desc="What components receive the request, includes MachineType and num";
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MessageSizeType MessageSize, desc="size category of the message";
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@ -84,7 +84,7 @@ structure(RequestMsg, desc="...", interface="NetworkMessage") {
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DataBlock DataBlk, desc="data for the cache line (DMA WRITE request)";
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int Acks, desc="How many acks to expect";
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MessageSizeType MessageSize, desc="size category of the message";
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AccessModeType AccessMode, desc="user/supervisor access type";
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RubyAccessMode AccessMode, desc="user/supervisor access type";
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PrefetchBit Prefetch, desc="Is this a prefetch request";
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}
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@ -149,7 +149,7 @@ machine(L1Cache, "Token protocol")
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AccessType AccessType, desc="Type of request (used for profiling)";
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Time IssueTime, desc="Time the request was issued";
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AccessModeType AccessMode, desc="user/supervisor access type";
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RubyAccessMode AccessMode, desc="user/supervisor access type";
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PrefetchBit Prefetch, desc="Is this a prefetch request";
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}
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@ -424,7 +424,7 @@ machine(Directory, "Token protocol")
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.MessageSize := MessageSizeType:Persistent_Control;
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out_msg.Prefetch := PrefetchBit:No;
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out_msg.AccessMode := AccessModeType:SupervisorMode;
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out_msg.AccessMode := RubyAccessMode:Supervisor;
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}
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markPersistentEntries(address);
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starving := true;
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@ -466,7 +466,7 @@ machine(Directory, "Token protocol")
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out_msg.RetryNum := 0;
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out_msg.MessageSize := MessageSizeType:Broadcast_Control;
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out_msg.Prefetch := PrefetchBit:No;
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out_msg.AccessMode := AccessModeType:SupervisorMode;
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out_msg.AccessMode := RubyAccessMode:Supervisor;
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}
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}
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}
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@ -494,7 +494,7 @@ machine(Directory, "Token protocol")
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.MessageSize := MessageSizeType:Persistent_Control;
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out_msg.Prefetch := PrefetchBit:No;
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out_msg.AccessMode := AccessModeType:SupervisorMode;
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out_msg.AccessMode := RubyAccessMode:Supervisor;
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}
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markPersistentEntries(address);
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starving := true;
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@ -532,7 +532,7 @@ machine(Directory, "Token protocol")
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out_msg.RetryNum := 0;
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out_msg.MessageSize := MessageSizeType:Broadcast_Control;
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out_msg.Prefetch := PrefetchBit:No;
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out_msg.AccessMode := AccessModeType:SupervisorMode;
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out_msg.AccessMode := RubyAccessMode:Supervisor;
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}
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}
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}
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@ -78,7 +78,7 @@ structure(PersistentMsg, desc="...", interface="NetworkMessage") {
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MachineID Requestor, desc="Node who initiated the request";
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NetDest Destination, desc="Destination set";
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MessageSizeType MessageSize, desc="size category of the message";
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AccessModeType AccessMode, desc="user/supervisor access type";
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RubyAccessMode AccessMode, desc="user/supervisor access type";
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PrefetchBit Prefetch, desc="Is this a prefetch request";
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}
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@ -91,7 +91,7 @@ structure(RequestMsg, desc="...", interface="NetworkMessage") {
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bool isLocal, desc="Is this request from a local L1";
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int RetryNum, desc="retry sequence number";
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MessageSizeType MessageSize, desc="size category of the message";
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AccessModeType AccessMode, desc="user/supervisor access type";
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RubyAccessMode AccessMode, desc="user/supervisor access type";
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PrefetchBit Prefetch, desc="Is this a prefetch request";
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}
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@ -193,10 +193,11 @@ enumeration(AccessType, desc="...") {
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Write, desc="Writing to cache";
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}
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// AccessModeType
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enumeration(AccessModeType, default="AccessModeType_UserMode", desc="...") {
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SupervisorMode, desc="Supervisor mode";
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UserMode, desc="User mode";
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// RubyAccessMode
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enumeration(RubyAccessMode, default="RubyAccessMode_User", desc="...") {
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Supervisor, desc="Supervisor mode";
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User, desc="User mode";
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Device, desc="Device mode";
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}
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enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") {
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@ -212,7 +213,7 @@ structure(CacheMsg, desc="...", interface="Message") {
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Address PhysicalAddress, desc="Physical address for this request";
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CacheRequestType Type, desc="Type of request (LD, ST, etc)";
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Address ProgramCounter, desc="Program counter of the instruction that caused the miss";
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AccessModeType AccessMode, desc="user/supervisor access type";
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RubyAccessMode AccessMode, desc="user/supervisor access type";
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int Size, desc="size in bytes of access";
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PrefetchBit Prefetch, desc="Is this a prefetch request";
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}
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@ -223,7 +224,7 @@ structure(SequencerMsg, desc="...", interface="Message") {
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Address PhysicalAddress, desc="Physical address for this request";
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SequencerRequestType Type, desc="Type of request (LD, ST, etc)";
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Address ProgramCounter, desc="Program counter of the instruction that caused the miss";
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AccessModeType AccessMode, desc="user/supervisor access type";
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RubyAccessMode AccessMode, desc="user/supervisor access type";
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DataBlock DataBlk, desc="Data";
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int Len, desc="size in bytes of access";
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PrefetchBit Prefetch, desc="Is this a prefetch request";
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@ -129,7 +129,7 @@ structure (CacheMemory, external = "yes") {
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void profileMiss(CacheMsg);
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void profileGenericRequest(GenericRequestType,
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AccessModeType,
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RubyAccessMode,
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PrefetchBit);
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void setMRU(Address);
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@ -59,7 +59,7 @@ AccessTraceForAddress::print(std::ostream& out) const
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void
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AccessTraceForAddress::update(CacheRequestType type,
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AccessModeType access_mode, NodeID cpu,
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RubyAccessMode access_mode, NodeID cpu,
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bool sharing_miss)
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{
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m_touched_by.add(cpu);
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@ -74,7 +74,7 @@ AccessTraceForAddress::update(CacheRequestType type,
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// ERROR_MSG("Trying to add invalid access to trace");
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}
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if (access_mode == AccessModeType_UserMode) {
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if (access_mode == RubyAccessMode_User) {
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m_user++;
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}
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@ -31,7 +31,7 @@
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#include <iostream>
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#include "mem/protocol/AccessModeType.hh"
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#include "mem/protocol/RubyAccessMode.hh"
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#include "mem/protocol/CacheRequestType.hh"
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/common/Global.hh"
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@ -50,7 +50,7 @@ class AccessTraceForAddress
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~AccessTraceForAddress();
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void setAddress(const Address& addr) { m_addr = addr; }
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void update(CacheRequestType type, AccessModeType access_mode, NodeID cpu,
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void update(CacheRequestType type, RubyAccessMode access_mode, NodeID cpu,
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bool sharing_miss);
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int getTotal() const;
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int getSharing() const { return m_sharing; }
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@ -257,7 +257,7 @@ AddressProfiler::profileGetX(const Address& datablock, const Address& PC,
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m_getx_sharing_histogram.add(num_indirections);
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bool indirection_miss = (num_indirections > 0);
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addTraceSample(datablock, PC, CacheRequestType_ST, AccessModeType(0),
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addTraceSample(datablock, PC, CacheRequestType_ST, RubyAccessMode(0),
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requestor, indirection_miss);
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}
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@ -274,14 +274,14 @@ AddressProfiler::profileGetS(const Address& datablock, const Address& PC,
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m_gets_sharing_histogram.add(num_indirections);
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bool indirection_miss = (num_indirections > 0);
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addTraceSample(datablock, PC, CacheRequestType_LD, AccessModeType(0),
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addTraceSample(datablock, PC, CacheRequestType_LD, RubyAccessMode(0),
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requestor, indirection_miss);
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}
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void
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AddressProfiler::addTraceSample(Address data_addr, Address pc_addr,
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CacheRequestType type,
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AccessModeType access_mode, NodeID id,
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RubyAccessMode access_mode, NodeID id,
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bool sharing_miss)
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{
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if (m_all_instructions) {
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@ -55,7 +55,7 @@ class AddressProfiler
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void clearStats();
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void addTraceSample(Address data_addr, Address pc_addr,
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CacheRequestType type, AccessModeType access_mode,
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CacheRequestType type, RubyAccessMode access_mode,
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NodeID id, bool sharing_miss);
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void profileRetry(const Address& data_addr, AccessType type, int count);
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void profileGetX(const Address& datablock, const Address& PC,
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@ -94,10 +94,10 @@ CacheProfiler::printStats(ostream& out) const
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out << endl;
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for (int i = 0; i < AccessModeType_NUM; i++){
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for (int i = 0; i < RubyAccessMode_NUM; i++){
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if (m_accessModeTypeHistogram[i] > 0) {
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out << description << "_access_mode_type_"
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<< (AccessModeType) i << ": "
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<< (RubyAccessMode) i << ": "
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<< m_accessModeTypeHistogram[i] << " "
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<< 100.0 * m_accessModeTypeHistogram[i] / requests
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<< "%" << endl;
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@ -122,14 +122,14 @@ CacheProfiler::clearStats()
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m_prefetches = 0;
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m_sw_prefetches = 0;
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m_hw_prefetches = 0;
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for (int i = 0; i < AccessModeType_NUM; i++) {
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for (int i = 0; i < RubyAccessMode_NUM; i++) {
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m_accessModeTypeHistogram[i] = 0;
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}
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}
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void
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CacheProfiler::addCacheStatSample(CacheRequestType requestType,
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AccessModeType accessType,
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RubyAccessMode accessType,
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PrefetchBit pfBit)
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{
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m_cacheRequestType[requestType]++;
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@ -138,7 +138,7 @@ CacheProfiler::addCacheStatSample(CacheRequestType requestType,
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void
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CacheProfiler::addGenericStatSample(GenericRequestType requestType,
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AccessModeType accessType,
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RubyAccessMode accessType,
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PrefetchBit pfBit)
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{
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m_genericRequestType[requestType]++;
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@ -146,7 +146,7 @@ CacheProfiler::addGenericStatSample(GenericRequestType requestType,
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}
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void
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CacheProfiler::addStatSample(AccessModeType accessType,
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CacheProfiler::addStatSample(RubyAccessMode accessType,
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PrefetchBit pfBit)
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{
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m_misses++;
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@ -33,7 +33,7 @@
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#include <string>
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#include <vector>
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#include "mem/protocol/AccessModeType.hh"
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#include "mem/protocol/RubyAccessMode.hh"
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#include "mem/protocol/CacheRequestType.hh"
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#include "mem/protocol/GenericRequestType.hh"
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#include "mem/protocol/PrefetchBit.hh"
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@ -51,11 +51,11 @@ class CacheProfiler
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void clearStats();
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void addCacheStatSample(CacheRequestType requestType,
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AccessModeType type,
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RubyAccessMode type,
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PrefetchBit pfBit);
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void addGenericStatSample(GenericRequestType requestType,
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AccessModeType type,
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RubyAccessMode type,
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PrefetchBit pfBit);
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void print(std::ostream& out) const;
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@ -64,7 +64,7 @@ class CacheProfiler
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// Private copy constructor and assignment operator
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CacheProfiler(const CacheProfiler& obj);
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CacheProfiler& operator=(const CacheProfiler& obj);
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void addStatSample(AccessModeType type, PrefetchBit pfBit);
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void addStatSample(RubyAccessMode type, PrefetchBit pfBit);
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std::string m_description;
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int64 m_misses;
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@ -72,7 +72,7 @@ class CacheProfiler
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int64 m_prefetches;
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int64 m_sw_prefetches;
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int64 m_hw_prefetches;
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int64 m_accessModeTypeHistogram[AccessModeType_NUM];
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int64 m_accessModeTypeHistogram[RubyAccessMode_NUM];
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std::vector<int> m_cacheRequestType;
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std::vector<int> m_genericRequestType;
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#include <vector>
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#include "base/hashmap.hh"
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#include "mem/protocol/AccessModeType.hh"
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#include "mem/protocol/RubyAccessMode.hh"
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#include "mem/protocol/AccessType.hh"
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#include "mem/protocol/CacheRequestType.hh"
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#include "mem/protocol/GenericMachineType.hh"
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@ -32,7 +32,7 @@
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#include <ostream>
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#include "mem/packet.hh"
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#include "mem/protocol/AccessModeType.hh"
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#include "mem/protocol/RubyAccessMode.hh"
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#include "mem/protocol/CacheRequestType.hh"
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#include "mem/protocol/Message.hh"
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#include "mem/protocol/PrefetchBit.hh"
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@ -53,12 +53,6 @@ enum RubyRequestType {
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RubyRequestType_NUM
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};
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enum RubyAccessMode {
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RubyAccessMode_User,
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RubyAccessMode_Supervisor,
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RubyAccessMode_Device
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};
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class RubyRequest
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{
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public:
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@ -353,7 +353,7 @@ CacheMemory::profileMiss(const CacheMsg& msg)
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void
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CacheMemory::profileGenericRequest(GenericRequestType requestType,
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AccessModeType accessType,
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RubyAccessMode accessType,
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PrefetchBit pfBit)
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{
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m_profiler_ptr->addGenericStatSample(requestType,
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@ -110,7 +110,7 @@ class CacheMemory : public SimObject
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void profileMiss(const CacheMsg & msg);
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void profileGenericRequest(GenericRequestType requestType,
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AccessModeType accessType,
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RubyAccessMode accessType,
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PrefetchBit pfBit);
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void getMemoryValue(const Address& addr, char* value,
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@ -644,16 +644,16 @@ Sequencer::issueRequest(const RubyRequest& request)
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assert(0);
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}
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AccessModeType amtype;
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RubyAccessMode amtype;
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switch(request.access_mode){
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case RubyAccessMode_User:
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amtype = AccessModeType_UserMode;
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amtype = RubyAccessMode_User;
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break;
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case RubyAccessMode_Supervisor:
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amtype = AccessModeType_SupervisorMode;
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amtype = RubyAccessMode_Supervisor;
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break;
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case RubyAccessMode_Device:
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amtype = AccessModeType_UserMode;
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amtype = RubyAccessMode_User;
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break;
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default:
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assert(0);
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@ -686,7 +686,7 @@ Sequencer::issueRequest(const RubyRequest& request)
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#if 0
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bool
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Sequencer::tryCacheAccess(const Address& addr, CacheRequestType type,
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AccessModeType access_mode,
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RubyAccessMode access_mode,
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int size, DataBlock*& data_ptr)
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{
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CacheMemory *cache =
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@ -32,7 +32,7 @@
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#include <iostream>
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#include "base/hashmap.hh"
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#include "mem/protocol/AccessModeType.hh"
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#include "mem/protocol/RubyAccessMode.hh"
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#include "mem/protocol/CacheRequestType.hh"
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#include "mem/protocol/GenericMachineType.hh"
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#include "mem/protocol/PrefetchBit.hh"
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@ -113,7 +113,7 @@ class Sequencer : public RubyPort, public Consumer
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private:
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bool tryCacheAccess(const Address& addr, CacheRequestType type,
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const Address& pc, AccessModeType access_mode,
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const Address& pc, RubyAccessMode access_mode,
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int size, DataBlock*& data_ptr);
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void issueRequest(const RubyRequest& request);
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