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Ruby: Convert AccessModeType to RubyAccessMode

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This patch converts AccessModeType to RubyAccessMode so that both the
protocol dependent and independent code uses the same access mode.
This commit is contained in:
Nilay Vaish 2011-03-19 18:34:37 -05:00
parent dd9083115e
commit 2f4276448b
21 changed files with 50 additions and 55 deletions
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2
src/cpu/testers/rubytest/Check.cc
View file

@ -44,7 +44,7 @@ Check::Check(const Address& address, const Address& pc,
pickInitiatingNode(); pickInitiatingNode();
changeAddress(address); changeAddress(address);
m_pc = pc; m_pc = pc;
m_access_mode = AccessModeType(random() % AccessModeType_NUM); m_access_mode = RubyAccessMode(random() % RubyAccessMode_NUM);
m_store_count = 0; m_store_count = 0;
} }

4
src/cpu/testers/rubytest/Check.hh
View file

@ -33,7 +33,7 @@
#include <iostream> #include <iostream>
#include "cpu/testers/rubytest/RubyTester.hh" #include "cpu/testers/rubytest/RubyTester.hh"
#include "mem/protocol/AccessModeType.hh" #include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/TesterStatus.hh" #include "mem/protocol/TesterStatus.hh"
#include "mem/ruby/common/Address.hh" #include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Global.hh" #include "mem/ruby/common/Global.hh"
@ -73,7 +73,7 @@ class Check
NodeID m_initiatingNode; NodeID m_initiatingNode;
Address m_address; Address m_address;
Address m_pc; Address m_pc;
AccessModeType m_access_mode; RubyAccessMode m_access_mode;
int m_num_cpu_sequencers; int m_num_cpu_sequencers;
RubyTester* m_tester_ptr; RubyTester* m_tester_ptr;
}; };

2
src/mem/protocol/MESI_CMP_directory-msg.sm
View file

@ -62,7 +62,7 @@ enumeration(CoherenceResponseType, desc="...") {
structure(RequestMsg, desc="...", interface="NetworkMessage") { structure(RequestMsg, desc="...", interface="NetworkMessage") {
Address Address, desc="Physical address for this request"; Address Address, desc="Physical address for this request";
CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)"; CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
AccessModeType AccessMode, desc="user/supervisor access type"; RubyAccessMode AccessMode, desc="user/supervisor access type";
MachineID Requestor , desc="What component request"; MachineID Requestor , desc="What component request";
NetDest Destination, desc="What components receive the request, includes MachineType and num"; NetDest Destination, desc="What components receive the request, includes MachineType and num";
MessageSizeType MessageSize, desc="size category of the message"; MessageSizeType MessageSize, desc="size category of the message";

2
src/mem/protocol/MOESI_CMP_directory-msg.sm
View file

@ -84,7 +84,7 @@ structure(RequestMsg, desc="...", interface="NetworkMessage") {
DataBlock DataBlk, desc="data for the cache line (DMA WRITE request)"; DataBlock DataBlk, desc="data for the cache line (DMA WRITE request)";
int Acks, desc="How many acks to expect"; int Acks, desc="How many acks to expect";
MessageSizeType MessageSize, desc="size category of the message"; MessageSizeType MessageSize, desc="size category of the message";
AccessModeType AccessMode, desc="user/supervisor access type"; RubyAccessMode AccessMode, desc="user/supervisor access type";
PrefetchBit Prefetch, desc="Is this a prefetch request"; PrefetchBit Prefetch, desc="Is this a prefetch request";
} }

2
src/mem/protocol/MOESI_CMP_token-L1cache.sm
View file

@ -149,7 +149,7 @@ machine(L1Cache, "Token protocol")
AccessType AccessType, desc="Type of request (used for profiling)"; AccessType AccessType, desc="Type of request (used for profiling)";
Time IssueTime, desc="Time the request was issued"; Time IssueTime, desc="Time the request was issued";
AccessModeType AccessMode, desc="user/supervisor access type"; RubyAccessMode AccessMode, desc="user/supervisor access type";
PrefetchBit Prefetch, desc="Is this a prefetch request"; PrefetchBit Prefetch, desc="Is this a prefetch request";
} }

8
src/mem/protocol/MOESI_CMP_token-dir.sm
View file

@ -424,7 +424,7 @@ machine(Directory, "Token protocol")
out_msg.Destination.add(map_Address_to_Directory(address)); out_msg.Destination.add(map_Address_to_Directory(address));
out_msg.MessageSize := MessageSizeType:Persistent_Control; out_msg.MessageSize := MessageSizeType:Persistent_Control;
out_msg.Prefetch := PrefetchBit:No; out_msg.Prefetch := PrefetchBit:No;
out_msg.AccessMode := AccessModeType:SupervisorMode; out_msg.AccessMode := RubyAccessMode:Supervisor;
} }
markPersistentEntries(address); markPersistentEntries(address);
starving := true; starving := true;
@ -466,7 +466,7 @@ machine(Directory, "Token protocol")
out_msg.RetryNum := 0; out_msg.RetryNum := 0;
out_msg.MessageSize := MessageSizeType:Broadcast_Control; out_msg.MessageSize := MessageSizeType:Broadcast_Control;
out_msg.Prefetch := PrefetchBit:No; out_msg.Prefetch := PrefetchBit:No;
out_msg.AccessMode := AccessModeType:SupervisorMode; out_msg.AccessMode := RubyAccessMode:Supervisor;
} }
} }
} }
@ -494,7 +494,7 @@ machine(Directory, "Token protocol")
out_msg.Destination.add(map_Address_to_Directory(address)); out_msg.Destination.add(map_Address_to_Directory(address));
out_msg.MessageSize := MessageSizeType:Persistent_Control; out_msg.MessageSize := MessageSizeType:Persistent_Control;
out_msg.Prefetch := PrefetchBit:No; out_msg.Prefetch := PrefetchBit:No;
out_msg.AccessMode := AccessModeType:SupervisorMode; out_msg.AccessMode := RubyAccessMode:Supervisor;
} }
markPersistentEntries(address); markPersistentEntries(address);
starving := true; starving := true;
@ -532,7 +532,7 @@ machine(Directory, "Token protocol")
out_msg.RetryNum := 0; out_msg.RetryNum := 0;
out_msg.MessageSize := MessageSizeType:Broadcast_Control; out_msg.MessageSize := MessageSizeType:Broadcast_Control;
out_msg.Prefetch := PrefetchBit:No; out_msg.Prefetch := PrefetchBit:No;
out_msg.AccessMode := AccessModeType:SupervisorMode; out_msg.AccessMode := RubyAccessMode:Supervisor;
} }
} }
} }

4
src/mem/protocol/MOESI_CMP_token-msg.sm
View file

@ -78,7 +78,7 @@ structure(PersistentMsg, desc="...", interface="NetworkMessage") {
MachineID Requestor, desc="Node who initiated the request"; MachineID Requestor, desc="Node who initiated the request";
NetDest Destination, desc="Destination set"; NetDest Destination, desc="Destination set";
MessageSizeType MessageSize, desc="size category of the message"; MessageSizeType MessageSize, desc="size category of the message";
AccessModeType AccessMode, desc="user/supervisor access type"; RubyAccessMode AccessMode, desc="user/supervisor access type";
PrefetchBit Prefetch, desc="Is this a prefetch request"; PrefetchBit Prefetch, desc="Is this a prefetch request";
} }
@ -91,7 +91,7 @@ structure(RequestMsg, desc="...", interface="NetworkMessage") {
bool isLocal, desc="Is this request from a local L1"; bool isLocal, desc="Is this request from a local L1";
int RetryNum, desc="retry sequence number"; int RetryNum, desc="retry sequence number";
MessageSizeType MessageSize, desc="size category of the message"; MessageSizeType MessageSize, desc="size category of the message";
AccessModeType AccessMode, desc="user/supervisor access type"; RubyAccessMode AccessMode, desc="user/supervisor access type";
PrefetchBit Prefetch, desc="Is this a prefetch request"; PrefetchBit Prefetch, desc="Is this a prefetch request";
} }

13
src/mem/protocol/RubySlicc_Exports.sm
View file

@ -193,10 +193,11 @@ enumeration(AccessType, desc="...") {
Write, desc="Writing to cache"; Write, desc="Writing to cache";
} }
// AccessModeType // RubyAccessMode
enumeration(AccessModeType, default="AccessModeType_UserMode", desc="...") { enumeration(RubyAccessMode, default="RubyAccessMode_User", desc="...") {
SupervisorMode, desc="Supervisor mode"; Supervisor, desc="Supervisor mode";
UserMode, desc="User mode"; User, desc="User mode";
Device, desc="Device mode";
} }
enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") { enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") {
@ -212,7 +213,7 @@ structure(CacheMsg, desc="...", interface="Message") {
Address PhysicalAddress, desc="Physical address for this request"; Address PhysicalAddress, desc="Physical address for this request";
CacheRequestType Type, desc="Type of request (LD, ST, etc)"; CacheRequestType Type, desc="Type of request (LD, ST, etc)";
Address ProgramCounter, desc="Program counter of the instruction that caused the miss"; Address ProgramCounter, desc="Program counter of the instruction that caused the miss";
AccessModeType AccessMode, desc="user/supervisor access type"; RubyAccessMode AccessMode, desc="user/supervisor access type";
int Size, desc="size in bytes of access"; int Size, desc="size in bytes of access";
PrefetchBit Prefetch, desc="Is this a prefetch request"; PrefetchBit Prefetch, desc="Is this a prefetch request";
} }
@ -223,7 +224,7 @@ structure(SequencerMsg, desc="...", interface="Message") {
Address PhysicalAddress, desc="Physical address for this request"; Address PhysicalAddress, desc="Physical address for this request";
SequencerRequestType Type, desc="Type of request (LD, ST, etc)"; SequencerRequestType Type, desc="Type of request (LD, ST, etc)";
Address ProgramCounter, desc="Program counter of the instruction that caused the miss"; Address ProgramCounter, desc="Program counter of the instruction that caused the miss";
AccessModeType AccessMode, desc="user/supervisor access type"; RubyAccessMode AccessMode, desc="user/supervisor access type";
DataBlock DataBlk, desc="Data"; DataBlock DataBlk, desc="Data";
int Len, desc="size in bytes of access"; int Len, desc="size in bytes of access";
PrefetchBit Prefetch, desc="Is this a prefetch request"; PrefetchBit Prefetch, desc="Is this a prefetch request";

2
src/mem/protocol/RubySlicc_Types.sm
View file

@ -129,7 +129,7 @@ structure (CacheMemory, external = "yes") {
void profileMiss(CacheMsg); void profileMiss(CacheMsg);
void profileGenericRequest(GenericRequestType, void profileGenericRequest(GenericRequestType,
AccessModeType, RubyAccessMode,
PrefetchBit); PrefetchBit);
void setMRU(Address); void setMRU(Address);

4
src/mem/ruby/profiler/AccessTraceForAddress.cc
View file

@ -59,7 +59,7 @@ AccessTraceForAddress::print(std::ostream& out) const
void void
AccessTraceForAddress::update(CacheRequestType type, AccessTraceForAddress::update(CacheRequestType type,
AccessModeType access_mode, NodeID cpu, RubyAccessMode access_mode, NodeID cpu,
bool sharing_miss) bool sharing_miss)
{ {
m_touched_by.add(cpu); m_touched_by.add(cpu);
@ -74,7 +74,7 @@ AccessTraceForAddress::update(CacheRequestType type,
// ERROR_MSG("Trying to add invalid access to trace"); // ERROR_MSG("Trying to add invalid access to trace");
} }
if (access_mode == AccessModeType_UserMode) { if (access_mode == RubyAccessMode_User) {
m_user++; m_user++;
} }

4
src/mem/ruby/profiler/AccessTraceForAddress.hh
View file

@ -31,7 +31,7 @@
#include <iostream> #include <iostream>
#include "mem/protocol/AccessModeType.hh" #include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/CacheRequestType.hh" #include "mem/protocol/CacheRequestType.hh"
#include "mem/ruby/common/Address.hh" #include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Global.hh" #include "mem/ruby/common/Global.hh"
@ -50,7 +50,7 @@ class AccessTraceForAddress
~AccessTraceForAddress(); ~AccessTraceForAddress();
void setAddress(const Address& addr) { m_addr = addr; } void setAddress(const Address& addr) { m_addr = addr; }
void update(CacheRequestType type, AccessModeType access_mode, NodeID cpu, void update(CacheRequestType type, RubyAccessMode access_mode, NodeID cpu,
bool sharing_miss); bool sharing_miss);
int getTotal() const; int getTotal() const;
int getSharing() const { return m_sharing; } int getSharing() const { return m_sharing; }

6
src/mem/ruby/profiler/AddressProfiler.cc
View file

@ -257,7 +257,7 @@ AddressProfiler::profileGetX(const Address& datablock, const Address& PC,
m_getx_sharing_histogram.add(num_indirections); m_getx_sharing_histogram.add(num_indirections);
bool indirection_miss = (num_indirections > 0); bool indirection_miss = (num_indirections > 0);
addTraceSample(datablock, PC, CacheRequestType_ST, AccessModeType(0), addTraceSample(datablock, PC, CacheRequestType_ST, RubyAccessMode(0),
requestor, indirection_miss); requestor, indirection_miss);
} }
@ -274,14 +274,14 @@ AddressProfiler::profileGetS(const Address& datablock, const Address& PC,
m_gets_sharing_histogram.add(num_indirections); m_gets_sharing_histogram.add(num_indirections);
bool indirection_miss = (num_indirections > 0); bool indirection_miss = (num_indirections > 0);
addTraceSample(datablock, PC, CacheRequestType_LD, AccessModeType(0), addTraceSample(datablock, PC, CacheRequestType_LD, RubyAccessMode(0),
requestor, indirection_miss); requestor, indirection_miss);
} }
void void
AddressProfiler::addTraceSample(Address data_addr, Address pc_addr, AddressProfiler::addTraceSample(Address data_addr, Address pc_addr,
CacheRequestType type, CacheRequestType type,
AccessModeType access_mode, NodeID id, RubyAccessMode access_mode, NodeID id,
bool sharing_miss) bool sharing_miss)
{ {
if (m_all_instructions) { if (m_all_instructions) {

2
src/mem/ruby/profiler/AddressProfiler.hh
View file

@ -55,7 +55,7 @@ class AddressProfiler
void clearStats(); void clearStats();
void addTraceSample(Address data_addr, Address pc_addr, void addTraceSample(Address data_addr, Address pc_addr,
CacheRequestType type, AccessModeType access_mode, CacheRequestType type, RubyAccessMode access_mode,
NodeID id, bool sharing_miss); NodeID id, bool sharing_miss);
void profileRetry(const Address& data_addr, AccessType type, int count); void profileRetry(const Address& data_addr, AccessType type, int count);
void profileGetX(const Address& datablock, const Address& PC, void profileGetX(const Address& datablock, const Address& PC,

12
src/mem/ruby/profiler/CacheProfiler.cc
View file

@ -94,10 +94,10 @@ CacheProfiler::printStats(ostream& out) const
out << endl; out << endl;
for (int i = 0; i < AccessModeType_NUM; i++){ for (int i = 0; i < RubyAccessMode_NUM; i++){
if (m_accessModeTypeHistogram[i] > 0) { if (m_accessModeTypeHistogram[i] > 0) {
out << description << "_access_mode_type_" out << description << "_access_mode_type_"
<< (AccessModeType) i << ": " << (RubyAccessMode) i << ": "
<< m_accessModeTypeHistogram[i] << " " << m_accessModeTypeHistogram[i] << " "
<< 100.0 * m_accessModeTypeHistogram[i] / requests << 100.0 * m_accessModeTypeHistogram[i] / requests
<< "%" << endl; << "%" << endl;
@ -122,14 +122,14 @@ CacheProfiler::clearStats()
m_prefetches = 0; m_prefetches = 0;
m_sw_prefetches = 0; m_sw_prefetches = 0;
m_hw_prefetches = 0; m_hw_prefetches = 0;
for (int i = 0; i < AccessModeType_NUM; i++) { for (int i = 0; i < RubyAccessMode_NUM; i++) {
m_accessModeTypeHistogram[i] = 0; m_accessModeTypeHistogram[i] = 0;
} }
} }
void void
CacheProfiler::addCacheStatSample(CacheRequestType requestType, CacheProfiler::addCacheStatSample(CacheRequestType requestType,
AccessModeType accessType, RubyAccessMode accessType,
PrefetchBit pfBit) PrefetchBit pfBit)
{ {
m_cacheRequestType[requestType]++; m_cacheRequestType[requestType]++;
@ -138,7 +138,7 @@ CacheProfiler::addCacheStatSample(CacheRequestType requestType,
void void
CacheProfiler::addGenericStatSample(GenericRequestType requestType, CacheProfiler::addGenericStatSample(GenericRequestType requestType,
AccessModeType accessType, RubyAccessMode accessType,
PrefetchBit pfBit) PrefetchBit pfBit)
{ {
m_genericRequestType[requestType]++; m_genericRequestType[requestType]++;
@ -146,7 +146,7 @@ CacheProfiler::addGenericStatSample(GenericRequestType requestType,
} }
void void
CacheProfiler::addStatSample(AccessModeType accessType, CacheProfiler::addStatSample(RubyAccessMode accessType,
PrefetchBit pfBit) PrefetchBit pfBit)
{ {
m_misses++; m_misses++;

10
src/mem/ruby/profiler/CacheProfiler.hh
View file

@ -33,7 +33,7 @@
#include <string> #include <string>
#include <vector> #include <vector>
#include "mem/protocol/AccessModeType.hh" #include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/CacheRequestType.hh" #include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/GenericRequestType.hh" #include "mem/protocol/GenericRequestType.hh"
#include "mem/protocol/PrefetchBit.hh" #include "mem/protocol/PrefetchBit.hh"
@ -51,11 +51,11 @@ class CacheProfiler
void clearStats(); void clearStats();
void addCacheStatSample(CacheRequestType requestType, void addCacheStatSample(CacheRequestType requestType,
AccessModeType type, RubyAccessMode type,
PrefetchBit pfBit); PrefetchBit pfBit);
void addGenericStatSample(GenericRequestType requestType, void addGenericStatSample(GenericRequestType requestType,
AccessModeType type, RubyAccessMode type,
PrefetchBit pfBit); PrefetchBit pfBit);
void print(std::ostream& out) const; void print(std::ostream& out) const;
@ -64,7 +64,7 @@ class CacheProfiler
// Private copy constructor and assignment operator // Private copy constructor and assignment operator
CacheProfiler(const CacheProfiler& obj); CacheProfiler(const CacheProfiler& obj);
CacheProfiler& operator=(const CacheProfiler& obj); CacheProfiler& operator=(const CacheProfiler& obj);
void addStatSample(AccessModeType type, PrefetchBit pfBit); void addStatSample(RubyAccessMode type, PrefetchBit pfBit);
std::string m_description; std::string m_description;
int64 m_misses; int64 m_misses;
@ -72,7 +72,7 @@ class CacheProfiler
int64 m_prefetches; int64 m_prefetches;
int64 m_sw_prefetches; int64 m_sw_prefetches;
int64 m_hw_prefetches; int64 m_hw_prefetches;
int64 m_accessModeTypeHistogram[AccessModeType_NUM]; int64 m_accessModeTypeHistogram[RubyAccessMode_NUM];
std::vector<int> m_cacheRequestType; std::vector<int> m_cacheRequestType;
std::vector<int> m_genericRequestType; std::vector<int> m_genericRequestType;

2
src/mem/ruby/profiler/Profiler.hh
View file

@ -51,7 +51,7 @@
#include <vector> #include <vector>
#include "base/hashmap.hh" #include "base/hashmap.hh"
#include "mem/protocol/AccessModeType.hh" #include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/AccessType.hh" #include "mem/protocol/AccessType.hh"
#include "mem/protocol/CacheRequestType.hh" #include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/GenericMachineType.hh" #include "mem/protocol/GenericMachineType.hh"

8
src/mem/ruby/slicc_interface/RubyRequest.hh
View file

@ -32,7 +32,7 @@
#include <ostream> #include <ostream>
#include "mem/packet.hh" #include "mem/packet.hh"
#include "mem/protocol/AccessModeType.hh" #include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/CacheRequestType.hh" #include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/Message.hh" #include "mem/protocol/Message.hh"
#include "mem/protocol/PrefetchBit.hh" #include "mem/protocol/PrefetchBit.hh"
@ -53,12 +53,6 @@ enum RubyRequestType {
RubyRequestType_NUM RubyRequestType_NUM
}; };
enum RubyAccessMode {
RubyAccessMode_User,
RubyAccessMode_Supervisor,
RubyAccessMode_Device
};
class RubyRequest class RubyRequest
{ {
public: public:

2
src/mem/ruby/system/CacheMemory.cc
View file

@ -353,7 +353,7 @@ CacheMemory::profileMiss(const CacheMsg& msg)
void void
CacheMemory::profileGenericRequest(GenericRequestType requestType, CacheMemory::profileGenericRequest(GenericRequestType requestType,
AccessModeType accessType, RubyAccessMode accessType,
PrefetchBit pfBit) PrefetchBit pfBit)
{ {
m_profiler_ptr->addGenericStatSample(requestType, m_profiler_ptr->addGenericStatSample(requestType,

2
src/mem/ruby/system/CacheMemory.hh
View file

@ -110,7 +110,7 @@ class CacheMemory : public SimObject
void profileMiss(const CacheMsg & msg); void profileMiss(const CacheMsg & msg);
void profileGenericRequest(GenericRequestType requestType, void profileGenericRequest(GenericRequestType requestType,
AccessModeType accessType, RubyAccessMode accessType,
PrefetchBit pfBit); PrefetchBit pfBit);
void getMemoryValue(const Address& addr, char* value, void getMemoryValue(const Address& addr, char* value,

10
src/mem/ruby/system/Sequencer.cc
View file

@ -644,16 +644,16 @@ Sequencer::issueRequest(const RubyRequest& request)
assert(0); assert(0);
} }
AccessModeType amtype; RubyAccessMode amtype;
switch(request.access_mode){ switch(request.access_mode){
case RubyAccessMode_User: case RubyAccessMode_User:
amtype = AccessModeType_UserMode; amtype = RubyAccessMode_User;
break; break;
case RubyAccessMode_Supervisor: case RubyAccessMode_Supervisor:
amtype = AccessModeType_SupervisorMode; amtype = RubyAccessMode_Supervisor;
break; break;
case RubyAccessMode_Device: case RubyAccessMode_Device:
amtype = AccessModeType_UserMode; amtype = RubyAccessMode_User;
break; break;
default: default:
assert(0); assert(0);
@ -686,7 +686,7 @@ Sequencer::issueRequest(const RubyRequest& request)
#if 0 #if 0
bool bool
Sequencer::tryCacheAccess(const Address& addr, CacheRequestType type, Sequencer::tryCacheAccess(const Address& addr, CacheRequestType type,
AccessModeType access_mode, RubyAccessMode access_mode,
int size, DataBlock*& data_ptr) int size, DataBlock*& data_ptr)
{ {
CacheMemory *cache = CacheMemory *cache =

4
src/mem/ruby/system/Sequencer.hh
View file

@ -32,7 +32,7 @@
#include <iostream> #include <iostream>
#include "base/hashmap.hh" #include "base/hashmap.hh"
#include "mem/protocol/AccessModeType.hh" #include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/CacheRequestType.hh" #include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/GenericMachineType.hh" #include "mem/protocol/GenericMachineType.hh"
#include "mem/protocol/PrefetchBit.hh" #include "mem/protocol/PrefetchBit.hh"
@ -113,7 +113,7 @@ class Sequencer : public RubyPort, public Consumer
private: private:
bool tryCacheAccess(const Address& addr, CacheRequestType type, bool tryCacheAccess(const Address& addr, CacheRequestType type,
const Address& pc, AccessModeType access_mode, const Address& pc, RubyAccessMode access_mode,
int size, DataBlock*& data_ptr); int size, DataBlock*& data_ptr);
void issueRequest(const RubyRequest& request); void issueRequest(const RubyRequest& request);