X86: Tell the function that sends int messages who to send to instead of figuring it out itself.
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88ab4bb257
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@ -510,11 +510,41 @@ X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
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bool timing = sys->getMemoryMode() == Enums::timing;
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// Be careful no updates of the delivery status bit get lost.
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regs[APIC_INTERRUPT_COMMAND_LOW] = low;
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ApicList apics;
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int numContexts = sys->numContexts();
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switch (low.destShorthand) {
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case 0:
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pendingIPIs++;
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intPort->sendMessage(message, timing);
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newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
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if (message.deliveryMode == DeliveryMode::LowestPriority) {
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panic("Lowest priority delivery mode "
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"IPIs aren't implemented.\n");
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}
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if (message.destMode == 1) {
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int dest = message.destination;
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hack_once("Assuming logical destinations are 1 << id.\n");
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for (int i = 0; i < numContexts; i++) {
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if (dest & 0x1)
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apics.push_back(i);
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dest = dest >> 1;
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}
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} else {
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if (message.destination == 0xFF) {
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for (int i = 0; i < numContexts; i++) {
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if (i == initialApicId) {
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requestInterrupt(message.vector,
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message.deliveryMode, message.trigger);
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} else {
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apics.push_back(i);
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}
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}
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} else {
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if (message.destination == initialApicId) {
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requestInterrupt(message.vector,
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message.deliveryMode, message.trigger);
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} else {
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apics.push_back(message.destination);
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}
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}
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}
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break;
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case 1:
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newVal = val;
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@ -527,22 +557,17 @@ X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
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// Fall through
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case 3:
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{
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int numContexts = sys->numContexts();
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pendingIPIs += (numContexts - 1);
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for (int i = 0; i < numContexts; i++) {
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int thisId = sys->getThreadContext(i)->contextId();
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if (thisId != initialApicId) {
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PacketPtr pkt = buildIntRequest(thisId, message);
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if (timing)
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intPort->sendMessageTiming(pkt, latency);
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else
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intPort->sendMessageAtomic(pkt);
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if (i != initialApicId) {
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apics.push_back(i);
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}
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}
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}
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newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
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break;
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}
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pendingIPIs += apics.size();
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intPort->sendMessage(apics, message, timing);
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newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
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}
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break;
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case APIC_LVT_TIMER:
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@ -28,6 +28,7 @@
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* Authors: Gabe Black
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*/
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#include "arch/x86/interrupts.hh"
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#include "arch/x86/intmessage.hh"
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#include "dev/x86/i82094aa.hh"
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#include "dev/x86/i8259.hh"
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@ -162,7 +163,38 @@ X86ISA::I82094AA::signalInterrupt(int line)
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message.destMode = entry.destMode;
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message.level = entry.polarity;
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message.trigger = entry.trigger;
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intPort->sendMessage(message, sys->getMemoryMode() == Enums::timing);
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ApicList apics;
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int numContexts = sys->numContexts();
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if (message.destMode == 0) {
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if (message.deliveryMode == DeliveryMode::LowestPriority) {
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panic("Lowest priority delivery mode from the "
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"IO APIC aren't supported in physical "
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"destination mode.\n");
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}
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if (message.destination == 0xFF) {
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for (int i = 0; i < numContexts; i++) {
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apics.push_back(i);
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}
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} else {
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apics.push_back(message.destination);
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}
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} else {
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for (int i = 0; i < numContexts; i++) {
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std::map<int, Interrupts *>::iterator localApicIt =
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localApics.find(i);
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assert(localApicIt != localApics.end());
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Interrupts *localApic = localApicIt->second;
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if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) &
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message.destination) {
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apics.push_back(localApicIt->first);
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}
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}
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if (message.deliveryMode == DeliveryMode::LowestPriority) {
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panic("Lowest priority delivery mode is not implemented.\n");
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}
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}
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intPort->sendMessage(apics, message,
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sys->getMemoryMode() == Enums::timing);
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}
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}
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@ -31,51 +31,17 @@
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#include "dev/x86/intdev.hh"
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void
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X86ISA::IntDev::IntPort::sendMessage(TriggerIntMessage message, bool timing)
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X86ISA::IntDev::IntPort::sendMessage(ApicList apics,
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TriggerIntMessage message, bool timing)
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{
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if (DeliveryMode::isReserved(message.deliveryMode)) {
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fatal("Tried to use reserved delivery mode %d\n",
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message.deliveryMode);
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} else if (DTRACE(IntDev)) {
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DPRINTF(IntDev, "Delivery mode is: %s.\n",
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DeliveryMode::names[message.deliveryMode]);
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DPRINTF(IntDev, "Vector is %#x.\n", message.vector);
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}
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if (message.destMode == 0) {
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DPRINTF(IntDev,
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"Sending interrupt to APIC ID %d.\n", message.destination);
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PacketPtr pkt = buildIntRequest(message.destination, message);
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if (timing) {
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sendMessageTiming(pkt, latency);
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} else {
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sendMessageAtomic(pkt);
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}
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} else {
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DPRINTF(IntDev, "Sending interrupts to APIC IDs:"
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"%s%s%s%s%s%s%s%s\n",
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bits((int)message.destination, 0) ? " 0": "",
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bits((int)message.destination, 1) ? " 1": "",
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bits((int)message.destination, 2) ? " 2": "",
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bits((int)message.destination, 3) ? " 3": "",
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bits((int)message.destination, 4) ? " 4": "",
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bits((int)message.destination, 5) ? " 5": "",
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bits((int)message.destination, 6) ? " 6": "",
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bits((int)message.destination, 7) ? " 7": ""
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);
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uint8_t dests = message.destination;
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uint8_t id = 0;
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while(dests) {
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if (dests & 0x1) {
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PacketPtr pkt = buildIntRequest(id, message);
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ApicList::iterator apicIt;
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for (apicIt = apics.begin(); apicIt != apics.end(); apicIt++) {
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PacketPtr pkt = buildIntRequest(*apicIt, message);
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if (timing)
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sendMessageTiming(pkt, latency);
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else
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sendMessageAtomic(pkt);
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}
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dests >>= 1;
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id++;
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}
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}
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}
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X86ISA::IntSourcePin *
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@ -43,8 +43,12 @@
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#include "params/X86IntSinkPin.hh"
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#include "params/X86IntLine.hh"
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#include <list>
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namespace X86ISA {
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typedef std::list<int> ApicList;
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class IntDev
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{
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protected:
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@ -78,7 +82,8 @@ class IntDev
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// This is x86 focused, so if this class becomes generic, this would
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// need to be moved into a subclass.
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void sendMessage(TriggerIntMessage message, bool timing);
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void sendMessage(ApicList apics,
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TriggerIntMessage message, bool timing);
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void recvStatusChange(Status status)
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{
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