X86: Mark IO reads and writes as non-speculative.
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72d35701e9
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2e4fb3f139
3 changed files with 37 additions and 21 deletions
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@ -42,22 +42,26 @@ microcode = '''
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def macroop IN_R_I {
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def macroop IN_R_I {
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.adjust_imm trimImm(8)
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.adjust_imm trimImm(8)
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limm t1, imm, dataSize=asz
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limm t1, imm, dataSize=asz
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ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8
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ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \
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nonSpec=True
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};
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};
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def macroop IN_R_R {
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def macroop IN_R_R {
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zexti t2, regm, 15, dataSize=8
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zexti t2, regm, 15, dataSize=8
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ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
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ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
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nonSpec=True
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};
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};
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def macroop OUT_I_R {
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def macroop OUT_I_R {
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.adjust_imm trimImm(8)
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.adjust_imm trimImm(8)
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limm t1, imm, dataSize=8
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limm t1, imm, dataSize=8
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st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8
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st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \
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nonSpec=True
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};
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};
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def macroop OUT_R_R {
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def macroop OUT_R_R {
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zexti t2, reg, 15, dataSize=8
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zexti t2, reg, 15, dataSize=8
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st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
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st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
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nonSpec=True
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};
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};
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'''
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'''
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@ -45,7 +45,8 @@ def macroop INS_M_R {
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zexti t2, reg, 15, dataSize=8
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zexti t2, reg, 15, dataSize=8
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ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
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ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
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nonSpec=True
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st t6, es, [1, t0, rdi]
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st t6, es, [1, t0, rdi]
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add rdi, rdi, t3, dataSize=asz
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add rdi, rdi, t3, dataSize=asz
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@ -63,7 +64,8 @@ def macroop INS_E_M_R {
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zexti t2, reg, 15, dataSize=8
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zexti t2, reg, 15, dataSize=8
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topOfLoop:
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topOfLoop:
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ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
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ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
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nonSpec=True
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st t6, es, [1, t0, rdi]
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st t6, es, [1, t0, rdi]
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subi rcx, rcx, 1, flags=(EZF,), dataSize=asz
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subi rcx, rcx, 1, flags=(EZF,), dataSize=asz
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@ -83,7 +85,8 @@ def macroop OUTS_R_M {
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zexti t2, reg, 15, dataSize=8
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zexti t2, reg, 15, dataSize=8
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ld t6, ds, [1, t0, rsi]
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ld t6, ds, [1, t0, rsi]
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st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
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st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
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nonSpec=True
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add rsi, rsi, t3, dataSize=asz
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add rsi, rsi, t3, dataSize=asz
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};
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};
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@ -101,7 +104,8 @@ def macroop OUTS_E_R_M {
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topOfLoop:
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topOfLoop:
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ld t6, ds, [1, t0, rsi]
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ld t6, ds, [1, t0, rsi]
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st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
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st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
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nonSpec=True
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subi rcx, rcx, 1, flags=(EZF,), dataSize=asz
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subi rcx, rcx, 1, flags=(EZF,), dataSize=asz
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add rsi, rsi, t3, dataSize=asz
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add rsi, rsi, t3, dataSize=asz
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@ -272,7 +272,7 @@ def template MicroLdStOpConstructor {{
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let {{
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let {{
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class LdStOp(X86Microop):
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class LdStOp(X86Microop):
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def __init__(self, data, segment, addr, disp,
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def __init__(self, data, segment, addr, disp,
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dataSize, addressSize, baseFlags, atCPL0, prefetch):
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dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec):
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self.data = data
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self.data = data
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[self.scale, self.index, self.base] = addr
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[self.scale, self.index, self.base] = addr
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self.disp = disp
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self.disp = disp
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@ -285,7 +285,9 @@ let {{
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self.instFlags = ""
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self.instFlags = ""
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if prefetch:
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if prefetch:
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self.memFlags += " | Request::PREFETCH"
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self.memFlags += " | Request::PREFETCH"
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self.instFlags += " | StaticInst::IsDataPrefetch"
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self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
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if nonSpec:
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self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
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self.memFlags += " | (machInst.legacy.addr ? " + \
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self.memFlags += " | (machInst.legacy.addr ? " + \
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"(AddrSizeFlagBit << FlagShift) : 0)"
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"(AddrSizeFlagBit << FlagShift) : 0)"
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@ -306,7 +308,7 @@ let {{
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class BigLdStOp(X86Microop):
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class BigLdStOp(X86Microop):
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def __init__(self, data, segment, addr, disp,
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def __init__(self, data, segment, addr, disp,
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dataSize, addressSize, baseFlags, atCPL0, prefetch):
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dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec):
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self.data = data
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self.data = data
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[self.scale, self.index, self.base] = addr
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[self.scale, self.index, self.base] = addr
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self.disp = disp
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self.disp = disp
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@ -316,8 +318,12 @@ let {{
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self.memFlags = baseFlags
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self.memFlags = baseFlags
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if atCPL0:
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if atCPL0:
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self.memFlags += " | (CPL0FlagBit << FlagShift)"
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self.memFlags += " | (CPL0FlagBit << FlagShift)"
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self.instFlags = ""
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if prefetch:
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if prefetch:
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self.memFlags += " | Request::PREFETCH"
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self.memFlags += " | Request::PREFETCH"
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self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
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if nonSpec:
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self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
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self.memFlags += " | (machInst.legacy.addr ? " + \
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self.memFlags += " | (machInst.legacy.addr ? " + \
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"(AddrSizeFlagBit << FlagShift) : 0)"
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"(AddrSizeFlagBit << FlagShift) : 0)"
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@ -335,7 +341,7 @@ let {{
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'''
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'''
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allocator = allocString % {
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allocator = allocString % {
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"class_name" : self.className,
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"class_name" : self.className,
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"flags" : self.microFlagsText(microFlags),
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"flags" : self.microFlagsText(microFlags) + self.instFlags,
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"scale" : self.scale, "index" : self.index,
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"scale" : self.scale, "index" : self.index,
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"base" : self.base,
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"base" : self.base,
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"disp" : self.disp,
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"disp" : self.disp,
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@ -386,10 +392,10 @@ let {{
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def __init__(self, data, segment, addr, disp = 0,
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def __init__(self, data, segment, addr, disp = 0,
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dataSize="env.dataSize",
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dataSize="env.dataSize",
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addressSize="env.addressSize",
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addressSize="env.addressSize",
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atCPL0=False, prefetch=False):
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atCPL0=False, prefetch=False, nonSpec=False):
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super(LoadOp, self).__init__(data, segment, addr,
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super(LoadOp, self).__init__(data, segment, addr,
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disp, dataSize, addressSize, mem_flags,
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disp, dataSize, addressSize, mem_flags,
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atCPL0, prefetch)
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atCPL0, prefetch, nonSpec)
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self.className = Name
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self.className = Name
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self.mnemonic = name
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self.mnemonic = name
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@ -430,9 +436,10 @@ let {{
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def __init__(self, data, segment, addr, disp = 0,
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def __init__(self, data, segment, addr, disp = 0,
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dataSize="env.dataSize",
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dataSize="env.dataSize",
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addressSize="env.addressSize",
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addressSize="env.addressSize",
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atCPL0=False):
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atCPL0=False, nonSpec=False):
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super(StoreOp, self).__init__(data, segment, addr,
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super(StoreOp, self).__init__(data, segment, addr, disp,
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disp, dataSize, addressSize, mem_flags, atCPL0, False)
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dataSize, addressSize, mem_flags, atCPL0, False,
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nonSpec)
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self.className = Name
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self.className = Name
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self.mnemonic = name
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self.mnemonic = name
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@ -456,8 +463,8 @@ let {{
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class LeaOp(LdStOp):
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class LeaOp(LdStOp):
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def __init__(self, data, segment, addr, disp = 0,
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def __init__(self, data, segment, addr, disp = 0,
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dataSize="env.dataSize", addressSize="env.addressSize"):
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dataSize="env.dataSize", addressSize="env.addressSize"):
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super(LeaOp, self).__init__(data, segment,
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super(LeaOp, self).__init__(data, segment, addr, disp,
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addr, disp, dataSize, addressSize, "0", False, False)
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dataSize, addressSize, "0", False, False, False)
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self.className = "Lea"
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self.className = "Lea"
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self.mnemonic = "lea"
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self.mnemonic = "lea"
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@ -476,7 +483,8 @@ let {{
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dataSize="env.dataSize",
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dataSize="env.dataSize",
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addressSize="env.addressSize"):
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addressSize="env.addressSize"):
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super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
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super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
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addr, disp, dataSize, addressSize, "0", False, False)
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addr, disp, dataSize, addressSize, "0", False, False,
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False)
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self.className = "Tia"
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self.className = "Tia"
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self.mnemonic = "tia"
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self.mnemonic = "tia"
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@ -488,7 +496,7 @@ let {{
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addressSize="env.addressSize", atCPL0=False):
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addressSize="env.addressSize", atCPL0=False):
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super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
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super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
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addr, disp, dataSize, addressSize, "Request::NO_ACCESS",
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addr, disp, dataSize, addressSize, "Request::NO_ACCESS",
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atCPL0, False)
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atCPL0, False, False)
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self.className = "Cda"
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self.className = "Cda"
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self.mnemonic = "cda"
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self.mnemonic = "cda"
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