ARM: Implement fault classes.
Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.
This commit is contained in:
Gabe Black
parent
4779020e13
commit
2e28da5583
9 changed files with 192 additions and 979 deletions
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@ -48,7 +48,7 @@ if env['TARGET_ISA'] == 'arm':
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SimObject('ArmTLB.py')
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SimObject('ArmTLB.py')
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TraceFlag('Arm')
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TraceFlag('Arm')
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TraceFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
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if env['FULL_SYSTEM']:
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if env['FULL_SYSTEM']:
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#Insert Full-System Files Here
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#Insert Full-System Files Here
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pass
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pass
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@ -26,488 +26,114 @@
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*
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* Authors: Gabe Black
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* Authors: Ali Saidi
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* Stephen Hines
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* Gabe Black
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*/
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*/
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#include "arch/arm/faults.hh"
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#include "arch/arm/faults.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/base.hh"
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#include "cpu/base.hh"
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#include "base/trace.hh"
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#include "base/trace.hh"
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#if !FULL_SYSTEM
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#include "sim/process.hh"
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#include "mem/page_table.hh"
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#endif
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namespace ArmISA
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namespace ArmISA
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{
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{
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FaultName MachineCheckFault::_name = "Machine Check";
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template<> ArmFaultBase::FaultVals ArmFault<Reset>::vals =
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FaultVect MachineCheckFault::_vect = 0x0401;
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{"reset", 0x00, MODE_SVC, 0, 0, true, true};
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FaultStat MachineCheckFault::_count;
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FaultName AlignmentFault::_name = "Alignment";
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template<> ArmFaultBase::FaultVals ArmFault<UndefinedInstruction>::vals =
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FaultVect AlignmentFault::_vect = 0x0301;
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{"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ;
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FaultStat AlignmentFault::_count;
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FaultName ResetFault::_name = "Reset Fault";
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template<> ArmFaultBase::FaultVals ArmFault<SupervisorCall>::vals =
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#if FULL_SYSTEM
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{"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false};
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FaultVect ResetFault::_vect = 0xBFC00000;
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#else
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FaultVect ResetFault::_vect = 0x001;
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#endif
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FaultStat ResetFault::_count;
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FaultName AddressErrorFault::_name = "Address Error";
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template<> ArmFaultBase::FaultVals ArmFault<PrefetchAbort>::vals =
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FaultVect AddressErrorFault::_vect = 0x0180;
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{"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false};
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FaultStat AddressErrorFault::_count;
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FaultName StoreAddressErrorFault::_name = "Store Address Error";
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template<> ArmFaultBase::FaultVals ArmFault<DataAbort>::vals =
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FaultVect StoreAddressErrorFault::_vect = 0x0180;
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{"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false};
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FaultStat StoreAddressErrorFault::_count;
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template<> ArmFaultBase::FaultVals ArmFault<Interrupt>::vals =
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{"IRQ", 0x18, MODE_IRQ, 4, 4, true, false};
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FaultName SystemCallFault::_name = "Syscall";
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template<> ArmFaultBase::FaultVals ArmFault<FastInterrupt>::vals =
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FaultVect SystemCallFault::_vect = 0x0180;
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{"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true};
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FaultStat SystemCallFault::_count;
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FaultName CoprocessorUnusableFault::_name = "Coprocessor Unusable Fault";
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Addr
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FaultVect CoprocessorUnusableFault::_vect = 0x180;
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ArmFaultBase::getVector(ThreadContext *tc)
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FaultStat CoprocessorUnusableFault::_count;
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{
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// ARM ARM B1-3
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FaultName ReservedInstructionFault::_name = "Reserved Instruction Fault";
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SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
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FaultVect ReservedInstructionFault::_vect = 0x0180;
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FaultStat ReservedInstructionFault::_count;
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// panic if SCTLR.VE because I have no idea what to do with vectored
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// interrupts
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assert(!sctlr.ve);
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if (!sctlr.v)
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return offset();
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return offset() + HighVecs;
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FaultName ThreadFault::_name = "Thread Fault";
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}
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FaultVect ThreadFault::_vect = 0x00F1;
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FaultStat ThreadFault::_count;
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FaultName ArithmeticFault::_name = "Arithmetic Overflow Exception";
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FaultVect ArithmeticFault::_vect = 0x180;
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FaultStat ArithmeticFault::_count;
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FaultName UnimplementedOpcodeFault::_name = "opdec";
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FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
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FaultStat UnimplementedOpcodeFault::_count;
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FaultName InterruptFault::_name = "interrupt";
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FaultVect InterruptFault::_vect = 0x0180;
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FaultStat InterruptFault::_count;
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FaultName TrapFault::_name = "Trap";
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FaultVect TrapFault::_vect = 0x0180;
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FaultStat TrapFault::_count;
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FaultName BreakpointFault::_name = "Breakpoint";
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FaultVect BreakpointFault::_vect = 0x0180;
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FaultStat BreakpointFault::_count;
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FaultName ItbInvalidFault::_name = "Invalid TLB Entry Exception (I-Fetch/LW)";
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FaultVect ItbInvalidFault::_vect = 0x0180;
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FaultStat ItbInvalidFault::_count;
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FaultName ItbPageFault::_name = "itbmiss";
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FaultVect ItbPageFault::_vect = 0x0181;
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FaultStat ItbPageFault::_count;
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FaultName ItbMissFault::_name = "itbmiss";
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FaultVect ItbMissFault::_vect = 0x0181;
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FaultStat ItbMissFault::_count;
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FaultName ItbAcvFault::_name = "iaccvio";
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FaultVect ItbAcvFault::_vect = 0x0081;
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FaultStat ItbAcvFault::_count;
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FaultName ItbRefillFault::_name = "TLB Refill Exception (I-Fetch/LW)";
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FaultVect ItbRefillFault::_vect = 0x0180;
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FaultStat ItbRefillFault::_count;
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FaultName NDtbMissFault::_name = "dtb_miss_single";
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FaultVect NDtbMissFault::_vect = 0x0201;
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FaultStat NDtbMissFault::_count;
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FaultName PDtbMissFault::_name = "dtb_miss_double";
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FaultVect PDtbMissFault::_vect = 0x0281;
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FaultStat PDtbMissFault::_count;
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FaultName DtbPageFault::_name = "dfault";
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FaultVect DtbPageFault::_vect = 0x0381;
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FaultStat DtbPageFault::_count;
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FaultName DtbAcvFault::_name = "dfault";
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FaultVect DtbAcvFault::_vect = 0x0381;
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FaultStat DtbAcvFault::_count;
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FaultName DtbInvalidFault::_name = "Invalid TLB Entry Exception (Store)";
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FaultVect DtbInvalidFault::_vect = 0x0180;
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FaultStat DtbInvalidFault::_count;
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FaultName DtbRefillFault::_name = "TLB Refill Exception (Store)";
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FaultVect DtbRefillFault::_vect = 0x0180;
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FaultStat DtbRefillFault::_count;
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FaultName TLBModifiedFault::_name = "TLB Modified Exception";
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FaultVect TLBModifiedFault::_vect = 0x0180;
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FaultStat TLBModifiedFault::_count;
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FaultName FloatEnableFault::_name = "float_enable_fault";
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FaultVect FloatEnableFault::_vect = 0x0581;
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FaultStat FloatEnableFault::_count;
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FaultName IntegerOverflowFault::_name = "Integer Overflow Fault";
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FaultVect IntegerOverflowFault::_vect = 0x0501;
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FaultStat IntegerOverflowFault::_count;
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FaultName DspStateDisabledFault::_name = "DSP Disabled Fault";
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FaultVect DspStateDisabledFault::_vect = 0x001a;
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FaultStat DspStateDisabledFault::_count;
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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void ArmFault::setHandlerPC(Addr HandlerBase, ThreadContext *tc)
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void
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ArmFaultBase::invoke(ThreadContext *tc)
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{
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{
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tc->setPC(HandlerBase);
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// ARM ARM B1.6.3
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tc->setNextPC(HandlerBase+sizeof(MachInst));
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FaultBase::invoke(tc);
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tc->setNextNPC(HandlerBase+2*sizeof(MachInst));
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countStat()++;
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SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
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CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
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CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) |
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tc->readIntReg(INTREG_CONDCODES);
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cpsr.mode = nextMode();
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cpsr.it1 = cpsr.it2 = 0;
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cpsr.j = 0;
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if (sctlr.te)
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cpsr.t = 1;
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cpsr.a = cpsr.a | abortDisable();
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cpsr.f = cpsr.f | fiqDisable();
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cpsr.i = 1;
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tc->setMiscReg(MISCREG_CPSR, cpsr);
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tc->setIntReg(INTREG_LR, tc->readPC() +
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(saved_cpsr.t ? thumbPcOffset() : armPcOffset()));
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switch (nextMode()) {
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case MODE_FIQ:
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tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
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break;
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case MODE_IRQ:
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tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
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break;
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case MODE_SVC:
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tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
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break;
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case MODE_UNDEFINED:
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tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
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break;
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case MODE_ABORT:
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tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
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break;
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default:
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panic("unknown Mode\n");
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}
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DPRINTF(Faults, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x\n", name(), cpsr,
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tc->readPC(), tc->readIntReg(INTREG_LR));
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tc->setPC(getVector(tc));
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tc->setNextPC(getVector(tc) + cpsr.t ? 2 : 4 );
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}
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}
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void ArmFault::setExceptionState(ThreadContext *tc,uint8_t ExcCode)
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{
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// modify SRS Ctl - Save CSS, put ESS into CSS
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MiscReg stat = tc->readMiscReg(ArmISA::Status);
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if(bits(stat,Status_EXL) != 1 && bits(stat,Status_BEV) != 1)
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{
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// SRS Ctl is modified only if Status_EXL and Status_BEV are not set
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MiscReg srs = tc->readMiscReg(ArmISA::SRSCtl);
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uint8_t CSS,ESS;
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CSS = bits(srs,SRSCtl_CSS_HI,SRSCtl_CSS_LO);
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ESS = bits(srs,SRSCtl_ESS_HI,SRSCtl_ESS_LO);
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// Move CSS to PSS
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replaceBits(srs,SRSCtl_PSS_HI,SRSCtl_PSS_LO,CSS);
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// Move ESS to CSS
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replaceBits(srs,SRSCtl_CSS_HI,SRSCtl_CSS_LO,ESS);
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tc->setMiscRegNoEffect(ArmISA::SRSCtl,srs);
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//tc->setShadowSet(ESS);
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}
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// set EXL bit (don't care if it is already set!)
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replaceBits(stat,Status_EXL_HI,Status_EXL_LO,1);
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tc->setMiscRegNoEffect(ArmISA::Status,stat);
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// write EPC
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// warn("Set EPC to %x\n",tc->readPC());
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// CHECK ME or FIXME or FIX ME or POSSIBLE HACK
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// Check to see if the exception occurred in the branch delay slot
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DPRINTF(Arm,"PC: %x, NextPC: %x, NNPC: %x\n",tc->readPC(),tc->readNextPC(),tc->readNextNPC());
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int C_BD=0;
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if(tc->readPC() + sizeof(MachInst) != tc->readNextPC()){
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tc->setMiscRegNoEffect(ArmISA::EPC,tc->readPC()-sizeof(MachInst));
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// In the branch delay slot? set CAUSE_31
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C_BD = 1;
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} else {
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tc->setMiscRegNoEffect(ArmISA::EPC,tc->readPC());
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// In the branch delay slot? reset CAUSE_31
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C_BD = 0;
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}
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// Set Cause_EXCCODE field
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MiscReg cause = tc->readMiscReg(ArmISA::Cause);
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replaceBits(cause,Cause_EXCCODE_HI,Cause_EXCCODE_LO,ExcCode);
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replaceBits(cause,Cause_BD_HI,Cause_BD_LO,C_BD);
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replaceBits(cause,Cause_CE_HI,Cause_CE_LO,0);
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tc->setMiscRegNoEffect(ArmISA::Cause,cause);
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}
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void ArithmeticFault::invoke(ThreadContext *tc)
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{
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DPRINTF(Arm,"%s encountered.\n", name());
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setExceptionState(tc,0xC);
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// Set new PC
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Addr HandlerBase;
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MiscReg stat = tc->readMiscReg(ArmISA::Status);
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// Here, the handler is dependent on BEV, which is not modified by setExceptionState()
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if(bits(stat,Status_BEV)==0){ // See MIPS ARM Vol 3, Revision 2, Page 38
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HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase);
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}else{
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HandlerBase = 0xBFC00200;
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}
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setHandlerPC(HandlerBase,tc);
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// warn("Exception Handler At: %x \n",HandlerBase);
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}
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void StoreAddressErrorFault::invoke(ThreadContext *tc)
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{
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DPRINTF(Arm,"%s encountered.\n", name());
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setExceptionState(tc,0x5);
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tc->setMiscRegNoEffect(ArmISA::BadVAddr,BadVAddr);
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// Set new PC
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Addr HandlerBase;
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HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
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setHandlerPC(HandlerBase,tc);
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// warn("Exception Handler At: %x \n",HandlerBase);
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// warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(ArmISA::EPC));
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}
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void TrapFault::invoke(ThreadContext *tc)
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{
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DPRINTF(Arm,"%s encountered.\n", name());
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// warn("%s encountered.\n", name());
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setExceptionState(tc,0xD);
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// Set new PC
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Addr HandlerBase;
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HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
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setHandlerPC(HandlerBase,tc);
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// warn("Exception Handler At: %x \n",HandlerBase);
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// warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(ArmISA::EPC));
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}
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void BreakpointFault::invoke(ThreadContext *tc)
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{
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setExceptionState(tc,0x9);
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// Set new PC
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Addr HandlerBase;
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HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
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setHandlerPC(HandlerBase,tc);
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// warn("Exception Handler At: %x \n",HandlerBase);
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|
||||||
// warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(ArmISA::EPC));
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
void DtbInvalidFault::invoke(ThreadContext *tc)
|
|
||||||
{
|
|
||||||
DPRINTF(Arm,"%s encountered.\n", name());
|
|
||||||
// warn("%s encountered.\n", name());
|
|
||||||
tc->setMiscRegNoEffect(ArmISA::BadVAddr,BadVAddr);
|
|
||||||
MiscReg eh = tc->readMiscReg(ArmISA::EntryHi);
|
|
||||||
replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
|
|
||||||
replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
|
|
||||||
replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
|
|
||||||
tc->setMiscRegNoEffect(ArmISA::EntryHi,eh);
|
|
||||||
MiscReg ctxt = tc->readMiscReg(ArmISA::Context);
|
|
||||||
replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
|
|
||||||
tc->setMiscRegNoEffect(ArmISA::Context,ctxt);
|
|
||||||
setExceptionState(tc,0x3);
|
|
||||||
|
|
||||||
|
|
||||||
// Set new PC
|
|
||||||
Addr HandlerBase;
|
|
||||||
HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
|
|
||||||
setHandlerPC(HandlerBase,tc);
|
|
||||||
// warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(ArmISA::EPC));
|
|
||||||
}
|
|
||||||
|
|
||||||
void AddressErrorFault::invoke(ThreadContext *tc)
|
|
||||||
{
|
|
||||||
DPRINTF(Arm,"%s encountered.\n", name());
|
|
||||||
setExceptionState(tc,0x4);
|
|
||||||
tc->setMiscRegNoEffect(ArmISA::BadVAddr,BadVAddr);
|
|
||||||
|
|
||||||
// Set new PC
|
|
||||||
Addr HandlerBase;
|
|
||||||
HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
|
|
||||||
setHandlerPC(HandlerBase,tc);
|
|
||||||
}
|
|
||||||
|
|
||||||
void ItbInvalidFault::invoke(ThreadContext *tc)
|
|
||||||
{
|
|
||||||
DPRINTF(Arm,"%s encountered.\n", name());
|
|
||||||
setExceptionState(tc,0x2);
|
|
||||||
tc->setMiscRegNoEffect(ArmISA::BadVAddr,BadVAddr);
|
|
||||||
MiscReg eh = tc->readMiscReg(ArmISA::EntryHi);
|
|
||||||
replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
|
|
||||||
replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
|
|
||||||
replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
|
|
||||||
tc->setMiscRegNoEffect(ArmISA::EntryHi,eh);
|
|
||||||
MiscReg ctxt = tc->readMiscReg(ArmISA::Context);
|
|
||||||
replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
|
|
||||||
tc->setMiscRegNoEffect(ArmISA::Context,ctxt);
|
|
||||||
|
|
||||||
|
|
||||||
// Set new PC
|
|
||||||
Addr HandlerBase;
|
|
||||||
HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
|
|
||||||
setHandlerPC(HandlerBase,tc);
|
|
||||||
DPRINTF(Arm,"Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(ArmISA::EPC));
|
|
||||||
}
|
|
||||||
|
|
||||||
void ItbRefillFault::invoke(ThreadContext *tc)
|
|
||||||
{
|
|
||||||
DPRINTF(Arm,"%s encountered (%x).\n", name(),BadVAddr);
|
|
||||||
Addr HandlerBase;
|
|
||||||
tc->setMiscRegNoEffect(ArmISA::BadVAddr,BadVAddr);
|
|
||||||
MiscReg eh = tc->readMiscReg(ArmISA::EntryHi);
|
|
||||||
replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
|
|
||||||
replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
|
|
||||||
replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
|
|
||||||
tc->setMiscRegNoEffect(ArmISA::EntryHi,eh);
|
|
||||||
MiscReg ctxt = tc->readMiscReg(ArmISA::Context);
|
|
||||||
replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
|
|
||||||
tc->setMiscRegNoEffect(ArmISA::Context,ctxt);
|
|
||||||
|
|
||||||
MiscReg stat = tc->readMiscReg(ArmISA::Status);
|
|
||||||
// Since handler depends on EXL bit, must check EXL bit before setting it!!
|
|
||||||
if(bits(stat,Status_EXL)==1){ // See MIPS ARM Vol 3, Revision 2, Page 38
|
|
||||||
HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
|
|
||||||
}else{
|
|
||||||
HandlerBase = tc->readMiscReg(ArmISA::EBase); // Offset 0x000
|
|
||||||
}
|
|
||||||
|
|
||||||
setExceptionState(tc,0x2);
|
|
||||||
setHandlerPC(HandlerBase,tc);
|
|
||||||
}
|
|
||||||
|
|
||||||
void DtbRefillFault::invoke(ThreadContext *tc)
|
|
||||||
{
|
|
||||||
// Set new PC
|
|
||||||
DPRINTF(Arm,"%s encountered.\n", name());
|
|
||||||
Addr HandlerBase;
|
|
||||||
tc->setMiscRegNoEffect(ArmISA::BadVAddr,BadVAddr);
|
|
||||||
MiscReg eh = tc->readMiscReg(ArmISA::EntryHi);
|
|
||||||
replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
|
|
||||||
replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
|
|
||||||
replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
|
|
||||||
tc->setMiscRegNoEffect(ArmISA::EntryHi,eh);
|
|
||||||
MiscReg ctxt = tc->readMiscReg(ArmISA::Context);
|
|
||||||
replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
|
|
||||||
tc->setMiscRegNoEffect(ArmISA::Context,ctxt);
|
|
||||||
|
|
||||||
MiscReg stat = tc->readMiscReg(ArmISA::Status);
|
|
||||||
// Since handler depends on EXL bit, must check EXL bit before setting it!!
|
|
||||||
if(bits(stat,Status_EXL)==1){ // See MIPS ARM Vol 3, Revision 2, Page 38
|
|
||||||
HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
|
|
||||||
}else{
|
|
||||||
HandlerBase = tc->readMiscReg(ArmISA::EBase); // Offset 0x000
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
setExceptionState(tc,0x3);
|
|
||||||
|
|
||||||
setHandlerPC(HandlerBase,tc);
|
|
||||||
}
|
|
||||||
|
|
||||||
void TLBModifiedFault::invoke(ThreadContext *tc)
|
|
||||||
{
|
|
||||||
DPRINTF(Arm,"%s encountered.\n", name());
|
|
||||||
tc->setMiscRegNoEffect(ArmISA::BadVAddr,BadVAddr);
|
|
||||||
MiscReg eh = tc->readMiscReg(ArmISA::EntryHi);
|
|
||||||
replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
|
|
||||||
replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
|
|
||||||
replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
|
|
||||||
tc->setMiscRegNoEffect(ArmISA::EntryHi,eh);
|
|
||||||
MiscReg ctxt = tc->readMiscReg(ArmISA::Context);
|
|
||||||
replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
|
|
||||||
tc->setMiscRegNoEffect(ArmISA::Context,ctxt);
|
|
||||||
|
|
||||||
// Set new PC
|
|
||||||
Addr HandlerBase;
|
|
||||||
HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
|
|
||||||
setExceptionState(tc,0x1);
|
|
||||||
setHandlerPC(HandlerBase,tc);
|
|
||||||
// warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(ArmISA::EPC));
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
void SystemCallFault::invoke(ThreadContext *tc)
|
|
||||||
{
|
|
||||||
DPRINTF(Arm,"%s encountered.\n", name());
|
|
||||||
setExceptionState(tc,0x8);
|
|
||||||
|
|
||||||
// Set new PC
|
|
||||||
Addr HandlerBase;
|
|
||||||
HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
|
|
||||||
setHandlerPC(HandlerBase,tc);
|
|
||||||
// warn("Exception Handler At: %x \n",HandlerBase);
|
|
||||||
// warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(ArmISA::EPC));
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
void InterruptFault::invoke(ThreadContext *tc)
|
|
||||||
{
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
DPRINTF(Arm,"%s encountered.\n", name());
|
|
||||||
setExceptionState(tc,0x0A);
|
|
||||||
Addr HandlerBase;
|
|
||||||
|
|
||||||
|
|
||||||
uint8_t IV = bits(tc->readMiscRegNoEffect(ArmISA::Cause),Cause_IV);
|
|
||||||
if (IV)// Offset 200 for release 2
|
|
||||||
HandlerBase= 0x20 + vect() + tc->readMiscRegNoEffect(ArmISA::EBase);
|
|
||||||
else//Ofset at 180 for release 1
|
|
||||||
HandlerBase= vect() + tc->readMiscRegNoEffect(ArmISA::EBase);
|
|
||||||
|
|
||||||
setHandlerPC(HandlerBase,tc);
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif // FULL_SYSTEM
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
void ResetFault::invoke(ThreadContext *tc)
|
// return via SUBS pc, lr, xxx; rfe, movs, ldm
|
||||||
{
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
DPRINTF(Arm,"%s encountered.\n", name());
|
|
||||||
/* All reset activity must be invoked from here */
|
|
||||||
tc->setPC(vect());
|
|
||||||
tc->setNextPC(vect()+sizeof(MachInst));
|
|
||||||
tc->setNextNPC(vect()+sizeof(MachInst)+sizeof(MachInst));
|
|
||||||
DPRINTF(Arm,"(%x) - ResetFault::invoke : PC set to %x",(unsigned)tc,(unsigned)tc->readPC());
|
|
||||||
#endif
|
|
||||||
|
|
||||||
// Set Coprocessor 1 (Floating Point) To Usable
|
|
||||||
//tc->setMiscReg(ArmISA::Status, ArmISA::Status | 0x20000000);
|
|
||||||
}
|
|
||||||
|
|
||||||
void ReservedInstructionFault::invoke(ThreadContext *tc)
|
|
||||||
{
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
DPRINTF(Arm,"%s encountered.\n", name());
|
|
||||||
setExceptionState(tc,0x0A);
|
|
||||||
Addr HandlerBase;
|
|
||||||
HandlerBase= vect() + tc->readMiscRegNoEffect(ArmISA::EBase); // Offset 0x180 - General Exception Vector
|
|
||||||
setHandlerPC(HandlerBase,tc);
|
|
||||||
#else
|
|
||||||
panic("%s encountered.\n", name());
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
void ThreadFault::invoke(ThreadContext *tc)
|
|
||||||
{
|
|
||||||
DPRINTF(Arm,"%s encountered.\n", name());
|
|
||||||
panic("%s encountered.\n", name());
|
|
||||||
}
|
|
||||||
|
|
||||||
void DspStateDisabledFault::invoke(ThreadContext *tc)
|
|
||||||
{
|
|
||||||
DPRINTF(Arm,"%s encountered.\n", name());
|
|
||||||
panic("%s encountered.\n", name());
|
|
||||||
}
|
|
||||||
|
|
||||||
void CoprocessorUnusableFault::invoke(ThreadContext *tc)
|
|
||||||
{
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
DPRINTF(Arm,"%s encountered.\n", name());
|
|
||||||
setExceptionState(tc,0xb);
|
|
||||||
/* The ID of the coprocessor causing the exception is stored in CoprocessorUnusableFault::coProcID */
|
|
||||||
MiscReg cause = tc->readMiscReg(ArmISA::Cause);
|
|
||||||
replaceBits(cause,Cause_CE_HI,Cause_CE_LO,coProcID);
|
|
||||||
tc->setMiscRegNoEffect(ArmISA::Cause,cause);
|
|
||||||
|
|
||||||
Addr HandlerBase;
|
|
||||||
HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase); // Offset 0x180 - General Exception Vector
|
|
||||||
setHandlerPC(HandlerBase,tc);
|
|
||||||
|
|
||||||
// warn("Status: %x, Cause: %x\n",tc->readMiscReg(ArmISA::Status),tc->readMiscReg(ArmISA::Cause));
|
|
||||||
#else
|
|
||||||
warn("%s (CP%d) encountered.\n", name(), coProcID);
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
} // namespace ArmISA
|
} // namespace ArmISA
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -26,548 +26,79 @@
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*
|
*
|
||||||
* Authors: Gabe Black
|
* Authors: Ali Saidi
|
||||||
* Stephen Hines
|
* Gabe Black
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __ARM_FAULTS_HH__
|
#ifndef __ARM_FAULTS_HH__
|
||||||
#define __ARM_FAULTS_HH__
|
#define __ARM_FAULTS_HH__
|
||||||
|
|
||||||
|
#include "arch/arm/types.hh"
|
||||||
|
#include "config/full_system.hh"
|
||||||
#include "sim/faults.hh"
|
#include "sim/faults.hh"
|
||||||
|
|
||||||
// The design of the "name" and "vect" functions is in sim/faults.hh
|
// The design of the "name" and "vect" functions is in sim/faults.hh
|
||||||
|
|
||||||
namespace ArmISA
|
namespace ArmISA
|
||||||
{
|
{
|
||||||
typedef const Addr FaultVect;
|
typedef const Addr FaultOffset;
|
||||||
|
|
||||||
class ArmFault : public FaultBase
|
class ArmFaultBase : public FaultBase
|
||||||
{
|
{
|
||||||
protected:
|
protected:
|
||||||
virtual bool skipFaultingInstruction() {return false;}
|
Addr getVector(ThreadContext *tc);
|
||||||
virtual bool setRestartAddress() {return true;}
|
|
||||||
public:
|
public:
|
||||||
Addr BadVAddr;
|
struct FaultVals
|
||||||
Addr EntryHi_Asid;
|
{
|
||||||
Addr EntryHi_VPN2;
|
const FaultName name;
|
||||||
Addr EntryHi_VPN2X;
|
const FaultOffset offset;
|
||||||
Addr Context_BadVPN2;
|
const OperatingMode nextMode;
|
||||||
|
const uint8_t armPcOffset;
|
||||||
|
const uint8_t thumbPcOffset;
|
||||||
|
const bool abortDisable;
|
||||||
|
const bool fiqDisable;
|
||||||
|
FaultStat count;
|
||||||
|
};
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
void invoke(ThreadContext * tc) {};
|
void invoke(ThreadContext *tc);
|
||||||
void setExceptionState(ThreadContext *,uint8_t);
|
|
||||||
void setHandlerPC(Addr,ThreadContext *);
|
|
||||||
#endif
|
#endif
|
||||||
virtual FaultVect vect() = 0;
|
virtual FaultStat& countStat() = 0;
|
||||||
virtual FaultStat & countStat() = 0;
|
virtual FaultOffset offset() = 0;
|
||||||
|
virtual OperatingMode nextMode() = 0;
|
||||||
|
virtual uint8_t armPcOffset() = 0;
|
||||||
|
virtual uint8_t thumbPcOffset() = 0;
|
||||||
|
virtual bool abortDisable() = 0;
|
||||||
|
virtual bool fiqDisable() = 0;
|
||||||
};
|
};
|
||||||
|
|
||||||
class MachineCheckFault : public ArmFault
|
template<typename T>
|
||||||
{
|
class ArmFault : public ArmFaultBase
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
bool isMachineCheckFault() {return true;}
|
|
||||||
};
|
|
||||||
|
|
||||||
class NonMaskableInterrupt : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
bool isNonMaskableInterrupt() {return true;}
|
|
||||||
};
|
|
||||||
|
|
||||||
class AlignmentFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
bool isAlignmentFault() {return true;}
|
|
||||||
};
|
|
||||||
|
|
||||||
class AddressErrorFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
void invoke(ThreadContext * tc);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
};
|
|
||||||
class StoreAddressErrorFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
void invoke(ThreadContext * tc);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
};
|
|
||||||
class UnimplementedOpcodeFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
class TLBRefillIFetchFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
Addr vaddr;
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
void invoke(ThreadContext * tc);
|
|
||||||
};
|
|
||||||
class TLBInvalidIFetchFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
Addr vaddr;
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
void invoke(ThreadContext * tc);
|
|
||||||
};
|
|
||||||
|
|
||||||
class NDtbMissFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
};
|
|
||||||
|
|
||||||
class PDtbMissFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
};
|
|
||||||
|
|
||||||
class DtbPageFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
};
|
|
||||||
|
|
||||||
class DtbAcvFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
};
|
|
||||||
|
|
||||||
class CacheErrorFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
Addr vaddr;
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
void invoke(ThreadContext * tc);
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
static inline Fault genMachineCheckFault()
|
|
||||||
{
|
|
||||||
return new MachineCheckFault;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline Fault genAlignmentFault()
|
|
||||||
{
|
|
||||||
return new AlignmentFault;
|
|
||||||
}
|
|
||||||
|
|
||||||
class ResetFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
void invoke(ThreadContext * tc);
|
|
||||||
|
|
||||||
};
|
|
||||||
class SystemCallFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
void invoke(ThreadContext * tc);
|
|
||||||
};
|
|
||||||
|
|
||||||
class SoftResetFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
void invoke(ThreadContext * tc);
|
|
||||||
};
|
|
||||||
class DebugSingleStep : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
void invoke(ThreadContext * tc);
|
|
||||||
};
|
|
||||||
class DebugInterrupt : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
void invoke(ThreadContext * tc);
|
|
||||||
};
|
|
||||||
|
|
||||||
class CoprocessorUnusableFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
int coProcID;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
void invoke(ThreadContext * tc);
|
|
||||||
CoprocessorUnusableFault(int _procid){ coProcID = _procid;}
|
|
||||||
};
|
|
||||||
|
|
||||||
class ReservedInstructionFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
void invoke(ThreadContext * tc);
|
|
||||||
};
|
|
||||||
|
|
||||||
class ThreadFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
void invoke(ThreadContext * tc);
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
class ArithmeticFault : public ArmFault
|
|
||||||
{
|
{
|
||||||
protected:
|
protected:
|
||||||
bool skipFaultingInstruction() {return true;}
|
static FaultVals vals;
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
public:
|
||||||
FaultName name() const {return _name;}
|
FaultName name() const { return vals.name; }
|
||||||
FaultVect vect() {return _vect;}
|
FaultStat & countStat() {return vals.count;}
|
||||||
FaultStat & countStat() {return _count;}
|
FaultOffset offset() { return vals.offset; }
|
||||||
#if FULL_SYSTEM
|
OperatingMode nextMode() { return vals.nextMode; }
|
||||||
void invoke(ThreadContext * tc);
|
uint8_t armPcOffset() { return vals.armPcOffset; }
|
||||||
#endif
|
uint8_t thumbPcOffset() { return vals.thumbPcOffset; }
|
||||||
|
bool abortDisable() { return vals.abortDisable; }
|
||||||
|
bool fiqDisable() { return vals.fiqDisable; }
|
||||||
};
|
};
|
||||||
|
|
||||||
class InterruptFault : public ArmFault
|
|
||||||
{
|
|
||||||
protected:
|
|
||||||
bool setRestartAddress() {return false;}
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
class Reset : public ArmFault<Reset> {};
|
||||||
void invoke(ThreadContext * tc);
|
class UndefinedInstruction : public ArmFault<UndefinedInstruction> {};
|
||||||
#endif
|
class SupervisorCall : public ArmFault<SupervisorCall> {};
|
||||||
|
class PrefetchAbort : public ArmFault<PrefetchAbort> {};
|
||||||
|
class DataAbort : public ArmFault<DataAbort> {};
|
||||||
|
class Interrupt : public ArmFault<Interrupt> {};
|
||||||
|
class FastInterrupt : public ArmFault<FastInterrupt> {};
|
||||||
|
|
||||||
//void invoke(ThreadContext * tc);
|
|
||||||
};
|
|
||||||
|
|
||||||
class TrapFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
void invoke(ThreadContext * tc);
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
class BreakpointFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
void invoke(ThreadContext * tc);
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
class ItbRefillFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
void invoke(ThreadContext * tc);
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
class DtbRefillFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
void invoke(ThreadContext * tc);
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
class ItbPageFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
void invoke(ThreadContext * tc);
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
class ItbInvalidFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
void invoke(ThreadContext * tc);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
};
|
|
||||||
class TLBModifiedFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
void invoke(ThreadContext * tc);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
};
|
|
||||||
|
|
||||||
class DtbInvalidFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
void invoke(ThreadContext * tc);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
};
|
|
||||||
|
|
||||||
class FloatEnableFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
};
|
|
||||||
|
|
||||||
class ItbMissFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
};
|
|
||||||
|
|
||||||
class ItbAcvFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
};
|
|
||||||
|
|
||||||
class IntegerOverflowFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
};
|
|
||||||
|
|
||||||
class DspStateDisabledFault : public ArmFault
|
|
||||||
{
|
|
||||||
private:
|
|
||||||
static FaultName _name;
|
|
||||||
static FaultVect _vect;
|
|
||||||
static FaultStat _count;
|
|
||||||
public:
|
|
||||||
FaultName name() const {return _name;}
|
|
||||||
FaultVect vect() {return _vect;}
|
|
||||||
FaultStat & countStat() {return _count;}
|
|
||||||
void invoke(ThreadContext * tc);
|
|
||||||
};
|
|
||||||
|
|
||||||
} // ArmISA namespace
|
} // ArmISA namespace
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -85,6 +85,14 @@ namespace ArmISA
|
||||||
cpsr.mode = MODE_USER;
|
cpsr.mode = MODE_USER;
|
||||||
miscRegs[MISCREG_CPSR] = cpsr;
|
miscRegs[MISCREG_CPSR] = cpsr;
|
||||||
updateRegMap(cpsr);
|
updateRegMap(cpsr);
|
||||||
|
|
||||||
|
SCTLR sctlr = 0;
|
||||||
|
sctlr.nmfi = 1;
|
||||||
|
sctlr.rao1 = 1;
|
||||||
|
sctlr.rao2 = 1;
|
||||||
|
sctlr.rao3 = 1;
|
||||||
|
sctlr.rao4 = 1;
|
||||||
|
|
||||||
//XXX We need to initialize the rest of the state.
|
//XXX We need to initialize the rest of the state.
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -115,7 +115,7 @@ output exec {{
|
||||||
panic("attempt to execute unimplemented instruction '%s' "
|
panic("attempt to execute unimplemented instruction '%s' "
|
||||||
"(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, OPCODE,
|
"(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, OPCODE,
|
||||||
inst2string(machInst));
|
inst2string(machInst));
|
||||||
return new UnimplementedOpcodeFault;
|
return new UnimpFault("Unimplemented Instruction");
|
||||||
}
|
}
|
||||||
|
|
||||||
Fault
|
Fault
|
||||||
|
|
|
||||||
|
|
@ -74,7 +74,7 @@ output exec {{
|
||||||
{
|
{
|
||||||
panic("attempt to execute unknown instruction "
|
panic("attempt to execute unknown instruction "
|
||||||
"(inst 0x%08x, opcode 0x%x, binary: %s)", machInst, OPCODE, inst2string(machInst));
|
"(inst 0x%08x, opcode 0x%x, binary: %s)", machInst, OPCODE, inst2string(machInst));
|
||||||
return new UnimplementedOpcodeFault;
|
return new UnimpFault("Unimplemented Instruction");
|
||||||
}
|
}
|
||||||
}};
|
}};
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -104,6 +104,8 @@ namespace ArmISA
|
||||||
const int WordBytes = 4;
|
const int WordBytes = 4;
|
||||||
const int HalfwordBytes = 2;
|
const int HalfwordBytes = 2;
|
||||||
const int ByteBytes = 1;
|
const int ByteBytes = 1;
|
||||||
|
|
||||||
|
const uint32_t HighVecs = 0xFFFF0000;
|
||||||
};
|
};
|
||||||
|
|
||||||
using namespace ArmISA;
|
using namespace ArmISA;
|
||||||
|
|
|
||||||
|
|
@ -55,7 +55,7 @@ namespace ArmISA
|
||||||
|
|
||||||
enum MiscRegIndex {
|
enum MiscRegIndex {
|
||||||
MISCREG_CPSR = 0,
|
MISCREG_CPSR = 0,
|
||||||
MISCREG_SPSR,
|
MISCREG_SPSR,
|
||||||
MISCREG_SPSR_FIQ,
|
MISCREG_SPSR_FIQ,
|
||||||
MISCREG_SPSR_IRQ,
|
MISCREG_SPSR_IRQ,
|
||||||
MISCREG_SPSR_SVC,
|
MISCREG_SPSR_SVC,
|
||||||
|
|
@ -66,13 +66,13 @@ namespace ArmISA
|
||||||
MISCREG_FPSID,
|
MISCREG_FPSID,
|
||||||
MISCREG_FPSCR,
|
MISCREG_FPSCR,
|
||||||
MISCREG_FPEXC,
|
MISCREG_FPEXC,
|
||||||
NUM_MISCREGS
|
MISCREG_SCTLR,
|
||||||
|
NUM_MISCREGS
|
||||||
};
|
};
|
||||||
|
|
||||||
const char * const miscRegName[NUM_MISCREGS] = {
|
const char * const miscRegName[NUM_MISCREGS] = {
|
||||||
"cpsr",
|
"cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_und",
|
||||||
"spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_und", "spsr_abt",
|
"spsr_abt", "fpsr", "fpsid", "fpscr", "fpexc", "sctlr"
|
||||||
"fpsr"
|
|
||||||
};
|
};
|
||||||
|
|
||||||
BitUnion32(CPSR)
|
BitUnion32(CPSR)
|
||||||
|
|
@ -81,8 +81,10 @@ namespace ArmISA
|
||||||
Bitfield<29> c;
|
Bitfield<29> c;
|
||||||
Bitfield<28> v;
|
Bitfield<28> v;
|
||||||
Bitfield<27> q;
|
Bitfield<27> q;
|
||||||
|
Bitfield<26,25> it1;
|
||||||
Bitfield<24> j;
|
Bitfield<24> j;
|
||||||
Bitfield<19, 16> ge;
|
Bitfield<19, 16> ge;
|
||||||
|
Bitfield<15,10> it2;
|
||||||
Bitfield<9> e;
|
Bitfield<9> e;
|
||||||
Bitfield<8> a;
|
Bitfield<8> a;
|
||||||
Bitfield<7> i;
|
Bitfield<7> i;
|
||||||
|
|
@ -90,6 +92,31 @@ namespace ArmISA
|
||||||
Bitfield<5> t;
|
Bitfield<5> t;
|
||||||
Bitfield<4, 0> mode;
|
Bitfield<4, 0> mode;
|
||||||
EndBitUnion(CPSR)
|
EndBitUnion(CPSR)
|
||||||
|
|
||||||
|
BitUnion32(SCTLR)
|
||||||
|
Bitfield<30> te; // Thumb Exception Enable
|
||||||
|
Bitfield<29> afe; // Access flag enable
|
||||||
|
Bitfield<28> tre; // TEX Remap bit
|
||||||
|
Bitfield<27> nmfi;// Non-maskable fast interrupts enable
|
||||||
|
Bitfield<25> ee; // Exception Endianness bit
|
||||||
|
Bitfield<24> ve; // Interrupt vectors enable
|
||||||
|
Bitfield<23> rao1;// Read as one
|
||||||
|
Bitfield<22> u; // Alignment (now unused)
|
||||||
|
Bitfield<21> fi; // Fast interrupts configuration enable
|
||||||
|
Bitfield<18> rao2;// Read as one
|
||||||
|
Bitfield<17> ha; // Hardware access flag enable
|
||||||
|
Bitfield<16> rao3;// Read as one
|
||||||
|
Bitfield<14> rr; // Round robin cache replacement
|
||||||
|
Bitfield<13> v; // Base address for exception vectors
|
||||||
|
Bitfield<12> i; // instruction cache enable
|
||||||
|
Bitfield<11> z; // branch prediction enable bit
|
||||||
|
Bitfield<10> sw; // Enable swp/swpb
|
||||||
|
Bitfield<6,3> rao4;// Read as one
|
||||||
|
Bitfield<7> b; // Endianness support (unused)
|
||||||
|
Bitfield<2> c; // Cache enable bit
|
||||||
|
Bitfield<1> a; // Alignment fault checking
|
||||||
|
Bitfield<0> m; // MMU enable bit
|
||||||
|
EndBitUnion(SCTLR)
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif // __ARCH_ARM_MISCREGS_HH__
|
#endif // __ARCH_ARM_MISCREGS_HH__
|
||||||
|
|
|
||||||
19
src/arch/arm/utility.cc
Normal file
19
src/arch/arm/utility.cc
Normal file
|
|
@ -0,0 +1,19 @@
|
||||||
|
|
||||||
|
#include <arch/arm/utility.hh>
|
||||||
|
#include <cpu/thread_context.hh>
|
||||||
|
|
||||||
|
|
||||||
|
namespace ArmISA {
|
||||||
|
|
||||||
|
void
|
||||||
|
initCPU(ThreadContext *tc, int cpuId)
|
||||||
|
{
|
||||||
|
// Reset CP15?? What does that mean -- ali
|
||||||
|
|
||||||
|
// FPEXC.EN = 0
|
||||||
|
|
||||||
|
static Fault reset = new Reset();
|
||||||
|
if (cpuId == 0)
|
||||||
|
reset->invoke(tc);
|
||||||
|
}
|
||||||
|
|
||||||
Loading…
Reference in a new issue