From 07e525e8b78fba0ebaf5c50f32fbf30d17051891 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Sun, 26 Nov 2006 11:46:58 -0500 Subject: [PATCH 01/20] Include check for making sure caches are enabled. --HG-- extra : convert_revision : e3902b065db524ebe5bf762e44a840133ccb8d75 --- configs/common/Simulation.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index 374ff3fc2..e037d0343 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -39,6 +39,9 @@ def setCPUClass(options): if options.timing: TmpClass = TimingSimpleCPU elif options.detailed: + if not options.caches: + print "O3 CPU must be used with caches" + sys.exit(1) TmpClass = DerivO3CPU else: TmpClass = AtomicSimpleCPU From 6bbb86dfa986d9a52e8b46ef3d3795bc8123331a Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Mon, 27 Nov 2006 02:16:24 -0500 Subject: [PATCH 02/20] Add TRACING_ON setting for m5.prof. --HG-- extra : convert_revision : ebda49bff30d76d3209acce55458d3f4e29594d3 --- src/SConscript | 1 + 1 file changed, 1 insertion(+) diff --git a/src/SConscript b/src/SConscript index 9d54174ab..429e1bee1 100644 --- a/src/SConscript +++ b/src/SConscript @@ -333,6 +333,7 @@ makeEnv('fast', '.fo', strip = True, # Profiled binary makeEnv('prof', '.po', CCFLAGS = Split('-O3 -g -pg'), + CPPDEFINES = ['NDEBUG', 'TRACING_ON=0'], LINKFLAGS = '-pg') Return('envList') From 2b5fdf603399c63a9344206f1593b20fcb834013 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Tue, 28 Nov 2006 11:41:08 -0500 Subject: [PATCH 03/20] Remove assertion. It's not needed and messes up writebacks when a 2 level cache is used in a uniprocessor setting. --HG-- extra : convert_revision : 020a9799cd7177fdb85a767701d6fcb8cf018827 --- src/mem/cache/coherence/uni_coherence.cc | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/mem/cache/coherence/uni_coherence.cc b/src/mem/cache/coherence/uni_coherence.cc index 5813a0281..ea615d70a 100644 --- a/src/mem/cache/coherence/uni_coherence.cc +++ b/src/mem/cache/coherence/uni_coherence.cc @@ -94,10 +94,6 @@ UniCoherence::handleBusRequest(PacketPtr &pkt, CacheBlk *blk, MSHR *mshr, bool UniCoherence::propogateInvalidate(PacketPtr pkt, bool isTiming) { - //Make sure we don't snoop a write - //we are expecting writeInvalidates on the snoop port of a uni-coherent cache - assert(!(!pkt->isInvalidate() && pkt->isWrite())); - if (pkt->isInvalidate()) { /* Temp Fix for now, forward all invalidates up as functional accesses */ if (isTiming) { From ed78fc257b7e55a94cae6a54a0eacf7090ed7f26 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 28 Nov 2006 16:02:13 -0500 Subject: [PATCH 04/20] add 2.0b2 release notes --HG-- extra : convert_revision : ce34f8086f682cc732bf868f6b9700e42c604ca3 --- RELEASE_NOTES | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/RELEASE_NOTES b/RELEASE_NOTES index 39086de89..03eec3aab 100644 --- a/RELEASE_NOTES +++ b/RELEASE_NOTES @@ -1,3 +1,19 @@ +Nov. 28, 2006: m5_2.0_beta2 +-------------------- +Bug fixes since beta 1: +1. Many cache issues resolved +2. Uni-coherence fixes in full-system +3. LL/SC Support +4. Draining/Switchover +5. Functional Accesses +6. Bus now has real timing +7. Single config file fro all SpecCPU2000 benchmarks +8. Several other minor bug fixes and enhancements + +Outstading issues for 2.0 release: +1. Simulator performance fixes for memory system/caches +2. Multiprocessor linux boot using the detailed O3 CPU model + Aug. 25, 2006: m5_2.0_beta patch 1 -------------------- Handful of minor bug fixes for m5_2.0_beta, From 610064c98a16a7c9cdc51e4e4c15cd5c1d2c2e4f Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Wed, 29 Nov 2006 11:50:03 -0500 Subject: [PATCH 05/20] Add in O3CPU to default CPU list. --HG-- extra : convert_revision : 4aaaae058cb763580ea0b9019d4a9346938121d4 --- SConstruct | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/SConstruct b/SConstruct index d8851f091..50ca2d6e4 100644 --- a/SConstruct +++ b/SConstruct @@ -344,7 +344,7 @@ sticky_opts.AddOptions( # values (more than one value) not to be able to be restored from # a saved option file. If this causes trouble then upgrade to # scons 0.96.90 or later. - ListOption('CPU_MODELS', 'CPU models', 'AtomicSimpleCPU,TimingSimpleCPU', + ListOption('CPU_MODELS', 'CPU models', 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU', env['ALL_CPU_LIST']), BoolOption('ALPHA_TLASER', 'Model Alpha TurboLaser platform (vs. Tsunami)', False), From c96160cef541b1b4b3e58bf0c56612ef17250e46 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Wed, 29 Nov 2006 16:07:55 -0500 Subject: [PATCH 06/20] Change the connecting of the physPort and virtPort to the memory object below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in. Right now this introduces a minor memory leak as old physPorts and virtPorts are not deleted when new ones are created. A flyspray task has been created for this issue. It can not be resolved until we determine how the bus will handle giving out ID's to functional ports that may be deleted. src/cpu/o3/cpu.cc: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: Change the setup of the physPort and virtPort to instead happen every time the CPU has a context activated. This is a little high overhead, but keeps it working correctly when the CPU does not have a physical memory attached to it until it switches in (like the case of switch CPUs). src/cpu/o3/thread_context.hh: Change function from being called at init() to just being called whenever the memory ports need to be connected. src/cpu/o3/thread_context_impl.hh: Update this to not delete the port if it's the same as the virtPort. src/cpu/thread_context.hh: Change function from being called at init() to whenever the memory ports need to be connected. src/cpu/thread_state.cc: Instead of initializing the ports, simply connect them, deleting any old ports that might exist. This allows these functions to be called multiple times. src/cpu/thread_state.hh: Ports are no longer initialized, but rather connected at context activation time. --HG-- extra : convert_revision : e399ce5dfbd6ad658c953a7c9c7b69b89a70219e --- src/cpu/o3/cpu.cc | 8 ++++++-- src/cpu/o3/thread_context.hh | 2 +- src/cpu/o3/thread_context_impl.hh | 6 ++++-- src/cpu/simple/atomic.cc | 10 +++++++--- src/cpu/simple/timing.cc | 10 +++++++--- src/cpu/thread_context.hh | 4 ++-- src/cpu/thread_state.cc | 16 +++++++++++----- src/cpu/thread_state.hh | 6 +++--- 8 files changed, 41 insertions(+), 21 deletions(-) diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 3dc353a9f..a5a00015f 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -497,8 +497,6 @@ FullO3CPU::init() } #if FULL_SYSTEM - src_tc->init(); - TheISA::initCPU(src_tc, src_tc->readCpuId()); #endif } @@ -554,6 +552,12 @@ template void FullO3CPU::activateContext(int tid, int delay) { +#if FULL_SYSTEM + // Connect the ThreadContext's memory ports (Functional/Virtual + // Ports) + threadContexts[tid]->connectMemPorts(); +#endif + // Needs to set each stage to running as well. if (delay){ DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 031f36480..390569c3d 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -92,7 +92,7 @@ class O3ThreadContext : public ThreadContext void delVirtPort(VirtualPort *vp); - virtual void init() { thread->init(); } + virtual void connectMemPorts() { thread->connectMemPorts(); } #else virtual TranslatingPort *getMemPort() { return thread->getMemPort(); } diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index 0180756e3..afebf294f 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -101,8 +101,10 @@ template void O3ThreadContext::delVirtPort(VirtualPort *vp) { - delete vp->getPeer(); - delete vp; + if (vp != thread->getVirtPort()) { + delete vp->getPeer(); + delete vp; + } } #endif diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index cd335e36d..8cfe2ee83 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -77,9 +77,6 @@ AtomicSimpleCPU::init() for (int i = 0; i < threadContexts.size(); ++i) { ThreadContext *tc = threadContexts[i]; - // initialize the mem pointers - tc->init(); - // initialize CPU, including PC TheISA::initCPU(tc, tc->readCpuId()); } @@ -240,6 +237,13 @@ AtomicSimpleCPU::activateContext(int thread_num, int delay) assert(!tickEvent.scheduled()); notIdleFraction++; + +#if FULL_SYSTEM + // Connect the ThreadContext's memory ports (Functional/Virtual + // Ports) + tc->connectMemPorts(); +#endif + //Make sure ticks are still on multiples of cycles tickEvent.schedule(nextCycle(curTick + cycles(delay))); _status = Running; diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index aa23a00e8..dfffb0b1f 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -59,9 +59,6 @@ TimingSimpleCPU::init() for (int i = 0; i < threadContexts.size(); ++i) { ThreadContext *tc = threadContexts[i]; - // initialize the mem pointers - tc->init(); - // initialize CPU, including PC TheISA::initCPU(tc, tc->readCpuId()); } @@ -241,6 +238,13 @@ TimingSimpleCPU::activateContext(int thread_num, int delay) notIdleFraction++; _status = Running; + +#if FULL_SYSTEM + // Connect the ThreadContext's memory ports (Functional/Virtual + // Ports) + tc->connectMemPorts(); +#endif + // kick things off by initiating the fetch of the next instruction fetchEvent = new EventWrapper(this, false); diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index baeb7a8be..bb9cc9e16 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -134,7 +134,7 @@ class ThreadContext virtual void delVirtPort(VirtualPort *vp) = 0; - virtual void init() = 0; + virtual void connectMemPorts() = 0; #else virtual TranslatingPort *getMemPort() = 0; @@ -308,7 +308,7 @@ class ProxyThreadContext : public ThreadContext void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); } - void init() {actualTC->init(); } + void connectMemPorts() { actualTC->connectMemPorts(); } #else TranslatingPort *getMemPort() { return actualTC->getMemPort(); } diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc index 9cac4fd26..93dd1e2eb 100644 --- a/src/cpu/thread_state.cc +++ b/src/cpu/thread_state.cc @@ -113,23 +113,29 @@ ThreadState::unserialize(Checkpoint *cp, const std::string §ion) #if FULL_SYSTEM void -ThreadState::init() +ThreadState::connectMemPorts() { - initPhysPort(); - initVirtPort(); + connectPhysPort(); + connectVirtPort(); } void -ThreadState::initPhysPort() +ThreadState::connectPhysPort() { + // @todo: For now this disregards any older port that may have + // already existed. Fix this memory leak once the bus port IDs + // for functional ports is resolved. physPort = new FunctionalPort(csprintf("%s-%d-funcport", baseCpu->name(), tid)); connectToMemFunc(physPort); } void -ThreadState::initVirtPort() +ThreadState::connectVirtPort() { + // @todo: For now this disregards any older port that may have + // already existed. Fix this memory leak once the bus port IDs + // for functional ports is resolved. virtPort = new VirtualPort(csprintf("%s-%d-vport", baseCpu->name(), tid)); connectToMemFunc(virtPort); diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh index 1844be8b7..4f878db1f 100644 --- a/src/cpu/thread_state.hh +++ b/src/cpu/thread_state.hh @@ -91,11 +91,11 @@ struct ThreadState { Tick readLastSuspend() { return lastSuspend; } #if FULL_SYSTEM - void init(); + void connectMemPorts(); - void initPhysPort(); + void connectPhysPort(); - void initVirtPort(); + void connectVirtPort(); void dumpFuncProfile(); From d2a71f6b2aaad36c6420204266f006304d364ad7 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Wed, 29 Nov 2006 13:17:41 -0800 Subject: [PATCH 07/20] cscope-find.py: Write directly to 'cscope.files' and run 'cscope -b' . Now this script does everything automatically. cscope-index.py: Rename: util/cscope-find.py -> util/cscope-index.py util/cscope-find.py: Write directly to 'cscope.files' and run 'cscope -b' . Now this script does everything automatically. --HG-- rename : util/cscope-find.py => util/cscope-index.py extra : convert_revision : cd6fa5cc0c2146f7184c9213956aff67c7cb9341 --- util/cscope-find.py | 38 ------------------------ util/cscope-index.py | 71 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 71 insertions(+), 38 deletions(-) delete mode 100755 util/cscope-find.py create mode 100755 util/cscope-index.py diff --git a/util/cscope-find.py b/util/cscope-find.py deleted file mode 100755 index 1775f1864..000000000 --- a/util/cscope-find.py +++ /dev/null @@ -1,38 +0,0 @@ -#! /usr/bin/python - -# Generate list of files to index with cscope. - -# From the m5 directory, run: -# util/cscope-find.py > cscope.files -# cscope -b - -import os - -# absolute paths to skip -skipdirs = [ 'src/unittest', 'src/doxygen' ] - -# suffixes of files to index -suffixes = [ '.cc', '.hh', '.c', '.h' ] - -def oksuffix(f): - for s in suffixes: - if f.endswith(s): - return True - return False - -for dirpath,subdirs,files in os.walk('src'): - # filter out undesirable subdirectories - for i,dir in enumerate(subdirs): - if dir == 'SCCS': - del subdirs[i] - break - - # filter out undesriable absolute paths - if dirpath in skipdirs: - del subdirs[:] - continue - - # find C/C++ sources - okfiles = [f for f in files if oksuffix(f)] - if okfiles: - print '\n'.join([os.path.join(dirpath, f) for f in okfiles]) diff --git a/util/cscope-index.py b/util/cscope-index.py new file mode 100755 index 000000000..1e653235f --- /dev/null +++ b/util/cscope-index.py @@ -0,0 +1,71 @@ +#! /usr/bin/python +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Steve Reinhardt + +# Generate list of files to index with cscope and then generate cscope index. + +# Should be run from root of m5 tree (i.e. as 'util/cscope-index.py'). + +import os + +# absolute paths to skip +skipdirs = [ 'src/unittest', 'src/doxygen' ] + +# suffixes of files to index +suffixes = [ '.cc', '.hh', '.c', '.h' ] + +def oksuffix(f): + for s in suffixes: + if f.endswith(s): + return True + return False + +file_list = file('cscope.files', 'w') + +for dirpath,subdirs,files in os.walk('src'): + # filter out undesirable subdirectories + for i,dir in enumerate(subdirs): + if dir == 'SCCS': + del subdirs[i] + break + + # filter out undesirable absolute paths + if dirpath in skipdirs: + del subdirs[:] + continue + + # find C/C++ sources + okfiles = [f for f in files if oksuffix(f)] + if okfiles: + print >> file_list, \ + '\n'.join([os.path.join(dirpath, f) for f in okfiles]) + +file_list.close() + +# run cscope to generate index +os.system("cscope -b") From df6c12e7160051ce77648eb659fa521c3a3e3cf8 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Thu, 30 Nov 2006 11:53:33 -0500 Subject: [PATCH 08/20] netperf-maerts-client.rcS: change /netperf/netperf to /netperf-bin/netperf nat-netperf-maerts-client.rcS: bad comment that went with the file - accidentally committed but probably doesn't matter, i ust eliminated an ivlb in the script. configs/boot/nat-netperf-maerts-client.rcS: replace netperf/netperf with netperf-bin/netperf configs/boot/netperf-maerts-client.rcS: change /netperf/netperf to /netperf-bin/netperf --HG-- extra : convert_revision : 32fed0042e267f315d3e688ebc4b66d7002b85f0 --- configs/boot/nat-netperf-maerts-client.rcS | 1 - configs/boot/netperf-maerts-client.rcS | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/configs/boot/nat-netperf-maerts-client.rcS b/configs/boot/nat-netperf-maerts-client.rcS index 863766a6b..d8a6d4dc4 100644 --- a/configs/boot/nat-netperf-maerts-client.rcS +++ b/configs/boot/nat-netperf-maerts-client.rcS @@ -41,7 +41,6 @@ eval $SHORT echo "netperf benchmark" echo $LONG -/sbin/m5 ivlb 1 /sbin/m5 resetstats /sbin/m5 dumpresetstats 200000000 2000000000 /sbin/m5 checkpoint 200000000 2000000000 diff --git a/configs/boot/netperf-maerts-client.rcS b/configs/boot/netperf-maerts-client.rcS index 3270d0058..7766713aa 100644 --- a/configs/boot/netperf-maerts-client.rcS +++ b/configs/boot/netperf-maerts-client.rcS @@ -21,7 +21,7 @@ echo "100000" > /proc/sys/net/core/netdev_max_backlog echo -n "waiting for server..." /usr/bin/netcat -c -l -p 8000 -BINARY=/benchmarks/netperf/netperf +BINARY=/benchmarks/netperf-bin/netperf TEST="TCP_MAERTS" SHORT_ARGS="-l -100k" LONG_ARGS="-k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144" From e38e893016631febd2736c7c4fd18a6a41bdbae6 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Thu, 30 Nov 2006 15:01:49 -0500 Subject: [PATCH 09/20] Update stats to match writeback fix that was made --HG-- extra : convert_revision : 3e0ed2b374d8d96798ea9b3416c9e5579cafacda --- .../ref/sparc/linux/simple-timing/m5stats.txt | 41 +++++++++---------- 1 file changed, 20 insertions(+), 21 deletions(-) diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt index 3645207b1..b0f73986b 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 48159 # Simulator instruction rate (inst/s) -host_mem_usage 179620 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -host_tick_rate 15510230 # Simulator tick rate (ticks/s) +host_inst_rate 158849 # Simulator instruction rate (inst/s) +host_mem_usage 179428 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 50697812 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4863 # Number of instructions simulated sim_seconds 0.000002 # Number of seconds simulated @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 3977.572464 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 2977.572464 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1131 # number of overall hits system.cpu.dcache.overall_miss_latency 548905 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.108747 # miss rate for overall accesses @@ -115,7 +115,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 4864 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 3977.960938 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 2977.960938 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 4608 # number of overall hits system.cpu.icache.overall_miss_latency 1018358 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.052632 # miss rate for overall accesses @@ -143,49 +143,48 @@ system.cpu.icache.total_refs 4608 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 394 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 391 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 2985.429668 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1984.429668 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_miss_latency 1167303 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.992386 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 391 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 775912 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992386 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 391 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.007673 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 394 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 391 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 2985.429668 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1984.429668 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 1167303 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.992386 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 391 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_miss_latency 775912 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.992386 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 391 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 394 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 391 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 2985.429668 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1984.429668 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 3 # number of overall hits +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 0 # number of overall hits system.cpu.l2cache.overall_miss_latency 1167303 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.992386 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 391 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_miss_latency 775912 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.992386 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 391 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -202,7 +201,7 @@ system.cpu.l2cache.replacements 0 # nu system.cpu.l2cache.sampled_refs 391 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.tagsinuse 195.424915 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. +system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles From 6e885ec9ba3faeb83971e1a0b0042c1103f1ffaf Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 30 Nov 2006 20:50:47 -0800 Subject: [PATCH 10/20] Get rid of the old release-edits script and create make_release.py which takes care of almost everything needed for putting together a release. --HG-- extra : convert_revision : b05d418a1002633b1286591eb8a8588ba33f5df1 --- util/make_release.py | 155 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 155 insertions(+) create mode 100755 util/make_release.py diff --git a/util/make_release.py b/util/make_release.py new file mode 100755 index 000000000..d1161166d --- /dev/null +++ b/util/make_release.py @@ -0,0 +1,155 @@ +#!/usr/bin/env python +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ali Saidi +# Steve Reinhardt +# Nathan Binkert + +import os +import re +import shutil +import sys + +from glob import glob +from os import system +from os.path import basename, dirname, exists, isdir, isfile, join as joinpath + +def mkdir(*args): + path = joinpath(*args) + os.mkdir(path) + +def touch(*args): + path = joinpath(*args) + os.utime(path, None) + +def rmtree(*args): + path = joinpath(*args) + for match in glob(path): + if isdir(match): + shutil.rmtree(match) + else: + os.unlink(match) + +def remove(*args): + path = joinpath(*args) + for match in glob(path): + if not isdir(match): + os.unlink(match) + +def movedir(srcdir, destdir, dir): + src = joinpath(srcdir, dir) + dest = joinpath(destdir, dir) + + if not isdir(src): + raise AttributeError + + os.makedirs(dirname(dest)) + shutil.move(src, dest) + +if not isdir('BitKeeper'): + sys.exit('Not in the top level of an m5 tree!') + +usage = '%s ' % sys.argv[0] + +if len(sys.argv) != 3: + sys.exit(usage) + +destdir = sys.argv[1] +releasename = sys.argv[2] + +if exists(destdir): + if not isdir(destdir): + raise AttributeError, '%s exists, but is not a directory' % destdir + rmtree(destdir) + +release_dir = joinpath(destdir, 'release', releasename) +encumbered_dir = joinpath(destdir, 'encumbered', releasename) + +mkdir(destdir) +mkdir(destdir, 'release') +mkdir(destdir, 'encumbered') +mkdir(release_dir) +mkdir(encumbered_dir) + +system('bk export -tplain -w -r+ %s' % release_dir) + +# make sure scons doesn't try to run flex unnecessarily +touch(release_dir, 'src/encumbered/eio/exolex.cc') + +# get rid of non-shipping code +rmtree(release_dir, 'src/encumbered/dev') +rmtree(release_dir, 'src/cpu/ozone') +rmtree(release_dir, 'src/mem/cache/tags/split*.cc') +rmtree(release_dir, 'src/mem/cache/tags/split*.hh') +rmtree(release_dir, 'src/mem/cache/prefetch/ghb_*.cc') +rmtree(release_dir, 'src/mem/cache/prefetch/ghb_*.hh') +rmtree(release_dir, 'src/mem/cache/prefetch/stride_*.cc') +rmtree(release_dir, 'src/mem/cache/prefetch/stride_*.hh') +rmtree(release_dir, 'src/oldmem') +rmtree(release_dir, 'configs/fullsys') +rmtree(release_dir, 'configs/test') +rmtree(release_dir, 'configs/splash2') +rmtree(release_dir, 'tests/long/*/ref') +rmtree(release_dir, 'tests/old') + +# get rid of some of private scripts +remove(release_dir, 'util/chgcopyright') +remove(release_dir, 'util/make_release.py') + +# fix up the SConscript to deal with files we've removed +mem_expr = re.compile('.*mem/cache/(tags/split|prefetch/(ghb|stride)).*') +inscript = file(joinpath(release_dir, 'src', 'SConscript'), 'r').readlines() +outscript = file(joinpath(release_dir, 'src', 'SConscript'), 'w') +for line in inscript: + if mem_expr.match(line): + continue + + outscript.write(line) +outscript.close() + +benches = [ 'bzip2', 'eon', 'gzip', 'mcf', 'parser', 'perlbmk', + 'twolf', 'vortex' ] +for bench in benches: + rmtree(release_dir, 'tests', 'test-progs', bench) + +movedir(release_dir, encumbered_dir, 'src/encumbered') +movedir(release_dir, encumbered_dir, 'tests/test-progs/anagram') +movedir(release_dir, encumbered_dir, 'tests/quick/20.eio-short') + +def taritup(directory, destdir, filename): + basedir = dirname(directory) + tarball = joinpath(destdir, filename) + tardir = basename(directory) + + system('cd %s; tar cfj %s %s' % (basedir, tarball, tardir)) + +taritup(release_dir, destdir, '%s.tar.bz2' % releasename) +taritup(encumbered_dir, destdir, '%s-encumbered.tar.bz2' % releasename) + +print "release created in %s" % destdir +print "don't forget to tag the repository! The following command will do it:" +print "bk tag %s" % releasename From 161b8d1a23ebd5dab767acde67c7aeb0987fb908 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Fri, 1 Dec 2006 01:24:01 -0500 Subject: [PATCH 11/20] add a simple netperf-stream test to the long tests. tests/SConscript: add a new configuration for two-system tests (atomic simple only) --HG-- extra : convert_revision : 16c260ab16f38779fe17b1cab18f36d5c7a70846 --- tests/SConscript | 4 +- tests/configs/twosys-tsunami-simple-atomic.py | 48 + .../twosys-tsunami-simple-atomic/config.ini | 1205 +++++++++++++++++ .../twosys-tsunami-simple-atomic/config.out | 1101 +++++++++++++++ .../console.drivesys.sim_console | 111 ++ .../console.testsys.sim_console | 120 ++ .../twosys-tsunami-simple-atomic/m5stats.txt | 476 +++++++ .../linux/twosys-tsunami-simple-atomic/stderr | 8 + .../linux/twosys-tsunami-simple-atomic/stdout | 17 + tests/long/80.netperf-stream/test.py | 2 + 10 files changed, 3091 insertions(+), 1 deletion(-) create mode 100644 tests/configs/twosys-tsunami-simple-atomic.py create mode 100644 tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini create mode 100644 tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out create mode 100644 tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console create mode 100644 tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console create mode 100644 tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt create mode 100644 tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr create mode 100644 tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout create mode 100644 tests/long/80.netperf-stream/test.py diff --git a/tests/SConscript b/tests/SConscript index 1228e78d2..8560363f9 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -205,7 +205,9 @@ if env['FULL_SYSTEM']: configs += ['tsunami-simple-atomic', 'tsunami-simple-timing', 'tsunami-simple-atomic-dual', - 'tsunami-simple-timing-dual'] + 'tsunami-simple-timing-dual', + 'twosys-tsunami-simple-atomic'] + else: configs += ['simple-atomic', 'simple-timing', 'o3-timing'] diff --git a/tests/configs/twosys-tsunami-simple-atomic.py b/tests/configs/twosys-tsunami-simple-atomic.py new file mode 100644 index 000000000..335cea27d --- /dev/null +++ b/tests/configs/twosys-tsunami-simple-atomic.py @@ -0,0 +1,48 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Lisa Hsu + +import m5 +from m5.objects import * +m5.AddToPath('../configs/common') +from SysPaths import * +from FSConfig import * +from Benchmarks import * + +test_sys = makeLinuxAlphaSystem('atomic', + SysConfig('netperf-stream-client.rcS')) +test_sys.cpu = AtomicSimpleCPU(cpu_id=0) +test_sys.cpu.connectMemPorts(test_sys.membus) + +drive_sys = makeLinuxAlphaSystem('atomic', + SysConfig('netperf-server.rcS')) +drive_sys.cpu = AtomicSimpleCPU(cpu_id=0) +drive_sys.cpu.connectMemPorts(drive_sys.membus) + +root = makeDualRoot(test_sys, drive_sys, "ethertrace") + +maxtick = 199999999 diff --git a/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini new file mode 100644 index 000000000..dff95e358 --- /dev/null +++ b/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -0,0 +1,1205 @@ +[root] +type=Root +children=drivesys etherdump etherlink testsys +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[drivesys] +type=LinuxAlphaSystem +children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami +boot_cpu_frequency=1 +boot_osflags=root=/dev/hda1 console=ttyS0 +console=/dist/m5/system/binaries/console +init_param=0 +kernel=/dist/m5/system/binaries/vmlinux +mem_mode=atomic +pal=/dist/m5/system/binaries/ts_osfpal +physmem=drivesys.physmem +readfile=/z/hsul/work/m5/newmem/configs/boot/netperf-server.rcS +symbolfile= +system_rev=1024 +system_type=34 + +[drivesys.bridge] +type=Bridge +delay=0 +queue_size_a=16 +queue_size_b=16 +write_ack=false +side_a=drivesys.iobus.port[0] +side_b=drivesys.membus.port[0] + +[drivesys.cpu] +type=AtomicSimpleCPU +children=dtb itb +clock=1 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=drivesys.cpu.dtb +function_trace=false +function_trace_start=0 +itb=drivesys.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +profile=0 +progress_interval=0 +simulate_stalls=false +system=drivesys +width=1 +dcache_port=drivesys.membus.port[3] +icache_port=drivesys.membus.port[2] + +[drivesys.cpu.dtb] +type=AlphaDTB +size=64 + +[drivesys.cpu.itb] +type=AlphaITB +size=48 + +[drivesys.disk0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=drivesys.disk0.image + +[drivesys.disk0.image] +type=CowDiskImage +children=child +child=drivesys.disk0.image.child +read_only=false +table_size=65536 + +[drivesys.disk0.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/myimg.img +read_only=true + +[drivesys.disk2] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=drivesys.disk2.image + +[drivesys.disk2.image] +type=CowDiskImage +children=child +child=drivesys.disk2.image.child +read_only=false +table_size=65536 + +[drivesys.disk2.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-bigswap2.img +read_only=true + +[drivesys.intrctrl] +type=IntrControl +cpu=drivesys.cpu + +[drivesys.iobus] +type=Bus +bus_id=0 +clock=1000 +responder_set=true +width=64 +default=drivesys.tsunami.pciconfig.pio +port=drivesys.bridge.side_a drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fake_sm_chip.pio drivesys.tsunami.fake_uart1.pio drivesys.tsunami.fake_uart2.pio drivesys.tsunami.fake_uart3.pio drivesys.tsunami.fake_uart4.pio drivesys.tsunami.fake_ppc.pio drivesys.tsunami.fake_OROM.pio drivesys.tsunami.fake_pnp_addr.pio drivesys.tsunami.fake_pnp_write.pio drivesys.tsunami.fake_pnp_read0.pio drivesys.tsunami.fake_pnp_read1.pio drivesys.tsunami.fake_pnp_read2.pio drivesys.tsunami.fake_pnp_read3.pio drivesys.tsunami.fake_pnp_read4.pio drivesys.tsunami.fake_pnp_read5.pio drivesys.tsunami.fake_pnp_read6.pio drivesys.tsunami.fake_pnp_read7.pio drivesys.tsunami.fake_ata0.pio drivesys.tsunami.fake_ata1.pio drivesys.tsunami.fb.pio drivesys.tsunami.io.pio drivesys.tsunami.uart.pio drivesys.tsunami.console.pio drivesys.tsunami.ide.pio drivesys.tsunami.ethernet.pio drivesys.tsunami.ethernet.config drivesys.tsunami.ethernet.dma drivesys.tsunami.ide.config drivesys.tsunami.ide.dma + +[drivesys.membus] +type=Bus +children=responder +bus_id=1 +clock=1000 +responder_set=false +width=64 +default=drivesys.membus.responder.pio +port=drivesys.bridge.side_b drivesys.physmem.port drivesys.cpu.icache_port drivesys.cpu.dcache_port + +[drivesys.membus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=true +ret_data=255 +system=drivesys +pio=drivesys.membus.default + +[drivesys.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=drivesys.membus.port[1] + +[drivesys.sim_console] +type=SimConsole +children=listener +append_name=true +intr_control=drivesys.intrctrl +listener=drivesys.sim_console.listener +number=0 +output=console + +[drivesys.sim_console.listener] +type=ConsoleListener +port=3456 + +[drivesys.simple_disk] +type=SimpleDisk +children=disk +disk=drivesys.simple_disk.disk +system=drivesys + +[drivesys.simple_disk.disk] +type=RawDiskImage +image_file=/dist/m5/system/disks/myimg.img +read_only=true + +[drivesys.tsunami] +type=Tsunami +children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +intrctrl=drivesys.intrctrl +system=drivesys + +[drivesys.tsunami.cchip] +type=TsunamiCChip +pio_addr=8803072344064 +pio_latency=1000 +platform=drivesys.tsunami +system=drivesys +tsunami=drivesys.tsunami +pio=drivesys.iobus.port[1] + +[drivesys.tsunami.console] +type=AlphaConsole +cpu=drivesys.cpu +disk=drivesys.simple_disk +pio_addr=8804682956800 +pio_latency=1000 +platform=drivesys.tsunami +sim_console=drivesys.sim_console +system=drivesys +pio=drivesys.iobus.port[25] + +[drivesys.tsunami.etherint] +type=NSGigEInt +device=drivesys.tsunami.ethernet +peer=Null + +[drivesys.tsunami.ethernet] +type=NSGigE +children=configdata +clock=0 +config_latency=20000 +configdata=drivesys.tsunami.ethernet.configdata +dma_data_free=false +dma_desc_free=false +dma_no_allocate=true +dma_read_delay=0 +dma_read_factor=0 +dma_write_delay=0 +dma_write_factor=0 +hardware_address=00:90:00:00:00:02 +intr_delay=10000000 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=1000 +platform=drivesys.tsunami +rss=false +rx_delay=1000000 +rx_fifo_size=524288 +rx_filter=true +rx_thread=false +system=drivesys +tx_delay=1000000 +tx_fifo_size=524288 +tx_thread=false +config=drivesys.iobus.port[28] +dma=drivesys.iobus.port[29] +pio=drivesys.iobus.port[27] + +[drivesys.tsunami.ethernet.configdata] +type=PciConfigData +BAR0=1 +BAR0Size=256 +BAR1=0 +BAR1Size=4096 +BAR2=0 +BAR2Size=0 +BAR3=0 +BAR3Size=0 +BAR4=0 +BAR4Size=0 +BAR5=0 +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=34 +ExpansionROM=0 +HeaderType=0 +InterruptLine=30 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=52 +MinimumGrant=176 +ProgIF=0 +Revision=0 +Status=656 +SubClassCode=0 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=4107 + +[drivesys.tsunami.fake_OROM] +type=IsaFake +pio_addr=8796093677568 +pio_latency=1000 +pio_size=393216 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[9] + +[drivesys.tsunami.fake_ata0] +type=IsaFake +pio_addr=8804615848432 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[20] + +[drivesys.tsunami.fake_ata1] +type=IsaFake +pio_addr=8804615848304 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[21] + +[drivesys.tsunami.fake_pnp_addr] +type=IsaFake +pio_addr=8804615848569 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[10] + +[drivesys.tsunami.fake_pnp_read0] +type=IsaFake +pio_addr=8804615848451 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[12] + +[drivesys.tsunami.fake_pnp_read1] +type=IsaFake +pio_addr=8804615848515 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[13] + +[drivesys.tsunami.fake_pnp_read2] +type=IsaFake +pio_addr=8804615848579 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[14] + +[drivesys.tsunami.fake_pnp_read3] +type=IsaFake +pio_addr=8804615848643 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[15] + +[drivesys.tsunami.fake_pnp_read4] +type=IsaFake +pio_addr=8804615848707 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[16] + +[drivesys.tsunami.fake_pnp_read5] +type=IsaFake +pio_addr=8804615848771 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[17] + +[drivesys.tsunami.fake_pnp_read6] +type=IsaFake +pio_addr=8804615848835 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[18] + +[drivesys.tsunami.fake_pnp_read7] +type=IsaFake +pio_addr=8804615848899 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[19] + +[drivesys.tsunami.fake_pnp_write] +type=IsaFake +pio_addr=8804615850617 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[11] + +[drivesys.tsunami.fake_ppc] +type=IsaFake +pio_addr=8804615848892 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[8] + +[drivesys.tsunami.fake_sm_chip] +type=IsaFake +pio_addr=8804615848816 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[3] + +[drivesys.tsunami.fake_uart1] +type=IsaFake +pio_addr=8804615848696 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[4] + +[drivesys.tsunami.fake_uart2] +type=IsaFake +pio_addr=8804615848936 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[5] + +[drivesys.tsunami.fake_uart3] +type=IsaFake +pio_addr=8804615848680 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[6] + +[drivesys.tsunami.fake_uart4] +type=IsaFake +pio_addr=8804615848944 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[7] + +[drivesys.tsunami.fb] +type=BadDevice +devicename=FrameBuffer +pio_addr=8804615848912 +pio_latency=1000 +platform=drivesys.tsunami +system=drivesys +pio=drivesys.iobus.port[22] + +[drivesys.tsunami.ide] +type=IdeController +children=configdata +config_latency=20000 +configdata=drivesys.tsunami.ide.configdata +disks=drivesys.disk0 drivesys.disk2 +pci_bus=0 +pci_dev=0 +pci_func=0 +pio_latency=1000 +platform=drivesys.tsunami +system=drivesys +config=drivesys.iobus.port[30] +dma=drivesys.iobus.port[31] +pio=drivesys.iobus.port[26] + +[drivesys.tsunami.ide.configdata] +type=PciConfigData +BAR0=1 +BAR0Size=8 +BAR1=1 +BAR1Size=4 +BAR2=1 +BAR2Size=8 +BAR3=1 +BAR3Size=4 +BAR4=1 +BAR4Size=16 +BAR5=1 +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=0 +MinimumGrant=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 + +[drivesys.tsunami.io] +type=TsunamiIO +frequency=976562500 +pio_addr=8804615847936 +pio_latency=1000 +platform=drivesys.tsunami +system=drivesys +time=1136073600 +tsunami=drivesys.tsunami +pio=drivesys.iobus.port[23] + +[drivesys.tsunami.pchip] +type=TsunamiPChip +pio_addr=8802535473152 +pio_latency=1000 +platform=drivesys.tsunami +system=drivesys +tsunami=drivesys.tsunami +pio=drivesys.iobus.port[2] + +[drivesys.tsunami.pciconfig] +type=PciConfigAll +bus=0 +pio_latency=1 +platform=drivesys.tsunami +size=16777216 +system=drivesys +pio=drivesys.iobus.default + +[drivesys.tsunami.uart] +type=Uart8250 +pio_addr=8804615848952 +pio_latency=1000 +platform=drivesys.tsunami +sim_console=drivesys.sim_console +system=drivesys +pio=drivesys.iobus.port[24] + +[etherdump] +type=EtherDump +file=ethertrace +maxlen=96 + +[etherlink] +type=EtherLink +delay=0 +delay_var=0 +dump=etherdump +int1=testsys.tsunami.etherint +int2=drivesys.tsunami.etherint +speed=8000.000000 + +[exetrace] +intel_format=false +legion_lockstep=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[testsys] +type=LinuxAlphaSystem +children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami +boot_cpu_frequency=1 +boot_osflags=root=/dev/hda1 console=ttyS0 +console=/dist/m5/system/binaries/console +init_param=0 +kernel=/dist/m5/system/binaries/vmlinux +mem_mode=atomic +pal=/dist/m5/system/binaries/ts_osfpal +physmem=testsys.physmem +readfile=/z/hsul/work/m5/newmem/configs/boot/netperf-stream-client.rcS +symbolfile= +system_rev=1024 +system_type=34 + +[testsys.bridge] +type=Bridge +delay=0 +queue_size_a=16 +queue_size_b=16 +write_ack=false +side_a=testsys.iobus.port[0] +side_b=testsys.membus.port[0] + +[testsys.cpu] +type=AtomicSimpleCPU +children=dtb itb +clock=1 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=testsys.cpu.dtb +function_trace=false +function_trace_start=0 +itb=testsys.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +profile=0 +progress_interval=0 +simulate_stalls=false +system=testsys +width=1 +dcache_port=testsys.membus.port[3] +icache_port=testsys.membus.port[2] + +[testsys.cpu.dtb] +type=AlphaDTB +size=64 + +[testsys.cpu.itb] +type=AlphaITB +size=48 + +[testsys.disk0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=testsys.disk0.image + +[testsys.disk0.image] +type=CowDiskImage +children=child +child=testsys.disk0.image.child +read_only=false +table_size=65536 + +[testsys.disk0.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/myimg.img +read_only=true + +[testsys.disk2] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=testsys.disk2.image + +[testsys.disk2.image] +type=CowDiskImage +children=child +child=testsys.disk2.image.child +read_only=false +table_size=65536 + +[testsys.disk2.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-bigswap2.img +read_only=true + +[testsys.intrctrl] +type=IntrControl +cpu=testsys.cpu + +[testsys.iobus] +type=Bus +bus_id=0 +clock=1000 +responder_set=true +width=64 +default=testsys.tsunami.pciconfig.pio +port=testsys.bridge.side_a testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_sm_chip.pio testsys.tsunami.fake_uart1.pio testsys.tsunami.fake_uart2.pio testsys.tsunami.fake_uart3.pio testsys.tsunami.fake_uart4.pio testsys.tsunami.fake_ppc.pio testsys.tsunami.fake_OROM.pio testsys.tsunami.fake_pnp_addr.pio testsys.tsunami.fake_pnp_write.pio testsys.tsunami.fake_pnp_read0.pio testsys.tsunami.fake_pnp_read1.pio testsys.tsunami.fake_pnp_read2.pio testsys.tsunami.fake_pnp_read3.pio testsys.tsunami.fake_pnp_read4.pio testsys.tsunami.fake_pnp_read5.pio testsys.tsunami.fake_pnp_read6.pio testsys.tsunami.fake_pnp_read7.pio testsys.tsunami.fake_ata0.pio testsys.tsunami.fake_ata1.pio testsys.tsunami.fb.pio testsys.tsunami.io.pio testsys.tsunami.uart.pio testsys.tsunami.console.pio testsys.tsunami.ide.pio testsys.tsunami.ethernet.pio testsys.tsunami.ethernet.config testsys.tsunami.ethernet.dma testsys.tsunami.ide.config testsys.tsunami.ide.dma + +[testsys.membus] +type=Bus +children=responder +bus_id=1 +clock=1000 +responder_set=false +width=64 +default=testsys.membus.responder.pio +port=testsys.bridge.side_b testsys.physmem.port testsys.cpu.icache_port testsys.cpu.dcache_port + +[testsys.membus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=true +ret_data=255 +system=testsys +pio=testsys.membus.default + +[testsys.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=testsys.membus.port[1] + +[testsys.sim_console] +type=SimConsole +children=listener +append_name=true +intr_control=testsys.intrctrl +listener=testsys.sim_console.listener +number=0 +output=console + +[testsys.sim_console.listener] +type=ConsoleListener +port=3456 + +[testsys.simple_disk] +type=SimpleDisk +children=disk +disk=testsys.simple_disk.disk +system=testsys + +[testsys.simple_disk.disk] +type=RawDiskImage +image_file=/dist/m5/system/disks/myimg.img +read_only=true + +[testsys.tsunami] +type=Tsunami +children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +intrctrl=testsys.intrctrl +system=testsys + +[testsys.tsunami.cchip] +type=TsunamiCChip +pio_addr=8803072344064 +pio_latency=1000 +platform=testsys.tsunami +system=testsys +tsunami=testsys.tsunami +pio=testsys.iobus.port[1] + +[testsys.tsunami.console] +type=AlphaConsole +cpu=testsys.cpu +disk=testsys.simple_disk +pio_addr=8804682956800 +pio_latency=1000 +platform=testsys.tsunami +sim_console=testsys.sim_console +system=testsys +pio=testsys.iobus.port[25] + +[testsys.tsunami.etherint] +type=NSGigEInt +device=testsys.tsunami.ethernet +peer=Null + +[testsys.tsunami.ethernet] +type=NSGigE +children=configdata +clock=0 +config_latency=20000 +configdata=testsys.tsunami.ethernet.configdata +dma_data_free=false +dma_desc_free=false +dma_no_allocate=true +dma_read_delay=0 +dma_read_factor=0 +dma_write_delay=0 +dma_write_factor=0 +hardware_address=00:90:00:00:00:02 +intr_delay=10000000 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=1000 +platform=testsys.tsunami +rss=false +rx_delay=1000000 +rx_fifo_size=524288 +rx_filter=true +rx_thread=false +system=testsys +tx_delay=1000000 +tx_fifo_size=524288 +tx_thread=false +config=testsys.iobus.port[28] +dma=testsys.iobus.port[29] +pio=testsys.iobus.port[27] + +[testsys.tsunami.ethernet.configdata] +type=PciConfigData +BAR0=1 +BAR0Size=256 +BAR1=0 +BAR1Size=4096 +BAR2=0 +BAR2Size=0 +BAR3=0 +BAR3Size=0 +BAR4=0 +BAR4Size=0 +BAR5=0 +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=34 +ExpansionROM=0 +HeaderType=0 +InterruptLine=30 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=52 +MinimumGrant=176 +ProgIF=0 +Revision=0 +Status=656 +SubClassCode=0 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=4107 + +[testsys.tsunami.fake_OROM] +type=IsaFake +pio_addr=8796093677568 +pio_latency=1000 +pio_size=393216 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[9] + +[testsys.tsunami.fake_ata0] +type=IsaFake +pio_addr=8804615848432 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[20] + +[testsys.tsunami.fake_ata1] +type=IsaFake +pio_addr=8804615848304 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[21] + +[testsys.tsunami.fake_pnp_addr] +type=IsaFake +pio_addr=8804615848569 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[10] + +[testsys.tsunami.fake_pnp_read0] +type=IsaFake +pio_addr=8804615848451 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[12] + +[testsys.tsunami.fake_pnp_read1] +type=IsaFake +pio_addr=8804615848515 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[13] + +[testsys.tsunami.fake_pnp_read2] +type=IsaFake +pio_addr=8804615848579 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[14] + +[testsys.tsunami.fake_pnp_read3] +type=IsaFake +pio_addr=8804615848643 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[15] + +[testsys.tsunami.fake_pnp_read4] +type=IsaFake +pio_addr=8804615848707 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[16] + +[testsys.tsunami.fake_pnp_read5] +type=IsaFake +pio_addr=8804615848771 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[17] + +[testsys.tsunami.fake_pnp_read6] +type=IsaFake +pio_addr=8804615848835 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[18] + +[testsys.tsunami.fake_pnp_read7] +type=IsaFake +pio_addr=8804615848899 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[19] + +[testsys.tsunami.fake_pnp_write] +type=IsaFake +pio_addr=8804615850617 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[11] + +[testsys.tsunami.fake_ppc] +type=IsaFake +pio_addr=8804615848892 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[8] + +[testsys.tsunami.fake_sm_chip] +type=IsaFake +pio_addr=8804615848816 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[3] + +[testsys.tsunami.fake_uart1] +type=IsaFake +pio_addr=8804615848696 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[4] + +[testsys.tsunami.fake_uart2] +type=IsaFake +pio_addr=8804615848936 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[5] + +[testsys.tsunami.fake_uart3] +type=IsaFake +pio_addr=8804615848680 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[6] + +[testsys.tsunami.fake_uart4] +type=IsaFake +pio_addr=8804615848944 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[7] + +[testsys.tsunami.fb] +type=BadDevice +devicename=FrameBuffer +pio_addr=8804615848912 +pio_latency=1000 +platform=testsys.tsunami +system=testsys +pio=testsys.iobus.port[22] + +[testsys.tsunami.ide] +type=IdeController +children=configdata +config_latency=20000 +configdata=testsys.tsunami.ide.configdata +disks=testsys.disk0 testsys.disk2 +pci_bus=0 +pci_dev=0 +pci_func=0 +pio_latency=1000 +platform=testsys.tsunami +system=testsys +config=testsys.iobus.port[30] +dma=testsys.iobus.port[31] +pio=testsys.iobus.port[26] + +[testsys.tsunami.ide.configdata] +type=PciConfigData +BAR0=1 +BAR0Size=8 +BAR1=1 +BAR1Size=4 +BAR2=1 +BAR2Size=8 +BAR3=1 +BAR3Size=4 +BAR4=1 +BAR4Size=16 +BAR5=1 +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=0 +MinimumGrant=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 + +[testsys.tsunami.io] +type=TsunamiIO +frequency=976562500 +pio_addr=8804615847936 +pio_latency=1000 +platform=testsys.tsunami +system=testsys +time=1136073600 +tsunami=testsys.tsunami +pio=testsys.iobus.port[23] + +[testsys.tsunami.pchip] +type=TsunamiPChip +pio_addr=8802535473152 +pio_latency=1000 +platform=testsys.tsunami +system=testsys +tsunami=testsys.tsunami +pio=testsys.iobus.port[2] + +[testsys.tsunami.pciconfig] +type=PciConfigAll +bus=0 +pio_latency=1 +platform=testsys.tsunami +size=16777216 +system=testsys +pio=testsys.iobus.default + +[testsys.tsunami.uart] +type=Uart8250 +pio_addr=8804615848952 +pio_latency=1000 +platform=testsys.tsunami +sim_console=testsys.sim_console +system=testsys +pio=testsys.iobus.port[24] + +[trace] +bufsize=0 +cycle=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out b/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out new file mode 100644 index 000000000..19bb5af44 --- /dev/null +++ b/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out @@ -0,0 +1,1101 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[testsys.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[testsys] +type=LinuxAlphaSystem +boot_cpu_frequency=1 +physmem=testsys.physmem +mem_mode=atomic +kernel=/dist/m5/system/binaries/vmlinux +console=/dist/m5/system/binaries/console +pal=/dist/m5/system/binaries/ts_osfpal +boot_osflags=root=/dev/hda1 console=ttyS0 +readfile=/z/hsul/work/m5/newmem/configs/boot/netperf-stream-client.rcS +symbolfile= +init_param=0 +system_type=34 +system_rev=1024 + +[testsys.cpu.itb] +type=AlphaITB +size=48 + +[testsys.cpu.dtb] +type=AlphaDTB +size=64 + +[testsys.cpu] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=testsys +cpu_id=0 +itb=testsys.cpu.itb +dtb=testsys.cpu.dtb +profile=0 +do_quiesce=true +do_checkpoint_insts=true +do_statistics_insts=true +clock=1 +phase=0 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + +[testsys.intrctrl] +type=IntrControl +cpu=testsys.cpu + +[testsys.tsunami] +type=Tsunami +system=testsys +intrctrl=testsys.intrctrl + +[testsys.tsunami.ethernet.configdata] +type=PciConfigData +VendorID=4107 +DeviceID=34 +Command=0 +Status=656 +Revision=0 +ProgIF=0 +SubClassCode=0 +ClassCode=2 +CacheLineSize=0 +LatencyTimer=0 +HeaderType=0 +BIST=0 +BAR0=1 +BAR1=0 +BAR2=0 +BAR3=0 +BAR4=0 +BAR5=0 +CardbusCIS=0 +SubsystemVendorID=0 +SubsystemID=0 +ExpansionROM=0 +InterruptLine=30 +InterruptPin=1 +MinimumGrant=176 +MaximumLatency=52 +BAR0Size=256 +BAR1Size=4096 +BAR2Size=0 +BAR3Size=0 +BAR4Size=0 +BAR5Size=0 + +[testsys.tsunami.ethernet] +type=NSGigE +system=testsys +platform=testsys.tsunami +configdata=testsys.tsunami.ethernet.configdata +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=1000 +config_latency=20000 +clock=0 +dma_desc_free=false +dma_data_free=false +dma_read_delay=0 +dma_write_delay=0 +dma_read_factor=0 +dma_write_factor=0 +dma_no_allocate=true +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 +rx_fifo_size=524288 +tx_fifo_size=524288 +rx_filter=true +hardware_address=00:90:00:00:00:02 +rx_thread=false +tx_thread=false +rss=false + +[testsys.tsunami.etherint] +type=NSGigEInt +peer=null +device=testsys.tsunami.ethernet + +[drivesys.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[drivesys] +type=LinuxAlphaSystem +boot_cpu_frequency=1 +physmem=drivesys.physmem +mem_mode=atomic +kernel=/dist/m5/system/binaries/vmlinux +console=/dist/m5/system/binaries/console +pal=/dist/m5/system/binaries/ts_osfpal +boot_osflags=root=/dev/hda1 console=ttyS0 +readfile=/z/hsul/work/m5/newmem/configs/boot/netperf-server.rcS +symbolfile= +init_param=0 +system_type=34 +system_rev=1024 + +[drivesys.cpu.itb] +type=AlphaITB +size=48 + +[drivesys.cpu.dtb] +type=AlphaDTB +size=64 + +[drivesys.cpu] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=drivesys +cpu_id=0 +itb=drivesys.cpu.itb +dtb=drivesys.cpu.dtb +profile=0 +do_quiesce=true +do_checkpoint_insts=true +do_statistics_insts=true +clock=1 +phase=0 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + +[drivesys.intrctrl] +type=IntrControl +cpu=drivesys.cpu + +[drivesys.tsunami] +type=Tsunami +system=drivesys +intrctrl=drivesys.intrctrl + +[drivesys.tsunami.ethernet.configdata] +type=PciConfigData +VendorID=4107 +DeviceID=34 +Command=0 +Status=656 +Revision=0 +ProgIF=0 +SubClassCode=0 +ClassCode=2 +CacheLineSize=0 +LatencyTimer=0 +HeaderType=0 +BIST=0 +BAR0=1 +BAR1=0 +BAR2=0 +BAR3=0 +BAR4=0 +BAR5=0 +CardbusCIS=0 +SubsystemVendorID=0 +SubsystemID=0 +ExpansionROM=0 +InterruptLine=30 +InterruptPin=1 +MinimumGrant=176 +MaximumLatency=52 +BAR0Size=256 +BAR1Size=4096 +BAR2Size=0 +BAR3Size=0 +BAR4Size=0 +BAR5Size=0 + +[drivesys.tsunami.ethernet] +type=NSGigE +system=drivesys +platform=drivesys.tsunami +configdata=drivesys.tsunami.ethernet.configdata +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=1000 +config_latency=20000 +clock=0 +dma_desc_free=false +dma_data_free=false +dma_read_delay=0 +dma_write_delay=0 +dma_read_factor=0 +dma_write_factor=0 +dma_no_allocate=true +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 +rx_fifo_size=524288 +tx_fifo_size=524288 +rx_filter=true +hardware_address=00:90:00:00:00:02 +rx_thread=false +tx_thread=false +rss=false + +[drivesys.tsunami.etherint] +type=NSGigEInt +peer=null +device=drivesys.tsunami.ethernet + +[etherdump] +type=EtherDump +file=ethertrace +maxlen=96 + +[etherlink] +type=EtherLink +int1=testsys.tsunami.etherint +int2=drivesys.tsunami.etherint +speed=8000 +delay=0 +delay_var=0 +dump=etherdump + +[testsys.membus] +type=Bus +bus_id=1 +clock=1000 +width=64 +responder_set=false + +[testsys.membus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.bridge] +type=Bridge +queue_size_a=16 +queue_size_b=16 +delay=0 +write_ack=false + +[testsys.disk0.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/myimg.img +read_only=true + +[testsys.disk0.image] +type=CowDiskImage +child=testsys.disk0.image.child +image_file= +table_size=65536 +read_only=false + +[testsys.disk0] +type=IdeDisk +image=testsys.disk0.image +driveID=master +delay=1000000 + +[testsys.disk2.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-bigswap2.img +read_only=true + +[testsys.disk2.image] +type=CowDiskImage +child=testsys.disk2.image.child +image_file= +table_size=65536 +read_only=false + +[testsys.disk2] +type=IdeDisk +image=testsys.disk2.image +driveID=master +delay=1000000 + +[testsys.simple_disk.disk] +type=RawDiskImage +image_file=/dist/m5/system/disks/myimg.img +read_only=true + +[testsys.simple_disk] +type=SimpleDisk +system=testsys +disk=testsys.simple_disk.disk + +[testsys.tsunami.fake_uart1] +type=IsaFake +pio_addr=8804615848696 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_uart2] +type=IsaFake +pio_addr=8804615848936 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_uart3] +type=IsaFake +pio_addr=8804615848680 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_uart4] +type=IsaFake +pio_addr=8804615848944 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_ppc] +type=IsaFake +pio_addr=8804615848892 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.cchip] +type=TsunamiCChip +pio_addr=8803072344064 +pio_latency=1000 +platform=testsys.tsunami +system=testsys +tsunami=testsys.tsunami + +[testsys.tsunami.io] +type=TsunamiIO +pio_addr=8804615847936 +pio_latency=1000 +frequency=976562500 +platform=testsys.tsunami +system=testsys +time=1136073600 +tsunami=testsys.tsunami + +[] +type=PciConfigAll +pio_latency=1 +bus=0 +size=16777216 +platform=testsys.tsunami +system=testsys + +[testsys.sim_console.listener] +type=ConsoleListener +port=3456 + +[testsys.sim_console] +type=SimConsole +listener=testsys.sim_console.listener +intr_control=testsys.intrctrl +output=console +append_name=true +number=0 + +[testsys.tsunami.console] +type=AlphaConsole +sim_console=testsys.sim_console +disk=testsys.simple_disk +pio_addr=8804682956800 +system=testsys +cpu=testsys.cpu +platform=testsys.tsunami +pio_latency=1000 + +[testsys.tsunami.fake_ata1] +type=IsaFake +pio_addr=8804615848304 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_ata0] +type=IsaFake +pio_addr=8804615848432 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.pchip] +type=TsunamiPChip +pio_addr=8802535473152 +pio_latency=1000 +platform=testsys.tsunami +system=testsys +tsunami=testsys.tsunami + +[testsys.tsunami.fake_pnp_read3] +type=IsaFake +pio_addr=8804615848643 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_pnp_read2] +type=IsaFake +pio_addr=8804615848579 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_pnp_read1] +type=IsaFake +pio_addr=8804615848515 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_pnp_read0] +type=IsaFake +pio_addr=8804615848451 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_pnp_read7] +type=IsaFake +pio_addr=8804615848899 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_pnp_read6] +type=IsaFake +pio_addr=8804615848835 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_pnp_read5] +type=IsaFake +pio_addr=8804615848771 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_pnp_read4] +type=IsaFake +pio_addr=8804615848707 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_pnp_write] +type=IsaFake +pio_addr=8804615850617 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fb] +type=BadDevice +devicename=FrameBuffer +pio_addr=8804615848912 +system=testsys +platform=testsys.tsunami +pio_latency=1000 + +[testsys.tsunami.fake_OROM] +type=IsaFake +pio_addr=8796093677568 +pio_latency=1000 +pio_size=393216 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.uart] +type=Uart8250 +pio_addr=8804615848952 +pio_latency=1000 +platform=testsys.tsunami +sim_console=testsys.sim_console +system=testsys + +[testsys.tsunami.fake_sm_chip] +type=IsaFake +pio_addr=8804615848816 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_pnp_addr] +type=IsaFake +pio_addr=8804615848569 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.ide.configdata] +type=PciConfigData +VendorID=32902 +DeviceID=28945 +Command=0 +Status=640 +Revision=0 +ProgIF=133 +SubClassCode=1 +ClassCode=1 +CacheLineSize=0 +LatencyTimer=0 +HeaderType=0 +BIST=0 +BAR0=1 +BAR1=1 +BAR2=1 +BAR3=1 +BAR4=1 +BAR5=1 +CardbusCIS=0 +SubsystemVendorID=0 +SubsystemID=0 +ExpansionROM=0 +InterruptLine=31 +InterruptPin=1 +MinimumGrant=0 +MaximumLatency=0 +BAR0Size=8 +BAR1Size=4 +BAR2Size=8 +BAR3Size=4 +BAR4Size=16 +BAR5Size=0 + +[testsys.tsunami.ide] +type=IdeController +system=testsys +platform=testsys.tsunami +configdata=testsys.tsunami.ide.configdata +pci_bus=0 +pci_dev=0 +pci_func=0 +pio_latency=1000 +config_latency=20000 +disks=testsys.disk0 testsys.disk2 + +[testsys.iobus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=true + +[drivesys.membus] +type=Bus +bus_id=1 +clock=1000 +width=64 +responder_set=false + +[drivesys.membus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.bridge] +type=Bridge +queue_size_a=16 +queue_size_b=16 +delay=0 +write_ack=false + +[drivesys.disk0.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/myimg.img +read_only=true + +[drivesys.disk0.image] +type=CowDiskImage +child=drivesys.disk0.image.child +image_file= +table_size=65536 +read_only=false + +[drivesys.disk0] +type=IdeDisk +image=drivesys.disk0.image +driveID=master +delay=1000000 + +[drivesys.disk2.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-bigswap2.img +read_only=true + +[drivesys.disk2.image] +type=CowDiskImage +child=drivesys.disk2.image.child +image_file= +table_size=65536 +read_only=false + +[drivesys.disk2] +type=IdeDisk +image=drivesys.disk2.image +driveID=master +delay=1000000 + +[drivesys.simple_disk.disk] +type=RawDiskImage +image_file=/dist/m5/system/disks/myimg.img +read_only=true + +[drivesys.simple_disk] +type=SimpleDisk +system=drivesys +disk=drivesys.simple_disk.disk + +[drivesys.tsunami.fake_uart1] +type=IsaFake +pio_addr=8804615848696 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_uart2] +type=IsaFake +pio_addr=8804615848936 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_uart3] +type=IsaFake +pio_addr=8804615848680 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_uart4] +type=IsaFake +pio_addr=8804615848944 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_ppc] +type=IsaFake +pio_addr=8804615848892 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.cchip] +type=TsunamiCChip +pio_addr=8803072344064 +pio_latency=1000 +platform=drivesys.tsunami +system=drivesys +tsunami=drivesys.tsunami + +[drivesys.tsunami.io] +type=TsunamiIO +pio_addr=8804615847936 +pio_latency=1000 +frequency=976562500 +platform=drivesys.tsunami +system=drivesys +time=1136073600 +tsunami=drivesys.tsunami + +[] +type=PciConfigAll +pio_latency=1 +bus=0 +size=16777216 +platform=drivesys.tsunami +system=drivesys + +[drivesys.sim_console.listener] +type=ConsoleListener +port=3456 + +[drivesys.sim_console] +type=SimConsole +listener=drivesys.sim_console.listener +intr_control=drivesys.intrctrl +output=console +append_name=true +number=0 + +[drivesys.tsunami.console] +type=AlphaConsole +sim_console=drivesys.sim_console +disk=drivesys.simple_disk +pio_addr=8804682956800 +system=drivesys +cpu=drivesys.cpu +platform=drivesys.tsunami +pio_latency=1000 + +[drivesys.tsunami.fake_ata1] +type=IsaFake +pio_addr=8804615848304 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_ata0] +type=IsaFake +pio_addr=8804615848432 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.pchip] +type=TsunamiPChip +pio_addr=8802535473152 +pio_latency=1000 +platform=drivesys.tsunami +system=drivesys +tsunami=drivesys.tsunami + +[drivesys.tsunami.fake_pnp_read3] +type=IsaFake +pio_addr=8804615848643 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_pnp_read2] +type=IsaFake +pio_addr=8804615848579 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_pnp_read1] +type=IsaFake +pio_addr=8804615848515 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_pnp_read0] +type=IsaFake +pio_addr=8804615848451 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_pnp_read7] +type=IsaFake +pio_addr=8804615848899 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_pnp_read6] +type=IsaFake +pio_addr=8804615848835 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_pnp_read5] +type=IsaFake +pio_addr=8804615848771 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_pnp_read4] +type=IsaFake +pio_addr=8804615848707 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_pnp_write] +type=IsaFake +pio_addr=8804615850617 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fb] +type=BadDevice +devicename=FrameBuffer +pio_addr=8804615848912 +system=drivesys +platform=drivesys.tsunami +pio_latency=1000 + +[drivesys.tsunami.fake_OROM] +type=IsaFake +pio_addr=8796093677568 +pio_latency=1000 +pio_size=393216 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.uart] +type=Uart8250 +pio_addr=8804615848952 +pio_latency=1000 +platform=drivesys.tsunami +sim_console=drivesys.sim_console +system=drivesys + +[drivesys.tsunami.fake_sm_chip] +type=IsaFake +pio_addr=8804615848816 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_pnp_addr] +type=IsaFake +pio_addr=8804615848569 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.ide.configdata] +type=PciConfigData +VendorID=32902 +DeviceID=28945 +Command=0 +Status=640 +Revision=0 +ProgIF=133 +SubClassCode=1 +ClassCode=1 +CacheLineSize=0 +LatencyTimer=0 +HeaderType=0 +BIST=0 +BAR0=1 +BAR1=1 +BAR2=1 +BAR3=1 +BAR4=1 +BAR5=1 +CardbusCIS=0 +SubsystemVendorID=0 +SubsystemID=0 +ExpansionROM=0 +InterruptLine=31 +InterruptPin=1 +MinimumGrant=0 +MaximumLatency=0 +BAR0Size=8 +BAR1Size=4 +BAR2Size=8 +BAR3Size=4 +BAR4Size=16 +BAR5Size=0 + +[drivesys.tsunami.ide] +type=IdeController +system=drivesys +platform=drivesys.tsunami +configdata=drivesys.tsunami.ide.configdata +pci_bus=0 +pci_dev=0 +pci_func=0 +pio_latency=1000 +config_latency=20000 +disks=drivesys.disk0 drivesys.disk2 + +[drivesys.iobus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=true + +[trace] +flags= +start=0 +cycle=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +legion_lockstep=false +trace_system=client + +[statsreset] +reset_cycle=0 + diff --git a/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console b/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console new file mode 100644 index 000000000..931411c03 --- /dev/null +++ b/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console @@ -0,0 +1,111 @@ +M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 + Got Configuration 623 + memsize 8000000 pages 4000 + First free page after ROM 0xFFFFFC0000018000 + HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 + kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 + CPU Clock at 1000000 MHz IntrClockFrequency=1024 + Booting with 1 processor(s) + KSP: 0x20043FE8 PTBR 0x20 + Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 + Memory cluster 0 [0 - 392] + Memory cluster 1 [392 - 15992] + Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 + ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 + unix_boot_mem ends at FFFFFC0000076000 + k_argc = 0 + jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) + CallbackFixup 0 18000, t7=FFFFFC000070C000 + Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 + Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM + Major Options: SMP LEGACY_START VERBOSE_MCHECK + Command line: root=/dev/hda1 console=ttyS0 + memcluster 0, usage 1, start 0, end 392 + memcluster 1, usage 0, start 392, end 16384 + freeing pages 1069:16384 + reserving pages 1069:1070 + SMP: 1 CPUs probed -- cpu_present_mask = 1 + Built 1 zonelists + Kernel command line: root=/dev/hda1 console=ttyS0 + PID hash table entries: 1024 (order: 10, 32768 bytes) + Using epoch = 1900 + Console: colour dummy device 80x25 + Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) + Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) + Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) + Mount-cache hash table entries: 512 + SMP mode deactivated. + Brought up 1 CPUs + SMP: Total of 1 processors activated (1998756.81 BogoMIPS). + NET: Registered protocol family 16 + EISA bus registered + pci: enabling save/restore of SRM state + SCSI subsystem initialized + srm_env: version 0.0.5 loaded successfully + Installing knfsd (copyright (C) 1996 okir@monad.swb.de). + Initializing Cryptographic API + rtc: Standard PC (1900) epoch (1900) detected + Real Time Clock Driver v1.12 + Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled + ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 + io scheduler noop registered + io scheduler anticipatory registered + io scheduler deadline registered + io scheduler cfq registered + loop: loaded (max 8 devices) + nbd: registered device at major 43 + ns83820.c: National Semiconductor DP83820 10/100/1000 driver. + eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 + eth0: enabling optical transceiver + eth0: using 64 bit addressing. + eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:02 io=0x09000000 irq=30 f=h,sg + tun: Universal TUN/TAP device driver, 1.6 + tun: (C) 1999-2004 Max Krasnyansky + Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 + ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx + PIIX4: IDE controller at PCI slot 0000:00:00.0 + PIIX4: chipset revision 0 + PIIX4: 100% native mode on irq 31 + ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA + ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA + hda: M5 IDE Disk, ATA DISK drive + hdb: M5 IDE Disk, ATA DISK drive + ide0 at 0x8410-0x8417,0x8422 on irq 31 + hda: max request size: 128KiB + hda: 409248 sectors (209 MB), CHS=406/16/63, UDMA(33) + hda: cache flushes not supported + hda: hda1 + hdb: max request size: 128KiB + hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) + hdb: cache flushes not supported + hdb: unknown partition table + mice: PS/2 mouse device common for all mice + NET: Registered protocol family 2 + IP route cache hash table entries: 4096 (order: 2, 32768 bytes) + TCP established hash table entries: 16384 (order: 5, 262144 bytes) + TCP bind hash table entries: 16384 (order: 5, 262144 bytes) + TCP: Hash tables configured (established 16384 bind 16384) + TCP reno registered + ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack + ip_tables: (C) 2000-2002 Netfilter core team + arp_tables: (C) 2002 David S. Miller + TCP bic registered + Initializing IPsec netlink socket + NET: Registered protocol family 1 + NET: Registered protocol family 17 + NET: Registered protocol family 15 + Bridge firewalling registered + 802.1Q VLAN Support v1.8 Ben Greear + All bugs added by David S. Miller + VFS: Mounted root (ext2 filesystem) readonly. + Freeing unused kernel memory: 224k freed + init started: BusyBox v1.1.0 (2006.10.31-01:25+0000) multi-call binary +mounting filesystems... +loading script... +setting up network... +eth0: link now 1000F mbps, full duplex and up. + running netserver... +Starting netserver at port 12865 +signal client to begin...done. +starting bash... +# \ No newline at end of file diff --git a/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console b/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console new file mode 100644 index 000000000..aea9af01d --- /dev/null +++ b/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console @@ -0,0 +1,120 @@ +M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 + Got Configuration 623 + memsize 8000000 pages 4000 + First free page after ROM 0xFFFFFC0000018000 + HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 + kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 + CPU Clock at 1000000 MHz IntrClockFrequency=1024 + Booting with 1 processor(s) + KSP: 0x20043FE8 PTBR 0x20 + Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 + Memory cluster 0 [0 - 392] + Memory cluster 1 [392 - 15992] + Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 + ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 + unix_boot_mem ends at FFFFFC0000076000 + k_argc = 0 + jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) + CallbackFixup 0 18000, t7=FFFFFC000070C000 + Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 + Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM + Major Options: SMP LEGACY_START VERBOSE_MCHECK + Command line: root=/dev/hda1 console=ttyS0 + memcluster 0, usage 1, start 0, end 392 + memcluster 1, usage 0, start 392, end 16384 + freeing pages 1069:16384 + reserving pages 1069:1070 + SMP: 1 CPUs probed -- cpu_present_mask = 1 + Built 1 zonelists + Kernel command line: root=/dev/hda1 console=ttyS0 + PID hash table entries: 1024 (order: 10, 32768 bytes) + Using epoch = 1900 + Console: colour dummy device 80x25 + Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) + Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) + Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) + Mount-cache hash table entries: 512 + SMP mode deactivated. + Brought up 1 CPUs + SMP: Total of 1 processors activated (1998756.81 BogoMIPS). + NET: Registered protocol family 16 + EISA bus registered + pci: enabling save/restore of SRM state + SCSI subsystem initialized + srm_env: version 0.0.5 loaded successfully + Installing knfsd (copyright (C) 1996 okir@monad.swb.de). + Initializing Cryptographic API + rtc: Standard PC (1900) epoch (1900) detected + Real Time Clock Driver v1.12 + Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled + ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 + io scheduler noop registered + io scheduler anticipatory registered + io scheduler deadline registered + io scheduler cfq registered + loop: loaded (max 8 devices) + nbd: registered device at major 43 + ns83820.c: National Semiconductor DP83820 10/100/1000 driver. + eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 + eth0: enabling optical transceiver + eth0: using 64 bit addressing. + eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:02 io=0x09000000 irq=30 f=h,sg + tun: Universal TUN/TAP device driver, 1.6 + tun: (C) 1999-2004 Max Krasnyansky + Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 + ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx + PIIX4: IDE controller at PCI slot 0000:00:00.0 + PIIX4: chipset revision 0 + PIIX4: 100% native mode on irq 31 + ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA + ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA + hda: M5 IDE Disk, ATA DISK drive + hdb: M5 IDE Disk, ATA DISK drive + ide0 at 0x8410-0x8417,0x8422 on irq 31 + hda: max request size: 128KiB + hda: 409248 sectors (209 MB), CHS=406/16/63, UDMA(33) + hda: cache flushes not supported + hda: hda1 + hdb: max request size: 128KiB + hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) + hdb: cache flushes not supported + hdb: unknown partition table + mice: PS/2 mouse device common for all mice + NET: Registered protocol family 2 + IP route cache hash table entries: 4096 (order: 2, 32768 bytes) + TCP established hash table entries: 16384 (order: 5, 262144 bytes) + TCP bind hash table entries: 16384 (order: 5, 262144 bytes) + TCP: Hash tables configured (established 16384 bind 16384) + TCP reno registered + ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack + ip_tables: (C) 2000-2002 Netfilter core team + arp_tables: (C) 2002 David S. Miller + TCP bic registered + Initializing IPsec netlink socket + NET: Registered protocol family 1 + NET: Registered protocol family 17 + NET: Registered protocol family 15 + Bridge firewalling registered + 802.1Q VLAN Support v1.8 Ben Greear + All bugs added by David S. Miller + VFS: Mounted root (ext2 filesystem) readonly. + Freeing unused kernel memory: 224k freed + init started: BusyBox v1.1.0 (2006.10.31-01:25+0000) multi-call binary +mounting filesystems... +loading script... +setting up network... +eth0: link now 1000F mbps, full duplex and up. + waiting for server...server ready +starting test... +netperf warmup +/benchmarks/netperf-bin/netperf -H 10.0.0.1 -t TCP_STREAM -l -100k +TCP STREAM TEST to 10.0.0.1 : dirty data +Recv Send Send +Socket Socket Message Elapsed +Size Size Size Time Throughput +bytes bytes bytes secs. 10^6bits/sec + +5000000 5000000 5000000 1.29 30.91 +netperf benchmark +/benchmarks/netperf-bin/netperf -H 10.0.0.1 -t TCP_STREAM -k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144 +TCP STREAM TEST to 10.0.0.1 : dirty data diff --git a/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt b/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt new file mode 100644 index 000000000..328846907 --- /dev/null +++ b/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt @@ -0,0 +1,476 @@ + +---------- Begin Simulation Statistics ---------- +drivesys.cpu.dtb.accesses 401302 # DTB accesses +drivesys.cpu.dtb.acv 40 # DTB access violations +drivesys.cpu.dtb.hits 624298 # DTB hits +drivesys.cpu.dtb.misses 569 # DTB misses +drivesys.cpu.dtb.read_accesses 268057 # DTB read accesses +drivesys.cpu.dtb.read_acv 30 # DTB read access violations +drivesys.cpu.dtb.read_hits 393538 # DTB read hits +drivesys.cpu.dtb.read_misses 487 # DTB read misses +drivesys.cpu.dtb.write_accesses 133245 # DTB write accesses +drivesys.cpu.dtb.write_acv 10 # DTB write access violations +drivesys.cpu.dtb.write_hits 230760 # DTB write hits +drivesys.cpu.dtb.write_misses 82 # DTB write misses +drivesys.cpu.idle_fraction 1.000000 # Percentage of idle cycles +drivesys.cpu.itb.accesses 1337980 # ITB accesses +drivesys.cpu.itb.acv 22 # ITB acv +drivesys.cpu.itb.hits 1337786 # ITB hits +drivesys.cpu.itb.misses 194 # ITB misses +drivesys.cpu.kern.callpal 4443 # number of callpals executed +drivesys.cpu.kern.callpal_swpctx 70 1.58% 1.58% # number of callpals executed +drivesys.cpu.kern.callpal_tbi 5 0.11% 1.69% # number of callpals executed +drivesys.cpu.kern.callpal_swpipl 3654 82.24% 83.93% # number of callpals executed +drivesys.cpu.kern.callpal_rdps 359 8.08% 92.01% # number of callpals executed +drivesys.cpu.kern.callpal_rdusp 1 0.02% 92.03% # number of callpals executed +drivesys.cpu.kern.callpal_rti 322 7.25% 99.28% # number of callpals executed +drivesys.cpu.kern.callpal_callsys 25 0.56% 99.84% # number of callpals executed +drivesys.cpu.kern.callpal_imb 7 0.16% 100.00% # number of callpals executed +drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed +drivesys.cpu.kern.inst.hwrei 5483 # number of hwrei instructions executed +drivesys.cpu.kern.inst.quiesce 215 # number of quiesce instructions executed +drivesys.cpu.kern.ipl_count 4191 # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count_0 1189 28.37% 28.37% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count_21 10 0.24% 28.61% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count_22 205 4.89% 33.50% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count_31 2787 66.50% 100.00% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_good 2593 # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good_0 1189 45.85% 45.85% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good_21 10 0.39% 46.24% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good_22 205 7.91% 54.15% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good_31 1189 45.85% 100.00% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_ticks 199572064366 # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks_0 199571744403 100.00% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks_21 1620 0.00% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks_31 300713 0.00% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_used 0.618707 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used_0 1 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used_31 0.426624 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.mode_good_kernel 110 +drivesys.cpu.kern.mode_good_user 107 +drivesys.cpu.kern.mode_good_idle 3 +drivesys.cpu.kern.mode_switch_kernel 174 # number of protection mode switches +drivesys.cpu.kern.mode_switch_user 107 # number of protection mode switches +drivesys.cpu.kern.mode_switch_idle 218 # number of protection mode switches +drivesys.cpu.kern.mode_switch_good 0.440882 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good_kernel 0.632184 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good_idle 0.013761 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_ticks_kernel 263475 0.24% 0.24% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_user 1278343 1.18% 1.43% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_idle 106483912 98.57% 100.00% # number of ticks spent at the given mode +drivesys.cpu.kern.swap_context 70 # number of times the context was actually changed +drivesys.cpu.kern.syscall 22 # number of syscalls executed +drivesys.cpu.kern.syscall_2 1 4.55% 4.55% # number of syscalls executed +drivesys.cpu.kern.syscall_6 3 13.64% 18.18% # number of syscalls executed +drivesys.cpu.kern.syscall_17 2 9.09% 27.27% # number of syscalls executed +drivesys.cpu.kern.syscall_97 1 4.55% 31.82% # number of syscalls executed +drivesys.cpu.kern.syscall_99 2 9.09% 40.91% # number of syscalls executed +drivesys.cpu.kern.syscall_101 2 9.09% 50.00% # number of syscalls executed +drivesys.cpu.kern.syscall_102 3 13.64% 63.64% # number of syscalls executed +drivesys.cpu.kern.syscall_104 1 4.55% 68.18% # number of syscalls executed +drivesys.cpu.kern.syscall_105 3 13.64% 81.82% # number of syscalls executed +drivesys.cpu.kern.syscall_106 1 4.55% 86.36% # number of syscalls executed +drivesys.cpu.kern.syscall_118 2 9.09% 95.45% # number of syscalls executed +drivesys.cpu.kern.syscall_150 1 4.55% 100.00% # number of syscalls executed +drivesys.cpu.not_idle_fraction 0.000000 # Percentage of non-idle cycles +drivesys.cpu.numCycles 1959293 # number of cpu cycles simulated +drivesys.cpu.num_insts 1959077 # Number of instructions executed +drivesys.cpu.num_refs 626286 # Number of memory references +drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). +drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. +drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions. +drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. +drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions. +drivesys.tsunami.ethernet.coalescedRxDesc 1 # average number of RxDesc's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +drivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post +drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +drivesys.tsunami.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +drivesys.tsunami.ethernet.descDMAReads 5 # Number of descriptors the device read w/ DMA +drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA +drivesys.tsunami.ethernet.descDmaReadBytes 120 # number of descriptor bytes read w/ DMA +drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA +drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped +drivesys.tsunami.ethernet.postedInterrupts 10 # number of posts to CPU +drivesys.tsunami.ethernet.postedRxDesc 6 # number of RxDesc interrupts posted to CPU +drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +drivesys.tsunami.ethernet.postedTxIdle 4 # number of TxIdle interrupts posted to CPU +drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +drivesys.tsunami.ethernet.rxBandwidth 38400 # Receive Bandwidth (bits/s) +drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received +drivesys.tsunami.ethernet.rxIpChecksums 8 # Number of rx IP Checksums done by device +drivesys.tsunami.ethernet.rxPPS 40 # Packet Reception Rate (packets/s) +drivesys.tsunami.ethernet.rxPackets 8 # Number of Packets Received +drivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device +drivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device +drivesys.tsunami.ethernet.totBandwidth 70320 # Total Bandwidth (bits/s) +drivesys.tsunami.ethernet.totBytes 1758 # Total Bytes +drivesys.tsunami.ethernet.totPackets 13 # Total Packets +drivesys.tsunami.ethernet.totalRxDesc 8 # total number of RxDesc written to ISR +drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +drivesys.tsunami.ethernet.totalTxIdle 5 # total number of TxIdle written to ISR +drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +drivesys.tsunami.ethernet.txBandwidth 31920 # Transmit Bandwidth (bits/s) +drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted +drivesys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device +drivesys.tsunami.ethernet.txPPS 25 # Packet Tranmission Rate (packets/s) +drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted +drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device +drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +host_inst_rate 38374803 # Simulator instruction rate (inst/s) +host_mem_usage 411180 # Number of bytes of host memory used +host_seconds 7.20 # Real time elapsed on the host +host_tick_rate 27794359444 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 276122825 # Number of instructions simulated +sim_seconds 0.200001 # Number of seconds simulated +sim_ticks 200000789468 # Number of ticks simulated +testsys.cpu.dtb.accesses 335402 # DTB accesses +testsys.cpu.dtb.acv 161 # DTB access violations +testsys.cpu.dtb.hits 1163399 # DTB hits +testsys.cpu.dtb.misses 3815 # DTB misses +testsys.cpu.dtb.read_accesses 225414 # DTB read accesses +testsys.cpu.dtb.read_acv 80 # DTB read access violations +testsys.cpu.dtb.read_hits 658556 # DTB read hits +testsys.cpu.dtb.read_misses 3287 # DTB read misses +testsys.cpu.dtb.write_accesses 109988 # DTB write accesses +testsys.cpu.dtb.write_acv 81 # DTB write access violations +testsys.cpu.dtb.write_hits 504843 # DTB write hits +testsys.cpu.dtb.write_misses 528 # DTB write misses +testsys.cpu.idle_fraction 0.999999 # Percentage of idle cycles +testsys.cpu.itb.accesses 1249804 # ITB accesses +testsys.cpu.itb.acv 69 # ITB acv +testsys.cpu.itb.hits 1248307 # ITB hits +testsys.cpu.itb.misses 1497 # ITB misses +testsys.cpu.kern.callpal 13124 # number of callpals executed +testsys.cpu.kern.callpal_swpctx 440 3.35% 3.35% # number of callpals executed +testsys.cpu.kern.callpal_tbi 20 0.15% 3.51% # number of callpals executed +testsys.cpu.kern.callpal_swpipl 11075 84.39% 87.89% # number of callpals executed +testsys.cpu.kern.callpal_rdps 359 2.74% 90.63% # number of callpals executed +testsys.cpu.kern.callpal_wrusp 3 0.02% 90.65% # number of callpals executed +testsys.cpu.kern.callpal_rdusp 3 0.02% 90.67% # number of callpals executed +testsys.cpu.kern.callpal_rti 1040 7.92% 98.60% # number of callpals executed +testsys.cpu.kern.callpal_callsys 140 1.07% 99.66% # number of callpals executed +testsys.cpu.kern.callpal_imb 44 0.34% 100.00% # number of callpals executed +testsys.cpu.kern.inst.arm 0 # number of arm instructions executed +testsys.cpu.kern.inst.hwrei 19054 # number of hwrei instructions executed +testsys.cpu.kern.inst.quiesce 377 # number of quiesce instructions executed +testsys.cpu.kern.ipl_count 12503 # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_0 5061 40.48% 40.48% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_21 183 1.46% 41.94% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_22 205 1.64% 43.58% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_31 7054 56.42% 100.00% # number of times we switched to this ipl +testsys.cpu.kern.ipl_good 10498 # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good_0 5055 48.15% 48.15% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good_21 183 1.74% 49.90% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good_22 205 1.95% 51.85% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good_31 5055 48.15% 100.00% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_ticks 199569923608 # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_0 199569308038 100.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_21 30857 0.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_31 567083 0.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_used 0.839638 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used_0 0.998814 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used_31 0.716615 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.mode_good_kernel 654 +testsys.cpu.kern.mode_good_user 649 +testsys.cpu.kern.mode_good_idle 5 +testsys.cpu.kern.mode_switch_kernel 1100 # number of protection mode switches +testsys.cpu.kern.mode_switch_user 649 # number of protection mode switches +testsys.cpu.kern.mode_switch_idle 381 # number of protection mode switches +testsys.cpu.kern.mode_switch_good 0.614085 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_kernel 0.594545 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_idle 0.013123 # fraction of useful protection mode switches +testsys.cpu.kern.mode_ticks_kernel 1821232 2.16% 2.16% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_user 1065606 1.26% 3.42% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_idle 81402474 96.58% 100.00% # number of ticks spent at the given mode +testsys.cpu.kern.swap_context 440 # number of times the context was actually changed +testsys.cpu.kern.syscall 83 # number of syscalls executed +testsys.cpu.kern.syscall_2 3 3.61% 3.61% # number of syscalls executed +testsys.cpu.kern.syscall_3 7 8.43% 12.05% # number of syscalls executed +testsys.cpu.kern.syscall_4 1 1.20% 13.25% # number of syscalls executed +testsys.cpu.kern.syscall_6 7 8.43% 21.69% # number of syscalls executed +testsys.cpu.kern.syscall_17 7 8.43% 30.12% # number of syscalls executed +testsys.cpu.kern.syscall_19 2 2.41% 32.53% # number of syscalls executed +testsys.cpu.kern.syscall_20 1 1.20% 33.73% # number of syscalls executed +testsys.cpu.kern.syscall_33 3 3.61% 37.35% # number of syscalls executed +testsys.cpu.kern.syscall_45 10 12.05% 49.40% # number of syscalls executed +testsys.cpu.kern.syscall_48 5 6.02% 55.42% # number of syscalls executed +testsys.cpu.kern.syscall_54 1 1.20% 56.63% # number of syscalls executed +testsys.cpu.kern.syscall_59 3 3.61% 60.24% # number of syscalls executed +testsys.cpu.kern.syscall_71 15 18.07% 78.31% # number of syscalls executed +testsys.cpu.kern.syscall_74 4 4.82% 83.13% # number of syscalls executed +testsys.cpu.kern.syscall_97 2 2.41% 85.54% # number of syscalls executed +testsys.cpu.kern.syscall_98 2 2.41% 87.95% # number of syscalls executed +testsys.cpu.kern.syscall_101 2 2.41% 90.36% # number of syscalls executed +testsys.cpu.kern.syscall_102 2 2.41% 92.77% # number of syscalls executed +testsys.cpu.kern.syscall_104 1 1.20% 93.98% # number of syscalls executed +testsys.cpu.kern.syscall_105 3 3.61% 97.59% # number of syscalls executed +testsys.cpu.kern.syscall_118 2 2.41% 100.00% # number of syscalls executed +testsys.cpu.not_idle_fraction 0.000001 # Percentage of non-idle cycles +testsys.cpu.numCycles 3566237 # number of cpu cycles simulated +testsys.cpu.num_insts 3564671 # Number of instructions executed +testsys.cpu.num_refs 1173698 # Number of memory references +testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). +testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. +testsys.disk0.dma_write_txs 0 # Number of DMA write transactions. +testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. +testsys.disk2.dma_write_txs 0 # Number of DMA write transactions. +testsys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +testsys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +testsys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post +testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post +testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +testsys.tsunami.ethernet.descDMAReads 8 # Number of descriptors the device read w/ DMA +testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA +testsys.tsunami.ethernet.descDmaReadBytes 192 # number of descriptor bytes read w/ DMA +testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA +testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped +testsys.tsunami.ethernet.postedInterrupts 10 # number of posts to CPU +testsys.tsunami.ethernet.postedRxDesc 4 # number of RxDesc interrupts posted to CPU +testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +testsys.tsunami.ethernet.postedTxIdle 6 # number of TxIdle interrupts posted to CPU +testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +testsys.tsunami.ethernet.rxBandwidth 31920 # Receive Bandwidth (bits/s) +testsys.tsunami.ethernet.rxBytes 798 # Bytes Received +testsys.tsunami.ethernet.rxIpChecksums 5 # Number of rx IP Checksums done by device +testsys.tsunami.ethernet.rxPPS 25 # Packet Reception Rate (packets/s) +testsys.tsunami.ethernet.rxPackets 5 # Number of Packets Received +testsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device +testsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device +testsys.tsunami.ethernet.totBandwidth 70320 # Total Bandwidth (bits/s) +testsys.tsunami.ethernet.totBytes 1758 # Total Bytes +testsys.tsunami.ethernet.totPackets 13 # Total Packets +testsys.tsunami.ethernet.totalRxDesc 5 # total number of RxDesc written to ISR +testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +testsys.tsunami.ethernet.totalTxIdle 8 # total number of TxIdle written to ISR +testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +testsys.tsunami.ethernet.txBandwidth 38400 # Transmit Bandwidth (bits/s) +testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted +testsys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device +testsys.tsunami.ethernet.txPPS 40 # Packet Tranmission Rate (packets/s) +testsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted +testsys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device +testsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device + +---------- End Simulation Statistics ---------- + +---------- Begin Simulation Statistics ---------- +drivesys.cpu.dtb.accesses 0 # DTB accesses +drivesys.cpu.dtb.acv 0 # DTB access violations +drivesys.cpu.dtb.hits 0 # DTB hits +drivesys.cpu.dtb.misses 0 # DTB misses +drivesys.cpu.dtb.read_accesses 0 # DTB read accesses +drivesys.cpu.dtb.read_acv 0 # DTB read access violations +drivesys.cpu.dtb.read_hits 0 # DTB read hits +drivesys.cpu.dtb.read_misses 0 # DTB read misses +drivesys.cpu.dtb.write_accesses 0 # DTB write accesses +drivesys.cpu.dtb.write_acv 0 # DTB write access violations +drivesys.cpu.dtb.write_hits 0 # DTB write hits +drivesys.cpu.dtb.write_misses 0 # DTB write misses +drivesys.cpu.idle_fraction 1 # Percentage of idle cycles +drivesys.cpu.itb.accesses 0 # ITB accesses +drivesys.cpu.itb.acv 0 # ITB acv +drivesys.cpu.itb.hits 0 # ITB hits +drivesys.cpu.itb.misses 0 # ITB misses +drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed +drivesys.cpu.kern.inst.hwrei 0 # number of hwrei instructions executed +drivesys.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed +drivesys.cpu.kern.mode_good_kernel 0 +drivesys.cpu.kern.mode_good_user 0 +drivesys.cpu.kern.mode_good_idle 0 +drivesys.cpu.kern.mode_switch_kernel 0 # number of protection mode switches +drivesys.cpu.kern.mode_switch_user 0 # number of protection mode switches +drivesys.cpu.kern.mode_switch_idle 0 # number of protection mode switches +drivesys.cpu.kern.mode_switch_good # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good_kernel # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good_user # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good_idle # fraction of useful protection mode switches +drivesys.cpu.kern.mode_ticks_kernel 0 # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_user 0 # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_idle 0 # number of ticks spent at the given mode +drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed +drivesys.cpu.not_idle_fraction 0 # Percentage of non-idle cycles +drivesys.cpu.numCycles 0 # number of cpu cycles simulated +drivesys.cpu.num_insts 0 # Number of instructions executed +drivesys.cpu.num_refs 0 # Number of memory references +drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). +drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. +drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions. +drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. +drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions. +drivesys.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post +drivesys.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post +drivesys.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post +drivesys.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post +drivesys.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post +drivesys.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post +drivesys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +drivesys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +drivesys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped +drivesys.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +drivesys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +drivesys.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +drivesys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +host_inst_rate 76361400719 # Simulator instruction rate (inst/s) +host_mem_usage 411180 # Number of bytes of host memory used +host_seconds 0.00 # Real time elapsed on the host +host_tick_rate 203621244 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 276122825 # Number of instructions simulated +sim_seconds 0.000001 # Number of seconds simulated +sim_ticks 785978 # Number of ticks simulated +testsys.cpu.dtb.accesses 0 # DTB accesses +testsys.cpu.dtb.acv 0 # DTB access violations +testsys.cpu.dtb.hits 0 # DTB hits +testsys.cpu.dtb.misses 0 # DTB misses +testsys.cpu.dtb.read_accesses 0 # DTB read accesses +testsys.cpu.dtb.read_acv 0 # DTB read access violations +testsys.cpu.dtb.read_hits 0 # DTB read hits +testsys.cpu.dtb.read_misses 0 # DTB read misses +testsys.cpu.dtb.write_accesses 0 # DTB write accesses +testsys.cpu.dtb.write_acv 0 # DTB write access violations +testsys.cpu.dtb.write_hits 0 # DTB write hits +testsys.cpu.dtb.write_misses 0 # DTB write misses +testsys.cpu.idle_fraction 1 # Percentage of idle cycles +testsys.cpu.itb.accesses 0 # ITB accesses +testsys.cpu.itb.acv 0 # ITB acv +testsys.cpu.itb.hits 0 # ITB hits +testsys.cpu.itb.misses 0 # ITB misses +testsys.cpu.kern.inst.arm 0 # number of arm instructions executed +testsys.cpu.kern.inst.hwrei 0 # number of hwrei instructions executed +testsys.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed +testsys.cpu.kern.mode_good_kernel 0 +testsys.cpu.kern.mode_good_user 0 +testsys.cpu.kern.mode_good_idle 0 +testsys.cpu.kern.mode_switch_kernel 0 # number of protection mode switches +testsys.cpu.kern.mode_switch_user 0 # number of protection mode switches +testsys.cpu.kern.mode_switch_idle 0 # number of protection mode switches +testsys.cpu.kern.mode_switch_good # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_kernel # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_user # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_idle # fraction of useful protection mode switches +testsys.cpu.kern.mode_ticks_kernel 0 # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_user 0 # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_idle 0 # number of ticks spent at the given mode +testsys.cpu.kern.swap_context 0 # number of times the context was actually changed +testsys.cpu.not_idle_fraction 0 # Percentage of non-idle cycles +testsys.cpu.numCycles 0 # number of cpu cycles simulated +testsys.cpu.num_insts 0 # Number of instructions executed +testsys.cpu.num_refs 0 # Number of memory references +testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). +testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. +testsys.disk0.dma_write_txs 0 # Number of DMA write transactions. +testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. +testsys.disk2.dma_write_txs 0 # Number of DMA write transactions. +testsys.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post +testsys.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post +testsys.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post +testsys.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post +testsys.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post +testsys.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post +testsys.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post +testsys.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post +testsys.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post +testsys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +testsys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +testsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped +testsys.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +testsys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +testsys.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +testsys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +testsys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR + +---------- End Simulation Statistics ---------- diff --git a/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr b/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr new file mode 100644 index 000000000..3aa8423b9 --- /dev/null +++ b/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr @@ -0,0 +1,8 @@ + 0: testsys.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006 +Listening for console connection on port 3456 + 0: drivesys.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006 +Listening for console connection on port 3457 +0: testsys.remote_gdb.listener: listening for remote gdb #0 on port 7000 +0: drivesys.remote_gdb.listener: listening for remote gdb #1 on port 7001 +warn: Entering event queue @ 0. Starting simulation... +warn: Obsolete M5 instruction ivlb encountered. diff --git a/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout new file mode 100644 index 000000000..765e59472 --- /dev/null +++ b/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 29 2006 16:48:25 +M5 started Fri Dec 1 01:07:49 2006 +M5 executing on zed.eecs.umich.edu +command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/long/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py long/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic +WTF +9685900: testsys.sim_console: attach console 0 +3327958029: drivesys.sim_console: attach console 0 +Resetting stats at cycle 4100234765800! +Resetting stats at cycle 4300235555268! +Exiting @ tick 4300236341246 because checkpoint diff --git a/tests/long/80.netperf-stream/test.py b/tests/long/80.netperf-stream/test.py new file mode 100644 index 000000000..139597f9c --- /dev/null +++ b/tests/long/80.netperf-stream/test.py @@ -0,0 +1,2 @@ + + From ed50763135885c339009738ff44a8db434ddc93c Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Fri, 1 Dec 2006 13:51:49 -0500 Subject: [PATCH 12/20] change this to be a quick one so that it's in the regressions every night - it's only maybe 15 min. long. tests/configs/twosys-tsunami-simple-atomic.py: don't need this import --HG-- rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr rename : tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout rename : tests/long/80.netperf-stream/test.py => tests/quick/80.netperf-stream/test.py extra : convert_revision : 68497b2ef8b21590cb6c636485703e46dc616513 --- tests/configs/twosys-tsunami-simple-atomic.py | 1 - tests/long/80.netperf-stream/test.py | 2 -- .../twosys-tsunami-simple-atomic/config.ini | 0 .../twosys-tsunami-simple-atomic/config.out | 0 .../console.drivesys.sim_console | 0 .../console.testsys.sim_console | 0 .../twosys-tsunami-simple-atomic/m5stats.txt | 0 .../linux/twosys-tsunami-simple-atomic/stderr | 0 .../linux/twosys-tsunami-simple-atomic/stdout | 0 tests/quick/80.netperf-stream/test.py | 28 +++++++++++++++++++ 10 files changed, 28 insertions(+), 3 deletions(-) delete mode 100644 tests/long/80.netperf-stream/test.py rename tests/{long => quick}/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini (100%) rename tests/{long => quick}/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out (100%) rename tests/{long => quick}/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console (100%) rename tests/{long => quick}/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console (100%) rename tests/{long => quick}/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt (100%) rename tests/{long => quick}/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr (100%) rename tests/{long => quick}/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout (100%) create mode 100644 tests/quick/80.netperf-stream/test.py diff --git a/tests/configs/twosys-tsunami-simple-atomic.py b/tests/configs/twosys-tsunami-simple-atomic.py index 335cea27d..e7214a059 100644 --- a/tests/configs/twosys-tsunami-simple-atomic.py +++ b/tests/configs/twosys-tsunami-simple-atomic.py @@ -29,7 +29,6 @@ import m5 from m5.objects import * m5.AddToPath('../configs/common') -from SysPaths import * from FSConfig import * from Benchmarks import * diff --git a/tests/long/80.netperf-stream/test.py b/tests/long/80.netperf-stream/test.py deleted file mode 100644 index 139597f9c..000000000 --- a/tests/long/80.netperf-stream/test.py +++ /dev/null @@ -1,2 +0,0 @@ - - diff --git a/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini similarity index 100% rename from tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini rename to tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini diff --git a/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out similarity index 100% rename from tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out rename to tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out diff --git a/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console similarity index 100% rename from tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console rename to tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console diff --git a/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console similarity index 100% rename from tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console rename to tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console diff --git a/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt similarity index 100% rename from tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt rename to tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt diff --git a/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr similarity index 100% rename from tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr rename to tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr diff --git a/tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout similarity index 100% rename from tests/long/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout rename to tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout diff --git a/tests/quick/80.netperf-stream/test.py b/tests/quick/80.netperf-stream/test.py new file mode 100644 index 000000000..1da47fca4 --- /dev/null +++ b/tests/quick/80.netperf-stream/test.py @@ -0,0 +1,28 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Lisa Hsu + From 5d637417a8fecc881df2f9a8a4e833e6709bafaf Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 1 Dec 2006 22:33:18 -0800 Subject: [PATCH 13/20] don't blow away the whole destination directory --HG-- extra : convert_revision : 7370bad15cc30e75ebb0c8685324d8db06fc2936 --- util/make_release.py | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/util/make_release.py b/util/make_release.py index d1161166d..47b6678fe 100755 --- a/util/make_release.py +++ b/util/make_release.py @@ -80,18 +80,31 @@ if len(sys.argv) != 3: destdir = sys.argv[1] releasename = sys.argv[2] +release_dest = joinpath(destdir, 'release') +encumbered_dest = joinpath(destdir, 'encumbered') +release_dir = joinpath(release_dest, releasename) +encumbered_dir = joinpath(encumbered_dest, releasename) if exists(destdir): if not isdir(destdir): raise AttributeError, '%s exists, but is not a directory' % destdir - rmtree(destdir) +else: + mkdir(destdir) -release_dir = joinpath(destdir, 'release', releasename) -encumbered_dir = joinpath(destdir, 'encumbered', releasename) +if exists(release_dest): + if not isdir(release_dest): + raise AttributeError, \ + '%s exists, but is not a directory' % release_dest + rmtree(release_dest) -mkdir(destdir) -mkdir(destdir, 'release') -mkdir(destdir, 'encumbered') +if exists(encumbered_dest): + if not isdir(encumbered_dest): + raise AttributeError, \ + '%s exists, but is not a directory' % encumbered_dest + rmtree(encumbered_dest) + +mkdir(release_dest) +mkdir(encumbered_dest) mkdir(release_dir) mkdir(encumbered_dir) From dc9438b1570c700d7261c7bf168953894624abf0 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Sat, 2 Dec 2006 11:11:58 -0500 Subject: [PATCH 14/20] stats update --HG-- extra : convert_revision : b47d3817d204a43e0afb89aafc8dacf619c3f910 --- .../twosys-tsunami-simple-atomic/config.ini | 8 ++-- .../twosys-tsunami-simple-atomic/config.out | 8 ++-- .../console.drivesys.sim_console | 4 +- .../console.testsys.sim_console | 4 +- .../twosys-tsunami-simple-atomic/m5stats.txt | 38 +++++++++---------- .../linux/twosys-tsunami-simple-atomic/stdout | 13 +++---- 6 files changed, 36 insertions(+), 39 deletions(-) diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index dff95e358..791395981 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -82,7 +82,7 @@ table_size=65536 [drivesys.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/myimg.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [drivesys.disk2] @@ -166,7 +166,7 @@ system=drivesys [drivesys.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/myimg.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [drivesys.tsunami] @@ -701,7 +701,7 @@ table_size=65536 [testsys.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/myimg.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [testsys.disk2] @@ -785,7 +785,7 @@ system=testsys [testsys.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/myimg.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [testsys.tsunami] diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out index 19bb5af44..21b542b9b 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out @@ -305,7 +305,7 @@ write_ack=false [testsys.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/myimg.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [testsys.disk0.image] @@ -341,7 +341,7 @@ delay=1000000 [testsys.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/myimg.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [testsys.simple_disk] @@ -691,7 +691,7 @@ write_ack=false [drivesys.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/myimg.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [drivesys.disk0.image] @@ -727,7 +727,7 @@ delay=1000000 [drivesys.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/myimg.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [drivesys.simple_disk] diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console index 931411c03..aa129d6a7 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console @@ -72,7 +72,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 hdb: M5 IDE Disk, ATA DISK drive ide0 at 0x8410-0x8417,0x8422 on irq 31 hda: max request size: 128KiB - hda: 409248 sectors (209 MB), CHS=406/16/63, UDMA(33) + hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33) hda: cache flushes not supported hda: hda1 hdb: max request size: 128KiB @@ -99,7 +99,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 All bugs added by David S. Miller VFS: Mounted root (ext2 filesystem) readonly. Freeing unused kernel memory: 224k freed - init started: BusyBox v1.1.0 (2006.10.31-01:25+0000) multi-call binary + init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary mounting filesystems... loading script... setting up network... diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console index aea9af01d..b8f1a6cae 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console @@ -72,7 +72,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 hdb: M5 IDE Disk, ATA DISK drive ide0 at 0x8410-0x8417,0x8422 on irq 31 hda: max request size: 128KiB - hda: 409248 sectors (209 MB), CHS=406/16/63, UDMA(33) + hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33) hda: cache flushes not supported hda: hda1 hdb: max request size: 128KiB @@ -99,7 +99,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 All bugs added by David S. Miller VFS: Mounted root (ext2 filesystem) readonly. Freeing unused kernel memory: 224k freed - init started: BusyBox v1.1.0 (2006.10.31-01:25+0000) multi-call binary + init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary mounting filesystems... loading script... setting up network... diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt index 328846907..dc4ea4a17 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt @@ -39,8 +39,8 @@ drivesys.cpu.kern.ipl_good_0 1189 45.85% 45.85% # nu drivesys.cpu.kern.ipl_good_21 10 0.39% 46.24% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good_22 205 7.91% 54.15% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good_31 1189 45.85% 100.00% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_ticks 199572064366 # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks_0 199571744403 100.00% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks 199572064367 # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks_0 199571744404 100.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks_21 1620 0.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks_31 300713 0.00% 100.00% # number of cycles we spent at this ipl @@ -61,7 +61,7 @@ drivesys.cpu.kern.mode_switch_good_user 1 # fr drivesys.cpu.kern.mode_switch_good_idle 0.013761 # fraction of useful protection mode switches drivesys.cpu.kern.mode_ticks_kernel 263475 0.24% 0.24% # number of ticks spent at the given mode drivesys.cpu.kern.mode_ticks_user 1278343 1.18% 1.43% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks_idle 106483912 98.57% 100.00% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_idle 106485234 98.57% 100.00% # number of ticks spent at the given mode drivesys.cpu.kern.swap_context 70 # number of times the context was actually changed drivesys.cpu.kern.syscall 22 # number of syscalls executed drivesys.cpu.kern.syscall_2 1 4.55% 4.55% # number of syscalls executed @@ -140,12 +140,12 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 38374803 # Simulator instruction rate (inst/s) -host_mem_usage 411180 # Number of bytes of host memory used -host_seconds 7.20 # Real time elapsed on the host -host_tick_rate 27794359444 # Simulator tick rate (ticks/s) +host_inst_rate 38710250 # Simulator instruction rate (inst/s) +host_mem_usage 411152 # Number of bytes of host memory used +host_seconds 7.14 # Real time elapsed on the host +host_tick_rate 28030590990 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 276122825 # Number of instructions simulated +sim_insts 276189231 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated sim_ticks 200000789468 # Number of ticks simulated testsys.cpu.dtb.accesses 335402 # DTB accesses @@ -188,8 +188,8 @@ testsys.cpu.kern.ipl_good_0 5055 48.15% 48.15% # nu testsys.cpu.kern.ipl_good_21 183 1.74% 49.90% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_22 205 1.95% 51.85% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_31 5055 48.15% 100.00% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks 199569923608 # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_0 199569308038 100.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks 199569923603 # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_0 199569308033 100.00% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks_21 30857 0.00% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks_31 567083 0.00% 100.00% # number of cycles we spent at this ipl @@ -210,7 +210,7 @@ testsys.cpu.kern.mode_switch_good_user 1 # fr testsys.cpu.kern.mode_switch_good_idle 0.013123 # fraction of useful protection mode switches testsys.cpu.kern.mode_ticks_kernel 1821232 2.16% 2.16% # number of ticks spent at the given mode testsys.cpu.kern.mode_ticks_user 1065606 1.26% 3.42% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_idle 81402474 96.58% 100.00% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_idle 81403567 96.58% 100.00% # number of ticks spent at the given mode testsys.cpu.kern.swap_context 440 # number of times the context was actually changed testsys.cpu.kern.syscall 83 # number of syscalls executed testsys.cpu.kern.syscall_2 3 3.61% 3.61% # number of syscalls executed @@ -383,12 +383,12 @@ drivesys.tsunami.ethernet.totalSwi 0 # to drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 76361400719 # Simulator instruction rate (inst/s) -host_mem_usage 411180 # Number of bytes of host memory used +host_inst_rate 75502796884 # Simulator instruction rate (inst/s) +host_mem_usage 411152 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 203621244 # Simulator tick rate (ticks/s) +host_tick_rate 201377914 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 276122825 # Number of instructions simulated +sim_insts 276189231 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated sim_ticks 785978 # Number of ticks simulated testsys.cpu.dtb.accesses 0 # DTB accesses @@ -417,10 +417,10 @@ testsys.cpu.kern.mode_good_idle 0 testsys.cpu.kern.mode_switch_kernel 0 # number of protection mode switches testsys.cpu.kern.mode_switch_user 0 # number of protection mode switches testsys.cpu.kern.mode_switch_idle 0 # number of protection mode switches -testsys.cpu.kern.mode_switch_good # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_kernel # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_user # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_idle # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good no value # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_kernel no value # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_user no value # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_idle no value # fraction of useful protection mode switches testsys.cpu.kern.mode_ticks_kernel 0 # number of ticks spent at the given mode testsys.cpu.kern.mode_ticks_user 0 # number of ticks spent at the given mode testsys.cpu.kern.mode_ticks_idle 0 # number of ticks spent at the given mode diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout index 765e59472..183b4bb4e 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout @@ -6,12 +6,9 @@ All Rights Reserved M5 compiled Nov 29 2006 16:48:25 -M5 started Fri Dec 1 01:07:49 2006 +M5 started Sat Dec 2 11:01:31 2006 M5 executing on zed.eecs.umich.edu -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/long/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py long/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -WTF -9685900: testsys.sim_console: attach console 0 -3327958029: drivesys.sim_console: attach console 0 -Resetting stats at cycle 4100234765800! -Resetting stats at cycle 4300235555268! -Exiting @ tick 4300236341246 because checkpoint +command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic +Resetting stats at cycle 4093398828306! +Resetting stats at cycle 4293399617774! +Exiting @ tick 4293400403752 because checkpoint From c0f21b09c81e5562a916f7cb562a7df7f7709f4a Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Sat, 2 Dec 2006 13:33:46 -0500 Subject: [PATCH 15/20] Fixes for MIPS_SE compiling. Regressions seem to work, but Korey should make sure these changes (commit especially) work okay. src/cpu/o3/commit_impl.hh: src/cpu/o3/fetch_impl.hh: Fixes for MIPS_SE compile. --HG-- extra : convert_revision : fde9616f8e72b397c5ca965774172372cff53790 --- src/cpu/o3/commit_impl.hh | 1 + src/cpu/o3/fetch_impl.hh | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index e72679710..43305f962 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -748,6 +748,7 @@ DefaultCommit::commit() } } else { bdelay_done_seq_num = squashed_inst; + squash_bdelay_slot = true; } #endif diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 63d22b293..4c378e18b 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -1139,6 +1139,8 @@ DefaultFetch::fetch(bool &status_change) ext_inst = TheISA::makeExtMI(inst, fetch_PC); #elif THE_ISA == SPARC_ISA ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC()); +#elif THE_ISA == MIPS_ISA + ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC()); #endif // Create a new DynInst from the instruction fetched. From 711dc47e8c002084ac71b9e40e7c4a66ecb12e32 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sun, 3 Dec 2006 01:11:24 -0500 Subject: [PATCH 16/20] Delete src/oldmem. util/make_release.py: src/oldmem gone from repo, no need to delete here. --HG-- extra : convert_revision : 570fa1b8d7144376cf13a010160a39d1c1cccbc2 --- util/make_release.py | 1 - 1 file changed, 1 deletion(-) diff --git a/util/make_release.py b/util/make_release.py index 47b6678fe..f07bafe3b 100755 --- a/util/make_release.py +++ b/util/make_release.py @@ -122,7 +122,6 @@ rmtree(release_dir, 'src/mem/cache/prefetch/ghb_*.cc') rmtree(release_dir, 'src/mem/cache/prefetch/ghb_*.hh') rmtree(release_dir, 'src/mem/cache/prefetch/stride_*.cc') rmtree(release_dir, 'src/mem/cache/prefetch/stride_*.hh') -rmtree(release_dir, 'src/oldmem') rmtree(release_dir, 'configs/fullsys') rmtree(release_dir, 'configs/test') rmtree(release_dir, 'configs/splash2') From 66a9697c4906f428cb67492dae691ab557092aee Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Mon, 4 Dec 2006 18:57:17 -0500 Subject: [PATCH 17/20] Clean up SPEC CPU2000 reference files. Get rid of reference files for o3-atomic (non-existent configuration) and mcf (doesn't seem to be working). Left in empty refs for parser/simple-timing... this appears to be dying because it's running out of memory, so maybe it will be OK once we get the memory leak fixed. --HG-- extra : convert_revision : ae3bc8dfec44d09a2a084da5041ec386fe16be8b --- .../ref/alpha/linux/o3-timing/smred.msg | 158 ++++++++++ .../ref/alpha/linux/o3-timing/smred.out | 258 ++++++++++++++++ .../ref/alpha/linux/simple-atomic/smred.msg | 158 ++++++++++ .../ref/alpha/linux/simple-atomic/smred.out | 258 ++++++++++++++++ .../ref/alpha/linux/simple-timing/smred.msg | 158 ++++++++++ .../ref/alpha/linux/simple-timing/smred.out | 258 ++++++++++++++++ .../ref/alpha/linux/o3-timing/smred.out | 276 ++++++++++++++++++ .../ref/alpha/linux/o3-timing/smred.pin | 17 ++ .../ref/alpha/linux/o3-timing/smred.pl1 | 11 + .../ref/alpha/linux/o3-timing/smred.pl2 | 2 + .../ref/alpha/linux/o3-timing/smred.sav | 18 ++ .../ref/alpha/linux/o3-timing/smred.sv2 | 19 ++ .../ref/alpha/linux/o3-timing/smred.twf | 29 ++ .../ref/alpha/linux/simple-atomic/smred.out | 276 ++++++++++++++++++ .../ref/alpha/linux/simple-atomic/smred.pin | 17 ++ .../ref/alpha/linux/simple-atomic/smred.pl1 | 11 + .../ref/alpha/linux/simple-atomic/smred.pl2 | 2 + .../ref/alpha/linux/simple-atomic/smred.sav | 18 ++ .../ref/alpha/linux/simple-atomic/smred.sv2 | 19 ++ .../ref/alpha/linux/simple-atomic/smred.twf | 29 ++ .../ref/alpha/linux/simple-timing/smred.out | 276 ++++++++++++++++++ .../ref/alpha/linux/simple-timing/smred.pin | 17 ++ .../ref/alpha/linux/simple-timing/smred.pl1 | 11 + .../ref/alpha/linux/simple-timing/smred.pl2 | 2 + .../ref/alpha/linux/simple-timing/smred.sav | 18 ++ .../ref/alpha/linux/simple-timing/smred.sv2 | 19 ++ .../ref/alpha/linux/simple-timing/smred.twf | 29 ++ 27 files changed, 2364 insertions(+) create mode 100644 tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.msg create mode 100644 tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.out create mode 100644 tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.msg create mode 100644 tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.out create mode 100644 tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.msg create mode 100644 tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.out create mode 100644 tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.out create mode 100644 tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pin create mode 100644 tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl1 create mode 100644 tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl2 create mode 100644 tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sav create mode 100644 tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sv2 create mode 100644 tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.twf create mode 100644 tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.out create mode 100644 tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pin create mode 100644 tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl1 create mode 100644 tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl2 create mode 100644 tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sav create mode 100644 tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sv2 create mode 100644 tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.twf create mode 100644 tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.out create mode 100644 tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pin create mode 100644 tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl1 create mode 100644 tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl2 create mode 100644 tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sav create mode 100644 tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sv2 create mode 100644 tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.twf diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.msg b/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.msg new file mode 100644 index 000000000..327142d7c --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.msg @@ -0,0 +1,158 @@ + + SYSTEM TYPE... + __ZTC__ := False + __UNIX__ := True + __RISC__ := True + SPEC_CPU2000_LP64 := True + __MAC__ := False + __BCC__ := False + __BORLANDC__ := False + __GUI__ := False + __WTC__ := False + __HP__ := False + + CODE OPTIONS... + __MACROIZE_HM__ := True + __MACROIZE_MEM__ := True + ENV01 := True + USE_HPP_STYPE_HDRS := False + USE_H_STYPE_HDRS := False + + CODE INCLUSION PARAMETERS... + INCLUDE_ALL_CODE := False + INCLUDE_DELETE_CODE := True + __SWAP_GRP_POS__ := True + __INCLUDE_MTRX__ := False + __BAD_CODE__ := False + API_INCLUDE := False + BE_CAREFUL := False + OLDWAY := False + NOTUSED := False + + SYSTEM PARAMETERS... + EXT_ENUM := 999999999L + CHUNK_CONSTANT := 55555555 + CORE_CONSTANT := 55555555 + CORE_LIMIT := 20971520 + CorePage_Size := 384000 + ALIGN_BYTES := True + CORE_BLOCK_ALIGN := 8 + FAR_MEM := False + + MEMORY MANAGEMENT PARAMETERS... + SYSTEM_ALLOC := True + SYSTEM_FREESTORE := True + __NO_DISKCACHE__ := False + __FREEZE_VCHUNKS__ := True + __FREEZE_GRP_PACKETS__ := True + __MINIMIZE_TREE_CACHE__:= True + + SYSTEM STD PARAMETERS... + __STDOUT__ := False + NULL := 0 + LPTR := False + False_Status := 1 + True_Status := 0 + LARGE := True + TWOBYTE_BOOL := False + __NOSTR__ := False + + MEMORY VALIDATION PARAMETERS... + CORE_CRC_CHECK := False + VALIDATE_MEM_CHUNKS := False + + SYSTEM DEBUG OPTIONS... + DEBUG := False + MCSTAT := False + TRACKBACK := False + FLUSH_FILES := False + DEBUG_CORE0 := False + DEBUG_RISC := False + __TREE_BUG__ := False + __TRACK_FILE_READS__ := False + PAGE_SPACE := False + LEAVE_NO_TRACE := True + NULL_TRACE_STRS := False + + TIME PARAMETERS... + CLOCK_IS_LONG := False + __DISPLAY_TIME__ := False + __TREE_TIME__ := False + __DISPLAY_ERRORS__ := False + + API MACROS... + __BMT01__ := True + OPTIMIZE := True + + END OF DEFINES. + + + + ... IMPLODE MEMORY ... + + SWAP to DiskCache := False + + FREEZE_GRP_PACKETS:= True + + QueBug := 1000 + + sizeof(boolean) = 4 + sizeof(sizetype) = 4 + sizeof(chunkstruc) = 32 + + sizeof(shorttype ) = 2 + sizeof(idtype ) = 2 + sizeof(sizetype ) = 4 + sizeof(indextype ) = 4 + sizeof(numtype ) = 4 + sizeof(handletype) = 4 + sizeof(tokentype ) = 8 + + sizeof(short ) = 2 + sizeof(int ) = 4 + + sizeof(lt64 ) = 4 + sizeof(farlongtype) = 4 + sizeof(long ) = 8 + sizeof(longaddr ) = 8 + + sizeof(float ) = 4 + sizeof(double ) = 8 + + sizeof(addrtype ) = 8 + sizeof(char * ) = 8 + ALLOC CORE_1 :: 16 + BHOOLE NATH + + OPEN File ./input/lendian.rnv + *Status = 0 + DB HDR restored from FileVbn[ 0] + DB BlkDirOffset : @ 2030c0 + DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] + DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] + DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] + DB Handle Chunk's StackPtr = 20797 + + DB[ 1] LOADED; Handles= 20797 + KERNEL in CORE[ 1] Restored @ 40054800 + + OPEN File ./input/lendian.wnv + *Status = 0 + DB HDR restored from FileVbn[ 0] + DB BlkDirOffset : @ 21c40 + DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] + DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] + DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] + DB Handle Chunk's StackPtr = 17 + + DB[ 2] LOADED; Handles= 17 + VORTEx_Status == -8 || fffffff8 + + BE HERE NOW !!! + + + + ... VORTEx ON LINE ... + + + ... END OF SESSION ... diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.out b/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.out new file mode 100644 index 000000000..726b45c60 --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.out @@ -0,0 +1,258 @@ + CREATE Db Header and Db Primal ... + NEW DB [ 3] Created. + +VORTEX INPUT PARAMETERS:: + MESSAGE FileName: smred.msg + OUTPUT FileName: smred.out + DISK CACHE FileName: NULL + PART DB FileName: parts.db + DRAW DB FileName: draw.db + PERSON DB FileName: emp.db + PERSONS Data FileName: ./input/persons.250 + PARTS Count : 100 + OUTER Loops : 1 + INNER Loops : 1 + LOOKUP Parts : 25 + DELETE Parts : 10 + STUFF Parts : 10 + DEPTH Traverse: 5 + % DECREASE Parts : 0 + % INCREASE LookUps : 0 + % INCREASE Deletes : 0 + % INCREASE Stuffs : 0 + FREEZE_PACKETS : 1 + ALLOC_CHUNKS : 10000 + EXTEND_CHUNKS : 5000 + DELETE Draw objects : True + DELETE Part objects : False + QUE_BUG : 1000 + VOID_BOUNDARY : 67108864 + VOID_RESERVE : 1048576 + + COMMIT_DBS : False + + + + BMT TEST :: files... + EdbName := PartLib + EdbFileName := parts.db + DrwName := DrawLib + DrwFileName := draw.db + EmpName := PersonLib + EmpFileName := emp.db + + Swap to DiskCache := False + Freeze the cache := True + + + BMT TEST :: parms... + DeBug modulo := 1000 + Create Parts count:= 100 + Outer Loops := 1 + Inner Loops := 1 + Look Ups := 25 + Delete Parts := 10 + Stuff Parts := 10 + Traverse Limit := 5 + Delete Draws := True + Delete Parts := False + Delete ALL Parts := after every Outer Loop + + INITIALIZE LIBRARY :: + + INITIALIZE SCHEMA :: + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 4] Created. + PartLibCreate:: Db[ 4]; VpartsDir= 1 + + Part Count= 1 + + Initialize the Class maps + LIST HEADS loaded ... DbListHead_Class = 207 + DbListNode_Class = 206 + +...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. + + +...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. + + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 5] Created. + DrawLibCreate:: Db[ 5]; VpartsDir= 1 + + Initialize the Class maps of this schema. + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 6] Created. + + ***NOTE*** Persons Library Extended! + + Create <131072> Persons. + ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; + + LAST Person Read:: + ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; + + BUILD for class:: + + if (link[1].length >= 5) :: + + Build Query2 for
class:: + + if (State == CA || State == T*) + + Build Query1 for class:: + + if (LastName >= H* && LastName <= P* && Query0(Residence)) :: + + BUILD for class:: + + if (Id >= 3000 + && (Id >= 3000 && Id <= 3001) + && Id >= 3002) + + BUILD for class:: + + if (Nam == Pre* + || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post + || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) + && Id <= 7) + SEED := 1008; Swap = False; RgnEntries = 135 + + OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. + + Create 100 New Parts + Create Part 1. Token[ 4: 2]. + + < 100> Parts Created. CurrentId= 100 + + Connect each instantiated Part TO 3 unique Parts + Connect Part 1. Token[ 4: 2] + Connect Part 25. Token[ 4: 26] FromList= 26. + Connect Part 12. Token[ 4: 13] FromList= 13. + Connect Part 59. Token[ 4: 60] FromList= 60. + + SET entries:: + 1. [ 5: 5] := <1 >; @[: 6] + Iteration count = 100 + + SET entries:: + 1. [ 5: 39] := <14 >; + Iteration count = 12 + + SET entries:: + 1. [ 5: 23] := <8 >; @[: 24] + Iteration count = 12 + + LIST entries:: + 1. [ 5: 23] + Iteration count = 12 + + SET entries:: + Iteration count = 250 + + COMMIT All Image copies:: Release=; Max Parts= 100 + < 100> Part images' Committed. + < 0> are Named. + < 50> Point images' Committed. + < 81> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in DB. + ItNum 0. Token[ 0: 0]. TestObj Committed. + < 0> TestObj images' Committed. + + Commit CartesianPoint_Class in DB. + ItNum 0. Token[ 0: 0]. CartesianPoint Committed. + < 0> CartesianPoint images' Committed. + + BEGIN Inner Loop Sequence::. + + INNER LOOP [ 1: 1] : + + LOOK UP 25 Random Parts and Export each Part. + + LookUp for 26 parts; Asserts = 8 + Asserts = 2; NULL Asserts = 3. + Asserts = 0; NULL Asserts = 5. + Asserts = 0; NULL Asserts = 0. + Asserts = 0; NULL Asserts = 5. + Asserts = 60; NULL Asserts = 0. + + DELETE 10 Random Parts. + + PartDelete :: Token[ 4: 91]. + PartDisconnect:: Token[ 4: 91] id:= 90 for each link. + DisConnect link [ 0]:= 50; PartToken[ 51: 51]. + DisConnect link [ 1]:= 17; PartToken[ 18: 18]. + DisConnect link [ 2]:= 72; PartToken[ 73: 73]. + DeleteFromList:: Vchunk[ 4: 91]. (* 1) + DisConnect FromList[ 0]:= 56; Token[ 57: 57]. + Vlists[ 89] := 100; + + Delete for 11 parts; + + Traverse Count= 0 + + TRAVERSE PartId[ 6] and all Connections to 5 Levels + SEED In Traverse Part [ 4: 65] @ Level = 4. + + Traverse Count= 357 + Traverse Asserts = 5. True Tests = 1 + < 5> DrawObj objects DELETED. + < 2> are Named. + < 2> Point objects DELETED. + + CREATE 10 Additional Parts + + Create 10 New Parts + Create Part 101. Token[ 4: 102]. + + < 10> Parts Created. CurrentId= 110 + + Connect each instantiated Part TO 3 unique Parts + + COMMIT All Image copies:: Release=; Max Parts= 110 + < 81> Part images' Committed. + < 0> are Named. + < 38> Point images' Committed. + < 31> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in DB. + ItNum 0. Token[ 3: 4]. TestObj Committed. + < 15> TestObj images' Committed. + + Commit CartesianPoint_Class in DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Committed. + < 16> CartesianPoint images' Committed. + + DELETE All TestObj objects; + + Delete TestObj_Class in DB. + ItNum 0. Token[ 3: 4]. TestObj Deleted. + < 15> TestObj objects Deleted. + + Commit CartesianPoint_Class in DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. + < 16> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + + END INNER LOOP [ 1: 1]. + + DELETE All TestObj objects; + + Delete TestObj_Class in DB. + < 0> TestObj objects Deleted. + + Commit CartesianPoint_Class in DB. + < 0> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + STATUS= -201 +V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.msg b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.msg new file mode 100644 index 000000000..327142d7c --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.msg @@ -0,0 +1,158 @@ + + SYSTEM TYPE... + __ZTC__ := False + __UNIX__ := True + __RISC__ := True + SPEC_CPU2000_LP64 := True + __MAC__ := False + __BCC__ := False + __BORLANDC__ := False + __GUI__ := False + __WTC__ := False + __HP__ := False + + CODE OPTIONS... + __MACROIZE_HM__ := True + __MACROIZE_MEM__ := True + ENV01 := True + USE_HPP_STYPE_HDRS := False + USE_H_STYPE_HDRS := False + + CODE INCLUSION PARAMETERS... + INCLUDE_ALL_CODE := False + INCLUDE_DELETE_CODE := True + __SWAP_GRP_POS__ := True + __INCLUDE_MTRX__ := False + __BAD_CODE__ := False + API_INCLUDE := False + BE_CAREFUL := False + OLDWAY := False + NOTUSED := False + + SYSTEM PARAMETERS... + EXT_ENUM := 999999999L + CHUNK_CONSTANT := 55555555 + CORE_CONSTANT := 55555555 + CORE_LIMIT := 20971520 + CorePage_Size := 384000 + ALIGN_BYTES := True + CORE_BLOCK_ALIGN := 8 + FAR_MEM := False + + MEMORY MANAGEMENT PARAMETERS... + SYSTEM_ALLOC := True + SYSTEM_FREESTORE := True + __NO_DISKCACHE__ := False + __FREEZE_VCHUNKS__ := True + __FREEZE_GRP_PACKETS__ := True + __MINIMIZE_TREE_CACHE__:= True + + SYSTEM STD PARAMETERS... + __STDOUT__ := False + NULL := 0 + LPTR := False + False_Status := 1 + True_Status := 0 + LARGE := True + TWOBYTE_BOOL := False + __NOSTR__ := False + + MEMORY VALIDATION PARAMETERS... + CORE_CRC_CHECK := False + VALIDATE_MEM_CHUNKS := False + + SYSTEM DEBUG OPTIONS... + DEBUG := False + MCSTAT := False + TRACKBACK := False + FLUSH_FILES := False + DEBUG_CORE0 := False + DEBUG_RISC := False + __TREE_BUG__ := False + __TRACK_FILE_READS__ := False + PAGE_SPACE := False + LEAVE_NO_TRACE := True + NULL_TRACE_STRS := False + + TIME PARAMETERS... + CLOCK_IS_LONG := False + __DISPLAY_TIME__ := False + __TREE_TIME__ := False + __DISPLAY_ERRORS__ := False + + API MACROS... + __BMT01__ := True + OPTIMIZE := True + + END OF DEFINES. + + + + ... IMPLODE MEMORY ... + + SWAP to DiskCache := False + + FREEZE_GRP_PACKETS:= True + + QueBug := 1000 + + sizeof(boolean) = 4 + sizeof(sizetype) = 4 + sizeof(chunkstruc) = 32 + + sizeof(shorttype ) = 2 + sizeof(idtype ) = 2 + sizeof(sizetype ) = 4 + sizeof(indextype ) = 4 + sizeof(numtype ) = 4 + sizeof(handletype) = 4 + sizeof(tokentype ) = 8 + + sizeof(short ) = 2 + sizeof(int ) = 4 + + sizeof(lt64 ) = 4 + sizeof(farlongtype) = 4 + sizeof(long ) = 8 + sizeof(longaddr ) = 8 + + sizeof(float ) = 4 + sizeof(double ) = 8 + + sizeof(addrtype ) = 8 + sizeof(char * ) = 8 + ALLOC CORE_1 :: 16 + BHOOLE NATH + + OPEN File ./input/lendian.rnv + *Status = 0 + DB HDR restored from FileVbn[ 0] + DB BlkDirOffset : @ 2030c0 + DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] + DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] + DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] + DB Handle Chunk's StackPtr = 20797 + + DB[ 1] LOADED; Handles= 20797 + KERNEL in CORE[ 1] Restored @ 40054800 + + OPEN File ./input/lendian.wnv + *Status = 0 + DB HDR restored from FileVbn[ 0] + DB BlkDirOffset : @ 21c40 + DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] + DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] + DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] + DB Handle Chunk's StackPtr = 17 + + DB[ 2] LOADED; Handles= 17 + VORTEx_Status == -8 || fffffff8 + + BE HERE NOW !!! + + + + ... VORTEx ON LINE ... + + + ... END OF SESSION ... diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.out b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.out new file mode 100644 index 000000000..726b45c60 --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.out @@ -0,0 +1,258 @@ + CREATE Db Header and Db Primal ... + NEW DB [ 3] Created. + +VORTEX INPUT PARAMETERS:: + MESSAGE FileName: smred.msg + OUTPUT FileName: smred.out + DISK CACHE FileName: NULL + PART DB FileName: parts.db + DRAW DB FileName: draw.db + PERSON DB FileName: emp.db + PERSONS Data FileName: ./input/persons.250 + PARTS Count : 100 + OUTER Loops : 1 + INNER Loops : 1 + LOOKUP Parts : 25 + DELETE Parts : 10 + STUFF Parts : 10 + DEPTH Traverse: 5 + % DECREASE Parts : 0 + % INCREASE LookUps : 0 + % INCREASE Deletes : 0 + % INCREASE Stuffs : 0 + FREEZE_PACKETS : 1 + ALLOC_CHUNKS : 10000 + EXTEND_CHUNKS : 5000 + DELETE Draw objects : True + DELETE Part objects : False + QUE_BUG : 1000 + VOID_BOUNDARY : 67108864 + VOID_RESERVE : 1048576 + + COMMIT_DBS : False + + + + BMT TEST :: files... + EdbName := PartLib + EdbFileName := parts.db + DrwName := DrawLib + DrwFileName := draw.db + EmpName := PersonLib + EmpFileName := emp.db + + Swap to DiskCache := False + Freeze the cache := True + + + BMT TEST :: parms... + DeBug modulo := 1000 + Create Parts count:= 100 + Outer Loops := 1 + Inner Loops := 1 + Look Ups := 25 + Delete Parts := 10 + Stuff Parts := 10 + Traverse Limit := 5 + Delete Draws := True + Delete Parts := False + Delete ALL Parts := after every Outer Loop + + INITIALIZE LIBRARY :: + + INITIALIZE SCHEMA :: + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 4] Created. + PartLibCreate:: Db[ 4]; VpartsDir= 1 + + Part Count= 1 + + Initialize the Class maps + LIST HEADS loaded ... DbListHead_Class = 207 + DbListNode_Class = 206 + +...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. + + +...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. + + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 5] Created. + DrawLibCreate:: Db[ 5]; VpartsDir= 1 + + Initialize the Class maps of this schema. + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 6] Created. + + ***NOTE*** Persons Library Extended! + + Create <131072> Persons. + ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; + + LAST Person Read:: + ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; + + BUILD for class:: + + if (link[1].length >= 5) :: + + Build Query2 for
class:: + + if (State == CA || State == T*) + + Build Query1 for class:: + + if (LastName >= H* && LastName <= P* && Query0(Residence)) :: + + BUILD for class:: + + if (Id >= 3000 + && (Id >= 3000 && Id <= 3001) + && Id >= 3002) + + BUILD for class:: + + if (Nam == Pre* + || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post + || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) + && Id <= 7) + SEED := 1008; Swap = False; RgnEntries = 135 + + OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. + + Create 100 New Parts + Create Part 1. Token[ 4: 2]. + + < 100> Parts Created. CurrentId= 100 + + Connect each instantiated Part TO 3 unique Parts + Connect Part 1. Token[ 4: 2] + Connect Part 25. Token[ 4: 26] FromList= 26. + Connect Part 12. Token[ 4: 13] FromList= 13. + Connect Part 59. Token[ 4: 60] FromList= 60. + + SET entries:: + 1. [ 5: 5] := <1 >; @[: 6] + Iteration count = 100 + + SET entries:: + 1. [ 5: 39] := <14 >; + Iteration count = 12 + + SET entries:: + 1. [ 5: 23] := <8 >; @[: 24] + Iteration count = 12 + + LIST entries:: + 1. [ 5: 23] + Iteration count = 12 + + SET entries:: + Iteration count = 250 + + COMMIT All Image copies:: Release=; Max Parts= 100 + < 100> Part images' Committed. + < 0> are Named. + < 50> Point images' Committed. + < 81> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in DB. + ItNum 0. Token[ 0: 0]. TestObj Committed. + < 0> TestObj images' Committed. + + Commit CartesianPoint_Class in DB. + ItNum 0. Token[ 0: 0]. CartesianPoint Committed. + < 0> CartesianPoint images' Committed. + + BEGIN Inner Loop Sequence::. + + INNER LOOP [ 1: 1] : + + LOOK UP 25 Random Parts and Export each Part. + + LookUp for 26 parts; Asserts = 8 + Asserts = 2; NULL Asserts = 3. + Asserts = 0; NULL Asserts = 5. + Asserts = 0; NULL Asserts = 0. + Asserts = 0; NULL Asserts = 5. + Asserts = 60; NULL Asserts = 0. + + DELETE 10 Random Parts. + + PartDelete :: Token[ 4: 91]. + PartDisconnect:: Token[ 4: 91] id:= 90 for each link. + DisConnect link [ 0]:= 50; PartToken[ 51: 51]. + DisConnect link [ 1]:= 17; PartToken[ 18: 18]. + DisConnect link [ 2]:= 72; PartToken[ 73: 73]. + DeleteFromList:: Vchunk[ 4: 91]. (* 1) + DisConnect FromList[ 0]:= 56; Token[ 57: 57]. + Vlists[ 89] := 100; + + Delete for 11 parts; + + Traverse Count= 0 + + TRAVERSE PartId[ 6] and all Connections to 5 Levels + SEED In Traverse Part [ 4: 65] @ Level = 4. + + Traverse Count= 357 + Traverse Asserts = 5. True Tests = 1 + < 5> DrawObj objects DELETED. + < 2> are Named. + < 2> Point objects DELETED. + + CREATE 10 Additional Parts + + Create 10 New Parts + Create Part 101. Token[ 4: 102]. + + < 10> Parts Created. CurrentId= 110 + + Connect each instantiated Part TO 3 unique Parts + + COMMIT All Image copies:: Release=; Max Parts= 110 + < 81> Part images' Committed. + < 0> are Named. + < 38> Point images' Committed. + < 31> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in DB. + ItNum 0. Token[ 3: 4]. TestObj Committed. + < 15> TestObj images' Committed. + + Commit CartesianPoint_Class in DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Committed. + < 16> CartesianPoint images' Committed. + + DELETE All TestObj objects; + + Delete TestObj_Class in DB. + ItNum 0. Token[ 3: 4]. TestObj Deleted. + < 15> TestObj objects Deleted. + + Commit CartesianPoint_Class in DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. + < 16> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + + END INNER LOOP [ 1: 1]. + + DELETE All TestObj objects; + + Delete TestObj_Class in DB. + < 0> TestObj objects Deleted. + + Commit CartesianPoint_Class in DB. + < 0> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + STATUS= -201 +V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.msg b/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.msg new file mode 100644 index 000000000..327142d7c --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.msg @@ -0,0 +1,158 @@ + + SYSTEM TYPE... + __ZTC__ := False + __UNIX__ := True + __RISC__ := True + SPEC_CPU2000_LP64 := True + __MAC__ := False + __BCC__ := False + __BORLANDC__ := False + __GUI__ := False + __WTC__ := False + __HP__ := False + + CODE OPTIONS... + __MACROIZE_HM__ := True + __MACROIZE_MEM__ := True + ENV01 := True + USE_HPP_STYPE_HDRS := False + USE_H_STYPE_HDRS := False + + CODE INCLUSION PARAMETERS... + INCLUDE_ALL_CODE := False + INCLUDE_DELETE_CODE := True + __SWAP_GRP_POS__ := True + __INCLUDE_MTRX__ := False + __BAD_CODE__ := False + API_INCLUDE := False + BE_CAREFUL := False + OLDWAY := False + NOTUSED := False + + SYSTEM PARAMETERS... + EXT_ENUM := 999999999L + CHUNK_CONSTANT := 55555555 + CORE_CONSTANT := 55555555 + CORE_LIMIT := 20971520 + CorePage_Size := 384000 + ALIGN_BYTES := True + CORE_BLOCK_ALIGN := 8 + FAR_MEM := False + + MEMORY MANAGEMENT PARAMETERS... + SYSTEM_ALLOC := True + SYSTEM_FREESTORE := True + __NO_DISKCACHE__ := False + __FREEZE_VCHUNKS__ := True + __FREEZE_GRP_PACKETS__ := True + __MINIMIZE_TREE_CACHE__:= True + + SYSTEM STD PARAMETERS... + __STDOUT__ := False + NULL := 0 + LPTR := False + False_Status := 1 + True_Status := 0 + LARGE := True + TWOBYTE_BOOL := False + __NOSTR__ := False + + MEMORY VALIDATION PARAMETERS... + CORE_CRC_CHECK := False + VALIDATE_MEM_CHUNKS := False + + SYSTEM DEBUG OPTIONS... + DEBUG := False + MCSTAT := False + TRACKBACK := False + FLUSH_FILES := False + DEBUG_CORE0 := False + DEBUG_RISC := False + __TREE_BUG__ := False + __TRACK_FILE_READS__ := False + PAGE_SPACE := False + LEAVE_NO_TRACE := True + NULL_TRACE_STRS := False + + TIME PARAMETERS... + CLOCK_IS_LONG := False + __DISPLAY_TIME__ := False + __TREE_TIME__ := False + __DISPLAY_ERRORS__ := False + + API MACROS... + __BMT01__ := True + OPTIMIZE := True + + END OF DEFINES. + + + + ... IMPLODE MEMORY ... + + SWAP to DiskCache := False + + FREEZE_GRP_PACKETS:= True + + QueBug := 1000 + + sizeof(boolean) = 4 + sizeof(sizetype) = 4 + sizeof(chunkstruc) = 32 + + sizeof(shorttype ) = 2 + sizeof(idtype ) = 2 + sizeof(sizetype ) = 4 + sizeof(indextype ) = 4 + sizeof(numtype ) = 4 + sizeof(handletype) = 4 + sizeof(tokentype ) = 8 + + sizeof(short ) = 2 + sizeof(int ) = 4 + + sizeof(lt64 ) = 4 + sizeof(farlongtype) = 4 + sizeof(long ) = 8 + sizeof(longaddr ) = 8 + + sizeof(float ) = 4 + sizeof(double ) = 8 + + sizeof(addrtype ) = 8 + sizeof(char * ) = 8 + ALLOC CORE_1 :: 16 + BHOOLE NATH + + OPEN File ./input/lendian.rnv + *Status = 0 + DB HDR restored from FileVbn[ 0] + DB BlkDirOffset : @ 2030c0 + DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] + DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] + DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] + DB Handle Chunk's StackPtr = 20797 + + DB[ 1] LOADED; Handles= 20797 + KERNEL in CORE[ 1] Restored @ 40054800 + + OPEN File ./input/lendian.wnv + *Status = 0 + DB HDR restored from FileVbn[ 0] + DB BlkDirOffset : @ 21c40 + DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] + DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] + DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] + DB Handle Chunk's StackPtr = 17 + + DB[ 2] LOADED; Handles= 17 + VORTEx_Status == -8 || fffffff8 + + BE HERE NOW !!! + + + + ... VORTEx ON LINE ... + + + ... END OF SESSION ... diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.out b/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.out new file mode 100644 index 000000000..726b45c60 --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.out @@ -0,0 +1,258 @@ + CREATE Db Header and Db Primal ... + NEW DB [ 3] Created. + +VORTEX INPUT PARAMETERS:: + MESSAGE FileName: smred.msg + OUTPUT FileName: smred.out + DISK CACHE FileName: NULL + PART DB FileName: parts.db + DRAW DB FileName: draw.db + PERSON DB FileName: emp.db + PERSONS Data FileName: ./input/persons.250 + PARTS Count : 100 + OUTER Loops : 1 + INNER Loops : 1 + LOOKUP Parts : 25 + DELETE Parts : 10 + STUFF Parts : 10 + DEPTH Traverse: 5 + % DECREASE Parts : 0 + % INCREASE LookUps : 0 + % INCREASE Deletes : 0 + % INCREASE Stuffs : 0 + FREEZE_PACKETS : 1 + ALLOC_CHUNKS : 10000 + EXTEND_CHUNKS : 5000 + DELETE Draw objects : True + DELETE Part objects : False + QUE_BUG : 1000 + VOID_BOUNDARY : 67108864 + VOID_RESERVE : 1048576 + + COMMIT_DBS : False + + + + BMT TEST :: files... + EdbName := PartLib + EdbFileName := parts.db + DrwName := DrawLib + DrwFileName := draw.db + EmpName := PersonLib + EmpFileName := emp.db + + Swap to DiskCache := False + Freeze the cache := True + + + BMT TEST :: parms... + DeBug modulo := 1000 + Create Parts count:= 100 + Outer Loops := 1 + Inner Loops := 1 + Look Ups := 25 + Delete Parts := 10 + Stuff Parts := 10 + Traverse Limit := 5 + Delete Draws := True + Delete Parts := False + Delete ALL Parts := after every Outer Loop + + INITIALIZE LIBRARY :: + + INITIALIZE SCHEMA :: + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 4] Created. + PartLibCreate:: Db[ 4]; VpartsDir= 1 + + Part Count= 1 + + Initialize the Class maps + LIST HEADS loaded ... DbListHead_Class = 207 + DbListNode_Class = 206 + +...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. + + +...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. + + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 5] Created. + DrawLibCreate:: Db[ 5]; VpartsDir= 1 + + Initialize the Class maps of this schema. + Primal_CreateDb Accessed !!! + CREATE Db Header and Db Primal ... + NEW DB [ 6] Created. + + ***NOTE*** Persons Library Extended! + + Create <131072> Persons. + ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; + + LAST Person Read:: + ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; + + BUILD for class:: + + if (link[1].length >= 5) :: + + Build Query2 for
class:: + + if (State == CA || State == T*) + + Build Query1 for class:: + + if (LastName >= H* && LastName <= P* && Query0(Residence)) :: + + BUILD for class:: + + if (Id >= 3000 + && (Id >= 3000 && Id <= 3001) + && Id >= 3002) + + BUILD for class:: + + if (Nam == Pre* + || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post + || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) + && Id <= 7) + SEED := 1008; Swap = False; RgnEntries = 135 + + OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. + + Create 100 New Parts + Create Part 1. Token[ 4: 2]. + + < 100> Parts Created. CurrentId= 100 + + Connect each instantiated Part TO 3 unique Parts + Connect Part 1. Token[ 4: 2] + Connect Part 25. Token[ 4: 26] FromList= 26. + Connect Part 12. Token[ 4: 13] FromList= 13. + Connect Part 59. Token[ 4: 60] FromList= 60. + + SET entries:: + 1. [ 5: 5] := <1 >; @[: 6] + Iteration count = 100 + + SET entries:: + 1. [ 5: 39] := <14 >; + Iteration count = 12 + + SET entries:: + 1. [ 5: 23] := <8 >; @[: 24] + Iteration count = 12 + + LIST entries:: + 1. [ 5: 23] + Iteration count = 12 + + SET entries:: + Iteration count = 250 + + COMMIT All Image copies:: Release=; Max Parts= 100 + < 100> Part images' Committed. + < 0> are Named. + < 50> Point images' Committed. + < 81> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in DB. + ItNum 0. Token[ 0: 0]. TestObj Committed. + < 0> TestObj images' Committed. + + Commit CartesianPoint_Class in DB. + ItNum 0. Token[ 0: 0]. CartesianPoint Committed. + < 0> CartesianPoint images' Committed. + + BEGIN Inner Loop Sequence::. + + INNER LOOP [ 1: 1] : + + LOOK UP 25 Random Parts and Export each Part. + + LookUp for 26 parts; Asserts = 8 + Asserts = 2; NULL Asserts = 3. + Asserts = 0; NULL Asserts = 5. + Asserts = 0; NULL Asserts = 0. + Asserts = 0; NULL Asserts = 5. + Asserts = 60; NULL Asserts = 0. + + DELETE 10 Random Parts. + + PartDelete :: Token[ 4: 91]. + PartDisconnect:: Token[ 4: 91] id:= 90 for each link. + DisConnect link [ 0]:= 50; PartToken[ 51: 51]. + DisConnect link [ 1]:= 17; PartToken[ 18: 18]. + DisConnect link [ 2]:= 72; PartToken[ 73: 73]. + DeleteFromList:: Vchunk[ 4: 91]. (* 1) + DisConnect FromList[ 0]:= 56; Token[ 57: 57]. + Vlists[ 89] := 100; + + Delete for 11 parts; + + Traverse Count= 0 + + TRAVERSE PartId[ 6] and all Connections to 5 Levels + SEED In Traverse Part [ 4: 65] @ Level = 4. + + Traverse Count= 357 + Traverse Asserts = 5. True Tests = 1 + < 5> DrawObj objects DELETED. + < 2> are Named. + < 2> Point objects DELETED. + + CREATE 10 Additional Parts + + Create 10 New Parts + Create Part 101. Token[ 4: 102]. + + < 10> Parts Created. CurrentId= 110 + + Connect each instantiated Part TO 3 unique Parts + + COMMIT All Image copies:: Release=; Max Parts= 110 + < 81> Part images' Committed. + < 0> are Named. + < 38> Point images' Committed. + < 31> Person images' Committed. + + COMMIT Parts(* 100) + + Commit TestObj_Class in DB. + ItNum 0. Token[ 3: 4]. TestObj Committed. + < 15> TestObj images' Committed. + + Commit CartesianPoint_Class in DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Committed. + < 16> CartesianPoint images' Committed. + + DELETE All TestObj objects; + + Delete TestObj_Class in DB. + ItNum 0. Token[ 3: 4]. TestObj Deleted. + < 15> TestObj objects Deleted. + + Commit CartesianPoint_Class in DB. + ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. + < 16> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + + END INNER LOOP [ 1: 1]. + + DELETE All TestObj objects; + + Delete TestObj_Class in DB. + < 0> TestObj objects Deleted. + + Commit CartesianPoint_Class in DB. + < 0> CartesianPoint objects Deleted. + + DELETE TestObj and Point objects... + STATUS= -201 +V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.out b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.out new file mode 100644 index 000000000..00387ae5c --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.out @@ -0,0 +1,276 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + + +NOTE: Restart file .rs2 not used + +TimberWolf will perform a global route step +rowSep: 1.000000 +feedThruWidth: 4 + +****************** +BLOCK DATA +block:1 desire:85 +block:2 desire:85 +Total Desired Length: 170 +total cell length: 168 +total block length: 168 +block x-span:84 block y-span:78 +implicit feed thru range: -84 +Using default value of bin.penalty.control:1.000000 +numBins automatically set to:5 +binWidth = average_cell_width + 0 sigma= 17 +average_cell_width is:16 +standard deviation of cell length is:23.6305 +TimberWolfSC starting from the beginning + + + +THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 +The number of nets with 1 pin is 4 +The number of nets with 2 pin is 9 +The number of nets with 3 pin is 0 +The number of nets with 4 pin is 2 +The number of nets with 5 pin is 0 +The number of nets with 6 pin is 0 +The number of nets with 7 pin is 0 +The number of nets with 8 pin is 0 +The number of nets with 9 pin is 0 +The number of nets with 10 pin or more is 0 + +New Cost Function: Initial Horizontal Cost:242 +New Cost Function: FEEDS:0 MISSING_ROWS:-46 + +bdxlen:86 bdylen:78 +l:0 t:78 r:86 b:0 + + + +THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 + + + +THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 + +The rand generator seed was at utemp() : 1 + + + tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 + tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 + tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 + tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 + + I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs + 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 + 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 + 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 + 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 + 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 + 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 + 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 + 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 + 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 + 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 + 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 + 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 + 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 + 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 + 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 + 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 + 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 + 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 + 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 + 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 + 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 + 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 + 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 + 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 + 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 + 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 + 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 + 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 + 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 + 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 + 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 + 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 + 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 + 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 + 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 + 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 + 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 + 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 + 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 + 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 + 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 + 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 + 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 + 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 + 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 + 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 + 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 + 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 + 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 + 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 + 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 + 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 + 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 + 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 + 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 + 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 + 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 + 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 + 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 + 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 + 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 + 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 + 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 + 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 + 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 + 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 + 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 + 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 + 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 + 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 + 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 + 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 + 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 + 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 + 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 + 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 + 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 + 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 + 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 + 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 + 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 + 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 + 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 + 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 + 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 + 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 + 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 + 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 + 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 + 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 + 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 + 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 + 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 + 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 + 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 +100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 +101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 +102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 +103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 +104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 +105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 +106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 +107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 +108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 +109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 +110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 +111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 +112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 +113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 +114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 +115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 +116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 +117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 +118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 +119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 +120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 +121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 + +Initial Wiring Cost: 645 Final Wiring Cost: 732 +############## Percent Wire Cost Reduction: -13 + + +Initial Wire Length: 645 Final Wire Length: 732 +************** Percent Wire Length Reduction: -13 + + +Initial Horiz. Wire: 216 Final Horiz. Wire: 147 +$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 + + +Initial Vert. Wire: 429 Final Vert. Wire: 585 +@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 + +Before Feeds are Added: +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 82 -20 + 2 86 -16 + +LONGEST Block is:2 Its length is:86 +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 86 -16 + 2 86 -16 + +LONGEST Block is:1 Its length is:86 +Added: 1 feed-through cells + +Removed the cell overlaps --- Will do neighbor interchanges only now + +TOTAL INTERCONNECT LENGTH: 994 +OVERLAP PENALTY: 0 + +initialRowControl: 1.650 +finalRowControl: 0.300 +iter T Wire accept + 122 0.001 976 16% + 123 0.001 971 0% + 124 0.001 971 0% +Total Feed-Alignment Movement (Pass 1): 0 +Total Feed-Alignment Movement (Pass 2): 0 +Total Feed-Alignment Movement (Pass 3): 0 +Total Feed-Alignment Movement (Pass 4): 0 +Total Feed-Alignment Movement (Pass 5): 0 +Total Feed-Alignment Movement (Pass 6): 0 +Total Feed-Alignment Movement (Pass 7): 0 +Total Feed-Alignment Movement (Pass 8): 0 + +The rand generator seed was at globroute() : 987654321 + + +Total Number of Net Segments: 9 +Number of Switchable Net Segments: 0 + +Number of channels: 3 + + + +THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 + + +no. of accepted flips: 0 +no. of attempted flips: 0 +THIS IS THE NUMBER OF TRACKS: 5 + + + +FINAL NUMBER OF ROUTING TRACKS: 5 + +MAX OF CHANNEL: 1 is: 0 +MAX OF CHANNEL: 2 is: 4 +MAX OF CHANNEL: 3 is: 1 +FINAL TOTAL INTERCONNECT LENGTH: 978 +FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 +MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 + + +cost_scale_factor:3.90616 + +Number of Feed Thrus: 0 +Number of Implicit Feed Thrus: 0 + +Statistics: +Number of Standard Cells: 10 +Number of Pads: 0 +Number of Nets: 15 +Number of Pins: 46 +Usage statistics not available diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pin b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pin new file mode 100644 index 000000000..62b922e4e --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pin @@ -0,0 +1,17 @@ +$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 +$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 +B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 +B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 +B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl1 b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl1 new file mode 100644 index 000000000..bdc569e39 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl1 @@ -0,0 +1,11 @@ +$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 +$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 +$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 +ACOUNT_1 14 0 18 26 2 1 +twfeed1 18 0 22 26 0 1 +$COUNT_1/$FJK3_1 22 0 86 26 0 1 +$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 +$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 +$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 +$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 +$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl2 b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl2 new file mode 100644 index 000000000..6e2601e82 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl2 @@ -0,0 +1,2 @@ +1 0 0 86 26 0 0 +2 0 52 86 78 0 0 diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sav b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sav new file mode 100644 index 000000000..04c8e9935 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sav @@ -0,0 +1,18 @@ +0.009592 +121 +0 +1 +0.000000 +0.500000 +3.906156 +1 +1 1 2 37 13 +2 2 0 34 65 +3 2 2 63 65 +4 1 0 59 13 +5 1 2 32 13 +6 2 0 23 65 +7 1 2 12 13 +8 2 0 6 65 +9 1 0 70 13 +10 2 0 70 65 diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sv2 b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sv2 new file mode 100644 index 000000000..9dd68ecdb --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sv2 @@ -0,0 +1,19 @@ +0.001000 +123 +0 +2 +0.000000 +0.500000 +3.906156 +1 +1 1 2 16 13 +2 2 2 19 65 +3 2 2 14 65 +4 1 0 11 13 +5 1 2 6 13 +6 2 0 3 65 +7 1 0 2 13 +8 2 2 9 65 +9 1 0 50 13 +10 2 0 54 65 +11 1 0 84 13 diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.twf b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.twf new file mode 100644 index 000000000..a4c2eac35 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.twf @@ -0,0 +1,29 @@ +net 1 +segment channel 2 + pin1 1 pin2 7 0 0 +net 2 +segment channel 3 +pin1 41 pin2 42 0 0 +segment channel 2 +pin1 12 pin2 3 0 0 +net 3 +segment channel 2 +pin1 35 pin2 36 0 0 +segment channel 2 +pin1 19 pin2 35 0 0 +net 4 +segment channel 2 + pin1 5 pin2 38 0 0 +net 5 +net 7 +segment channel 2 + pin1 14 pin2 43 0 0 +net 8 +segment channel 2 + pin1 23 pin2 17 0 0 +net 9 +net 11 +segment channel 2 + pin1 25 pin2 31 0 0 +net 14 +net 15 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.out b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.out new file mode 100644 index 000000000..00387ae5c --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.out @@ -0,0 +1,276 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + + +NOTE: Restart file .rs2 not used + +TimberWolf will perform a global route step +rowSep: 1.000000 +feedThruWidth: 4 + +****************** +BLOCK DATA +block:1 desire:85 +block:2 desire:85 +Total Desired Length: 170 +total cell length: 168 +total block length: 168 +block x-span:84 block y-span:78 +implicit feed thru range: -84 +Using default value of bin.penalty.control:1.000000 +numBins automatically set to:5 +binWidth = average_cell_width + 0 sigma= 17 +average_cell_width is:16 +standard deviation of cell length is:23.6305 +TimberWolfSC starting from the beginning + + + +THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 +The number of nets with 1 pin is 4 +The number of nets with 2 pin is 9 +The number of nets with 3 pin is 0 +The number of nets with 4 pin is 2 +The number of nets with 5 pin is 0 +The number of nets with 6 pin is 0 +The number of nets with 7 pin is 0 +The number of nets with 8 pin is 0 +The number of nets with 9 pin is 0 +The number of nets with 10 pin or more is 0 + +New Cost Function: Initial Horizontal Cost:242 +New Cost Function: FEEDS:0 MISSING_ROWS:-46 + +bdxlen:86 bdylen:78 +l:0 t:78 r:86 b:0 + + + +THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 + + + +THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 + +The rand generator seed was at utemp() : 1 + + + tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 + tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 + tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 + tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 + + I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs + 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 + 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 + 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 + 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 + 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 + 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 + 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 + 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 + 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 + 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 + 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 + 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 + 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 + 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 + 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 + 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 + 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 + 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 + 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 + 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 + 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 + 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 + 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 + 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 + 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 + 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 + 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 + 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 + 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 + 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 + 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 + 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 + 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 + 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 + 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 + 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 + 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 + 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 + 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 + 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 + 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 + 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 + 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 + 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 + 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 + 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 + 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 + 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 + 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 + 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 + 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 + 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 + 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 + 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 + 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 + 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 + 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 + 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 + 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 + 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 + 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 + 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 + 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 + 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 + 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 + 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 + 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 + 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 + 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 + 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 + 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 + 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 + 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 + 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 + 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 + 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 + 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 + 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 + 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 + 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 + 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 + 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 + 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 + 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 + 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 + 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 + 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 + 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 + 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 + 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 + 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 + 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 + 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 + 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 + 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 +100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 +101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 +102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 +103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 +104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 +105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 +106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 +107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 +108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 +109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 +110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 +111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 +112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 +113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 +114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 +115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 +116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 +117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 +118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 +119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 +120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 +121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 + +Initial Wiring Cost: 645 Final Wiring Cost: 732 +############## Percent Wire Cost Reduction: -13 + + +Initial Wire Length: 645 Final Wire Length: 732 +************** Percent Wire Length Reduction: -13 + + +Initial Horiz. Wire: 216 Final Horiz. Wire: 147 +$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 + + +Initial Vert. Wire: 429 Final Vert. Wire: 585 +@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 + +Before Feeds are Added: +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 82 -20 + 2 86 -16 + +LONGEST Block is:2 Its length is:86 +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 86 -16 + 2 86 -16 + +LONGEST Block is:1 Its length is:86 +Added: 1 feed-through cells + +Removed the cell overlaps --- Will do neighbor interchanges only now + +TOTAL INTERCONNECT LENGTH: 994 +OVERLAP PENALTY: 0 + +initialRowControl: 1.650 +finalRowControl: 0.300 +iter T Wire accept + 122 0.001 976 16% + 123 0.001 971 0% + 124 0.001 971 0% +Total Feed-Alignment Movement (Pass 1): 0 +Total Feed-Alignment Movement (Pass 2): 0 +Total Feed-Alignment Movement (Pass 3): 0 +Total Feed-Alignment Movement (Pass 4): 0 +Total Feed-Alignment Movement (Pass 5): 0 +Total Feed-Alignment Movement (Pass 6): 0 +Total Feed-Alignment Movement (Pass 7): 0 +Total Feed-Alignment Movement (Pass 8): 0 + +The rand generator seed was at globroute() : 987654321 + + +Total Number of Net Segments: 9 +Number of Switchable Net Segments: 0 + +Number of channels: 3 + + + +THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 + + +no. of accepted flips: 0 +no. of attempted flips: 0 +THIS IS THE NUMBER OF TRACKS: 5 + + + +FINAL NUMBER OF ROUTING TRACKS: 5 + +MAX OF CHANNEL: 1 is: 0 +MAX OF CHANNEL: 2 is: 4 +MAX OF CHANNEL: 3 is: 1 +FINAL TOTAL INTERCONNECT LENGTH: 978 +FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 +MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 + + +cost_scale_factor:3.90616 + +Number of Feed Thrus: 0 +Number of Implicit Feed Thrus: 0 + +Statistics: +Number of Standard Cells: 10 +Number of Pads: 0 +Number of Nets: 15 +Number of Pins: 46 +Usage statistics not available diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pin b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pin new file mode 100644 index 000000000..62b922e4e --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pin @@ -0,0 +1,17 @@ +$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 +$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 +B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 +B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 +B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl1 b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl1 new file mode 100644 index 000000000..bdc569e39 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl1 @@ -0,0 +1,11 @@ +$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 +$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 +$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 +ACOUNT_1 14 0 18 26 2 1 +twfeed1 18 0 22 26 0 1 +$COUNT_1/$FJK3_1 22 0 86 26 0 1 +$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 +$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 +$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 +$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 +$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl2 b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl2 new file mode 100644 index 000000000..6e2601e82 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl2 @@ -0,0 +1,2 @@ +1 0 0 86 26 0 0 +2 0 52 86 78 0 0 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sav b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sav new file mode 100644 index 000000000..04c8e9935 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sav @@ -0,0 +1,18 @@ +0.009592 +121 +0 +1 +0.000000 +0.500000 +3.906156 +1 +1 1 2 37 13 +2 2 0 34 65 +3 2 2 63 65 +4 1 0 59 13 +5 1 2 32 13 +6 2 0 23 65 +7 1 2 12 13 +8 2 0 6 65 +9 1 0 70 13 +10 2 0 70 65 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sv2 b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sv2 new file mode 100644 index 000000000..9dd68ecdb --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sv2 @@ -0,0 +1,19 @@ +0.001000 +123 +0 +2 +0.000000 +0.500000 +3.906156 +1 +1 1 2 16 13 +2 2 2 19 65 +3 2 2 14 65 +4 1 0 11 13 +5 1 2 6 13 +6 2 0 3 65 +7 1 0 2 13 +8 2 2 9 65 +9 1 0 50 13 +10 2 0 54 65 +11 1 0 84 13 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.twf b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.twf new file mode 100644 index 000000000..a4c2eac35 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.twf @@ -0,0 +1,29 @@ +net 1 +segment channel 2 + pin1 1 pin2 7 0 0 +net 2 +segment channel 3 +pin1 41 pin2 42 0 0 +segment channel 2 +pin1 12 pin2 3 0 0 +net 3 +segment channel 2 +pin1 35 pin2 36 0 0 +segment channel 2 +pin1 19 pin2 35 0 0 +net 4 +segment channel 2 + pin1 5 pin2 38 0 0 +net 5 +net 7 +segment channel 2 + pin1 14 pin2 43 0 0 +net 8 +segment channel 2 + pin1 23 pin2 17 0 0 +net 9 +net 11 +segment channel 2 + pin1 25 pin2 31 0 0 +net 14 +net 15 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.out b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.out new file mode 100644 index 000000000..00387ae5c --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.out @@ -0,0 +1,276 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + + +NOTE: Restart file .rs2 not used + +TimberWolf will perform a global route step +rowSep: 1.000000 +feedThruWidth: 4 + +****************** +BLOCK DATA +block:1 desire:85 +block:2 desire:85 +Total Desired Length: 170 +total cell length: 168 +total block length: 168 +block x-span:84 block y-span:78 +implicit feed thru range: -84 +Using default value of bin.penalty.control:1.000000 +numBins automatically set to:5 +binWidth = average_cell_width + 0 sigma= 17 +average_cell_width is:16 +standard deviation of cell length is:23.6305 +TimberWolfSC starting from the beginning + + + +THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 +The number of nets with 1 pin is 4 +The number of nets with 2 pin is 9 +The number of nets with 3 pin is 0 +The number of nets with 4 pin is 2 +The number of nets with 5 pin is 0 +The number of nets with 6 pin is 0 +The number of nets with 7 pin is 0 +The number of nets with 8 pin is 0 +The number of nets with 9 pin is 0 +The number of nets with 10 pin or more is 0 + +New Cost Function: Initial Horizontal Cost:242 +New Cost Function: FEEDS:0 MISSING_ROWS:-46 + +bdxlen:86 bdylen:78 +l:0 t:78 r:86 b:0 + + + +THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 + + + +THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 + +The rand generator seed was at utemp() : 1 + + + tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 + tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 + tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 + tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 + + I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs + 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 + 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 + 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 + 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 + 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 + 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 + 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 + 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 + 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 + 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 + 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 + 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 + 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 + 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 + 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 + 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 + 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 + 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 + 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 + 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 + 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 + 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 + 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 + 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 + 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 + 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 + 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 + 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 + 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 + 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 + 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 + 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 + 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 + 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 + 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 + 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 + 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 + 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 + 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 + 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 + 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 + 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 + 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 + 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 + 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 + 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 + 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 + 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 + 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 + 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 + 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 + 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 + 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 + 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 + 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 + 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 + 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 + 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 + 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 + 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 + 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 + 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 + 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 + 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 + 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 + 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 + 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 + 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 + 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 + 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 + 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 + 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 + 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 + 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 + 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 + 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 + 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 + 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 + 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 + 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 + 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 + 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 + 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 + 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 + 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 + 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 + 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 + 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 + 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 + 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 + 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 + 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 + 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 + 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 + 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 +100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 +101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 +102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 +103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 +104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 +105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 +106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 +107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 +108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 +109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 +110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 +111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 +112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 +113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 +114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 +115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 +116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 +117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 +118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 +119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 +120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 +121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 + +Initial Wiring Cost: 645 Final Wiring Cost: 732 +############## Percent Wire Cost Reduction: -13 + + +Initial Wire Length: 645 Final Wire Length: 732 +************** Percent Wire Length Reduction: -13 + + +Initial Horiz. Wire: 216 Final Horiz. Wire: 147 +$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 + + +Initial Vert. Wire: 429 Final Vert. Wire: 585 +@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 + +Before Feeds are Added: +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 82 -20 + 2 86 -16 + +LONGEST Block is:2 Its length is:86 +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 86 -16 + 2 86 -16 + +LONGEST Block is:1 Its length is:86 +Added: 1 feed-through cells + +Removed the cell overlaps --- Will do neighbor interchanges only now + +TOTAL INTERCONNECT LENGTH: 994 +OVERLAP PENALTY: 0 + +initialRowControl: 1.650 +finalRowControl: 0.300 +iter T Wire accept + 122 0.001 976 16% + 123 0.001 971 0% + 124 0.001 971 0% +Total Feed-Alignment Movement (Pass 1): 0 +Total Feed-Alignment Movement (Pass 2): 0 +Total Feed-Alignment Movement (Pass 3): 0 +Total Feed-Alignment Movement (Pass 4): 0 +Total Feed-Alignment Movement (Pass 5): 0 +Total Feed-Alignment Movement (Pass 6): 0 +Total Feed-Alignment Movement (Pass 7): 0 +Total Feed-Alignment Movement (Pass 8): 0 + +The rand generator seed was at globroute() : 987654321 + + +Total Number of Net Segments: 9 +Number of Switchable Net Segments: 0 + +Number of channels: 3 + + + +THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 + + +no. of accepted flips: 0 +no. of attempted flips: 0 +THIS IS THE NUMBER OF TRACKS: 5 + + + +FINAL NUMBER OF ROUTING TRACKS: 5 + +MAX OF CHANNEL: 1 is: 0 +MAX OF CHANNEL: 2 is: 4 +MAX OF CHANNEL: 3 is: 1 +FINAL TOTAL INTERCONNECT LENGTH: 978 +FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 +MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 + + +cost_scale_factor:3.90616 + +Number of Feed Thrus: 0 +Number of Implicit Feed Thrus: 0 + +Statistics: +Number of Standard Cells: 10 +Number of Pads: 0 +Number of Nets: 15 +Number of Pins: 46 +Usage statistics not available diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pin b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pin new file mode 100644 index 000000000..62b922e4e --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pin @@ -0,0 +1,17 @@ +$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 +$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 +B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 +B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 +B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl1 b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl1 new file mode 100644 index 000000000..bdc569e39 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl1 @@ -0,0 +1,11 @@ +$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 +$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 +$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 +ACOUNT_1 14 0 18 26 2 1 +twfeed1 18 0 22 26 0 1 +$COUNT_1/$FJK3_1 22 0 86 26 0 1 +$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 +$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 +$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 +$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 +$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl2 b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl2 new file mode 100644 index 000000000..6e2601e82 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl2 @@ -0,0 +1,2 @@ +1 0 0 86 26 0 0 +2 0 52 86 78 0 0 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sav b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sav new file mode 100644 index 000000000..04c8e9935 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sav @@ -0,0 +1,18 @@ +0.009592 +121 +0 +1 +0.000000 +0.500000 +3.906156 +1 +1 1 2 37 13 +2 2 0 34 65 +3 2 2 63 65 +4 1 0 59 13 +5 1 2 32 13 +6 2 0 23 65 +7 1 2 12 13 +8 2 0 6 65 +9 1 0 70 13 +10 2 0 70 65 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sv2 b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sv2 new file mode 100644 index 000000000..9dd68ecdb --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sv2 @@ -0,0 +1,19 @@ +0.001000 +123 +0 +2 +0.000000 +0.500000 +3.906156 +1 +1 1 2 16 13 +2 2 2 19 65 +3 2 2 14 65 +4 1 0 11 13 +5 1 2 6 13 +6 2 0 3 65 +7 1 0 2 13 +8 2 2 9 65 +9 1 0 50 13 +10 2 0 54 65 +11 1 0 84 13 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.twf b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.twf new file mode 100644 index 000000000..a4c2eac35 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.twf @@ -0,0 +1,29 @@ +net 1 +segment channel 2 + pin1 1 pin2 7 0 0 +net 2 +segment channel 3 +pin1 41 pin2 42 0 0 +segment channel 2 +pin1 12 pin2 3 0 0 +net 3 +segment channel 2 +pin1 35 pin2 36 0 0 +segment channel 2 +pin1 19 pin2 35 0 0 +net 4 +segment channel 2 + pin1 5 pin2 38 0 0 +net 5 +net 7 +segment channel 2 + pin1 14 pin2 43 0 0 +net 8 +segment channel 2 + pin1 23 pin2 17 0 0 +net 9 +net 11 +segment channel 2 + pin1 25 pin2 31 0 0 +net 14 +net 15 From 34a1f9e14e0e0afe42ed21dff8e7ed96462f7267 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Mon, 4 Dec 2006 19:05:09 -0500 Subject: [PATCH 18/20] Only update stderr, stdout, m5stats.txt, and config.* on update_ref, since we don't know which of the other files are outputs and which are inputs. --HG-- extra : convert_revision : b038bd15930721ab9fceb0a18ab5c895aacb5309 --- tests/SConscript | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/tests/SConscript b/tests/SConscript index 8560363f9..8c9029be6 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -114,11 +114,7 @@ def update_test(target, source, env): src_dir = str(source[1].get_dir()) dest_files = os.listdir(dest_dir) src_files = os.listdir(src_dir) - # Exclude status & diff outputs - for f in ('outdiff', 'statsdiff', 'status'): - if f in src_files: - src_files.remove(f) - for f in src_files: + for f in ('stdout', 'stderr', 'm5stats.txt', 'config.ini', 'config.out'): if f in dest_files: print " Replacing file", f dest_files.remove(f) From 9d39407500f5c5df37ca32fcbed574a2cdc454b9 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Mon, 4 Dec 2006 19:07:00 -0500 Subject: [PATCH 19/20] Update SPEC CPU2000 tests with actual benchmark output. tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini: tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out: tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt: tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr: tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout: tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini: tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out: tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt: tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr: tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout: tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini: tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out: tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt: tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr: tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout: tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini: tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out: tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt: tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr: tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout: tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini: tests/long/30.eon/ref/alpha/linux/simple-timing/config.out: tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt: tests/long/30.eon/ref/alpha/linux/simple-timing/stderr: tests/long/30.eon/ref/alpha/linux/simple-timing/stdout: tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini: tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out: tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt: tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr: tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout: tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini: tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out: tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt: tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr: tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout: tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini: tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out: tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt: tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr: tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout: tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini: tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out: tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt: tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr: tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout: tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini: tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out: tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt: tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr: tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout: tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini: tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out: tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt: tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr: tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout: tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini: tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out: tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt: tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr: tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout: tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini: tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out: tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt: tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr: tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout: tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini: tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out: tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt: tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr: tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout: tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini: tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out: tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt: tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr: tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout: tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini: tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out: tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt: tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr: tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout: Update with actual benchmark output. --HG-- extra : convert_revision : 12e8de58172dd717d9cc8c5c27dd926a7257153c --- .../ref/alpha/linux/o3-timing/config.ini | 28 +- .../ref/alpha/linux/o3-timing/config.out | 105 +- .../ref/alpha/linux/o3-timing/m5stats.txt | 2157 +++------------- .../00.gzip/ref/alpha/linux/o3-timing/stderr | 2 - .../00.gzip/ref/alpha/linux/o3-timing/stdout | 44 +- .../ref/alpha/linux/simple-atomic/config.ini | 352 +-- .../ref/alpha/linux/simple-atomic/config.out | 346 +-- .../ref/alpha/linux/simple-atomic/m5stats.txt | 1980 +-------------- .../ref/alpha/linux/simple-atomic/stderr | 2 - .../ref/alpha/linux/simple-atomic/stdout | 44 +- .../ref/alpha/linux/simple-timing/config.ini | 225 +- .../ref/alpha/linux/simple-timing/config.out | 265 +- .../ref/alpha/linux/simple-timing/m5stats.txt | 2040 ++-------------- .../ref/alpha/linux/simple-timing/stderr | 2 - .../ref/alpha/linux/simple-timing/stdout | 44 +- .../ref/alpha/linux/simple-atomic/config.ini | 352 +-- .../ref/alpha/linux/simple-atomic/config.out | 346 +-- .../ref/alpha/linux/simple-atomic/m5stats.txt | 1982 +-------------- .../ref/alpha/linux/simple-atomic/stderr | 48 +- .../ref/alpha/linux/simple-atomic/stdout | 15 +- .../ref/alpha/linux/simple-timing/config.ini | 225 +- .../ref/alpha/linux/simple-timing/config.out | 265 +- .../ref/alpha/linux/simple-timing/m5stats.txt | 2036 ++-------------- .../ref/alpha/linux/simple-timing/stderr | 48 +- .../ref/alpha/linux/simple-timing/stdout | 15 +- .../ref/alpha/linux/simple-atomic/config.ini | 352 +-- .../ref/alpha/linux/simple-atomic/config.out | 346 +-- .../ref/alpha/linux/simple-atomic/m5stats.txt | 1982 +-------------- .../ref/alpha/linux/simple-atomic/stderr | 3 +- .../ref/alpha/linux/simple-atomic/stdout | 1389 ++++++++++- .../ref/alpha/linux/simple-timing/config.ini | 225 +- .../ref/alpha/linux/simple-timing/config.out | 265 +- .../ref/alpha/linux/simple-timing/m5stats.txt | 2048 ++-------------- .../ref/alpha/linux/simple-timing/stderr | 3 +- .../ref/alpha/linux/simple-timing/stdout | 1389 ++++++++++- .../ref/alpha/linux/o3-timing/config.ini | 28 +- .../ref/alpha/linux/o3-timing/config.out | 105 +- .../ref/alpha/linux/o3-timing/m5stats.txt | 2167 +++-------------- .../ref/alpha/linux/o3-timing/stderr | 2 - .../ref/alpha/linux/o3-timing/stdout | 13 - .../ref/alpha/linux/simple-atomic/config.ini | 352 +-- .../ref/alpha/linux/simple-atomic/config.out | 346 +-- .../ref/alpha/linux/simple-atomic/m5stats.txt | 1982 +-------------- .../ref/alpha/linux/simple-atomic/stderr | 2 - .../ref/alpha/linux/simple-atomic/stdout | 13 - .../ref/alpha/linux/simple-timing/config.ini | 225 +- .../ref/alpha/linux/simple-timing/config.out | 265 +- .../ref/alpha/linux/simple-timing/m5stats.txt | 2048 ++-------------- .../ref/alpha/linux/simple-timing/stderr | 2 - .../ref/alpha/linux/simple-timing/stdout | 13 - .../ref/alpha/linux/o3-timing/config.ini | 28 +- .../ref/alpha/linux/o3-timing/config.out | 105 +- .../ref/alpha/linux/o3-timing/m5stats.txt | 2167 +++-------------- .../60.bzip2/ref/alpha/linux/o3-timing/stderr | 2 - .../60.bzip2/ref/alpha/linux/o3-timing/stdout | 27 +- .../ref/alpha/linux/simple-atomic/config.ini | 352 +-- .../ref/alpha/linux/simple-atomic/config.out | 346 +-- .../ref/alpha/linux/simple-atomic/m5stats.txt | 1982 +-------------- .../ref/alpha/linux/simple-atomic/stderr | 2 - .../ref/alpha/linux/simple-atomic/stdout | 27 +- .../ref/alpha/linux/simple-timing/config.ini | 225 +- .../ref/alpha/linux/simple-timing/config.out | 265 +- .../ref/alpha/linux/simple-timing/m5stats.txt | 2048 ++-------------- .../ref/alpha/linux/simple-timing/stderr | 2 - .../ref/alpha/linux/simple-timing/stdout | 27 +- .../ref/alpha/linux/o3-timing/config.ini | 28 +- .../ref/alpha/linux/o3-timing/config.out | 105 +- .../ref/alpha/linux/o3-timing/m5stats.txt | 2167 +++-------------- .../70.twolf/ref/alpha/linux/o3-timing/stderr | 2 - .../70.twolf/ref/alpha/linux/o3-timing/stdout | 25 +- .../ref/alpha/linux/simple-atomic/config.ini | 352 +-- .../ref/alpha/linux/simple-atomic/config.out | 346 +-- .../ref/alpha/linux/simple-atomic/m5stats.txt | 1982 +-------------- .../ref/alpha/linux/simple-atomic/stderr | 2 - .../ref/alpha/linux/simple-atomic/stdout | 25 +- .../ref/alpha/linux/simple-timing/config.ini | 225 +- .../ref/alpha/linux/simple-timing/config.out | 265 +- .../ref/alpha/linux/simple-timing/m5stats.txt | 2036 ++-------------- .../ref/alpha/linux/simple-timing/stderr | 2 - .../ref/alpha/linux/simple-timing/stdout | 25 +- 80 files changed, 6180 insertions(+), 37545 deletions(-) diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini index c3a59fbce..b221360e2 100644 --- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini @@ -7,11 +7,9 @@ max_tick=0 output_file=cout progress_interval=0 -[debug] -break_cycles= - [exetrace] intel_format=false +legion_lockstep=false pc_symbol=true print_cpseq=false print_cycle=true @@ -102,14 +100,15 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.dcache numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 +phase=0 predType=tournament +progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 renameToIEWDelay=2 @@ -131,7 +130,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -308,7 +306,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -348,7 +345,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -384,20 +380,33 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +responder_set=false +width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess -cmd=hello +cmd=gzip input.log 1 +cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/o3-timing +egid=100 env= -executable=tests/test-progs/hello/bin/alpha/linux/hello +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +responder_set=false +width=64 port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] @@ -409,6 +418,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out b/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out index f491a3081..704fa2535 100644 --- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out +++ b/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out @@ -19,54 +19,25 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 +responder_set=false [system.cpu.workload] type=LiveProcess -cmd=hello -executable=tests/test-progs/hello/bin/alpha/linux/hello +cmd=gzip input.log 1 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip input=cin output=cout env= +cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/o3-timing system=system - -[system.cpu.dcache] -type=BaseCache -size=262144 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu.fuPool.FUList0.opList0] type=OpDesc @@ -199,15 +170,16 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU clock=1 +phase=0 numThreads=1 activity=0 workload=system.cpu.workload -mem=system.cpu.dcache checker=null max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 cachePorts=200 decodeToFetchDelay=1 renameToFetchDelay=1 @@ -283,7 +255,44 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false protocol=null trace_addr=0 hash_delay=1 @@ -322,7 +331,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -354,10 +362,14 @@ hit_latency=1 [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 +responder_set=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -396,8 +408,9 @@ print_cpseq=false print_reg_delta=false pc_symbol=true intel_format=false +legion_lockstep=false trace_system=client -[debug] -break_cycles= +[statsreset] +reset_cycle=0 diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt index 5d4f9235a..bd4e6c524 100644 --- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,112 +1,112 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 542 # Number of BTB hits -global.BPredUnit.BTBLookups 1938 # Number of BTB lookups -global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted -global.BPredUnit.lookups 2256 # Number of BP lookups -global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 41797 # Simulator instruction rate (inst/s) -host_mem_usage 160344 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 50948 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 97621780 # Number of BTB hits +global.BPredUnit.BTBLookups 104888901 # Number of BTB lookups +global.BPredUnit.RASInCorrect 203 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 4270829 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 101462576 # Number of conditional branches predicted +global.BPredUnit.lookups 108029652 # Number of BP lookups +global.BPredUnit.usedRAS 1765818 # Number of times the RAS was used to get a target. +host_inst_rate 49266 # Simulator instruction rate (inst/s) +host_mem_usage 315608 # Number of bytes of host memory used +host_seconds 11479.54 # Real time elapsed on the host +host_tick_rate 147031 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 20975706 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 18042230 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 207074480 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 57063120 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 6870 # Number of ticks simulated -system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached +sim_insts 565552443 # Number of instructions simulated +sim_seconds 0.001688 # Number of seconds simulated +sim_ticks 1687849017 # Number of ticks simulated +system.cpu.commit.COM:branches 62547159 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 17132854 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.samples 701581491 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3908 6389.80% - 1 1064 1739.70% - 2 389 636.04% - 3 210 343.36% - 4 153 250.16% - 5 93 152.06% - 6 76 124.26% - 7 149 243.62% - 8 74 120.99% + 0 480309675 6846.10% + 1 104094392 1483.71% + 2 40244499 573.63% + 3 11990473 170.91% + 4 15113210 215.42% + 5 17360338 247.45% + 6 10367558 147.77% + 7 4968492 70.82% + 8 17132854 244.20% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 5640 # Number of instructions committed -system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:count 601856963 # Number of instructions committed +system.cpu.commit.COM:loads 115049510 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:refs 154862033 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions +system.cpu.commit.branchMispredicts 4270194 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5623 # Number of Instructions Simulated -system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.commit.commitSquashedInsts 331156834 # The number of squashed insts skipped by commit +system.cpu.committedInsts 565552443 # Number of Instructions Simulated +system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated +system.cpu.cpi 2.984425 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.984425 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 114919015 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3573.284961 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3259.194046 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 114199728 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2570217420 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.006259 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 719287 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 495902 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 728055062 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001944 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 223385 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3753.412851 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3080.837357 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 38221364 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4616536410 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.031177 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1229957 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 972712 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 792530006 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006521 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 257245 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 329.539233 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 2285.588257 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 317.127712 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 3492 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 327032 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 1150751 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 747460499 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses -system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 154370336 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3686.944185 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3163.733159 # average overall mshr miss latency +system.cpu.dcache.demand_hits 152421092 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 7186753830 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.012627 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1949244 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1468614 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 1520585068 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003113 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 480630 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 154370336 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3686.944185 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3163.733159 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2048 # number of overall hits -system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses -system.cpu.dcache.overall_misses 311 # number of overall misses -system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_hits 152421092 # number of overall hits +system.cpu.dcache.overall_miss_latency 7186753830 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.012627 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1949244 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1468614 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 1520585068 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003113 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 480630 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 476534 # number of replacements +system.cpu.dcache.sampled_refs 480630 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use -system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched -system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4061.534340 # Cycle average of tags in use +system.cpu.dcache.total_refs 152421092 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 22778000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 337990 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 113629190 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 667 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 4610173 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 1474333999 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 347767079 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 231043933 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 53597030 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 1980 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 9141290 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 108029652 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 167528188 # Number of cache lines fetched +system.cpu.fetch.Cycles 410392582 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 7840605 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 1486495774 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 39151172 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.143052 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 167528188 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 99387598 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.968403 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.samples 755178522 system.cpu.fetch.rateDist.min_value 0 - 0 4549 6620.58% - 1 174 253.24% - 2 186 270.70% - 3 157 228.50% - 4 211 307.09% - 5 153 222.68% - 6 171 248.87% - 7 105 152.82% - 8 1165 1695.53% + 0 512314112 6784.01% + 1 11453310 151.66% + 2 16801464 222.48% + 3 16318450 216.09% + 4 18767749 248.52% + 5 15201778 201.30% + 6 32935567 436.13% + 7 7297838 96.64% + 8 124088254 1643.16% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.icache.ReadReq_accesses 167528184 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5600.855285 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4703.251892 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 167526954 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 6889052 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1230 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 305 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 4350508 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 925 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets 5880.941176 # average number of cycles each access was blocked +system.cpu.icache.avg_refs 181110.220541 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 17 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 99976 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses -system.cpu.icache.demand_misses 327 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 167528184 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5600.855285 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4703.251892 # average overall mshr miss latency +system.cpu.icache.demand_hits 167526954 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 6889052 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses +system.cpu.icache.demand_misses 1230 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 305 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 4350508 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000006 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 925 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_accesses 167528184 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5600.855285 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4703.251892 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1255 # number of overall hits -system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses -system.cpu.icache.overall_misses 327 # number of overall misses -system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_hits 167526954 # number of overall hits +system.cpu.icache.overall_miss_latency 6889052 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses +system.cpu.icache.overall_misses 1230 # number of overall misses +system.cpu.icache.overall_mshr_hits 305 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 4350508 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 925 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,1646 +215,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.replacements 47 # number of replacements +system.cpu.icache.sampled_refs 925 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use -system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 739.927243 # Cycle average of tags in use +system.cpu.icache.total_refs 167526954 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:insts 7969 # Number of executed instructions -system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed -system.cpu.iew.EXEC:nop 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate -system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute -system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.idleCycles 932670496 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 92484798 # Number of branches executed +system.cpu.iew.EXEC:nop 154927960 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.987080 # Inst execution rate +system.cpu.iew.EXEC:refs 253735466 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 51400640 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5438 # num instructions consuming a value -system.cpu.iew.WB:count 7722 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:consumers 486804101 # num instructions consuming a value +system.cpu.iew.WB:count 671280122 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.809385 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4049 # num instructions producing a value -system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle -system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 394011709 # num instructions producing a value +system.cpu.iew.WB:rate 0.888903 # insts written-back per cycle +system.cpu.iew.WB:sent 673021204 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4738518 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 26824121 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 207074480 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 169524029 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 57063120 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 933012139 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 202334826 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7294318 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 745421559 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 36474 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.iewLSQFullEvents 1439 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 53597030 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 214253 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 5548 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 70837719 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 7377596 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 20150 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemWrite.max_value 0 -system.cpu.iq.IQ:residence:MemWrite.end_dist - -system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 1892 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 5548 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 92024970 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 17250597 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 1892 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2705247 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 2033271 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.335073 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.335073 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 752715877 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5594 66.69% # Type of FU issued - IntMult 1 0.01% # Type of FU issued + (null) 0 0.00% # Type of FU issued + IntAlu 496182294 65.92% # Type of FU issued + IntMult 8208 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued + FloatAdd 33 0.00% # Type of FU issued + FloatCmp 6 0.00% # Type of FU issued + FloatCvt 5 0.00% # Type of FU issued + FloatMult 5 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1757 20.95% # Type of FU issued - MemWrite 1032 12.30% # Type of FU issued + MemRead 204178453 27.13% # Type of FU issued + MemWrite 52346873 6.95% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 3466320 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.004605 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 0.87% # attempts to use FU when none available + IntAlu 2723724 78.58% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -1863,78 +297,80 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 76 66.09% # attempts to use FU when none available - MemWrite 38 33.04% # attempts to use FU when none available + MemRead 683243 19.71% # attempts to use FU when none available + MemWrite 59353 1.71% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.samples 755178522 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3753 5462.09% - 1 894 1301.12% - 2 723 1052.25% - 3 614 893.61% - 4 451 656.38% - 5 279 406.05% - 6 104 151.36% - 7 41 59.67% - 8 12 17.46% + 0 450030250 5959.26% + 1 91846319 1216.22% + 2 83470092 1105.30% + 3 53962116 714.56% + 4 57175468 757.11% + 5 10089384 133.60% + 6 7448894 98.64% + 7 1047122 13.87% + 8 108877 1.44% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate -system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.iq.ISSUE:rate 0.996739 # Inst issue rate +system.cpu.iq.iqInstsAdded 778084154 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 752715877 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 210836257 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 250496 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 119170992 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 481555 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 6806.870170 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2221.284395 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 455236 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 179150016 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.054654 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 26319 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 58461984 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054654 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 26319 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 337990 # number of WriteReqNoAck|Writeback accesses(hits+misses) +system.cpu.l2cache.WriteReqNoAck|Writeback_hits 337990 # number of WriteReqNoAck|Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 30.138911 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 481555 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 6806.870170 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2221.284395 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 455236 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 179150016 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.054654 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 26319 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 58461984 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.054654 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 26319 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_accesses 819545 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 6806.870170 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2221.284395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 793226 # number of overall hits +system.cpu.l2cache.overall_miss_latency 179150016 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.032114 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 26319 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 58461984 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.032114 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 26319 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -1946,29 +382,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 934 # number of replacements +system.cpu.l2cache.sampled_refs 26319 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 24352.046438 # Cycle average of tags in use +system.cpu.l2cache.total_refs 793226 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 6871 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed +system.cpu.l2cache.writebacks 907 # number of writebacks +system.cpu.numCycles 755178522 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 71954881 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 32102756 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 363513131 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 18414484 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 164520 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 1301215151 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 1374424300 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 698904999 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 224329578 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 53597030 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 41747264 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 235050110 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 36638 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 30 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 105666858 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 28 # count of temporary serializing insts renamed +system.cpu.timesIdled 349047 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr b/tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr index 8893caac8..87866a2a5 100644 --- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr +++ b/tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr @@ -1,3 +1 @@ warn: Entering event queue @ 0. Starting simulation... -warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 -warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout b/tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout index fbb329a2f..9aaca3eeb 100644 --- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout +++ b/tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout @@ -1,13 +1,31 @@ -Hello world! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:12 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Exiting @ tick 6870 because target called exit() +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini index c3a59fbce..841e8766f 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini @@ -7,11 +7,9 @@ max_tick=0 output_file=cout progress_interval=0 -[debug] -break_cycles= - [exetrace] intel_format=false +legion_lockstep=false pc_symbol=true print_cpseq=false print_cycle=true @@ -53,352 +51,49 @@ mem_mode=atomic physmem=system.physmem [system.cpu] -type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus workload -BTBEntries=4096 -BTBTagSize=16 -LFSTSize=1024 -LQEntries=32 -RASSize=16 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -choiceCtrBits=2 -choicePredictorSize=8192 +type=AtomicSimpleCPU +children=workload clock=1 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 +cpu_id=0 defer_registration=false -dispatchWidth=8 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -instShiftAmt=2 -issueToExecuteDelay=1 -issueWidth=8 -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.dcache -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -predType=tournament -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -squashWidth=8 +phase=0 +progress_interval=0 +simulate_stalls=false system=system -trapLatency=13 -wbDepth=1 -wbWidth=8 +width=1 workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -do_copy=false -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=262144 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList0 -count=6 -opList=system.cpu.fuPool.FUList0.opList0 - -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList4.opList0 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList5.opList0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 -count=1 -opList=system.cpu.fuPool.FUList7.opList0 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - -[system.cpu.icache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -do_copy=false -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=131072 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.l2cache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -do_copy=false -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=2097152 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] - -[system.cpu.toL2Bus] -type=Bus -bus_id=0 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess -cmd=hello +cmd=gzip input.log 1 +cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-atomic +egid=100 env= -executable=tests/test-progs/hello/bin/alpha/linux/hello +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 -port=system.physmem.port system.cpu.l2cache.mem_side +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory @@ -409,6 +104,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out index f491a3081..b5a24e5fb 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out +++ b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out @@ -19,345 +19,48 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 +responder_set=false [system.cpu.workload] type=LiveProcess -cmd=hello -executable=tests/test-progs/hello/bin/alpha/linux/hello +cmd=gzip input.log 1 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip input=cin output=cout env= +cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-atomic system=system - -[system.cpu.dcache] -type=BaseCache -size=262144 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -opClass=IntAlu -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList0] -type=FUDesc -opList=system.cpu.fuPool.FUList0.opList0 -count=6 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -opClass=IntMult -opLat=3 -issueLat=1 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -opClass=IntDiv -opLat=20 -issueLat=19 - -[system.cpu.fuPool.FUList1] -type=FUDesc -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 -count=2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -opClass=FloatAdd -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -opClass=FloatCmp -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -opClass=FloatCvt -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2] -type=FUDesc -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 -count=4 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -opClass=FloatMult -opLat=4 -issueLat=1 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -opClass=FloatDiv -opLat=12 -issueLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -opClass=FloatSqrt -opLat=24 -issueLat=24 - -[system.cpu.fuPool.FUList3] -type=FUDesc -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 -count=2 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList4] -type=FUDesc -opList=system.cpu.fuPool.FUList4.opList0 -count=0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -opList=system.cpu.fuPool.FUList5.opList0 -count=0 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -count=4 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -opClass=IprAccess -opLat=3 -issueLat=3 - -[system.cpu.fuPool.FUList7] -type=FUDesc -opList=system.cpu.fuPool.FUList7.opList0 -count=1 - -[system.cpu.fuPool] -type=FUPool -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] -type=DerivO3CPU -clock=1 -numThreads=1 -activity=0 -workload=system.cpu.workload -mem=system.cpu.dcache -checker=null +type=AtomicSimpleCPU max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 -cachePorts=200 -decodeToFetchDelay=1 -renameToFetchDelay=1 -iewToFetchDelay=1 -commitToFetchDelay=1 -fetchWidth=8 -renameToDecodeDelay=1 -iewToDecodeDelay=1 -commitToDecodeDelay=1 -fetchToDecodeDelay=1 -decodeWidth=8 -iewToRenameDelay=1 -commitToRenameDelay=1 -decodeToRenameDelay=1 -renameWidth=8 -commitToIEWDelay=1 -renameToIEWDelay=2 -issueToExecuteDelay=1 -dispatchWidth=8 -issueWidth=8 -wbWidth=8 -wbDepth=1 -fuPool=system.cpu.fuPool -iewToCommitDelay=1 -renameToROBDelay=1 -commitWidth=8 -squashWidth=8 -trapLatency=13 -backComSize=5 -forwardComSize=5 -predType=tournament -localPredictorSize=2048 -localCtrBits=2 -localHistoryTableSize=2048 -localHistoryBits=11 -globalPredictorSize=8192 -globalCtrBits=2 -globalHistoryBits=13 -choicePredictorSize=8192 -choiceCtrBits=2 -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -LQEntries=32 -SQEntries=32 -LFSTSize=1024 -SSITSize=1024 -numPhysIntRegs=256 -numPhysFloatRegs=256 -numIQEntries=64 -numROBEntries=192 -smtNumFetchingThreads=1 -smtFetchPolicy=SingleThread -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtROBPolicy=Partitioned -smtROBThreshold=100 -smtCommitPolicy=RoundRobin -instShiftAmt=2 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 defer_registration=false +width=1 function_trace=false function_trace_start=0 - -[system.cpu.icache] -type=BaseCache -size=131072 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.l2cache] -type=BaseCache -size=2097152 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.toL2Bus] -type=Bus -bus_id=0 +simulate_stalls=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -396,8 +99,9 @@ print_cpseq=false print_reg_delta=false pc_symbol=true intel_format=false +legion_lockstep=false trace_system=client -[debug] -break_cycles= +[statsreset] +reset_cycle=0 diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt index 5d4f9235a..b8593d3a3 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,1974 +1,18 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 542 # Number of BTB hits -global.BPredUnit.BTBLookups 1938 # Number of BTB lookups -global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted -global.BPredUnit.lookups 2256 # Number of BP lookups -global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 41797 # Simulator instruction rate (inst/s) -host_mem_usage 160344 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 50948 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +host_inst_rate 970342 # Simulator instruction rate (inst/s) +host_mem_usage 144620 # Number of bytes of host memory used +host_seconds 620.25 # Real time elapsed on the host +host_tick_rate 970342 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 6870 # Number of ticks simulated -system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6116 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3908 6389.80% - 1 1064 1739.70% - 2 389 636.04% - 3 210 343.36% - 4 153 250.16% - 5 93 152.06% - 6 76 124.26% - 7 149 243.62% - 8 74 120.99% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 5640 # Number of instructions committed -system.cpu.commit.COM:loads 979 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 1791 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5623 # Number of Instructions Simulated -system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses -system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2048 # number of overall hits -system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses -system.cpu.dcache.overall_misses 311 # number of overall misses -system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use -system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched -system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6871 -system.cpu.fetch.rateDist.min_value 0 - 0 4549 6620.58% - 1 174 253.24% - 2 186 270.70% - 3 157 228.50% - 4 211 307.09% - 5 153 222.68% - 6 171 248.87% - 7 105 152.82% - 8 1165 1695.53% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses -system.cpu.icache.demand_misses 327 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1255 # number of overall hits -system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses -system.cpu.icache.overall_misses 327 # number of overall misses -system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use -system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:insts 7969 # Number of executed instructions -system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed -system.cpu.iew.EXEC:nop 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate -system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute -system.cpu.iew.EXEC:stores 989 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5438 # num instructions consuming a value -system.cpu.iew.WB:count 7722 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4049 # num instructions producing a value -system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle -system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemWrite.max_value 0 -system.cpu.iq.IQ:residence:MemWrite.end_dist - -system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5594 66.69% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 1757 20.95% # Type of FU issued - MemWrite 1032 12.30% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 0.87% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 76 66.09% # attempts to use FU when none available - MemWrite 38 33.04% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3753 5462.09% - 1 894 1301.12% - 2 723 1052.25% - 3 614 893.61% - 4 451 656.38% - 5 279 406.05% - 6 104 151.36% - 7 41 59.67% - 8 12 17.46% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate -system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 497 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 6871 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed +sim_insts 601856965 # Number of instructions simulated +sim_seconds 0.000602 # Number of seconds simulated +sim_ticks 601856964 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 601856965 # number of cpu cycles simulated +system.cpu.num_insts 601856965 # Number of instructions executed +system.cpu.num_refs 154862034 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr index 8893caac8..87866a2a5 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr +++ b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr @@ -1,3 +1 @@ warn: Entering event queue @ 0. Starting simulation... -warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 -warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout index fbb329a2f..9aaca3eeb 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout @@ -1,13 +1,31 @@ -Hello world! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:12 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Exiting @ tick 6870 because target called exit() +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini index c3a59fbce..48a760b08 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini @@ -7,11 +7,9 @@ max_tick=0 output_file=cout progress_interval=0 -[debug] -break_cycles= - [exetrace] intel_format=false +legion_lockstep=false pc_symbol=true print_cpseq=false print_cycle=true @@ -53,73 +51,20 @@ mem_mode=atomic physmem=system.physmem [system.cpu] -type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus workload -BTBEntries=4096 -BTBTagSize=16 -LFSTSize=1024 -LQEntries=32 -RASSize=16 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -choiceCtrBits=2 -choicePredictorSize=8192 +type=TimingSimpleCPU +children=dcache icache l2cache toL2Bus workload clock=1 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 +cpu_id=0 defer_registration=false -dispatchWidth=8 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -instShiftAmt=2 -issueToExecuteDelay=1 -issueWidth=8 -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.dcache -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -predType=tournament -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -squashWidth=8 +phase=0 +progress_interval=0 system=system -trapLatency=13 -wbDepth=1 -wbWidth=8 workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -131,7 +76,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -164,143 +108,6 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList0 -count=6 -opList=system.cpu.fuPool.FUList0.opList0 - -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList4.opList0 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList5.opList0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 -count=1 -opList=system.cpu.fuPool.FUList7.opList0 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - [system.cpu.icache] type=BaseCache adaptive_compression=false @@ -308,7 +115,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -348,7 +154,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -384,20 +189,33 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +responder_set=false +width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess -cmd=hello +cmd=gzip input.log 1 +cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-timing +egid=100 env= -executable=tests/test-progs/hello/bin/alpha/linux/hello +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +responder_set=false +width=64 port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] @@ -409,6 +227,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out b/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out index f491a3081..eddb9ff53 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out @@ -19,19 +19,54 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 +responder_set=false [system.cpu.workload] type=LiveProcess -cmd=hello -executable=tests/test-progs/hello/bin/alpha/linux/hello +cmd=gzip input.log 1 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip input=cin output=cout env= +cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-timing system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 -[system.cpu.dcache] +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.icache] type=BaseCache -size=262144 +size=131072 assoc=2 block_size=64 latency=1 @@ -39,7 +74,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -68,214 +102,9 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -opClass=IntAlu -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList0] -type=FUDesc -opList=system.cpu.fuPool.FUList0.opList0 -count=6 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -opClass=IntMult -opLat=3 -issueLat=1 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -opClass=IntDiv -opLat=20 -issueLat=19 - -[system.cpu.fuPool.FUList1] -type=FUDesc -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 -count=2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -opClass=FloatAdd -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -opClass=FloatCmp -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -opClass=FloatCvt -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2] -type=FUDesc -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 -count=4 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -opClass=FloatMult -opLat=4 -issueLat=1 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -opClass=FloatDiv -opLat=12 -issueLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -opClass=FloatSqrt -opLat=24 -issueLat=24 - -[system.cpu.fuPool.FUList3] -type=FUDesc -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 -count=2 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList4] -type=FUDesc -opList=system.cpu.fuPool.FUList4.opList0 -count=0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -opList=system.cpu.fuPool.FUList5.opList0 -count=0 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -count=4 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -opClass=IprAccess -opLat=3 -issueLat=3 - -[system.cpu.fuPool.FUList7] -type=FUDesc -opList=system.cpu.fuPool.FUList7.opList0 -count=1 - -[system.cpu.fuPool] -type=FUPool -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 - -[system.cpu] -type=DerivO3CPU -clock=1 -numThreads=1 -activity=0 -workload=system.cpu.workload -mem=system.cpu.dcache -checker=null -max_insts_any_thread=0 -max_insts_all_threads=0 -max_loads_any_thread=0 -max_loads_all_threads=0 -cachePorts=200 -decodeToFetchDelay=1 -renameToFetchDelay=1 -iewToFetchDelay=1 -commitToFetchDelay=1 -fetchWidth=8 -renameToDecodeDelay=1 -iewToDecodeDelay=1 -commitToDecodeDelay=1 -fetchToDecodeDelay=1 -decodeWidth=8 -iewToRenameDelay=1 -commitToRenameDelay=1 -decodeToRenameDelay=1 -renameWidth=8 -commitToIEWDelay=1 -renameToIEWDelay=2 -issueToExecuteDelay=1 -dispatchWidth=8 -issueWidth=8 -wbWidth=8 -wbDepth=1 -fuPool=system.cpu.fuPool -iewToCommitDelay=1 -renameToROBDelay=1 -commitWidth=8 -squashWidth=8 -trapLatency=13 -backComSize=5 -forwardComSize=5 -predType=tournament -localPredictorSize=2048 -localCtrBits=2 -localHistoryTableSize=2048 -localHistoryBits=11 -globalPredictorSize=8192 -globalCtrBits=2 -globalHistoryBits=13 -choicePredictorSize=8192 -choiceCtrBits=2 -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -LQEntries=32 -SQEntries=32 -LFSTSize=1024 -SSITSize=1024 -numPhysIntRegs=256 -numPhysFloatRegs=256 -numIQEntries=64 -numROBEntries=192 -smtNumFetchingThreads=1 -smtFetchPolicy=SingleThread -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtROBPolicy=Partitioned -smtROBThreshold=100 -smtCommitPolicy=RoundRobin -instShiftAmt=2 -defer_registration=false -function_trace=false -function_trace_start=0 - -[system.cpu.icache] +[system.cpu.dcache] type=BaseCache -size=131072 +size=262144 assoc=2 block_size=64 latency=1 @@ -283,7 +112,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -322,7 +150,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -351,13 +178,10 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[system.cpu.toL2Bus] -type=Bus -bus_id=0 - [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -396,8 +220,9 @@ print_cpseq=false print_reg_delta=false pc_symbol=true intel_format=false +legion_lockstep=false trace_system=client -[debug] -break_cycles= +[statsreset] +reset_cycle=0 diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt index 5d4f9235a..5e7441c54 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,112 +1,67 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 542 # Number of BTB hits -global.BPredUnit.BTBLookups 1938 # Number of BTB lookups -global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted -global.BPredUnit.lookups 2256 # Number of BP lookups -global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 41797 # Simulator instruction rate (inst/s) -host_mem_usage 160344 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 50948 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +host_inst_rate 549029 # Simulator instruction rate (inst/s) +host_mem_usage 300652 # Number of bytes of host memory used +host_seconds 1096.22 # Real time elapsed on the host +host_tick_rate 1916109 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 6870 # Number of ticks simulated -system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6116 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3908 6389.80% - 1 1064 1739.70% - 2 389 636.04% - 3 210 343.36% - 4 153 250.16% - 5 93 152.06% - 6 76 124.26% - 7 149 243.62% - 8 74 120.99% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 5640 # Number of instructions committed -system.cpu.commit.COM:loads 979 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 1791 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5623 # Number of Instructions Simulated -system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +sim_insts 601856965 # Number of instructions simulated +sim_seconds 0.002100 # Number of seconds simulated +sim_ticks 2100480012 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 2845.396229 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1845.396229 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 572584774 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 371352774 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3026.723012 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2026.723012 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 769281001 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 515118001 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses -system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2946.597514 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 1946.597514 # average overall mshr miss latency +system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1341865775 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses +system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 886470775 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2946.597514 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 1946.597514 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2048 # number of overall hits -system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses -system.cpu.dcache.overall_misses 311 # number of overall misses -system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_hits 153509968 # number of overall hits +system.cpu.dcache.overall_miss_latency 1341865775 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses +system.cpu.dcache.overall_misses 455395 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 886470775 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 451299 # number of replacements +system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use -system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched -system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6871 -system.cpu.fetch.rateDist.min_value 0 - 0 4549 6620.58% - 1 174 253.24% - 2 186 270.70% - 3 157 228.50% - 4 211 307.09% - 5 153 222.68% - 6 171 248.87% - 7 105 152.82% - 8 1165 1695.53% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 4053.427393 # Cycle average of tags in use +system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 33693000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 325723 # number of writebacks +system.cpu.icache.ReadReq_accesses 601856966 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 4085.659119 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3085.659119 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 601856171 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 3248099 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 2453099 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 757051.787421 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses -system.cpu.icache.demand_misses 327 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 601856966 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 4085.659119 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3085.659119 # average overall mshr miss latency +system.cpu.icache.demand_hits 601856171 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 3248099 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses +system.cpu.icache.demand_misses 795 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 2453099 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_accesses 601856966 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 4085.659119 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3085.659119 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1255 # number of overall hits -system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses -system.cpu.icache.overall_misses 327 # number of overall misses -system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_hits 601856171 # number of overall hits +system.cpu.icache.overall_miss_latency 3248099 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses +system.cpu.icache.overall_misses 795 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 2453099 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,1726 +135,60 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.replacements 24 # number of replacements +system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use -system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 642.094524 # Cycle average of tags in use +system.cpu.icache.total_refs 601856171 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:insts 7969 # Number of executed instructions -system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed -system.cpu.iew.EXEC:nop 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate -system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute -system.cpu.iew.EXEC:stores 989 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5438 # num instructions consuming a value -system.cpu.iew.WB:count 7722 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4049 # num instructions producing a value -system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle -system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemWrite.max_value 0 -system.cpu.iq.IQ:residence:MemWrite.end_dist - -system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5594 66.69% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 1757 20.95% # Type of FU issued - MemWrite 1032 12.30% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 0.87% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 76 66.09% # attempts to use FU when none available - MemWrite 38 33.04% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3753 5462.09% - 1 894 1301.12% - 2 723 1052.25% - 3 614 893.61% - 4 451 656.38% - 5 279 406.05% - 6 104 151.36% - 7 41 59.67% - 8 12 17.46% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate -system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadReq_accesses 456190 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3251.348149 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1946.946471 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 430092 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 84853684 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.057209 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 26098 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 50811409 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.057209 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 26098 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 325723 # number of WriteReqNoAck|Writeback accesses(hits+misses) +system.cpu.l2cache.WriteReqNoAck|Writeback_hits 325723 # number of WriteReqNoAck|Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 28.960648 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3251.348149 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1946.946471 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 430092 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 84853684 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.057209 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 26098 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 50811409 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.057209 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 26098 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 781913 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3251.348149 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1946.946471 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_hits 755815 # number of overall hits +system.cpu.l2cache.overall_miss_latency 84853684 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.033377 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 26098 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 50811409 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.033377 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 26098 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -1946,29 +200,17 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 903 # number of replacements +system.cpu.l2cache.sampled_refs 26098 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 24085.007455 # Cycle average of tags in use +system.cpu.l2cache.total_refs 755815 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 6871 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed +system.cpu.l2cache.writebacks 883 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 2100480012 # number of cpu cycles simulated +system.cpu.num_insts 601856965 # Number of instructions executed +system.cpu.num_refs 154862034 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr b/tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr index 8893caac8..87866a2a5 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr +++ b/tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr @@ -1,3 +1 @@ warn: Entering event queue @ 0. Starting simulation... -warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 -warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout b/tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout index fbb329a2f..9aaca3eeb 100644 --- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout +++ b/tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout @@ -1,13 +1,31 @@ -Hello world! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:12 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Exiting @ tick 6870 because target called exit() +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini index c3a59fbce..088cd1a9f 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini @@ -7,11 +7,9 @@ max_tick=0 output_file=cout progress_interval=0 -[debug] -break_cycles= - [exetrace] intel_format=false +legion_lockstep=false pc_symbol=true print_cpseq=false print_cycle=true @@ -53,352 +51,49 @@ mem_mode=atomic physmem=system.physmem [system.cpu] -type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus workload -BTBEntries=4096 -BTBTagSize=16 -LFSTSize=1024 -LQEntries=32 -RASSize=16 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -choiceCtrBits=2 -choicePredictorSize=8192 +type=AtomicSimpleCPU +children=workload clock=1 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 +cpu_id=0 defer_registration=false -dispatchWidth=8 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -instShiftAmt=2 -issueToExecuteDelay=1 -issueWidth=8 -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.dcache -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -predType=tournament -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -squashWidth=8 +phase=0 +progress_interval=0 +simulate_stalls=false system=system -trapLatency=13 -wbDepth=1 -wbWidth=8 +width=1 workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -do_copy=false -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=262144 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList0 -count=6 -opList=system.cpu.fuPool.FUList0.opList0 - -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList4.opList0 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList5.opList0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 -count=1 -opList=system.cpu.fuPool.FUList7.opList0 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - -[system.cpu.icache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -do_copy=false -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=131072 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.l2cache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -do_copy=false -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=2097152 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] - -[system.cpu.toL2Bus] -type=Bus -bus_id=0 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess -cmd=hello +cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook +cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-atomic +egid=100 env= -executable=tests/test-progs/hello/bin/alpha/linux/hello +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 -port=system.physmem.port system.cpu.l2cache.mem_side +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory @@ -409,6 +104,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out b/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out index f491a3081..bec900d0f 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out +++ b/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out @@ -19,345 +19,48 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 +responder_set=false [system.cpu.workload] type=LiveProcess -cmd=hello -executable=tests/test-progs/hello/bin/alpha/linux/hello +cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook +executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon input=cin output=cout env= +cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-atomic system=system - -[system.cpu.dcache] -type=BaseCache -size=262144 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -opClass=IntAlu -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList0] -type=FUDesc -opList=system.cpu.fuPool.FUList0.opList0 -count=6 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -opClass=IntMult -opLat=3 -issueLat=1 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -opClass=IntDiv -opLat=20 -issueLat=19 - -[system.cpu.fuPool.FUList1] -type=FUDesc -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 -count=2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -opClass=FloatAdd -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -opClass=FloatCmp -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -opClass=FloatCvt -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2] -type=FUDesc -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 -count=4 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -opClass=FloatMult -opLat=4 -issueLat=1 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -opClass=FloatDiv -opLat=12 -issueLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -opClass=FloatSqrt -opLat=24 -issueLat=24 - -[system.cpu.fuPool.FUList3] -type=FUDesc -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 -count=2 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList4] -type=FUDesc -opList=system.cpu.fuPool.FUList4.opList0 -count=0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -opList=system.cpu.fuPool.FUList5.opList0 -count=0 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -count=4 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -opClass=IprAccess -opLat=3 -issueLat=3 - -[system.cpu.fuPool.FUList7] -type=FUDesc -opList=system.cpu.fuPool.FUList7.opList0 -count=1 - -[system.cpu.fuPool] -type=FUPool -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] -type=DerivO3CPU -clock=1 -numThreads=1 -activity=0 -workload=system.cpu.workload -mem=system.cpu.dcache -checker=null +type=AtomicSimpleCPU max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 -cachePorts=200 -decodeToFetchDelay=1 -renameToFetchDelay=1 -iewToFetchDelay=1 -commitToFetchDelay=1 -fetchWidth=8 -renameToDecodeDelay=1 -iewToDecodeDelay=1 -commitToDecodeDelay=1 -fetchToDecodeDelay=1 -decodeWidth=8 -iewToRenameDelay=1 -commitToRenameDelay=1 -decodeToRenameDelay=1 -renameWidth=8 -commitToIEWDelay=1 -renameToIEWDelay=2 -issueToExecuteDelay=1 -dispatchWidth=8 -issueWidth=8 -wbWidth=8 -wbDepth=1 -fuPool=system.cpu.fuPool -iewToCommitDelay=1 -renameToROBDelay=1 -commitWidth=8 -squashWidth=8 -trapLatency=13 -backComSize=5 -forwardComSize=5 -predType=tournament -localPredictorSize=2048 -localCtrBits=2 -localHistoryTableSize=2048 -localHistoryBits=11 -globalPredictorSize=8192 -globalCtrBits=2 -globalHistoryBits=13 -choicePredictorSize=8192 -choiceCtrBits=2 -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -LQEntries=32 -SQEntries=32 -LFSTSize=1024 -SSITSize=1024 -numPhysIntRegs=256 -numPhysFloatRegs=256 -numIQEntries=64 -numROBEntries=192 -smtNumFetchingThreads=1 -smtFetchPolicy=SingleThread -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtROBPolicy=Partitioned -smtROBThreshold=100 -smtCommitPolicy=RoundRobin -instShiftAmt=2 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 defer_registration=false +width=1 function_trace=false function_trace_start=0 - -[system.cpu.icache] -type=BaseCache -size=131072 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.l2cache] -type=BaseCache -size=2097152 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.toL2Bus] -type=Bus -bus_id=0 +simulate_stalls=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -396,8 +99,9 @@ print_cpseq=false print_reg_delta=false pc_symbol=true intel_format=false +legion_lockstep=false trace_system=client -[debug] -break_cycles= +[statsreset] +reset_cycle=0 diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt index 5d4f9235a..a308f5e36 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,1974 +1,18 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 542 # Number of BTB hits -global.BPredUnit.BTBLookups 1938 # Number of BTB lookups -global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted -global.BPredUnit.lookups 2256 # Number of BP lookups -global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 41797 # Simulator instruction rate (inst/s) -host_mem_usage 160344 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 50948 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +host_inst_rate 841426 # Simulator instruction rate (inst/s) +host_mem_usage 147172 # Number of bytes of host memory used +host_seconds 473.80 # Real time elapsed on the host +host_tick_rate 841425 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 6870 # Number of ticks simulated -system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6116 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3908 6389.80% - 1 1064 1739.70% - 2 389 636.04% - 3 210 343.36% - 4 153 250.16% - 5 93 152.06% - 6 76 124.26% - 7 149 243.62% - 8 74 120.99% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 5640 # Number of instructions committed -system.cpu.commit.COM:loads 979 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 1791 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5623 # Number of Instructions Simulated -system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses -system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2048 # number of overall hits -system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses -system.cpu.dcache.overall_misses 311 # number of overall misses -system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use -system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched -system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6871 -system.cpu.fetch.rateDist.min_value 0 - 0 4549 6620.58% - 1 174 253.24% - 2 186 270.70% - 3 157 228.50% - 4 211 307.09% - 5 153 222.68% - 6 171 248.87% - 7 105 152.82% - 8 1165 1695.53% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses -system.cpu.icache.demand_misses 327 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1255 # number of overall hits -system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses -system.cpu.icache.overall_misses 327 # number of overall misses -system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use -system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:insts 7969 # Number of executed instructions -system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed -system.cpu.iew.EXEC:nop 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate -system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute -system.cpu.iew.EXEC:stores 989 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5438 # num instructions consuming a value -system.cpu.iew.WB:count 7722 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4049 # num instructions producing a value -system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle -system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemWrite.max_value 0 -system.cpu.iq.IQ:residence:MemWrite.end_dist - -system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5594 66.69% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 1757 20.95% # Type of FU issued - MemWrite 1032 12.30% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 0.87% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 76 66.09% # attempts to use FU when none available - MemWrite 38 33.04% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3753 5462.09% - 1 894 1301.12% - 2 723 1052.25% - 3 614 893.61% - 4 451 656.38% - 5 279 406.05% - 6 104 151.36% - 7 41 59.67% - 8 12 17.46% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate -system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 497 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 6871 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +sim_insts 398664450 # Number of instructions simulated +sim_seconds 0.000399 # Number of seconds simulated +sim_ticks 398664449 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 398664450 # number of cpu cycles simulated +system.cpu.num_insts 398664450 # Number of instructions executed +system.cpu.num_refs 174183390 # Number of memory references +system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr b/tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr index 8893caac8..1d6957eca 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr +++ b/tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr @@ -1,3 +1,47 @@ warn: Entering event queue @ 0. Starting simulation... -warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 -warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 +getting pixel output filename pixels_out.cook +opening control file chair.control.cook +opening camera file chair.camera +opening surfaces file chair.surfaces +reading data +processing 8parts +Grid measure is 6 by 3.0001 by 6 +cell dimension is 0.863065 +Creating grid for list of length 21 +Grid size = 7 by 4 by 7 +Total occupancy = 236 +reading control stream +reading camera stream +Writing to chair.cook.ppm +calculating 15 by 15 image with 196 samples +col 0. . . +col 1. . . +col 2. . . +col 3. . . +col 4. . . +col 5. . . +col 6. . . +col 7. . . +col 8. . . +col 9. . . +col 10. . . +col 11. . . +col 12. . . +col 13. . . +col 14. . . +Writing to chair.cook.ppm +0 8 14 +1 8 14 +2 8 14 +3 8 14 +4 8 14 +5 8 14 +6 8 14 +7 8 14 +8 8 14 +9 8 14 +10 8 14 +11 8 14 +12 8 14 +13 8 14 +14 8 14 diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout b/tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout index fbb329a2f..039e2d4ce 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout +++ b/tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout @@ -1,13 +1,2 @@ -Hello world! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:12 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Exiting @ tick 6870 because target called exit() +Eon, Version 1.1 +OO-style eon Time= 0.000000 diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini index c3a59fbce..b56d96049 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini @@ -7,11 +7,9 @@ max_tick=0 output_file=cout progress_interval=0 -[debug] -break_cycles= - [exetrace] intel_format=false +legion_lockstep=false pc_symbol=true print_cpseq=false print_cycle=true @@ -53,73 +51,20 @@ mem_mode=atomic physmem=system.physmem [system.cpu] -type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus workload -BTBEntries=4096 -BTBTagSize=16 -LFSTSize=1024 -LQEntries=32 -RASSize=16 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -choiceCtrBits=2 -choicePredictorSize=8192 +type=TimingSimpleCPU +children=dcache icache l2cache toL2Bus workload clock=1 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 +cpu_id=0 defer_registration=false -dispatchWidth=8 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -instShiftAmt=2 -issueToExecuteDelay=1 -issueWidth=8 -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.dcache -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -predType=tournament -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -squashWidth=8 +phase=0 +progress_interval=0 system=system -trapLatency=13 -wbDepth=1 -wbWidth=8 workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -131,7 +76,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -164,143 +108,6 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList0 -count=6 -opList=system.cpu.fuPool.FUList0.opList0 - -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList4.opList0 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList5.opList0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 -count=1 -opList=system.cpu.fuPool.FUList7.opList0 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - [system.cpu.icache] type=BaseCache adaptive_compression=false @@ -308,7 +115,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -348,7 +154,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -384,20 +189,33 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +responder_set=false +width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess -cmd=hello +cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook +cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-timing +egid=100 env= -executable=tests/test-progs/hello/bin/alpha/linux/hello +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +responder_set=false +width=64 port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] @@ -409,6 +227,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out b/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out index f491a3081..0af9e3f29 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out @@ -19,19 +19,54 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 +responder_set=false [system.cpu.workload] type=LiveProcess -cmd=hello -executable=tests/test-progs/hello/bin/alpha/linux/hello +cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook +executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon input=cin output=cout env= +cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-timing system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 -[system.cpu.dcache] +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.icache] type=BaseCache -size=262144 +size=131072 assoc=2 block_size=64 latency=1 @@ -39,7 +74,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -68,214 +102,9 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -opClass=IntAlu -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList0] -type=FUDesc -opList=system.cpu.fuPool.FUList0.opList0 -count=6 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -opClass=IntMult -opLat=3 -issueLat=1 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -opClass=IntDiv -opLat=20 -issueLat=19 - -[system.cpu.fuPool.FUList1] -type=FUDesc -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 -count=2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -opClass=FloatAdd -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -opClass=FloatCmp -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -opClass=FloatCvt -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2] -type=FUDesc -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 -count=4 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -opClass=FloatMult -opLat=4 -issueLat=1 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -opClass=FloatDiv -opLat=12 -issueLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -opClass=FloatSqrt -opLat=24 -issueLat=24 - -[system.cpu.fuPool.FUList3] -type=FUDesc -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 -count=2 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList4] -type=FUDesc -opList=system.cpu.fuPool.FUList4.opList0 -count=0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -opList=system.cpu.fuPool.FUList5.opList0 -count=0 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -count=4 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -opClass=IprAccess -opLat=3 -issueLat=3 - -[system.cpu.fuPool.FUList7] -type=FUDesc -opList=system.cpu.fuPool.FUList7.opList0 -count=1 - -[system.cpu.fuPool] -type=FUPool -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 - -[system.cpu] -type=DerivO3CPU -clock=1 -numThreads=1 -activity=0 -workload=system.cpu.workload -mem=system.cpu.dcache -checker=null -max_insts_any_thread=0 -max_insts_all_threads=0 -max_loads_any_thread=0 -max_loads_all_threads=0 -cachePorts=200 -decodeToFetchDelay=1 -renameToFetchDelay=1 -iewToFetchDelay=1 -commitToFetchDelay=1 -fetchWidth=8 -renameToDecodeDelay=1 -iewToDecodeDelay=1 -commitToDecodeDelay=1 -fetchToDecodeDelay=1 -decodeWidth=8 -iewToRenameDelay=1 -commitToRenameDelay=1 -decodeToRenameDelay=1 -renameWidth=8 -commitToIEWDelay=1 -renameToIEWDelay=2 -issueToExecuteDelay=1 -dispatchWidth=8 -issueWidth=8 -wbWidth=8 -wbDepth=1 -fuPool=system.cpu.fuPool -iewToCommitDelay=1 -renameToROBDelay=1 -commitWidth=8 -squashWidth=8 -trapLatency=13 -backComSize=5 -forwardComSize=5 -predType=tournament -localPredictorSize=2048 -localCtrBits=2 -localHistoryTableSize=2048 -localHistoryBits=11 -globalPredictorSize=8192 -globalCtrBits=2 -globalHistoryBits=13 -choicePredictorSize=8192 -choiceCtrBits=2 -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -LQEntries=32 -SQEntries=32 -LFSTSize=1024 -SSITSize=1024 -numPhysIntRegs=256 -numPhysFloatRegs=256 -numIQEntries=64 -numROBEntries=192 -smtNumFetchingThreads=1 -smtFetchPolicy=SingleThread -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtROBPolicy=Partitioned -smtROBThreshold=100 -smtCommitPolicy=RoundRobin -instShiftAmt=2 -defer_registration=false -function_trace=false -function_trace_start=0 - -[system.cpu.icache] +[system.cpu.dcache] type=BaseCache -size=131072 +size=262144 assoc=2 block_size=64 latency=1 @@ -283,7 +112,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -322,7 +150,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -351,13 +178,10 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[system.cpu.toL2Bus] -type=Bus -bus_id=0 - [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -396,8 +220,9 @@ print_cpseq=false print_reg_delta=false pc_symbol=true intel_format=false +legion_lockstep=false trace_system=client -[debug] -break_cycles= +[statsreset] +reset_cycle=0 diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt index 5d4f9235a..28328cd0e 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,112 +1,67 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 542 # Number of BTB hits -global.BPredUnit.BTBLookups 1938 # Number of BTB lookups -global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted -global.BPredUnit.lookups 2256 # Number of BP lookups -global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 41797 # Simulator instruction rate (inst/s) -host_mem_usage 160344 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 50948 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +host_inst_rate 490401 # Simulator instruction rate (inst/s) +host_mem_usage 178744 # Number of bytes of host memory used +host_seconds 812.94 # Real time elapsed on the host +host_tick_rate 734822 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 6870 # Number of ticks simulated -system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6116 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3908 6389.80% - 1 1064 1739.70% - 2 389 636.04% - 3 210 343.36% - 4 153 250.16% - 5 93 152.06% - 6 76 124.26% - 7 149 243.62% - 8 74 120.99% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 5640 # Number of instructions committed -system.cpu.commit.COM:loads 979 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 1791 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5623 # Number of Instructions Simulated -system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +sim_insts 398664450 # Number of instructions simulated +sim_seconds 0.000597 # Number of seconds simulated +sim_ticks 597363012 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 94754482 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3956.610526 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2956.610526 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 94753532 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3758780 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 2808780 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 73520727 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3939.646399 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2939.646399 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73517520 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 12634446 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 3207 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 9427446 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 3207 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 40478.963676 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses -system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 168275209 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3943.523214 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2943.523214 # average overall mshr miss latency +system.cpu.dcache.demand_hits 168271052 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 16393226 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses +system.cpu.dcache.demand_misses 4157 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 12236226 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 4157 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 168275209 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3943.523214 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2943.523214 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2048 # number of overall hits -system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses -system.cpu.dcache.overall_misses 311 # number of overall misses -system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_hits 168271052 # number of overall hits +system.cpu.dcache.overall_miss_latency 16393226 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses +system.cpu.dcache.overall_misses 4157 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 12236226 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 4157 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 764 # number of replacements +system.cpu.dcache.sampled_refs 4157 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use -system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3222.448687 # Cycle average of tags in use +system.cpu.dcache.total_refs 168271052 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched -system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6871 -system.cpu.fetch.rateDist.min_value 0 - 0 4549 6620.58% - 1 174 253.24% - 2 186 270.70% - 3 157 228.50% - 4 211 307.09% - 5 153 222.68% - 6 171 248.87% - 7 105 152.82% - 8 1165 1695.53% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.dcache.writebacks 625 # number of writebacks +system.cpu.icache.ReadReq_accesses 398664451 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3820.892216 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2820.892216 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 398660777 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 14037958 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 3674 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 10363958 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 3674 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 108508.649156 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses -system.cpu.icache.demand_misses 327 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 398664451 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3820.892216 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2820.892216 # average overall mshr miss latency +system.cpu.icache.demand_hits 398660777 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 14037958 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses +system.cpu.icache.demand_misses 3674 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 10363958 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 3674 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_accesses 398664451 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3820.892216 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2820.892216 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1255 # number of overall hits -system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses -system.cpu.icache.overall_misses 327 # number of overall misses -system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_hits 398660777 # number of overall hits +system.cpu.icache.overall_miss_latency 14037958 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses +system.cpu.icache.overall_misses 3674 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 10363958 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 3674 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,1726 +135,60 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1770 # number of replacements +system.cpu.icache.sampled_refs 3674 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use -system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1765.884663 # Cycle average of tags in use +system.cpu.icache.total_refs 398660777 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:insts 7969 # Number of executed instructions -system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed -system.cpu.iew.EXEC:nop 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate -system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute -system.cpu.iew.EXEC:stores 989 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5438 # num instructions consuming a value -system.cpu.iew.WB:count 7722 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4049 # num instructions producing a value -system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle -system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemWrite.max_value 0 -system.cpu.iq.IQ:residence:MemWrite.end_dist - -system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5594 66.69% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 1757 20.95% # Type of FU issued - MemWrite 1032 12.30% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 0.87% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 76 66.09% # attempts to use FU when none available - MemWrite 38 33.04% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3753 5462.09% - 1 894 1301.12% - 2 723 1052.25% - 3 614 893.61% - 4 451 656.38% - 5 279 406.05% - 6 104 151.36% - 7 41 59.67% - 8 12 17.46% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate -system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadReq_accesses 7831 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2982.860028 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1924.618942 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 651 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 21416935 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.916869 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 7180 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 13818764 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916869 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 7180 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 625 # number of WriteReqNoAck|Writeback accesses(hits+misses) +system.cpu.l2cache.WriteReqNoAck|Writeback_hits 625 # number of WriteReqNoAck|Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.177716 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 7831 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2982.860028 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1924.618942 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 651 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 21416935 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.916869 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7180 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 13818764 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.916869 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7180 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 8456 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2982.860028 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1924.618942 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_hits 1276 # number of overall hits +system.cpu.l2cache.overall_miss_latency 21416935 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.849101 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7180 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 13818764 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.849101 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7180 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -1947,28 +201,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 7180 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 6344.085280 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1276 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 6871 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 597363012 # number of cpu cycles simulated +system.cpu.num_insts 398664450 # Number of instructions executed +system.cpu.num_refs 174183390 # Number of memory references +system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/stderr b/tests/long/30.eon/ref/alpha/linux/simple-timing/stderr index 8893caac8..1d6957eca 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-timing/stderr +++ b/tests/long/30.eon/ref/alpha/linux/simple-timing/stderr @@ -1,3 +1,47 @@ warn: Entering event queue @ 0. Starting simulation... -warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 -warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 +getting pixel output filename pixels_out.cook +opening control file chair.control.cook +opening camera file chair.camera +opening surfaces file chair.surfaces +reading data +processing 8parts +Grid measure is 6 by 3.0001 by 6 +cell dimension is 0.863065 +Creating grid for list of length 21 +Grid size = 7 by 4 by 7 +Total occupancy = 236 +reading control stream +reading camera stream +Writing to chair.cook.ppm +calculating 15 by 15 image with 196 samples +col 0. . . +col 1. . . +col 2. . . +col 3. . . +col 4. . . +col 5. . . +col 6. . . +col 7. . . +col 8. . . +col 9. . . +col 10. . . +col 11. . . +col 12. . . +col 13. . . +col 14. . . +Writing to chair.cook.ppm +0 8 14 +1 8 14 +2 8 14 +3 8 14 +4 8 14 +5 8 14 +6 8 14 +7 8 14 +8 8 14 +9 8 14 +10 8 14 +11 8 14 +12 8 14 +13 8 14 +14 8 14 diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/stdout b/tests/long/30.eon/ref/alpha/linux/simple-timing/stdout index fbb329a2f..039e2d4ce 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-timing/stdout +++ b/tests/long/30.eon/ref/alpha/linux/simple-timing/stdout @@ -1,13 +1,2 @@ -Hello world! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:12 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Exiting @ tick 6870 because target called exit() +Eon, Version 1.1 +OO-style eon Time= 0.000000 diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini index c3a59fbce..81e1071eb 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini @@ -7,11 +7,9 @@ max_tick=0 output_file=cout progress_interval=0 -[debug] -break_cycles= - [exetrace] intel_format=false +legion_lockstep=false pc_symbol=true print_cpseq=false print_cycle=true @@ -53,352 +51,49 @@ mem_mode=atomic physmem=system.physmem [system.cpu] -type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus workload -BTBEntries=4096 -BTBTagSize=16 -LFSTSize=1024 -LQEntries=32 -RASSize=16 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -choiceCtrBits=2 -choicePredictorSize=8192 +type=AtomicSimpleCPU +children=workload clock=1 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 +cpu_id=0 defer_registration=false -dispatchWidth=8 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -instShiftAmt=2 -issueToExecuteDelay=1 -issueWidth=8 -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.dcache -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -predType=tournament -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -squashWidth=8 +phase=0 +progress_interval=0 +simulate_stalls=false system=system -trapLatency=13 -wbDepth=1 -wbWidth=8 +width=1 workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -do_copy=false -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=262144 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList0 -count=6 -opList=system.cpu.fuPool.FUList0.opList0 - -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList4.opList0 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList5.opList0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 -count=1 -opList=system.cpu.fuPool.FUList7.opList0 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - -[system.cpu.icache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -do_copy=false -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=131072 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.l2cache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -do_copy=false -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=2097152 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] - -[system.cpu.toL2Bus] -type=Bus -bus_id=0 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess -cmd=hello +cmd=perlbmk -I. -I lib lgred.makerand.pl +cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-atomic +egid=100 env= -executable=tests/test-progs/hello/bin/alpha/linux/hello +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 -port=system.physmem.port system.cpu.l2cache.mem_side +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory @@ -409,6 +104,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out index f491a3081..e5012d953 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out @@ -19,345 +19,48 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 +responder_set=false [system.cpu.workload] type=LiveProcess -cmd=hello -executable=tests/test-progs/hello/bin/alpha/linux/hello +cmd=perlbmk -I. -I lib lgred.makerand.pl +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk input=cin output=cout env= +cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-atomic system=system - -[system.cpu.dcache] -type=BaseCache -size=262144 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -opClass=IntAlu -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList0] -type=FUDesc -opList=system.cpu.fuPool.FUList0.opList0 -count=6 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -opClass=IntMult -opLat=3 -issueLat=1 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -opClass=IntDiv -opLat=20 -issueLat=19 - -[system.cpu.fuPool.FUList1] -type=FUDesc -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 -count=2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -opClass=FloatAdd -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -opClass=FloatCmp -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -opClass=FloatCvt -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2] -type=FUDesc -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 -count=4 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -opClass=FloatMult -opLat=4 -issueLat=1 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -opClass=FloatDiv -opLat=12 -issueLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -opClass=FloatSqrt -opLat=24 -issueLat=24 - -[system.cpu.fuPool.FUList3] -type=FUDesc -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 -count=2 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList4] -type=FUDesc -opList=system.cpu.fuPool.FUList4.opList0 -count=0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -opList=system.cpu.fuPool.FUList5.opList0 -count=0 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -count=4 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -opClass=IprAccess -opLat=3 -issueLat=3 - -[system.cpu.fuPool.FUList7] -type=FUDesc -opList=system.cpu.fuPool.FUList7.opList0 -count=1 - -[system.cpu.fuPool] -type=FUPool -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] -type=DerivO3CPU -clock=1 -numThreads=1 -activity=0 -workload=system.cpu.workload -mem=system.cpu.dcache -checker=null +type=AtomicSimpleCPU max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 -cachePorts=200 -decodeToFetchDelay=1 -renameToFetchDelay=1 -iewToFetchDelay=1 -commitToFetchDelay=1 -fetchWidth=8 -renameToDecodeDelay=1 -iewToDecodeDelay=1 -commitToDecodeDelay=1 -fetchToDecodeDelay=1 -decodeWidth=8 -iewToRenameDelay=1 -commitToRenameDelay=1 -decodeToRenameDelay=1 -renameWidth=8 -commitToIEWDelay=1 -renameToIEWDelay=2 -issueToExecuteDelay=1 -dispatchWidth=8 -issueWidth=8 -wbWidth=8 -wbDepth=1 -fuPool=system.cpu.fuPool -iewToCommitDelay=1 -renameToROBDelay=1 -commitWidth=8 -squashWidth=8 -trapLatency=13 -backComSize=5 -forwardComSize=5 -predType=tournament -localPredictorSize=2048 -localCtrBits=2 -localHistoryTableSize=2048 -localHistoryBits=11 -globalPredictorSize=8192 -globalCtrBits=2 -globalHistoryBits=13 -choicePredictorSize=8192 -choiceCtrBits=2 -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -LQEntries=32 -SQEntries=32 -LFSTSize=1024 -SSITSize=1024 -numPhysIntRegs=256 -numPhysFloatRegs=256 -numIQEntries=64 -numROBEntries=192 -smtNumFetchingThreads=1 -smtFetchPolicy=SingleThread -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtROBPolicy=Partitioned -smtROBThreshold=100 -smtCommitPolicy=RoundRobin -instShiftAmt=2 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 defer_registration=false +width=1 function_trace=false function_trace_start=0 - -[system.cpu.icache] -type=BaseCache -size=131072 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.l2cache] -type=BaseCache -size=2097152 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.toL2Bus] -type=Bus -bus_id=0 +simulate_stalls=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -396,8 +99,9 @@ print_cpseq=false print_reg_delta=false pc_symbol=true intel_format=false +legion_lockstep=false trace_system=client -[debug] -break_cycles= +[statsreset] +reset_cycle=0 diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt index 5d4f9235a..f553125a6 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,1974 +1,18 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 542 # Number of BTB hits -global.BPredUnit.BTBLookups 1938 # Number of BTB lookups -global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted -global.BPredUnit.lookups 2256 # Number of BP lookups -global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 41797 # Simulator instruction rate (inst/s) -host_mem_usage 160344 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 50948 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +host_inst_rate 906784 # Simulator instruction rate (inst/s) +host_mem_usage 147280 # Number of bytes of host memory used +host_seconds 2215.51 # Real time elapsed on the host +host_tick_rate 906784 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 6870 # Number of ticks simulated -system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6116 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3908 6389.80% - 1 1064 1739.70% - 2 389 636.04% - 3 210 343.36% - 4 153 250.16% - 5 93 152.06% - 6 76 124.26% - 7 149 243.62% - 8 74 120.99% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 5640 # Number of instructions committed -system.cpu.commit.COM:loads 979 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 1791 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5623 # Number of Instructions Simulated -system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses -system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2048 # number of overall hits -system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses -system.cpu.dcache.overall_misses 311 # number of overall misses -system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use -system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched -system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6871 -system.cpu.fetch.rateDist.min_value 0 - 0 4549 6620.58% - 1 174 253.24% - 2 186 270.70% - 3 157 228.50% - 4 211 307.09% - 5 153 222.68% - 6 171 248.87% - 7 105 152.82% - 8 1165 1695.53% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses -system.cpu.icache.demand_misses 327 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1255 # number of overall hits -system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses -system.cpu.icache.overall_misses 327 # number of overall misses -system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use -system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:insts 7969 # Number of executed instructions -system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed -system.cpu.iew.EXEC:nop 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate -system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute -system.cpu.iew.EXEC:stores 989 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5438 # num instructions consuming a value -system.cpu.iew.WB:count 7722 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4049 # num instructions producing a value -system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle -system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemWrite.max_value 0 -system.cpu.iq.IQ:residence:MemWrite.end_dist - -system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5594 66.69% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 1757 20.95% # Type of FU issued - MemWrite 1032 12.30% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 0.87% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 76 66.09% # attempts to use FU when none available - MemWrite 38 33.04% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3753 5462.09% - 1 894 1301.12% - 2 723 1052.25% - 3 614 893.61% - 4 451 656.38% - 5 279 406.05% - 6 104 151.36% - 7 41 59.67% - 8 12 17.46% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate -system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 497 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 6871 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +sim_insts 2008987724 # Number of instructions simulated +sim_seconds 0.002009 # Number of seconds simulated +sim_ticks 2008987723 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 2008987724 # number of cpu cycles simulated +system.cpu.num_insts 2008987724 # Number of instructions executed +system.cpu.num_refs 722390480 # Number of memory references +system.cpu.workload.PROG:num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr index 8893caac8..9135960d0 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr @@ -1,3 +1,2 @@ warn: Entering event queue @ 0. Starting simulation... -warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 -warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 +warn: ignoring syscall sigprocmask(1, 0, ...) diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout index fbb329a2f..d4a078b85 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout @@ -1,13 +1,1376 @@ -Hello world! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:12 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Exiting @ tick 6870 because target called exit() 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3259365221 +29000: 3960625204 +28000: 3476394666 +27000: 1995310421 +26000: 1884341166 +25000: 3181801013 +24000: 116492838 +23000: 3276567587 +22000: 3693343729 +21000: 2595820568 +20000: 2397879436 +19000: 2692679578 +18000: 2368648652 +17000: 3098196844 +16000: 3913788179 +15000: 1240694507 +14000: 1586030084 +13000: 1211450031 +12000: 3458253062 +11000: 1804606651 +10000: 2128587109 +9000: 1894810186 +8000: 2221431098 +7000: 113605713 +6000: 4020003580 +5000: 2988041351 +4000: 2310084217 +3000: 1475476779 +2000: 760651391 +1000: 4031656975 +0: 2206428413 diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini index c3a59fbce..fa4ee72da 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini @@ -7,11 +7,9 @@ max_tick=0 output_file=cout progress_interval=0 -[debug] -break_cycles= - [exetrace] intel_format=false +legion_lockstep=false pc_symbol=true print_cpseq=false print_cycle=true @@ -53,73 +51,20 @@ mem_mode=atomic physmem=system.physmem [system.cpu] -type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus workload -BTBEntries=4096 -BTBTagSize=16 -LFSTSize=1024 -LQEntries=32 -RASSize=16 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -choiceCtrBits=2 -choicePredictorSize=8192 +type=TimingSimpleCPU +children=dcache icache l2cache toL2Bus workload clock=1 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 +cpu_id=0 defer_registration=false -dispatchWidth=8 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -instShiftAmt=2 -issueToExecuteDelay=1 -issueWidth=8 -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.dcache -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -predType=tournament -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -squashWidth=8 +phase=0 +progress_interval=0 system=system -trapLatency=13 -wbDepth=1 -wbWidth=8 workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -131,7 +76,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -164,143 +108,6 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList0 -count=6 -opList=system.cpu.fuPool.FUList0.opList0 - -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList4.opList0 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList5.opList0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 -count=1 -opList=system.cpu.fuPool.FUList7.opList0 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - [system.cpu.icache] type=BaseCache adaptive_compression=false @@ -308,7 +115,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -348,7 +154,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -384,20 +189,33 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +responder_set=false +width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess -cmd=hello +cmd=perlbmk -I. -I lib lgred.makerand.pl +cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-timing +egid=100 env= -executable=tests/test-progs/hello/bin/alpha/linux/hello +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +responder_set=false +width=64 port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] @@ -409,6 +227,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out index f491a3081..ea12fcb9a 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out @@ -19,19 +19,54 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 +responder_set=false [system.cpu.workload] type=LiveProcess -cmd=hello -executable=tests/test-progs/hello/bin/alpha/linux/hello +cmd=perlbmk -I. -I lib lgred.makerand.pl +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk input=cin output=cout env= +cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-timing system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 -[system.cpu.dcache] +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.icache] type=BaseCache -size=262144 +size=131072 assoc=2 block_size=64 latency=1 @@ -39,7 +74,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -68,214 +102,9 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -opClass=IntAlu -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList0] -type=FUDesc -opList=system.cpu.fuPool.FUList0.opList0 -count=6 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -opClass=IntMult -opLat=3 -issueLat=1 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -opClass=IntDiv -opLat=20 -issueLat=19 - -[system.cpu.fuPool.FUList1] -type=FUDesc -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 -count=2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -opClass=FloatAdd -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -opClass=FloatCmp -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -opClass=FloatCvt -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2] -type=FUDesc -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 -count=4 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -opClass=FloatMult -opLat=4 -issueLat=1 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -opClass=FloatDiv -opLat=12 -issueLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -opClass=FloatSqrt -opLat=24 -issueLat=24 - -[system.cpu.fuPool.FUList3] -type=FUDesc -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 -count=2 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList4] -type=FUDesc -opList=system.cpu.fuPool.FUList4.opList0 -count=0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -opList=system.cpu.fuPool.FUList5.opList0 -count=0 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -count=4 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -opClass=IprAccess -opLat=3 -issueLat=3 - -[system.cpu.fuPool.FUList7] -type=FUDesc -opList=system.cpu.fuPool.FUList7.opList0 -count=1 - -[system.cpu.fuPool] -type=FUPool -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 - -[system.cpu] -type=DerivO3CPU -clock=1 -numThreads=1 -activity=0 -workload=system.cpu.workload -mem=system.cpu.dcache -checker=null -max_insts_any_thread=0 -max_insts_all_threads=0 -max_loads_any_thread=0 -max_loads_all_threads=0 -cachePorts=200 -decodeToFetchDelay=1 -renameToFetchDelay=1 -iewToFetchDelay=1 -commitToFetchDelay=1 -fetchWidth=8 -renameToDecodeDelay=1 -iewToDecodeDelay=1 -commitToDecodeDelay=1 -fetchToDecodeDelay=1 -decodeWidth=8 -iewToRenameDelay=1 -commitToRenameDelay=1 -decodeToRenameDelay=1 -renameWidth=8 -commitToIEWDelay=1 -renameToIEWDelay=2 -issueToExecuteDelay=1 -dispatchWidth=8 -issueWidth=8 -wbWidth=8 -wbDepth=1 -fuPool=system.cpu.fuPool -iewToCommitDelay=1 -renameToROBDelay=1 -commitWidth=8 -squashWidth=8 -trapLatency=13 -backComSize=5 -forwardComSize=5 -predType=tournament -localPredictorSize=2048 -localCtrBits=2 -localHistoryTableSize=2048 -localHistoryBits=11 -globalPredictorSize=8192 -globalCtrBits=2 -globalHistoryBits=13 -choicePredictorSize=8192 -choiceCtrBits=2 -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -LQEntries=32 -SQEntries=32 -LFSTSize=1024 -SSITSize=1024 -numPhysIntRegs=256 -numPhysFloatRegs=256 -numIQEntries=64 -numROBEntries=192 -smtNumFetchingThreads=1 -smtFetchPolicy=SingleThread -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtROBPolicy=Partitioned -smtROBThreshold=100 -smtCommitPolicy=RoundRobin -instShiftAmt=2 -defer_registration=false -function_trace=false -function_trace_start=0 - -[system.cpu.icache] +[system.cpu.dcache] type=BaseCache -size=131072 +size=262144 assoc=2 block_size=64 latency=1 @@ -283,7 +112,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -322,7 +150,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -351,13 +178,10 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[system.cpu.toL2Bus] -type=Bus -bus_id=0 - [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -396,8 +220,9 @@ print_cpseq=false print_reg_delta=false pc_symbol=true intel_format=false +legion_lockstep=false trace_system=client -[debug] -break_cycles= +[statsreset] +reset_cycle=0 diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt index 5d4f9235a..4d20e663a 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,112 +1,67 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 542 # Number of BTB hits -global.BPredUnit.BTBLookups 1938 # Number of BTB lookups -global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted -global.BPredUnit.lookups 2256 # Number of BP lookups -global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 41797 # Simulator instruction rate (inst/s) -host_mem_usage 160344 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 50948 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +host_inst_rate 502967 # Simulator instruction rate (inst/s) +host_mem_usage 217744 # Number of bytes of host memory used +host_seconds 3994.27 # Real time elapsed on the host +host_tick_rate 1895851 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 6870 # Number of ticks simulated -system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6116 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3908 6389.80% - 1 1064 1739.70% - 2 389 636.04% - 3 210 343.36% - 4 153 250.16% - 5 93 152.06% - 6 76 124.26% - 7 149 243.62% - 8 74 120.99% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 5640 # Number of instructions committed -system.cpu.commit.COM:loads 979 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 1791 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5623 # Number of Instructions Simulated -system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +sim_insts 2008987724 # Number of instructions simulated +sim_seconds 0.007573 # Number of seconds simulated +sim_ticks 7572549003 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 511070058 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3107.171711 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2107.171711 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 509611866 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4530852932 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3072660932 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 210794909 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3884.294897 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2884.294897 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 210722955 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 279490555 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000341 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 71954 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 207536555 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000341 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 71954 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 470.762150 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses -system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 721864967 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3143.715362 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2143.715362 # average overall mshr miss latency +system.cpu.dcache.demand_hits 720334821 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 4810343487 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002120 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1530146 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3280197487 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002120 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1530146 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 721864967 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3143.715362 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2143.715362 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2048 # number of overall hits -system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses -system.cpu.dcache.overall_misses 311 # number of overall misses -system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_hits 720334821 # number of overall hits +system.cpu.dcache.overall_miss_latency 4810343487 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002120 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1530146 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3280197487 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002120 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1530146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1526050 # number of replacements +system.cpu.dcache.sampled_refs 1530146 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use -system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched -system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6871 -system.cpu.fetch.rateDist.min_value 0 - 0 4549 6620.58% - 1 174 253.24% - 2 186 270.70% - 3 157 228.50% - 4 211 307.09% - 5 153 222.68% - 6 171 248.87% - 7 105 152.82% - 8 1165 1695.53% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 4087.472566 # Cycle average of tags in use +system.cpu.dcache.total_refs 720334821 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 35194000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 74591 # number of writebacks +system.cpu.icache.ReadReq_accesses 2008987725 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3103.752500 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2103.752500 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2008977127 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 32893569 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 10598 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 22295569 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 10598 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 189561.910455 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses -system.cpu.icache.demand_misses 327 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 2008987725 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3103.752500 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2103.752500 # average overall mshr miss latency +system.cpu.icache.demand_hits 2008977127 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 32893569 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses +system.cpu.icache.demand_misses 10598 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 22295569 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 10598 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_accesses 2008987725 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3103.752500 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2103.752500 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1255 # number of overall hits -system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses -system.cpu.icache.overall_misses 327 # number of overall misses -system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_hits 2008977127 # number of overall hits +system.cpu.icache.overall_miss_latency 32893569 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses +system.cpu.icache.overall_misses 10598 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 22295569 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 10598 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,1726 +135,64 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.replacements 9048 # number of replacements +system.cpu.icache.sampled_refs 10598 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use -system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1472.251444 # Cycle average of tags in use +system.cpu.icache.total_refs 2008977127 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:insts 7969 # Number of executed instructions -system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed -system.cpu.iew.EXEC:nop 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate -system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute -system.cpu.iew.EXEC:stores 989 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5438 # num instructions consuming a value -system.cpu.iew.WB:count 7722 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4049 # num instructions producing a value -system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle -system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemWrite.max_value 0 -system.cpu.iq.IQ:residence:MemWrite.end_dist - -system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5594 66.69% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 1757 20.95% # Type of FU issued - MemWrite 1032 12.30% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 0.87% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 76 66.09% # attempts to use FU when none available - MemWrite 38 33.04% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3753 5462.09% - 1 894 1301.12% - 2 723 1052.25% - 3 614 893.61% - 4 451 656.38% - 5 279 406.05% - 6 104 151.36% - 7 41 59.67% - 8 12 17.46% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate -system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadReq_accesses 1540744 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2153.831026 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1111.660796 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 33878 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 3245534743 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.978012 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1506866 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1675123857 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.978012 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1506866 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 74591 # number of WriteReqNoAck|Writeback accesses(hits+misses) +system.cpu.l2cache.WriteReqNoAck|Writeback_hits 73517 # number of WriteReqNoAck|Writeback hits +system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.014399 # miss rate for WriteReqNoAck|Writeback accesses +system.cpu.l2cache.WriteReqNoAck|Writeback_misses 1074 # number of WriteReqNoAck|Writeback misses +system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.014399 # mshr miss rate for WriteReqNoAck|Writeback accesses +system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 1074 # number of WriteReqNoAck|Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.071270 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 1540744 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2153.831026 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1111.660796 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 33878 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 3245534743 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.978012 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1506866 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 1675123857 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.978012 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1506866 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 1615335 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2152.297003 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1111.660796 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_hits 107395 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3245534743 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.933515 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1507940 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 1675123857 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.932850 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1506866 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -1946,29 +204,17 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 1474098 # number of replacements +system.cpu.l2cache.sampled_refs 1506866 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 6871 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.l2cache.tagsinuse 32444.673070 # Cycle average of tags in use +system.cpu.l2cache.total_refs 107395 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 164218000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 66806 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 7572549003 # number of cpu cycles simulated +system.cpu.num_insts 2008987724 # Number of instructions executed +system.cpu.num_refs 722390480 # Number of memory references +system.cpu.workload.PROG:num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr index 8893caac8..9135960d0 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr @@ -1,3 +1,2 @@ warn: Entering event queue @ 0. Starting simulation... -warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 -warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 +warn: ignoring syscall sigprocmask(1, 0, ...) diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout index fbb329a2f..d4a078b85 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout @@ -1,13 +1,1376 @@ -Hello world! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:12 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Exiting @ tick 6870 because target called exit() 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3259365221 +29000: 3960625204 +28000: 3476394666 +27000: 1995310421 +26000: 1884341166 +25000: 3181801013 +24000: 116492838 +23000: 3276567587 +22000: 3693343729 +21000: 2595820568 +20000: 2397879436 +19000: 2692679578 +18000: 2368648652 +17000: 3098196844 +16000: 3913788179 +15000: 1240694507 +14000: 1586030084 +13000: 1211450031 +12000: 3458253062 +11000: 1804606651 +10000: 2128587109 +9000: 1894810186 +8000: 2221431098 +7000: 113605713 +6000: 4020003580 +5000: 2988041351 +4000: 2310084217 +3000: 1475476779 +2000: 760651391 +1000: 4031656975 +0: 2206428413 diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini index c3a59fbce..46f72ac13 100644 --- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini @@ -7,11 +7,9 @@ max_tick=0 output_file=cout progress_interval=0 -[debug] -break_cycles= - [exetrace] intel_format=false +legion_lockstep=false pc_symbol=true print_cpseq=false print_cycle=true @@ -102,14 +100,15 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.dcache numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 +phase=0 predType=tournament +progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 renameToIEWDelay=2 @@ -131,7 +130,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -308,7 +306,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -348,7 +345,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -384,20 +380,33 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +responder_set=false +width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess -cmd=hello +cmd=vortex lendian.raw +cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/o3-timing +egid=100 env= -executable=tests/test-progs/hello/bin/alpha/linux/hello +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +responder_set=false +width=64 port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] @@ -409,6 +418,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out b/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out index f491a3081..9e0ede146 100644 --- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out +++ b/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out @@ -19,54 +19,25 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 +responder_set=false [system.cpu.workload] type=LiveProcess -cmd=hello -executable=tests/test-progs/hello/bin/alpha/linux/hello +cmd=vortex lendian.raw +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex input=cin output=cout env= +cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/o3-timing system=system - -[system.cpu.dcache] -type=BaseCache -size=262144 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu.fuPool.FUList0.opList0] type=OpDesc @@ -199,15 +170,16 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU clock=1 +phase=0 numThreads=1 activity=0 workload=system.cpu.workload -mem=system.cpu.dcache checker=null max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 cachePorts=200 decodeToFetchDelay=1 renameToFetchDelay=1 @@ -283,7 +255,44 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false protocol=null trace_addr=0 hash_delay=1 @@ -322,7 +331,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -354,10 +362,14 @@ hit_latency=1 [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 +responder_set=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -396,8 +408,9 @@ print_cpseq=false print_reg_delta=false pc_symbol=true intel_format=false +legion_lockstep=false trace_system=client -[debug] -break_cycles= +[statsreset] +reset_cycle=0 diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt index 5d4f9235a..34a47022b 100644 --- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,112 +1,112 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 542 # Number of BTB hits -global.BPredUnit.BTBLookups 1938 # Number of BTB lookups -global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted -global.BPredUnit.lookups 2256 # Number of BP lookups -global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 41797 # Simulator instruction rate (inst/s) -host_mem_usage 160344 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 50948 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 13144986 # Number of BTB hits +global.BPredUnit.BTBLookups 21876990 # Number of BTB lookups +global.BPredUnit.RASInCorrect 30485 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 454636 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 16268422 # Number of conditional branches predicted +global.BPredUnit.lookups 26797394 # Number of BP lookups +global.BPredUnit.usedRAS 4858022 # Number of times the RAS was used to get a target. +host_inst_rate 52852 # Simulator instruction rate (inst/s) +host_mem_usage 259420 # Number of bytes of host memory used +host_seconds 1506.34 # Real time elapsed on the host +host_tick_rate 744190 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 14725219 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 11320400 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 28503669 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 16218894 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 6870 # Number of ticks simulated -system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached +sim_insts 79613339 # Number of instructions simulated +sim_seconds 0.001121 # Number of seconds simulated +sim_ticks 1121005014 # Number of ticks simulated +system.cpu.commit.COM:branches 13759853 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 3902181 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.samples 88439527 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3908 6389.80% - 1 1064 1739.70% - 2 389 636.04% - 3 210 343.36% - 4 153 250.16% - 5 93 152.06% - 6 76 124.26% - 7 149 243.62% - 8 74 120.99% + 0 61749847 6982.15% + 1 8803671 995.45% + 2 5177009 585.37% + 3 3274877 370.30% + 4 2188473 247.45% + 5 1421818 160.77% + 6 1152410 130.30% + 7 769241 86.98% + 8 3902181 441.23% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 5640 # Number of instructions committed -system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:count 88361897 # Number of instructions committed +system.cpu.commit.COM:loads 20383045 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:refs 35229375 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5623 # Number of Instructions Simulated -system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.commit.branchMispredicts 360073 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 88361897 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 4706 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 20725845 # The number of squashed insts skipped by commit +system.cpu.committedInsts 79613339 # Number of Instructions Simulated +system.cpu.committedInsts_total 79613339 # Number of Instructions Simulated +system.cpu.cpi 14.080618 # CPI: Cycles Per Instruction +system.cpu.cpi_total 14.080618 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 19542402 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 4437.586724 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3280.646620 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 19388897 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 681191750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007855 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 153505 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 94427 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 193814041 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 59078 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 14615683 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 4852.594089 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4028.169523 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 13950409 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3228304680 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.045518 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 665274 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 523305 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 571875199 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009713 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 141969 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 3068.165217 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 3779.642588 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 165.828418 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 115 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 125189 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 352839 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 473169676 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses -system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 34158085 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4774.788349 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3808.508657 # average overall mshr miss latency +system.cpu.dcache.demand_hits 33339306 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 3909496430 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.023970 # miss rate for demand accesses +system.cpu.dcache.demand_misses 818779 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 617732 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 765689240 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005886 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 201047 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 34158085 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4774.788349 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3808.508657 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2048 # number of overall hits -system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses -system.cpu.dcache.overall_misses 311 # number of overall misses -system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_hits 33339306 # number of overall hits +system.cpu.dcache.overall_miss_latency 3909496430 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.023970 # miss rate for overall accesses +system.cpu.dcache.overall_misses 818779 # number of overall misses +system.cpu.dcache.overall_mshr_hits 617732 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 765689240 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005886 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 201047 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 196951 # number of replacements +system.cpu.dcache.sampled_refs 201047 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use -system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched -system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4057.206862 # Cycle average of tags in use +system.cpu.dcache.total_refs 33339306 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 27763000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147199 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 11824495 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 95570 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3548160 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 129766996 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 51039022 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 25179247 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 4520828 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 280755 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 396764 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 26797394 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 22435045 # Number of cache lines fetched +system.cpu.fetch.Cycles 50869599 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 152238 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 146401648 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 3850495 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.288267 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 22435045 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 18003008 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.574883 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.samples 92960356 system.cpu.fetch.rateDist.min_value 0 - 0 4549 6620.58% - 1 174 253.24% - 2 186 270.70% - 3 157 228.50% - 4 211 307.09% - 5 153 222.68% - 6 171 248.87% - 7 105 152.82% - 8 1165 1695.53% + 0 64525729 6941.21% + 1 1650999 177.60% + 2 1736489 186.80% + 3 1914591 205.96% + 4 6963270 749.06% + 5 6073717 653.37% + 6 756313 81.36% + 7 1939629 208.65% + 8 7399619 796.00% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.icache.ReadReq_accesses 22435044 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3343.146524 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2355.643274 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 22333491 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 339506559 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.004527 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 101553 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 13791 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 206735965 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.003912 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 87762 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets 3964.923913 # average number of cycles each access was blocked +system.cpu.icache.avg_refs 254.480817 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 92 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 364773 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses -system.cpu.icache.demand_misses 327 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 22435044 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3343.146524 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2355.643274 # average overall mshr miss latency +system.cpu.icache.demand_hits 22333491 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 339506559 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.004527 # miss rate for demand accesses +system.cpu.icache.demand_misses 101553 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 13791 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 206735965 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.003912 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 87762 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_accesses 22435044 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3343.146524 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2355.643274 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1255 # number of overall hits -system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses -system.cpu.icache.overall_misses 327 # number of overall misses -system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_hits 22333491 # number of overall hits +system.cpu.icache.overall_miss_latency 339506559 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.004527 # miss rate for overall accesses +system.cpu.icache.overall_misses 101553 # number of overall misses +system.cpu.icache.overall_mshr_hits 13791 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 206735965 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.003912 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 87762 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,1646 +215,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.replacements 85714 # number of replacements +system.cpu.icache.sampled_refs 87761 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use -system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1835.660061 # Cycle average of tags in use +system.cpu.icache.total_refs 22333491 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:insts 7969 # Number of executed instructions -system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed -system.cpu.iew.EXEC:nop 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate -system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute -system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.idleCycles 1028044659 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14368697 # Number of branches executed +system.cpu.iew.EXEC:nop 9207761 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.998957 # Inst execution rate +system.cpu.iew.EXEC:refs 42889191 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15296362 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5438 # num instructions consuming a value -system.cpu.iew.WB:count 7722 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:consumers 46149810 # num instructions consuming a value +system.cpu.iew.WB:count 85978243 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.741638 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4049 # num instructions producing a value -system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle -system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 34226464 # num instructions producing a value +system.cpu.iew.WB:rate 0.924891 # insts written-back per cycle +system.cpu.iew.WB:sent 86043563 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 388948 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 3476074 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 28503669 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 5221 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1221579 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 16218894 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 109084579 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 27592829 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 454683 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 92863355 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 28537 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.iewLSQFullEvents 13436 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 4520828 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 193035 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1537 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 6697780 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 1365345 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 4018 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemWrite.max_value 0 -system.cpu.iq.IQ:residence:MemWrite.end_dist - -system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 3952 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1537 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 8120624 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1372564 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 3952 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 217352 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 171596 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.071020 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.071020 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 93318038 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5594 66.69% # Type of FU issued - IntMult 1 0.01% # Type of FU issued + (null) 0 0.00% # Type of FU issued + IntAlu 49917747 53.49% # Type of FU issued + IntMult 43212 0.05% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued + FloatAdd 123778 0.13% # Type of FU issued + FloatCmp 88 0.00% # Type of FU issued + FloatCvt 122460 0.13% # Type of FU issued + FloatMult 54 0.00% # Type of FU issued + FloatDiv 37863 0.04% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1757 20.95% # Type of FU issued - MemWrite 1032 12.30% # Type of FU issued + MemRead 27694961 29.68% # Type of FU issued + MemWrite 15377875 16.48% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 1239796 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013286 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 0.87% # attempts to use FU when none available + IntAlu 81158 6.55% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -1863,78 +297,84 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 76 66.09% # attempts to use FU when none available - MemWrite 38 33.04% # attempts to use FU when none available + MemRead 587235 47.37% # attempts to use FU when none available + MemWrite 571403 46.09% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.samples 92960356 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3753 5462.09% - 1 894 1301.12% - 2 723 1052.25% - 3 614 893.61% - 4 451 656.38% - 5 279 406.05% - 6 104 151.36% - 7 41 59.67% - 8 12 17.46% + 0 53328498 5736.69% + 1 13184129 1418.25% + 2 10577669 1137.87% + 3 8760562 942.40% + 4 4405028 473.86% + 5 1612052 173.41% + 6 698100 75.10% + 7 326631 35.14% + 8 67687 7.28% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate -system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.iq.ISSUE:rate 1.003848 # Inst issue rate +system.cpu.iq.iqInstsAdded 99871597 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 93318038 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 5221 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 20057396 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 77651 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 515 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 15480029 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 288801 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3932.513738 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2042.965502 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 119343 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 666395913 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.586764 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 169458 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 346196848 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.586764 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 169458 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 147199 # number of WriteReqNoAck|Writeback accesses(hits+misses) +system.cpu.l2cache.WriteReqNoAck|Writeback_hits 146588 # number of WriteReqNoAck|Writeback hits +system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.004151 # miss rate for WriteReqNoAck|Writeback accesses +system.cpu.l2cache.WriteReqNoAck|Writeback_misses 611 # number of WriteReqNoAck|Writeback misses +system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.004151 # mshr miss rate for WriteReqNoAck|Writeback accesses +system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 611 # number of WriteReqNoAck|Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.569313 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 288801 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3932.513738 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2042.965502 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 119343 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 666395913 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.586764 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 169458 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 346196848 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.586764 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 169458 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 436000 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3918.385555 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2042.965502 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_hits 265931 # number of overall hits +system.cpu.l2cache.overall_miss_latency 666395913 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.390067 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 170069 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 346196848 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.388665 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 169458 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -1946,29 +386,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 136689 # number of replacements +system.cpu.l2cache.sampled_refs 169457 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 6871 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.l2cache.tagsinuse 30306.924097 # Cycle average of tags in use +system.cpu.l2cache.total_refs 265931 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 442261000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 115687 # number of writebacks +system.cpu.numCycles 92960356 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 7634208 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 52562815 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 86713 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 51709233 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 3226687 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 2442 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 152860701 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 128373944 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 81757058 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 24895195 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 4520828 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 3457989 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 29194243 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 742903 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 5237 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 6117149 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 5235 # count of temporary serializing insts renamed +system.cpu.timesIdled 271656 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 4706 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr b/tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr index 8893caac8..87866a2a5 100644 --- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr @@ -1,3 +1 @@ warn: Entering event queue @ 0. Starting simulation... -warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 -warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout b/tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout index fbb329a2f..e69de29bb 100644 --- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout +++ b/tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout @@ -1,13 +0,0 @@ -Hello world! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:12 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Exiting @ tick 6870 because target called exit() diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini index c3a59fbce..6d8732496 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini @@ -7,11 +7,9 @@ max_tick=0 output_file=cout progress_interval=0 -[debug] -break_cycles= - [exetrace] intel_format=false +legion_lockstep=false pc_symbol=true print_cpseq=false print_cycle=true @@ -53,352 +51,49 @@ mem_mode=atomic physmem=system.physmem [system.cpu] -type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus workload -BTBEntries=4096 -BTBTagSize=16 -LFSTSize=1024 -LQEntries=32 -RASSize=16 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -choiceCtrBits=2 -choicePredictorSize=8192 +type=AtomicSimpleCPU +children=workload clock=1 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 +cpu_id=0 defer_registration=false -dispatchWidth=8 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -instShiftAmt=2 -issueToExecuteDelay=1 -issueWidth=8 -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.dcache -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -predType=tournament -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -squashWidth=8 +phase=0 +progress_interval=0 +simulate_stalls=false system=system -trapLatency=13 -wbDepth=1 -wbWidth=8 +width=1 workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -do_copy=false -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=262144 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList0 -count=6 -opList=system.cpu.fuPool.FUList0.opList0 - -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList4.opList0 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList5.opList0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 -count=1 -opList=system.cpu.fuPool.FUList7.opList0 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - -[system.cpu.icache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -do_copy=false -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=131072 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.l2cache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -do_copy=false -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=2097152 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] - -[system.cpu.toL2Bus] -type=Bus -bus_id=0 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess -cmd=hello +cmd=vortex lendian.raw +cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-atomic +egid=100 env= -executable=tests/test-progs/hello/bin/alpha/linux/hello +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 -port=system.physmem.port system.cpu.l2cache.mem_side +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory @@ -409,6 +104,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out index f491a3081..38f919464 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out +++ b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out @@ -19,345 +19,48 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 +responder_set=false [system.cpu.workload] type=LiveProcess -cmd=hello -executable=tests/test-progs/hello/bin/alpha/linux/hello +cmd=vortex lendian.raw +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex input=cin output=cout env= +cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-atomic system=system - -[system.cpu.dcache] -type=BaseCache -size=262144 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -opClass=IntAlu -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList0] -type=FUDesc -opList=system.cpu.fuPool.FUList0.opList0 -count=6 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -opClass=IntMult -opLat=3 -issueLat=1 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -opClass=IntDiv -opLat=20 -issueLat=19 - -[system.cpu.fuPool.FUList1] -type=FUDesc -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 -count=2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -opClass=FloatAdd -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -opClass=FloatCmp -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -opClass=FloatCvt -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2] -type=FUDesc -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 -count=4 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -opClass=FloatMult -opLat=4 -issueLat=1 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -opClass=FloatDiv -opLat=12 -issueLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -opClass=FloatSqrt -opLat=24 -issueLat=24 - -[system.cpu.fuPool.FUList3] -type=FUDesc -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 -count=2 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList4] -type=FUDesc -opList=system.cpu.fuPool.FUList4.opList0 -count=0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -opList=system.cpu.fuPool.FUList5.opList0 -count=0 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -count=4 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -opClass=IprAccess -opLat=3 -issueLat=3 - -[system.cpu.fuPool.FUList7] -type=FUDesc -opList=system.cpu.fuPool.FUList7.opList0 -count=1 - -[system.cpu.fuPool] -type=FUPool -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] -type=DerivO3CPU -clock=1 -numThreads=1 -activity=0 -workload=system.cpu.workload -mem=system.cpu.dcache -checker=null +type=AtomicSimpleCPU max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 -cachePorts=200 -decodeToFetchDelay=1 -renameToFetchDelay=1 -iewToFetchDelay=1 -commitToFetchDelay=1 -fetchWidth=8 -renameToDecodeDelay=1 -iewToDecodeDelay=1 -commitToDecodeDelay=1 -fetchToDecodeDelay=1 -decodeWidth=8 -iewToRenameDelay=1 -commitToRenameDelay=1 -decodeToRenameDelay=1 -renameWidth=8 -commitToIEWDelay=1 -renameToIEWDelay=2 -issueToExecuteDelay=1 -dispatchWidth=8 -issueWidth=8 -wbWidth=8 -wbDepth=1 -fuPool=system.cpu.fuPool -iewToCommitDelay=1 -renameToROBDelay=1 -commitWidth=8 -squashWidth=8 -trapLatency=13 -backComSize=5 -forwardComSize=5 -predType=tournament -localPredictorSize=2048 -localCtrBits=2 -localHistoryTableSize=2048 -localHistoryBits=11 -globalPredictorSize=8192 -globalCtrBits=2 -globalHistoryBits=13 -choicePredictorSize=8192 -choiceCtrBits=2 -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -LQEntries=32 -SQEntries=32 -LFSTSize=1024 -SSITSize=1024 -numPhysIntRegs=256 -numPhysFloatRegs=256 -numIQEntries=64 -numROBEntries=192 -smtNumFetchingThreads=1 -smtFetchPolicy=SingleThread -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtROBPolicy=Partitioned -smtROBThreshold=100 -smtCommitPolicy=RoundRobin -instShiftAmt=2 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 defer_registration=false +width=1 function_trace=false function_trace_start=0 - -[system.cpu.icache] -type=BaseCache -size=131072 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.l2cache] -type=BaseCache -size=2097152 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.toL2Bus] -type=Bus -bus_id=0 +simulate_stalls=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -396,8 +99,9 @@ print_cpseq=false print_reg_delta=false pc_symbol=true intel_format=false +legion_lockstep=false trace_system=client -[debug] -break_cycles= +[statsreset] +reset_cycle=0 diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt index 5d4f9235a..d73ff13a7 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,1974 +1,18 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 542 # Number of BTB hits -global.BPredUnit.BTBLookups 1938 # Number of BTB lookups -global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted -global.BPredUnit.lookups 2256 # Number of BP lookups -global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 41797 # Simulator instruction rate (inst/s) -host_mem_usage 160344 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 50948 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +host_inst_rate 857494 # Simulator instruction rate (inst/s) +host_mem_usage 149092 # Number of bytes of host memory used +host_seconds 103.05 # Real time elapsed on the host +host_tick_rate 857491 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 6870 # Number of ticks simulated -system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6116 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3908 6389.80% - 1 1064 1739.70% - 2 389 636.04% - 3 210 343.36% - 4 153 250.16% - 5 93 152.06% - 6 76 124.26% - 7 149 243.62% - 8 74 120.99% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 5640 # Number of instructions committed -system.cpu.commit.COM:loads 979 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 1791 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5623 # Number of Instructions Simulated -system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses -system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2048 # number of overall hits -system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses -system.cpu.dcache.overall_misses 311 # number of overall misses -system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use -system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched -system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6871 -system.cpu.fetch.rateDist.min_value 0 - 0 4549 6620.58% - 1 174 253.24% - 2 186 270.70% - 3 157 228.50% - 4 211 307.09% - 5 153 222.68% - 6 171 248.87% - 7 105 152.82% - 8 1165 1695.53% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses -system.cpu.icache.demand_misses 327 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1255 # number of overall hits -system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses -system.cpu.icache.overall_misses 327 # number of overall misses -system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use -system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:insts 7969 # Number of executed instructions -system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed -system.cpu.iew.EXEC:nop 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate -system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute -system.cpu.iew.EXEC:stores 989 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5438 # num instructions consuming a value -system.cpu.iew.WB:count 7722 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4049 # num instructions producing a value -system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle -system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemWrite.max_value 0 -system.cpu.iq.IQ:residence:MemWrite.end_dist - -system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5594 66.69% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 1757 20.95% # Type of FU issued - MemWrite 1032 12.30% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 0.87% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 76 66.09% # attempts to use FU when none available - MemWrite 38 33.04% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3753 5462.09% - 1 894 1301.12% - 2 723 1052.25% - 3 614 893.61% - 4 451 656.38% - 5 279 406.05% - 6 104 151.36% - 7 41 59.67% - 8 12 17.46% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate -system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 497 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 6871 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +sim_insts 88361899 # Number of instructions simulated +sim_seconds 0.000088 # Number of seconds simulated +sim_ticks 88361898 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 88361899 # number of cpu cycles simulated +system.cpu.num_insts 88361899 # Number of instructions executed +system.cpu.num_refs 35229376 # Number of memory references +system.cpu.workload.PROG:num_syscalls 4706 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr index 8893caac8..87866a2a5 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr +++ b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr @@ -1,3 +1 @@ warn: Entering event queue @ 0. Starting simulation... -warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 -warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout index fbb329a2f..e69de29bb 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout +++ b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout @@ -1,13 +0,0 @@ -Hello world! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:12 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Exiting @ tick 6870 because target called exit() diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini index c3a59fbce..3e5bdc569 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini @@ -7,11 +7,9 @@ max_tick=0 output_file=cout progress_interval=0 -[debug] -break_cycles= - [exetrace] intel_format=false +legion_lockstep=false pc_symbol=true print_cpseq=false print_cycle=true @@ -53,73 +51,20 @@ mem_mode=atomic physmem=system.physmem [system.cpu] -type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus workload -BTBEntries=4096 -BTBTagSize=16 -LFSTSize=1024 -LQEntries=32 -RASSize=16 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -choiceCtrBits=2 -choicePredictorSize=8192 +type=TimingSimpleCPU +children=dcache icache l2cache toL2Bus workload clock=1 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 +cpu_id=0 defer_registration=false -dispatchWidth=8 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -instShiftAmt=2 -issueToExecuteDelay=1 -issueWidth=8 -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.dcache -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -predType=tournament -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -squashWidth=8 +phase=0 +progress_interval=0 system=system -trapLatency=13 -wbDepth=1 -wbWidth=8 workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -131,7 +76,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -164,143 +108,6 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList0 -count=6 -opList=system.cpu.fuPool.FUList0.opList0 - -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList4.opList0 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList5.opList0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 -count=1 -opList=system.cpu.fuPool.FUList7.opList0 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - [system.cpu.icache] type=BaseCache adaptive_compression=false @@ -308,7 +115,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -348,7 +154,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -384,20 +189,33 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +responder_set=false +width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess -cmd=hello +cmd=vortex lendian.raw +cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-timing +egid=100 env= -executable=tests/test-progs/hello/bin/alpha/linux/hello +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +responder_set=false +width=64 port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] @@ -409,6 +227,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out b/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out index f491a3081..9ecf4b55d 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out @@ -19,19 +19,54 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 +responder_set=false [system.cpu.workload] type=LiveProcess -cmd=hello -executable=tests/test-progs/hello/bin/alpha/linux/hello +cmd=vortex lendian.raw +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex input=cin output=cout env= +cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-timing system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 -[system.cpu.dcache] +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.icache] type=BaseCache -size=262144 +size=131072 assoc=2 block_size=64 latency=1 @@ -39,7 +74,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -68,214 +102,9 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -opClass=IntAlu -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList0] -type=FUDesc -opList=system.cpu.fuPool.FUList0.opList0 -count=6 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -opClass=IntMult -opLat=3 -issueLat=1 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -opClass=IntDiv -opLat=20 -issueLat=19 - -[system.cpu.fuPool.FUList1] -type=FUDesc -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 -count=2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -opClass=FloatAdd -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -opClass=FloatCmp -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -opClass=FloatCvt -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2] -type=FUDesc -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 -count=4 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -opClass=FloatMult -opLat=4 -issueLat=1 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -opClass=FloatDiv -opLat=12 -issueLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -opClass=FloatSqrt -opLat=24 -issueLat=24 - -[system.cpu.fuPool.FUList3] -type=FUDesc -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 -count=2 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList4] -type=FUDesc -opList=system.cpu.fuPool.FUList4.opList0 -count=0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -opList=system.cpu.fuPool.FUList5.opList0 -count=0 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -count=4 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -opClass=IprAccess -opLat=3 -issueLat=3 - -[system.cpu.fuPool.FUList7] -type=FUDesc -opList=system.cpu.fuPool.FUList7.opList0 -count=1 - -[system.cpu.fuPool] -type=FUPool -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 - -[system.cpu] -type=DerivO3CPU -clock=1 -numThreads=1 -activity=0 -workload=system.cpu.workload -mem=system.cpu.dcache -checker=null -max_insts_any_thread=0 -max_insts_all_threads=0 -max_loads_any_thread=0 -max_loads_all_threads=0 -cachePorts=200 -decodeToFetchDelay=1 -renameToFetchDelay=1 -iewToFetchDelay=1 -commitToFetchDelay=1 -fetchWidth=8 -renameToDecodeDelay=1 -iewToDecodeDelay=1 -commitToDecodeDelay=1 -fetchToDecodeDelay=1 -decodeWidth=8 -iewToRenameDelay=1 -commitToRenameDelay=1 -decodeToRenameDelay=1 -renameWidth=8 -commitToIEWDelay=1 -renameToIEWDelay=2 -issueToExecuteDelay=1 -dispatchWidth=8 -issueWidth=8 -wbWidth=8 -wbDepth=1 -fuPool=system.cpu.fuPool -iewToCommitDelay=1 -renameToROBDelay=1 -commitWidth=8 -squashWidth=8 -trapLatency=13 -backComSize=5 -forwardComSize=5 -predType=tournament -localPredictorSize=2048 -localCtrBits=2 -localHistoryTableSize=2048 -localHistoryBits=11 -globalPredictorSize=8192 -globalCtrBits=2 -globalHistoryBits=13 -choicePredictorSize=8192 -choiceCtrBits=2 -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -LQEntries=32 -SQEntries=32 -LFSTSize=1024 -SSITSize=1024 -numPhysIntRegs=256 -numPhysFloatRegs=256 -numIQEntries=64 -numROBEntries=192 -smtNumFetchingThreads=1 -smtFetchPolicy=SingleThread -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtROBPolicy=Partitioned -smtROBThreshold=100 -smtCommitPolicy=RoundRobin -instShiftAmt=2 -defer_registration=false -function_trace=false -function_trace_start=0 - -[system.cpu.icache] +[system.cpu.dcache] type=BaseCache -size=131072 +size=262144 assoc=2 block_size=64 latency=1 @@ -283,7 +112,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -322,7 +150,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -351,13 +178,10 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[system.cpu.toL2Bus] -type=Bus -bus_id=0 - [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -396,8 +220,9 @@ print_cpseq=false print_reg_delta=false pc_symbol=true intel_format=false +legion_lockstep=false trace_system=client -[debug] -break_cycles= +[statsreset] +reset_cycle=0 diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt index 5d4f9235a..ae340ffef 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,112 +1,67 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 542 # Number of BTB hits -global.BPredUnit.BTBLookups 1938 # Number of BTB lookups -global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted -global.BPredUnit.lookups 2256 # Number of BP lookups -global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 41797 # Simulator instruction rate (inst/s) -host_mem_usage 160344 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 50948 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +host_inst_rate 471701 # Simulator instruction rate (inst/s) +host_mem_usage 255440 # Number of bytes of host memory used +host_seconds 187.33 # Real time elapsed on the host +host_tick_rate 6446013 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 6870 # Number of ticks simulated -system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6116 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3908 6389.80% - 1 1064 1739.70% - 2 389 636.04% - 3 210 343.36% - 4 153 250.16% - 5 93 152.06% - 6 76 124.26% - 7 149 243.62% - 8 74 120.99% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 5640 # Number of instructions committed -system.cpu.commit.COM:loads 979 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 1791 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5623 # Number of Instructions Simulated -system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +sim_insts 88361899 # Number of instructions simulated +sim_seconds 0.001208 # Number of seconds simulated +sim_ticks 1207510003 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 20281385 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3631.637073 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2631.637073 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 20223321 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 210867375 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002863 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 58064 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 152803375 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002863 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 58064 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 14615683 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 4569.538784 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3569.538784 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 14473602 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 649244640 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.009721 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 142081 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 507163640 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009721 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 142081 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 173.358930 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses -system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 34897068 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4297.444428 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3297.444428 # average overall mshr miss latency +system.cpu.dcache.demand_hits 34696923 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 860112015 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005735 # miss rate for demand accesses +system.cpu.dcache.demand_misses 200145 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 659967015 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005735 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 200145 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 34897068 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4297.444428 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3297.444428 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2048 # number of overall hits -system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses -system.cpu.dcache.overall_misses 311 # number of overall misses -system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_hits 34696923 # number of overall hits +system.cpu.dcache.overall_miss_latency 860112015 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005735 # miss rate for overall accesses +system.cpu.dcache.overall_misses 200145 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 659967015 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005735 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 200145 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 196049 # number of replacements +system.cpu.dcache.sampled_refs 200145 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use -system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched -system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6871 -system.cpu.fetch.rateDist.min_value 0 - 0 4549 6620.58% - 1 174 253.24% - 2 186 270.70% - 3 157 228.50% - 4 211 307.09% - 5 153 222.68% - 6 171 248.87% - 7 105 152.82% - 8 1165 1695.53% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 4056.501584 # Cycle average of tags in use +system.cpu.dcache.total_refs 34696923 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 28890000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147135 # number of writebacks +system.cpu.icache.ReadReq_accesses 88361900 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2933.039863 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1933.039863 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 88285387 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 224415679 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000866 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 76513 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 147902679 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000866 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 76513 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1153.861265 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses -system.cpu.icache.demand_misses 327 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 88361900 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2933.039863 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1933.039863 # average overall mshr miss latency +system.cpu.icache.demand_hits 88285387 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 224415679 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000866 # miss rate for demand accesses +system.cpu.icache.demand_misses 76513 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 147902679 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000866 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 76513 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_accesses 88361900 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2933.039863 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1933.039863 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1255 # number of overall hits -system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses -system.cpu.icache.overall_misses 327 # number of overall misses -system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_hits 88285387 # number of overall hits +system.cpu.icache.overall_miss_latency 224415679 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000866 # miss rate for overall accesses +system.cpu.icache.overall_misses 76513 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 147902679 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000866 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 76513 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,1726 +135,64 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.replacements 74468 # number of replacements +system.cpu.icache.sampled_refs 76513 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use -system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1798.721885 # Cycle average of tags in use +system.cpu.icache.total_refs 88285387 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:insts 7969 # Number of executed instructions -system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed -system.cpu.iew.EXEC:nop 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate -system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute -system.cpu.iew.EXEC:stores 989 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5438 # num instructions consuming a value -system.cpu.iew.WB:count 7722 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4049 # num instructions producing a value -system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle -system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 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-system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5594 66.69% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 1757 20.95% # Type of FU issued - MemWrite 1032 12.30% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 0.87% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 76 66.09% # attempts to use FU when none available - MemWrite 38 33.04% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3753 5462.09% - 1 894 1301.12% - 2 723 1052.25% - 3 614 893.61% - 4 451 656.38% - 5 279 406.05% - 6 104 151.36% - 7 41 59.67% - 8 12 17.46% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate -system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadReq_accesses 276658 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3650.746755 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1972.771607 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 108220 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 614924482 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.608831 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 168438 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 332289704 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.608831 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 168438 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 147135 # number of WriteReqNoAck|Writeback accesses(hits+misses) +system.cpu.l2cache.WriteReqNoAck|Writeback_hits 146550 # number of WriteReqNoAck|Writeback hits +system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.003976 # miss rate for WriteReqNoAck|Writeback accesses +system.cpu.l2cache.WriteReqNoAck|Writeback_misses 585 # number of WriteReqNoAck|Writeback misses +system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.003976 # mshr miss rate for WriteReqNoAck|Writeback accesses +system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 585 # number of WriteReqNoAck|Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.512545 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 276658 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3650.746755 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1972.771607 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 108220 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 614924482 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.608831 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 168438 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 332289704 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.608831 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 168438 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 423793 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3638.111275 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1972.771607 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_hits 254770 # number of overall hits +system.cpu.l2cache.overall_miss_latency 614924482 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.398834 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 169023 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 332289704 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.397453 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 168438 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -1946,29 +204,17 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 135670 # number of replacements +system.cpu.l2cache.sampled_refs 168438 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 6871 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.l2cache.tagsinuse 30358.430189 # Cycle average of tags in use +system.cpu.l2cache.total_refs 254770 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 475381000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 115647 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1207510003 # number of cpu cycles simulated +system.cpu.num_insts 88361899 # Number of instructions executed +system.cpu.num_refs 35229376 # Number of memory references +system.cpu.workload.PROG:num_syscalls 4706 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr b/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr index 8893caac8..87866a2a5 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr @@ -1,3 +1 @@ warn: Entering event queue @ 0. Starting simulation... -warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 -warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout b/tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout index fbb329a2f..e69de29bb 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout +++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout @@ -1,13 +0,0 @@ -Hello world! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:12 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Exiting @ tick 6870 because target called exit() diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini index c3a59fbce..7a3bd9383 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini @@ -7,11 +7,9 @@ max_tick=0 output_file=cout progress_interval=0 -[debug] -break_cycles= - [exetrace] intel_format=false +legion_lockstep=false pc_symbol=true print_cpseq=false print_cycle=true @@ -102,14 +100,15 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.dcache numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 +phase=0 predType=tournament +progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 renameToIEWDelay=2 @@ -131,7 +130,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -308,7 +306,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -348,7 +345,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -384,20 +380,33 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +responder_set=false +width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess -cmd=hello +cmd=bzip2 input.source 1 +cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/o3-timing +egid=100 env= -executable=tests/test-progs/hello/bin/alpha/linux/hello +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +responder_set=false +width=64 port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] @@ -409,6 +418,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out index f491a3081..1077b5dd7 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out +++ b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out @@ -19,54 +19,25 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 +responder_set=false [system.cpu.workload] type=LiveProcess -cmd=hello -executable=tests/test-progs/hello/bin/alpha/linux/hello +cmd=bzip2 input.source 1 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 input=cin output=cout env= +cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/o3-timing system=system - -[system.cpu.dcache] -type=BaseCache -size=262144 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu.fuPool.FUList0.opList0] type=OpDesc @@ -199,15 +170,16 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU clock=1 +phase=0 numThreads=1 activity=0 workload=system.cpu.workload -mem=system.cpu.dcache checker=null max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 cachePorts=200 decodeToFetchDelay=1 renameToFetchDelay=1 @@ -283,7 +255,44 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false protocol=null trace_addr=0 hash_delay=1 @@ -322,7 +331,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -354,10 +362,14 @@ hit_latency=1 [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 +responder_set=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -396,8 +408,9 @@ print_cpseq=false print_reg_delta=false pc_symbol=true intel_format=false +legion_lockstep=false trace_system=client -[debug] -break_cycles= +[statsreset] +reset_cycle=0 diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt index 5d4f9235a..73d6efd18 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,112 +1,112 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 542 # Number of BTB hits -global.BPredUnit.BTBLookups 1938 # Number of BTB lookups -global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted -global.BPredUnit.lookups 2256 # Number of BP lookups -global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 41797 # Simulator instruction rate (inst/s) -host_mem_usage 160344 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 50948 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 1060300638 # Number of BTB hits +global.BPredUnit.BTBLookups 1075264664 # Number of BTB lookups +global.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 20658855 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1028649695 # Number of conditional branches predicted +global.BPredUnit.lookups 1098978166 # Number of BP lookups +global.BPredUnit.usedRAS 20738311 # Number of times the RAS was used to get a target. +host_inst_rate 27542 # Simulator instruction rate (inst/s) +host_mem_usage 1254844 # Number of bytes of host memory used +host_seconds 63032.08 # Real time elapsed on the host +host_tick_rate 395232 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 114920109 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 60881817 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 938731548 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 389309694 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 6870 # Number of ticks simulated -system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached +sim_insts 1736043781 # Number of instructions simulated +sim_seconds 0.024912 # Number of seconds simulated +sim_ticks 24912272090 # Number of ticks simulated +system.cpu.commit.COM:branches 214632552 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 72343657 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.samples 5678957793 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3908 6389.80% - 1 1064 1739.70% - 2 389 636.04% - 3 210 343.36% - 4 153 250.16% - 5 93 152.06% - 6 76 124.26% - 7 149 243.62% - 8 74 120.99% + 0 5103057521 8985.90% + 1 193842571 341.33% + 2 126727829 223.15% + 3 63255233 111.39% + 4 47590442 83.80% + 5 34302037 60.40% + 6 22774532 40.10% + 7 15063971 26.53% + 8 72343657 127.39% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 5640 # Number of instructions committed -system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:count 1819780126 # Number of instructions committed +system.cpu.commit.COM:loads 445666361 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:refs 606571343 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5623 # Number of Instructions Simulated -system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.commit.branchMispredicts 20658355 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 3012390712 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1736043781 # Number of Instructions Simulated +system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated +system.cpu.cpi 14.350025 # CPI: Cycles Per Instruction +system.cpu.cpi_total 14.350025 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 466176479 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5764.172372 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5678.042412 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 454097633 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 69624550394 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.025910 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 12078846 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 4784670 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 41416640690 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.015647 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7294176 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 11148.179412 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14223.476157 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 157574910 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 35156809407 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.019621 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 3153592 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1270515 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 26783900812 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.011716 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1883077 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 972.020892 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 2881.979981 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 66.650940 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 659829 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 896062 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 641367573 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 2582432746 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses -system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 626904981 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 6878.830546 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 7431.476663 # average overall mshr miss latency +system.cpu.dcache.demand_hits 611672543 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 104781359801 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.024298 # miss rate for demand accesses +system.cpu.dcache.demand_misses 15232438 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 6055185 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 68200541502 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.014639 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9177253 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 626904981 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 6878.830546 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 7431.476663 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2048 # number of overall hits -system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses -system.cpu.dcache.overall_misses 311 # number of overall misses -system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_hits 611672543 # number of overall hits +system.cpu.dcache.overall_miss_latency 104781359801 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.024298 # miss rate for overall accesses +system.cpu.dcache.overall_misses 15232438 # number of overall misses +system.cpu.dcache.overall_mshr_hits 6055185 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 68200541502 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.014639 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9177253 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 9173157 # number of replacements +system.cpu.dcache.sampled_refs 9177253 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use -system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched -system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4093.061614 # Cycle average of tags in use +system.cpu.dcache.total_refs 611672543 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 39716000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2244715 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 3168036062 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 511 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 48557069 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 6641345328 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 1298412925 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 1202046298 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 501929792 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 1629 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 10462509 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 1098978166 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 541280485 # Number of cache lines fetched +system.cpu.fetch.Cycles 1955627258 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 11328270 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 7938391391 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 242391708 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.177803 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 541280485 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1081038949 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.284345 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.samples 6180887586 system.cpu.fetch.rateDist.min_value 0 - 0 4549 6620.58% - 1 174 253.24% - 2 186 270.70% - 3 157 228.50% - 4 211 307.09% - 5 153 222.68% - 6 171 248.87% - 7 105 152.82% - 8 1165 1695.53% + 0 4766540797 7711.74% + 1 80764415 130.67% + 2 63598055 102.89% + 3 58203597 94.17% + 4 424384465 686.61% + 5 69131012 111.85% + 6 94422767 152.77% + 7 44649271 72.24% + 8 579193207 937.07% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.icache.ReadReq_accesses 541280484 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5378.819380 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4616.750831 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 541279194 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 6938677 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1290 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 387 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 4168926 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 903 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets 4207.523810 # average number of cycles each access was blocked +system.cpu.icache.avg_refs 599423.249169 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 21 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 88358 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses -system.cpu.icache.demand_misses 327 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 541280484 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5378.819380 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4616.750831 # average overall mshr miss latency +system.cpu.icache.demand_hits 541279194 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 6938677 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses +system.cpu.icache.demand_misses 1290 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 387 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 4168926 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 903 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_accesses 541280484 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5378.819380 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4616.750831 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1255 # number of overall hits -system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses -system.cpu.icache.overall_misses 327 # number of overall misses -system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_hits 541279194 # number of overall hits +system.cpu.icache.overall_miss_latency 6938677 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses +system.cpu.icache.overall_misses 1290 # number of overall misses +system.cpu.icache.overall_mshr_hits 387 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 4168926 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 903 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,1646 +215,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1 # number of replacements +system.cpu.icache.sampled_refs 903 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use -system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 716.132429 # Cycle average of tags in use +system.cpu.icache.total_refs 541279194 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:insts 7969 # Number of executed instructions -system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed -system.cpu.iew.EXEC:nop 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate -system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute -system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.idleCycles 18731384505 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 250098653 # Number of branches executed +system.cpu.iew.EXEC:nop 147895912 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.440971 # Inst execution rate +system.cpu.iew.EXEC:refs 918923683 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 177016651 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5438 # num instructions consuming a value -system.cpu.iew.WB:count 7722 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:consumers 1839076786 # num instructions consuming a value +system.cpu.iew.WB:count 2471794731 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.797100 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4049 # num instructions producing a value -system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle -system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1465928228 # num instructions producing a value +system.cpu.iew.WB:rate 0.399909 # insts written-back per cycle +system.cpu.iew.WB:sent 2475054397 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 21956654 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2471410228 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 938731548 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 111073783 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 389309694 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 4831881465 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 741907032 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 286170200 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2725595031 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 1536928 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.iewLSQFullEvents 161620 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 501929792 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 6153373 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 8 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 233590575 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 41593346 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 516978 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 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- 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemWrite.max_value 0 -system.cpu.iq.IQ:residence:MemWrite.end_dist - -system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 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-system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 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-system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 47985 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 8 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 493065187 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 228404712 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 47985 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 11190791 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 10765863 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.069686 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.069686 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 3011765231 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5594 66.69% # Type of FU issued - IntMult 1 0.01% # Type of FU issued + (null) 0 0.00% # Type of FU issued + IntAlu 1970711875 65.43% # Type of FU issued + IntMult 679 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued + FloatAdd 206 0.00% # Type of FU issued + FloatCmp 15 0.00% # Type of FU issued + FloatCvt 146 0.00% # Type of FU issued + FloatMult 12 0.00% # Type of FU issued + FloatDiv 24 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1757 20.95% # Type of FU issued - MemWrite 1032 12.30% # Type of FU issued + MemRead 862446019 28.64% # Type of FU issued + MemWrite 178606255 5.93% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 11307551 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.003754 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 0.87% # attempts to use FU when none available + IntAlu 509990 4.51% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -1863,78 +297,84 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 76 66.09% # attempts to use FU when none available - MemWrite 38 33.04% # attempts to use FU when none available + MemRead 9173598 81.13% # attempts to use FU when none available + MemWrite 1623963 14.36% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.samples 6180887586 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3753 5462.09% - 1 894 1301.12% - 2 723 1052.25% - 3 614 893.61% - 4 451 656.38% - 5 279 406.05% - 6 104 151.36% - 7 41 59.67% - 8 12 17.46% + 0 4878979324 7893.65% + 1 360055339 582.53% + 2 481197713 778.53% + 3 280796976 454.30% + 4 94854448 153.46% + 5 50760526 82.12% + 6 26723872 43.24% + 7 6795220 10.99% + 8 724168 1.17% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate -system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.iq.ISSUE:rate 0.487271 # Inst issue rate +system.cpu.iq.iqInstsAdded 4683985508 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3011765231 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 2916477755 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 6096386 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 3050829124 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 9178154 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 7336.712513 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2076.036854 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7008989 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 15914539999 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.236340 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 2169165 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 4503266483 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236340 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 2169165 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 2244715 # number of WriteReqNoAck|Writeback accesses(hits+misses) +system.cpu.l2cache.WriteReqNoAck|Writeback_hits 2215400 # number of WriteReqNoAck|Writeback hits +system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.013060 # miss rate for WriteReqNoAck|Writeback accesses +system.cpu.l2cache.WriteReqNoAck|Writeback_misses 29315 # number of WriteReqNoAck|Writeback misses +system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.013060 # mshr miss rate for WriteReqNoAck|Writeback accesses +system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 29315 # number of WriteReqNoAck|Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.252507 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 9178154 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 7336.712513 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2076.036854 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7008989 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 15914539999 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.236340 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 2169165 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 4503266483 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.236340 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 2169165 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 11422869 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 7238.883228 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2076.036854 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_hits 9224389 # number of overall hits +system.cpu.l2cache.overall_miss_latency 15914539999 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.192463 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 2198480 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 4503266483 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.189897 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 2169165 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -1946,29 +386,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 2136397 # number of replacements +system.cpu.l2cache.sampled_refs 2169165 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 6871 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.l2cache.tagsinuse 32623.472165 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9224389 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 520424000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1039341 # number of writebacks +system.cpu.numCycles 6180887586 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 2894504060 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 6511750 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 1451413065 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 266047107 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 3125053 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 8501370508 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 6112671585 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 4584914520 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1056218413 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 501929792 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 276756270 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 3208711557 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 65986 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 1117979447 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 47 # count of temporary serializing insts renamed +system.cpu.timesIdled 7293390 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr index 8893caac8..87866a2a5 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr +++ b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr @@ -1,3 +1 @@ warn: Entering event queue @ 0. Starting simulation... -warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 -warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout index fbb329a2f..0c5c00118 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout +++ b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout @@ -1,13 +1,14 @@ -Hello world! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:12 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Exiting @ tick 6870 because target called exit() +spec_init +Loading Input Data +Input data 1048576 bytes in length +Compressing Input Data, level 7 +Compressed data 198546 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 198677 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini index c3a59fbce..ad57a5293 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini @@ -7,11 +7,9 @@ max_tick=0 output_file=cout progress_interval=0 -[debug] -break_cycles= - [exetrace] intel_format=false +legion_lockstep=false pc_symbol=true print_cpseq=false print_cycle=true @@ -53,352 +51,49 @@ mem_mode=atomic physmem=system.physmem [system.cpu] -type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus workload -BTBEntries=4096 -BTBTagSize=16 -LFSTSize=1024 -LQEntries=32 -RASSize=16 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -choiceCtrBits=2 -choicePredictorSize=8192 +type=AtomicSimpleCPU +children=workload clock=1 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 +cpu_id=0 defer_registration=false -dispatchWidth=8 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -instShiftAmt=2 -issueToExecuteDelay=1 -issueWidth=8 -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.dcache -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -predType=tournament -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -squashWidth=8 +phase=0 +progress_interval=0 +simulate_stalls=false system=system -trapLatency=13 -wbDepth=1 -wbWidth=8 +width=1 workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -do_copy=false -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=262144 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList0 -count=6 -opList=system.cpu.fuPool.FUList0.opList0 - -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList4.opList0 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList5.opList0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 -count=1 -opList=system.cpu.fuPool.FUList7.opList0 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - -[system.cpu.icache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -do_copy=false -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=131072 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.l2cache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -do_copy=false -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=2097152 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] - -[system.cpu.toL2Bus] -type=Bus -bus_id=0 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess -cmd=hello +cmd=bzip2 input.source 1 +cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-atomic +egid=100 env= -executable=tests/test-progs/hello/bin/alpha/linux/hello +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 -port=system.physmem.port system.cpu.l2cache.mem_side +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory @@ -409,6 +104,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out index f491a3081..891519c26 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out +++ b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out @@ -19,345 +19,48 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 +responder_set=false [system.cpu.workload] type=LiveProcess -cmd=hello -executable=tests/test-progs/hello/bin/alpha/linux/hello +cmd=bzip2 input.source 1 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 input=cin output=cout env= +cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-atomic system=system - -[system.cpu.dcache] -type=BaseCache -size=262144 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -opClass=IntAlu -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList0] -type=FUDesc -opList=system.cpu.fuPool.FUList0.opList0 -count=6 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -opClass=IntMult -opLat=3 -issueLat=1 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -opClass=IntDiv -opLat=20 -issueLat=19 - -[system.cpu.fuPool.FUList1] -type=FUDesc -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 -count=2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -opClass=FloatAdd -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -opClass=FloatCmp -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -opClass=FloatCvt -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2] -type=FUDesc -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 -count=4 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -opClass=FloatMult -opLat=4 -issueLat=1 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -opClass=FloatDiv -opLat=12 -issueLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -opClass=FloatSqrt -opLat=24 -issueLat=24 - -[system.cpu.fuPool.FUList3] -type=FUDesc -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 -count=2 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList4] -type=FUDesc -opList=system.cpu.fuPool.FUList4.opList0 -count=0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -opList=system.cpu.fuPool.FUList5.opList0 -count=0 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -count=4 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -opClass=IprAccess -opLat=3 -issueLat=3 - -[system.cpu.fuPool.FUList7] -type=FUDesc -opList=system.cpu.fuPool.FUList7.opList0 -count=1 - -[system.cpu.fuPool] -type=FUPool -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] -type=DerivO3CPU -clock=1 -numThreads=1 -activity=0 -workload=system.cpu.workload -mem=system.cpu.dcache -checker=null +type=AtomicSimpleCPU max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 -cachePorts=200 -decodeToFetchDelay=1 -renameToFetchDelay=1 -iewToFetchDelay=1 -commitToFetchDelay=1 -fetchWidth=8 -renameToDecodeDelay=1 -iewToDecodeDelay=1 -commitToDecodeDelay=1 -fetchToDecodeDelay=1 -decodeWidth=8 -iewToRenameDelay=1 -commitToRenameDelay=1 -decodeToRenameDelay=1 -renameWidth=8 -commitToIEWDelay=1 -renameToIEWDelay=2 -issueToExecuteDelay=1 -dispatchWidth=8 -issueWidth=8 -wbWidth=8 -wbDepth=1 -fuPool=system.cpu.fuPool -iewToCommitDelay=1 -renameToROBDelay=1 -commitWidth=8 -squashWidth=8 -trapLatency=13 -backComSize=5 -forwardComSize=5 -predType=tournament -localPredictorSize=2048 -localCtrBits=2 -localHistoryTableSize=2048 -localHistoryBits=11 -globalPredictorSize=8192 -globalCtrBits=2 -globalHistoryBits=13 -choicePredictorSize=8192 -choiceCtrBits=2 -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -LQEntries=32 -SQEntries=32 -LFSTSize=1024 -SSITSize=1024 -numPhysIntRegs=256 -numPhysFloatRegs=256 -numIQEntries=64 -numROBEntries=192 -smtNumFetchingThreads=1 -smtFetchPolicy=SingleThread -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtROBPolicy=Partitioned -smtROBThreshold=100 -smtCommitPolicy=RoundRobin -instShiftAmt=2 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 defer_registration=false +width=1 function_trace=false function_trace_start=0 - -[system.cpu.icache] -type=BaseCache -size=131072 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.l2cache] -type=BaseCache -size=2097152 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.toL2Bus] -type=Bus -bus_id=0 +simulate_stalls=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -396,8 +99,9 @@ print_cpseq=false print_reg_delta=false pc_symbol=true intel_format=false +legion_lockstep=false trace_system=client -[debug] -break_cycles= +[statsreset] +reset_cycle=0 diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt index 5d4f9235a..7422e3ae7 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,1974 +1,18 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 542 # Number of BTB hits -global.BPredUnit.BTBLookups 1938 # Number of BTB lookups -global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted -global.BPredUnit.lookups 2256 # Number of BP lookups -global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 41797 # Simulator instruction rate (inst/s) -host_mem_usage 160344 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 50948 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +host_inst_rate 927424 # Simulator instruction rate (inst/s) +host_mem_usage 144704 # Number of bytes of host memory used +host_seconds 1962.19 # Real time elapsed on the host +host_tick_rate 927424 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 6870 # Number of ticks simulated -system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6116 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3908 6389.80% - 1 1064 1739.70% - 2 389 636.04% - 3 210 343.36% - 4 153 250.16% - 5 93 152.06% - 6 76 124.26% - 7 149 243.62% - 8 74 120.99% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 5640 # Number of instructions committed -system.cpu.commit.COM:loads 979 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 1791 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5623 # Number of Instructions Simulated -system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses -system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2048 # number of overall hits -system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses -system.cpu.dcache.overall_misses 311 # number of overall misses -system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use -system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched -system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6871 -system.cpu.fetch.rateDist.min_value 0 - 0 4549 6620.58% - 1 174 253.24% - 2 186 270.70% - 3 157 228.50% - 4 211 307.09% - 5 153 222.68% - 6 171 248.87% - 7 105 152.82% - 8 1165 1695.53% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses -system.cpu.icache.demand_misses 327 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1255 # number of overall hits -system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses -system.cpu.icache.overall_misses 327 # number of overall misses -system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use -system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:insts 7969 # Number of executed instructions -system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed -system.cpu.iew.EXEC:nop 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate -system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute -system.cpu.iew.EXEC:stores 989 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5438 # num instructions consuming a value -system.cpu.iew.WB:count 7722 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4049 # num instructions producing a value -system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle -system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemWrite.max_value 0 -system.cpu.iq.IQ:residence:MemWrite.end_dist - -system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5594 66.69% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 1757 20.95% # Type of FU issued - MemWrite 1032 12.30% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 0.87% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 76 66.09% # attempts to use FU when none available - MemWrite 38 33.04% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3753 5462.09% - 1 894 1301.12% - 2 723 1052.25% - 3 614 893.61% - 4 451 656.38% - 5 279 406.05% - 6 104 151.36% - 7 41 59.67% - 8 12 17.46% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate -system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 497 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 6871 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +sim_insts 1819780129 # Number of instructions simulated +sim_seconds 0.001820 # Number of seconds simulated +sim_ticks 1819780128 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1819780129 # number of cpu cycles simulated +system.cpu.num_insts 1819780129 # Number of instructions executed +system.cpu.num_refs 606571345 # Number of memory references +system.cpu.workload.PROG:num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr index 8893caac8..87866a2a5 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr +++ b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr @@ -1,3 +1 @@ warn: Entering event queue @ 0. Starting simulation... -warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 -warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout index fbb329a2f..0c5c00118 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout +++ b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout @@ -1,13 +1,14 @@ -Hello world! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:12 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Exiting @ tick 6870 because target called exit() +spec_init +Loading Input Data +Input data 1048576 bytes in length +Compressing Input Data, level 7 +Compressed data 198546 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 198677 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini index c3a59fbce..0a123d4a4 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini @@ -7,11 +7,9 @@ max_tick=0 output_file=cout progress_interval=0 -[debug] -break_cycles= - [exetrace] intel_format=false +legion_lockstep=false pc_symbol=true print_cpseq=false print_cycle=true @@ -53,73 +51,20 @@ mem_mode=atomic physmem=system.physmem [system.cpu] -type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus workload -BTBEntries=4096 -BTBTagSize=16 -LFSTSize=1024 -LQEntries=32 -RASSize=16 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -choiceCtrBits=2 -choicePredictorSize=8192 +type=TimingSimpleCPU +children=dcache icache l2cache toL2Bus workload clock=1 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 +cpu_id=0 defer_registration=false -dispatchWidth=8 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -instShiftAmt=2 -issueToExecuteDelay=1 -issueWidth=8 -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.dcache -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -predType=tournament -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -squashWidth=8 +phase=0 +progress_interval=0 system=system -trapLatency=13 -wbDepth=1 -wbWidth=8 workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -131,7 +76,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -164,143 +108,6 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList0 -count=6 -opList=system.cpu.fuPool.FUList0.opList0 - -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList4.opList0 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList5.opList0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 -count=1 -opList=system.cpu.fuPool.FUList7.opList0 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - [system.cpu.icache] type=BaseCache adaptive_compression=false @@ -308,7 +115,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -348,7 +154,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -384,20 +189,33 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +responder_set=false +width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess -cmd=hello +cmd=bzip2 input.source 1 +cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing +egid=100 env= -executable=tests/test-progs/hello/bin/alpha/linux/hello +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +responder_set=false +width=64 port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] @@ -409,6 +227,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out index f491a3081..4692c5d40 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out @@ -19,19 +19,54 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 +responder_set=false [system.cpu.workload] type=LiveProcess -cmd=hello -executable=tests/test-progs/hello/bin/alpha/linux/hello +cmd=bzip2 input.source 1 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 input=cin output=cout env= +cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 -[system.cpu.dcache] +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.icache] type=BaseCache -size=262144 +size=131072 assoc=2 block_size=64 latency=1 @@ -39,7 +74,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -68,214 +102,9 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -opClass=IntAlu -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList0] -type=FUDesc -opList=system.cpu.fuPool.FUList0.opList0 -count=6 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -opClass=IntMult -opLat=3 -issueLat=1 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -opClass=IntDiv -opLat=20 -issueLat=19 - -[system.cpu.fuPool.FUList1] -type=FUDesc -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 -count=2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -opClass=FloatAdd -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -opClass=FloatCmp -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -opClass=FloatCvt -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2] -type=FUDesc -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 -count=4 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -opClass=FloatMult -opLat=4 -issueLat=1 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -opClass=FloatDiv -opLat=12 -issueLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -opClass=FloatSqrt -opLat=24 -issueLat=24 - -[system.cpu.fuPool.FUList3] -type=FUDesc -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 -count=2 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList4] -type=FUDesc -opList=system.cpu.fuPool.FUList4.opList0 -count=0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -opList=system.cpu.fuPool.FUList5.opList0 -count=0 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -count=4 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -opClass=IprAccess -opLat=3 -issueLat=3 - -[system.cpu.fuPool.FUList7] -type=FUDesc -opList=system.cpu.fuPool.FUList7.opList0 -count=1 - -[system.cpu.fuPool] -type=FUPool -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 - -[system.cpu] -type=DerivO3CPU -clock=1 -numThreads=1 -activity=0 -workload=system.cpu.workload -mem=system.cpu.dcache -checker=null -max_insts_any_thread=0 -max_insts_all_threads=0 -max_loads_any_thread=0 -max_loads_all_threads=0 -cachePorts=200 -decodeToFetchDelay=1 -renameToFetchDelay=1 -iewToFetchDelay=1 -commitToFetchDelay=1 -fetchWidth=8 -renameToDecodeDelay=1 -iewToDecodeDelay=1 -commitToDecodeDelay=1 -fetchToDecodeDelay=1 -decodeWidth=8 -iewToRenameDelay=1 -commitToRenameDelay=1 -decodeToRenameDelay=1 -renameWidth=8 -commitToIEWDelay=1 -renameToIEWDelay=2 -issueToExecuteDelay=1 -dispatchWidth=8 -issueWidth=8 -wbWidth=8 -wbDepth=1 -fuPool=system.cpu.fuPool -iewToCommitDelay=1 -renameToROBDelay=1 -commitWidth=8 -squashWidth=8 -trapLatency=13 -backComSize=5 -forwardComSize=5 -predType=tournament -localPredictorSize=2048 -localCtrBits=2 -localHistoryTableSize=2048 -localHistoryBits=11 -globalPredictorSize=8192 -globalCtrBits=2 -globalHistoryBits=13 -choicePredictorSize=8192 -choiceCtrBits=2 -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -LQEntries=32 -SQEntries=32 -LFSTSize=1024 -SSITSize=1024 -numPhysIntRegs=256 -numPhysFloatRegs=256 -numIQEntries=64 -numROBEntries=192 -smtNumFetchingThreads=1 -smtFetchPolicy=SingleThread -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtROBPolicy=Partitioned -smtROBThreshold=100 -smtCommitPolicy=RoundRobin -instShiftAmt=2 -defer_registration=false -function_trace=false -function_trace_start=0 - -[system.cpu.icache] +[system.cpu.dcache] type=BaseCache -size=131072 +size=262144 assoc=2 block_size=64 latency=1 @@ -283,7 +112,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -322,7 +150,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -351,13 +178,10 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[system.cpu.toL2Bus] -type=Bus -bus_id=0 - [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -396,8 +220,9 @@ print_cpseq=false print_reg_delta=false pc_symbol=true intel_format=false +legion_lockstep=false trace_system=client -[debug] -break_cycles= +[statsreset] +reset_cycle=0 diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt index 5d4f9235a..45b7beb7c 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,112 +1,67 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 542 # Number of BTB hits -global.BPredUnit.BTBLookups 1938 # Number of BTB lookups -global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted -global.BPredUnit.lookups 2256 # Number of BP lookups -global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 41797 # Simulator instruction rate (inst/s) -host_mem_usage 160344 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 50948 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +host_inst_rate 486900 # Simulator instruction rate (inst/s) +host_mem_usage 1198232 # Number of bytes of host memory used +host_seconds 3737.50 # Real time elapsed on the host +host_tick_rate 8500130 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 6870 # Number of ticks simulated -system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6116 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3908 6389.80% - 1 1064 1739.70% - 2 389 636.04% - 3 210 343.36% - 4 153 250.16% - 5 93 152.06% - 6 76 124.26% - 7 149 243.62% - 8 74 120.99% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 5640 # Number of instructions committed -system.cpu.commit.COM:loads 979 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 1791 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5623 # Number of Instructions Simulated -system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +sim_insts 1819780129 # Number of instructions simulated +sim_seconds 0.031769 # Number of seconds simulated +sim_ticks 31769223012 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3121.340330 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2121.340330 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 22543612099 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 15321198099 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3602.533807 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2602.533807 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 6806339173 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 4917019173 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses -system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3221.115901 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2221.115901 # average overall mshr miss latency +system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 29349951272 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses +system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 20238217272 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3221.115901 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2221.115901 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2048 # number of overall hits -system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses -system.cpu.dcache.overall_misses 311 # number of overall misses -system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_hits 596212431 # number of overall hits +system.cpu.dcache.overall_miss_latency 29349951272 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses +system.cpu.dcache.overall_misses 9111734 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 20238217272 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 9107638 # number of replacements +system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use -system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched -system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6871 -system.cpu.fetch.rateDist.min_value 0 - 0 4549 6620.58% - 1 174 253.24% - 2 186 270.70% - 3 157 228.50% - 4 211 307.09% - 5 153 222.68% - 6 171 248.87% - 7 105 152.82% - 8 1165 1695.53% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 4091.845274 # Cycle average of tags in use +system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 75264000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2244708 # number of writebacks +system.cpu.icache.ReadReq_accesses 1819780130 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 4089.753117 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3089.753117 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1819779328 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 3279982 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 2477982 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 2269051.531172 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses -system.cpu.icache.demand_misses 327 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1819780130 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 4089.753117 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3089.753117 # average overall mshr miss latency +system.cpu.icache.demand_hits 1819779328 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 3279982 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses +system.cpu.icache.demand_misses 802 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 2477982 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1819780130 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 4089.753117 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3089.753117 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1255 # number of overall hits -system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses -system.cpu.icache.overall_misses 327 # number of overall misses -system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_hits 1819779328 # number of overall hits +system.cpu.icache.overall_miss_latency 3279982 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses +system.cpu.icache.overall_misses 802 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 2477982 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,1726 +135,64 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1 # number of replacements +system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use -system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 625.996248 # Cycle average of tags in use +system.cpu.icache.total_refs 1819779328 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:insts 7969 # Number of executed instructions -system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed -system.cpu.iew.EXEC:nop 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate -system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute -system.cpu.iew.EXEC:stores 989 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5438 # num instructions consuming a value -system.cpu.iew.WB:count 7722 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4049 # num instructions producing a value -system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle -system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemWrite.max_value 0 -system.cpu.iq.IQ:residence:MemWrite.end_dist - -system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5594 66.69% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 1757 20.95% # Type of FU issued - MemWrite 1032 12.30% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 0.87% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 76 66.09% # attempts to use FU when none available - MemWrite 38 33.04% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3753 5462.09% - 1 894 1301.12% - 2 723 1052.25% - 3 614 893.61% - 4 451 656.38% - 5 279 406.05% - 6 104 151.36% - 7 41 59.67% - 8 12 17.46% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate -system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadReq_accesses 9112536 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3215.890455 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1919.394872 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 6952383 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 6946815413 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.237053 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 2160153 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 4146186590 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.237053 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 2160153 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 2244708 # number of WriteReqNoAck|Writeback accesses(hits+misses) +system.cpu.l2cache.WriteReqNoAck|Writeback_hits 2215611 # number of WriteReqNoAck|Writeback hits +system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.012962 # miss rate for WriteReqNoAck|Writeback accesses +system.cpu.l2cache.WriteReqNoAck|Writeback_misses 29097 # number of WriteReqNoAck|Writeback misses +system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.012962 # mshr miss rate for WriteReqNoAck|Writeback accesses +system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 29097 # number of WriteReqNoAck|Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.244141 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3215.890455 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1919.394872 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 6952383 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 6946815413 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.237053 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 2160153 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 4146186590 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.237053 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 2160153 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 11357244 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3173.148527 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1919.394872 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_hits 9167994 # number of overall hits +system.cpu.l2cache.overall_miss_latency 6946815413 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.192762 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 2189250 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 4146186590 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.190200 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 2160153 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -1946,29 +204,17 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 2127385 # number of replacements +system.cpu.l2cache.sampled_refs 2160153 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 6871 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.l2cache.tagsinuse 32563.117941 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9167994 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 748591000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1038202 # number of writebacks +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 31769223012 # number of cpu cycles simulated +system.cpu.num_insts 1819780129 # Number of instructions executed +system.cpu.num_refs 606571345 # Number of memory references +system.cpu.workload.PROG:num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr index 8893caac8..87866a2a5 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr +++ b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr @@ -1,3 +1 @@ warn: Entering event queue @ 0. Starting simulation... -warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 -warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout index fbb329a2f..0c5c00118 100644 --- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout +++ b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout @@ -1,13 +1,14 @@ -Hello world! -M5 Simulator System - -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:12 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Exiting @ tick 6870 because target called exit() +spec_init +Loading Input Data +Input data 1048576 bytes in length +Compressing Input Data, level 7 +Compressed data 198546 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 198677 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini index c3a59fbce..fb3d24c55 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini @@ -7,11 +7,9 @@ max_tick=0 output_file=cout progress_interval=0 -[debug] -break_cycles= - [exetrace] intel_format=false +legion_lockstep=false pc_symbol=true print_cpseq=false print_cycle=true @@ -102,14 +100,15 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.dcache numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 +phase=0 predType=tournament +progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 renameToIEWDelay=2 @@ -131,7 +130,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -308,7 +306,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -348,7 +345,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -384,20 +380,33 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +responder_set=false +width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess -cmd=hello +cmd=twolf smred +cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/o3-timing +egid=100 env= -executable=tests/test-progs/hello/bin/alpha/linux/hello +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +responder_set=false +width=64 port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] @@ -409,6 +418,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out b/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out index f491a3081..e4ed95acf 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out +++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out @@ -19,54 +19,25 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 +responder_set=false [system.cpu.workload] type=LiveProcess -cmd=hello -executable=tests/test-progs/hello/bin/alpha/linux/hello +cmd=twolf smred +executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf input=cin output=cout env= +cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/o3-timing system=system - -[system.cpu.dcache] -type=BaseCache -size=262144 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu.fuPool.FUList0.opList0] type=OpDesc @@ -199,15 +170,16 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU clock=1 +phase=0 numThreads=1 activity=0 workload=system.cpu.workload -mem=system.cpu.dcache checker=null max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 cachePorts=200 decodeToFetchDelay=1 renameToFetchDelay=1 @@ -283,7 +255,44 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false protocol=null trace_addr=0 hash_delay=1 @@ -322,7 +331,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -354,10 +362,14 @@ hit_latency=1 [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 +responder_set=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -396,8 +408,9 @@ print_cpseq=false print_reg_delta=false pc_symbol=true intel_format=false +legion_lockstep=false trace_system=client -[debug] -break_cycles= +[statsreset] +reset_cycle=0 diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt index 5d4f9235a..dfa1fbe0b 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,112 +1,112 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 542 # Number of BTB hits -global.BPredUnit.BTBLookups 1938 # Number of BTB lookups -global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted -global.BPredUnit.lookups 2256 # Number of BP lookups -global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 41797 # Simulator instruction rate (inst/s) -host_mem_usage 160344 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 50948 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 11837684 # Number of BTB hits +global.BPredUnit.BTBLookups 15197122 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1217 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1998573 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 12917224 # Number of conditional branches predicted +global.BPredUnit.lookups 17533197 # Number of BP lookups +global.BPredUnit.usedRAS 1687018 # Number of times the RAS was used to get a target. +host_inst_rate 57997 # Simulator instruction rate (inst/s) +host_mem_usage 178748 # Number of bytes of host memory used +host_seconds 1423.90 # Real time elapsed on the host +host_tick_rate 73521 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 10104667 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 3292311 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 29530804 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 9370879 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 6870 # Number of ticks simulated -system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached +sim_insts 82582323 # Number of instructions simulated +sim_seconds 0.000105 # Number of seconds simulated +sim_ticks 104686099 # Number of ticks simulated +system.cpu.commit.COM:branches 10071057 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 3175901 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.samples 65490840 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3908 6389.80% - 1 1064 1739.70% - 2 389 636.04% - 3 210 343.36% - 4 153 250.16% - 5 93 152.06% - 6 76 124.26% - 7 149 243.62% - 8 74 120.99% + 0 32034998 4891.52% + 1 13785472 2104.95% + 2 8057025 1230.25% + 3 3669149 560.25% + 4 1988059 303.56% + 5 1377349 210.31% + 6 785420 119.93% + 7 617467 94.28% + 8 3175901 484.94% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 5640 # Number of instructions committed -system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:count 90187947 # Number of instructions committed +system.cpu.commit.COM:loads 19613586 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:refs 25981086 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5623 # Number of Instructions Simulated -system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.commit.branchMispredicts 1985168 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 90187947 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 387 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 40679620 # The number of squashed insts skipped by commit +system.cpu.committedInsts 82582323 # Number of Instructions Simulated +system.cpu.committedInsts_total 82582323 # Number of Instructions Simulated +system.cpu.cpi 1.267657 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.267657 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 22673452 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5439.841232 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4838.693712 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 22672608 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4591226 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000037 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 844 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 351 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2385476 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 493 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6365908 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 5074.130393 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4849.051425 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6360739 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 26228180 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000812 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 5169 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 3555 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 7826369 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000254 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1614 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 2811.600000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 3114.692857 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 13779.471761 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 700 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 28116 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 2180285 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses -system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 29039360 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 5125.462498 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4846.627907 # average overall mshr miss latency +system.cpu.dcache.demand_hits 29033347 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 30819406 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000207 # miss rate for demand accesses +system.cpu.dcache.demand_misses 6013 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 3906 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 10211845 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000073 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2107 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 29039360 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 5125.462498 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4846.627907 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2048 # number of overall hits -system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses -system.cpu.dcache.overall_misses 311 # number of overall misses -system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_hits 29033347 # number of overall hits +system.cpu.dcache.overall_miss_latency 30819406 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000207 # miss rate for overall accesses +system.cpu.dcache.overall_misses 6013 # number of overall misses +system.cpu.dcache.overall_mshr_hits 3906 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 10211845 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000073 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2107 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 104 # number of replacements +system.cpu.dcache.sampled_refs 2107 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use -system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1404.053454 # Cycle average of tags in use +system.cpu.dcache.total_refs 29033347 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched -system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.dcache.writebacks 75 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 2221252 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 13564 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 2815361 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 145659694 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 36080141 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 27108364 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 6243203 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 50032 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 81084 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 17533197 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 17509399 # Number of cache lines fetched +system.cpu.fetch.Cycles 45531133 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 484323 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 150299775 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2040341 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.244419 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 17509399 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 13524702 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.095236 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.samples 71734044 system.cpu.fetch.rateDist.min_value 0 - 0 4549 6620.58% - 1 174 253.24% - 2 186 270.70% - 3 157 228.50% - 4 211 307.09% - 5 153 222.68% - 6 171 248.87% - 7 105 152.82% - 8 1165 1695.53% + 0 43713095 6093.77% + 1 2792314 389.26% + 2 2129360 296.84% + 3 3194083 445.27% + 4 4028588 561.60% + 5 1363321 190.05% + 6 1870461 260.75% + 7 1629807 227.20% + 8 11013015 1535.26% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.icache.ReadReq_accesses 17509399 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3388.211547 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2494.269154 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 17495889 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 45774738 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000772 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 13510 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 3486 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 25002554 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000572 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 10024 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets 3400.454545 # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1745.399940 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 22 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 74810 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses -system.cpu.icache.demand_misses 327 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 17509399 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3388.211547 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2494.269154 # average overall mshr miss latency +system.cpu.icache.demand_hits 17495889 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 45774738 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000772 # miss rate for demand accesses +system.cpu.icache.demand_misses 13510 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 3486 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 25002554 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000572 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 10024 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_accesses 17509399 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3388.211547 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2494.269154 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1255 # number of overall hits -system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses -system.cpu.icache.overall_misses 327 # number of overall misses -system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_hits 17495889 # number of overall hits +system.cpu.icache.overall_miss_latency 45774738 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000772 # miss rate for overall accesses +system.cpu.icache.overall_misses 13510 # number of overall misses +system.cpu.icache.overall_mshr_hits 3486 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 25002554 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000572 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 10024 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,1726 +215,162 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.replacements 8115 # number of replacements +system.cpu.icache.sampled_refs 10024 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use -system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1481.631027 # Cycle average of tags in use +system.cpu.icache.total_refs 17495889 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:insts 7969 # Number of executed instructions -system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed -system.cpu.iew.EXEC:nop 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate -system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute -system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.idleCycles 32952056 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 12456785 # Number of branches executed +system.cpu.iew.EXEC:nop 11559797 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.365191 # Inst execution rate +system.cpu.iew.EXEC:refs 30958353 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7006627 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5438 # num instructions consuming a value -system.cpu.iew.WB:count 7722 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:consumers 86914579 # num instructions consuming a value +system.cpu.iew.WB:count 96291361 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.729319 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4049 # num instructions producing a value -system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle -system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 63388475 # num instructions producing a value +system.cpu.iew.WB:rate 1.342338 # insts written-back per cycle +system.cpu.iew.WB:sent 96947832 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2153450 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 156060 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 29530804 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 437 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2057217 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 9370879 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 130866464 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 23951726 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2095770 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 97930658 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 43929 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.iewLSQFullEvents 720 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 6243203 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 62133 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 9874 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 40553 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 855538 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 3321 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemWrite.max_value 0 -system.cpu.iq.IQ:residence:MemWrite.end_dist - -system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 18493 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 9874 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 9917218 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 3003379 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 18493 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1143572 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1009878 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.788857 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.788857 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 100026428 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5594 66.69% # Type of FU issued - IntMult 1 0.01% # Type of FU issued + (null) 7 0.00% # Type of FU issued + IntAlu 61666427 61.65% # Type of FU issued + IntMult 468908 0.47% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 1757 20.95% # Type of FU issued - MemWrite 1032 12.30% # Type of FU issued + FloatAdd 2704055 2.70% # Type of FU issued + FloatCmp 112834 0.11% # Type of FU issued + FloatCvt 2307257 2.31% # Type of FU issued + FloatMult 295394 0.30% # Type of FU issued + FloatDiv 735688 0.74% # Type of FU issued + FloatSqrt 122 0.00% # Type of FU issued + MemRead 24586382 24.58% # Type of FU issued + MemWrite 7149354 7.15% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 1620744 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.016203 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 0.87% # attempts to use FU when none available + IntAlu 195067 12.04% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available + FloatAdd 1678 0.10% # attempts to use FU when none available + FloatCmp 197 0.01% # attempts to use FU when none available + FloatCvt 4552 0.28% # attempts to use FU when none available + FloatMult 2392 0.15% # attempts to use FU when none available + FloatDiv 951463 58.71% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 76 66.09% # attempts to use FU when none available - MemWrite 38 33.04% # attempts to use FU when none available + MemRead 401417 24.77% # attempts to use FU when none available + MemWrite 63978 3.95% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.samples 71734044 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3753 5462.09% - 1 894 1301.12% - 2 723 1052.25% - 3 614 893.61% - 4 451 656.38% - 5 279 406.05% - 6 104 151.36% - 7 41 59.67% - 8 12 17.46% + 0 28631398 3991.33% + 1 15448994 2153.65% + 2 12333631 1719.36% + 3 7046540 982.31% + 4 4503539 627.81% + 5 2295007 319.93% + 6 1113179 155.18% + 7 291761 40.67% + 8 69995 9.76% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate -system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.iq.ISSUE:rate 1.394407 # Inst issue rate +system.cpu.iq.iqInstsAdded 119306230 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 100026428 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 437 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 35838359 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 150449 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 50 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 30462150 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 12131 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3919.717352 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2067.943230 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7146 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 19539791 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.410931 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4985 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 10308697 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.410931 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 4985 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 75 # number of WriteReqNoAck|Writeback accesses(hits+misses) +system.cpu.l2cache.WriteReqNoAck|Writeback_hits 75 # number of WriteReqNoAck|Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.448546 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 12131 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3919.717352 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2067.943230 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7146 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 19539791 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.410931 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 4985 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 10308697 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.410931 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 4985 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 12206 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3919.717352 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2067.943230 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_hits 7221 # number of overall hits +system.cpu.l2cache.overall_miss_latency 19539791 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.408406 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 4985 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 10308697 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.408406 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 4985 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -1947,28 +383,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 4985 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3244.539242 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7221 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 6871 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.numCycles 71734044 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 969328 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 67122956 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 411688 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 37058676 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 742595 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 109 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 181728449 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 141044897 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 103457127 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 26196123 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 6243203 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1187915 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 36334171 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 78799 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 513 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 2731208 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 502 # count of temporary serializing insts renamed +system.cpu.timesIdled 10186 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 387 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr b/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr index 8893caac8..87866a2a5 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr +++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr @@ -1,3 +1 @@ warn: Entering event queue @ 0. Starting simulation... -warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 -warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout b/tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout index fbb329a2f..f32f0a972 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout +++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout @@ -1,13 +1,14 @@ -Hello world! -M5 Simulator System -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:12 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Exiting @ tick 6870 because target called exit() +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 \ No newline at end of file diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini index c3a59fbce..fbf8dd865 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini @@ -7,11 +7,9 @@ max_tick=0 output_file=cout progress_interval=0 -[debug] -break_cycles= - [exetrace] intel_format=false +legion_lockstep=false pc_symbol=true print_cpseq=false print_cycle=true @@ -53,352 +51,49 @@ mem_mode=atomic physmem=system.physmem [system.cpu] -type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus workload -BTBEntries=4096 -BTBTagSize=16 -LFSTSize=1024 -LQEntries=32 -RASSize=16 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -choiceCtrBits=2 -choicePredictorSize=8192 +type=AtomicSimpleCPU +children=workload clock=1 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 +cpu_id=0 defer_registration=false -dispatchWidth=8 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -instShiftAmt=2 -issueToExecuteDelay=1 -issueWidth=8 -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.dcache -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -predType=tournament -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -squashWidth=8 +phase=0 +progress_interval=0 +simulate_stalls=false system=system -trapLatency=13 -wbDepth=1 -wbWidth=8 +width=1 workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -do_copy=false -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=262144 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList0 -count=6 -opList=system.cpu.fuPool.FUList0.opList0 - -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList4.opList0 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList5.opList0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 -count=1 -opList=system.cpu.fuPool.FUList7.opList0 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - -[system.cpu.icache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -do_copy=false -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=131072 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] - -[system.cpu.l2cache] -type=BaseCache -adaptive_compression=false -assoc=2 -block_size=64 -compressed_bus=false -compression_latency=0 -do_copy=false -hash_delay=1 -hit_latency=1 -latency=1 -lifo=false -max_miss_count=0 -mshrs=10 -prefetch_access=false -prefetch_cache_check_push=true -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10 -prefetch_miss=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -protocol=Null -repl=Null -size=2097152 -split=false -split_size=0 -store_compressed=false -subblock_size=0 -tgts_per_mshr=5 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] - -[system.cpu.toL2Bus] -type=Bus -bus_id=0 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess -cmd=hello +cmd=twolf smred +cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-atomic +egid=100 env= -executable=tests/test-progs/hello/bin/alpha/linux/hello +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 -port=system.physmem.port system.cpu.l2cache.mem_side +clock=1000 +responder_set=false +width=64 +port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory @@ -409,6 +104,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out index f491a3081..5375d2a8f 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out +++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out @@ -19,345 +19,48 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 +responder_set=false [system.cpu.workload] type=LiveProcess -cmd=hello -executable=tests/test-progs/hello/bin/alpha/linux/hello +cmd=twolf smred +executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf input=cin output=cout env= +cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-atomic system=system - -[system.cpu.dcache] -type=BaseCache -size=262144 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -opClass=IntAlu -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList0] -type=FUDesc -opList=system.cpu.fuPool.FUList0.opList0 -count=6 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -opClass=IntMult -opLat=3 -issueLat=1 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -opClass=IntDiv -opLat=20 -issueLat=19 - -[system.cpu.fuPool.FUList1] -type=FUDesc -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 -count=2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -opClass=FloatAdd -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -opClass=FloatCmp -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -opClass=FloatCvt -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2] -type=FUDesc -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 -count=4 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -opClass=FloatMult -opLat=4 -issueLat=1 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -opClass=FloatDiv -opLat=12 -issueLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -opClass=FloatSqrt -opLat=24 -issueLat=24 - -[system.cpu.fuPool.FUList3] -type=FUDesc -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 -count=2 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList4] -type=FUDesc -opList=system.cpu.fuPool.FUList4.opList0 -count=0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -opList=system.cpu.fuPool.FUList5.opList0 -count=0 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -count=4 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -opClass=IprAccess -opLat=3 -issueLat=3 - -[system.cpu.fuPool.FUList7] -type=FUDesc -opList=system.cpu.fuPool.FUList7.opList0 -count=1 - -[system.cpu.fuPool] -type=FUPool -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] -type=DerivO3CPU -clock=1 -numThreads=1 -activity=0 -workload=system.cpu.workload -mem=system.cpu.dcache -checker=null +type=AtomicSimpleCPU max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 -cachePorts=200 -decodeToFetchDelay=1 -renameToFetchDelay=1 -iewToFetchDelay=1 -commitToFetchDelay=1 -fetchWidth=8 -renameToDecodeDelay=1 -iewToDecodeDelay=1 -commitToDecodeDelay=1 -fetchToDecodeDelay=1 -decodeWidth=8 -iewToRenameDelay=1 -commitToRenameDelay=1 -decodeToRenameDelay=1 -renameWidth=8 -commitToIEWDelay=1 -renameToIEWDelay=2 -issueToExecuteDelay=1 -dispatchWidth=8 -issueWidth=8 -wbWidth=8 -wbDepth=1 -fuPool=system.cpu.fuPool -iewToCommitDelay=1 -renameToROBDelay=1 -commitWidth=8 -squashWidth=8 -trapLatency=13 -backComSize=5 -forwardComSize=5 -predType=tournament -localPredictorSize=2048 -localCtrBits=2 -localHistoryTableSize=2048 -localHistoryBits=11 -globalPredictorSize=8192 -globalCtrBits=2 -globalHistoryBits=13 -choicePredictorSize=8192 -choiceCtrBits=2 -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -LQEntries=32 -SQEntries=32 -LFSTSize=1024 -SSITSize=1024 -numPhysIntRegs=256 -numPhysFloatRegs=256 -numIQEntries=64 -numROBEntries=192 -smtNumFetchingThreads=1 -smtFetchPolicy=SingleThread -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtROBPolicy=Partitioned -smtROBThreshold=100 -smtCommitPolicy=RoundRobin -instShiftAmt=2 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 defer_registration=false +width=1 function_trace=false function_trace_start=0 - -[system.cpu.icache] -type=BaseCache -size=131072 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.l2cache] -type=BaseCache -size=2097152 -assoc=2 -block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 - -[system.cpu.toL2Bus] -type=Bus -bus_id=0 +simulate_stalls=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -396,8 +99,9 @@ print_cpseq=false print_reg_delta=false pc_symbol=true intel_format=false +legion_lockstep=false trace_system=client -[debug] -break_cycles= +[statsreset] +reset_cycle=0 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt index 5d4f9235a..e5e0a4991 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,1974 +1,18 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 542 # Number of BTB hits -global.BPredUnit.BTBLookups 1938 # Number of BTB lookups -global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted -global.BPredUnit.lookups 2256 # Number of BP lookups -global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 41797 # Simulator instruction rate (inst/s) -host_mem_usage 160344 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 50948 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +host_inst_rate 827042 # Simulator instruction rate (inst/s) +host_mem_usage 146736 # Number of bytes of host memory used +host_seconds 111.12 # Real time elapsed on the host +host_tick_rate 827039 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 6870 # Number of ticks simulated -system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6116 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3908 6389.80% - 1 1064 1739.70% - 2 389 636.04% - 3 210 343.36% - 4 153 250.16% - 5 93 152.06% - 6 76 124.26% - 7 149 243.62% - 8 74 120.99% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 5640 # Number of instructions committed -system.cpu.commit.COM:loads 979 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 1791 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5623 # Number of Instructions Simulated -system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses -system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2048 # number of overall hits -system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses -system.cpu.dcache.overall_misses 311 # number of overall misses -system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use -system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched -system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6871 -system.cpu.fetch.rateDist.min_value 0 - 0 4549 6620.58% - 1 174 253.24% - 2 186 270.70% - 3 157 228.50% - 4 211 307.09% - 5 153 222.68% - 6 171 248.87% - 7 105 152.82% - 8 1165 1695.53% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses -system.cpu.icache.demand_misses 327 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1255 # number of overall hits -system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses -system.cpu.icache.overall_misses 327 # number of overall misses -system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use -system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:insts 7969 # Number of executed instructions -system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed -system.cpu.iew.EXEC:nop 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate -system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute -system.cpu.iew.EXEC:stores 989 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5438 # num instructions consuming a value -system.cpu.iew.WB:count 7722 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4049 # num instructions producing a value -system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle -system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemWrite.max_value 0 -system.cpu.iq.IQ:residence:MemWrite.end_dist - -system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5594 66.69% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 1757 20.95% # Type of FU issued - MemWrite 1032 12.30% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 0.87% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 76 66.09% # attempts to use FU when none available - MemWrite 38 33.04% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3753 5462.09% - 1 894 1301.12% - 2 723 1052.25% - 3 614 893.61% - 4 451 656.38% - 5 279 406.05% - 6 104 151.36% - 7 41 59.67% - 8 12 17.46% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate -system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 497 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 6871 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +sim_insts 91900700 # Number of instructions simulated +sim_seconds 0.000092 # Number of seconds simulated +sim_ticks 91900699 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 91900700 # number of cpu cycles simulated +system.cpu.num_insts 91900700 # Number of instructions executed +system.cpu.num_refs 26536244 # Number of memory references +system.cpu.workload.PROG:num_syscalls 387 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr index 8893caac8..87866a2a5 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr +++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr @@ -1,3 +1 @@ warn: Entering event queue @ 0. Starting simulation... -warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 -warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout index fbb329a2f..f32f0a972 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout @@ -1,13 +1,14 @@ -Hello world! -M5 Simulator System -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:12 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Exiting @ tick 6870 because target called exit() +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 \ No newline at end of file diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini index c3a59fbce..9f6151e4d 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini @@ -7,11 +7,9 @@ max_tick=0 output_file=cout progress_interval=0 -[debug] -break_cycles= - [exetrace] intel_format=false +legion_lockstep=false pc_symbol=true print_cpseq=false print_cycle=true @@ -53,73 +51,20 @@ mem_mode=atomic physmem=system.physmem [system.cpu] -type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus workload -BTBEntries=4096 -BTBTagSize=16 -LFSTSize=1024 -LQEntries=32 -RASSize=16 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -choiceCtrBits=2 -choicePredictorSize=8192 +type=TimingSimpleCPU +children=dcache icache l2cache toL2Bus workload clock=1 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 +cpu_id=0 defer_registration=false -dispatchWidth=8 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -instShiftAmt=2 -issueToExecuteDelay=1 -issueWidth=8 -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.dcache -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -predType=tournament -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -squashWidth=8 +phase=0 +progress_interval=0 system=system -trapLatency=13 -wbDepth=1 -wbWidth=8 workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -131,7 +76,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -164,143 +108,6 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList0 -count=6 -opList=system.cpu.fuPool.FUList0.opList0 - -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList4.opList0 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList0 -count=0 -opList=system.cpu.fuPool.FUList5.opList0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 -count=1 -opList=system.cpu.fuPool.FUList7.opList0 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - [system.cpu.icache] type=BaseCache adaptive_compression=false @@ -308,7 +115,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -348,7 +154,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -384,20 +189,33 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +responder_set=false +width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess -cmd=hello +cmd=twolf smred +cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-timing +egid=100 env= -executable=tests/test-progs/hello/bin/alpha/linux/hello +euid=100 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +responder_set=false +width=64 port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] @@ -409,6 +227,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out b/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out index f491a3081..c27975bcb 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out @@ -19,19 +19,54 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 +responder_set=false [system.cpu.workload] type=LiveProcess -cmd=hello -executable=tests/test-progs/hello/bin/alpha/linux/hello +cmd=twolf smred +executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf input=cin output=cout env= +cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-timing system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 -[system.cpu.dcache] +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=1 +phase=0 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.icache] type=BaseCache -size=262144 +size=131072 assoc=2 block_size=64 latency=1 @@ -39,7 +74,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -68,214 +102,9 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[system.cpu.fuPool.FUList0.opList0] -type=OpDesc -opClass=IntAlu -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList0] -type=FUDesc -opList=system.cpu.fuPool.FUList0.opList0 -count=6 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -opClass=IntMult -opLat=3 -issueLat=1 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -opClass=IntDiv -opLat=20 -issueLat=19 - -[system.cpu.fuPool.FUList1] -type=FUDesc -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 -count=2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -opClass=FloatAdd -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -opClass=FloatCmp -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -opClass=FloatCvt -opLat=2 -issueLat=1 - -[system.cpu.fuPool.FUList2] -type=FUDesc -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 -count=4 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -opClass=FloatMult -opLat=4 -issueLat=1 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -opClass=FloatDiv -opLat=12 -issueLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -opClass=FloatSqrt -opLat=24 -issueLat=24 - -[system.cpu.fuPool.FUList3] -type=FUDesc -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 -count=2 - -[system.cpu.fuPool.FUList4.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList4] -type=FUDesc -opList=system.cpu.fuPool.FUList4.opList0 -count=0 - -[system.cpu.fuPool.FUList5.opList0] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -opList=system.cpu.fuPool.FUList5.opList0 -count=0 - -[system.cpu.fuPool.FUList6.opList0] -type=OpDesc -opClass=MemRead -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6.opList1] -type=OpDesc -opClass=MemWrite -opLat=1 -issueLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -count=4 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -opClass=IprAccess -opLat=3 -issueLat=3 - -[system.cpu.fuPool.FUList7] -type=FUDesc -opList=system.cpu.fuPool.FUList7.opList0 -count=1 - -[system.cpu.fuPool] -type=FUPool -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 - -[system.cpu] -type=DerivO3CPU -clock=1 -numThreads=1 -activity=0 -workload=system.cpu.workload -mem=system.cpu.dcache -checker=null -max_insts_any_thread=0 -max_insts_all_threads=0 -max_loads_any_thread=0 -max_loads_all_threads=0 -cachePorts=200 -decodeToFetchDelay=1 -renameToFetchDelay=1 -iewToFetchDelay=1 -commitToFetchDelay=1 -fetchWidth=8 -renameToDecodeDelay=1 -iewToDecodeDelay=1 -commitToDecodeDelay=1 -fetchToDecodeDelay=1 -decodeWidth=8 -iewToRenameDelay=1 -commitToRenameDelay=1 -decodeToRenameDelay=1 -renameWidth=8 -commitToIEWDelay=1 -renameToIEWDelay=2 -issueToExecuteDelay=1 -dispatchWidth=8 -issueWidth=8 -wbWidth=8 -wbDepth=1 -fuPool=system.cpu.fuPool -iewToCommitDelay=1 -renameToROBDelay=1 -commitWidth=8 -squashWidth=8 -trapLatency=13 -backComSize=5 -forwardComSize=5 -predType=tournament -localPredictorSize=2048 -localCtrBits=2 -localHistoryTableSize=2048 -localHistoryBits=11 -globalPredictorSize=8192 -globalCtrBits=2 -globalHistoryBits=13 -choicePredictorSize=8192 -choiceCtrBits=2 -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -LQEntries=32 -SQEntries=32 -LFSTSize=1024 -SSITSize=1024 -numPhysIntRegs=256 -numPhysFloatRegs=256 -numIQEntries=64 -numROBEntries=192 -smtNumFetchingThreads=1 -smtFetchPolicy=SingleThread -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtROBPolicy=Partitioned -smtROBThreshold=100 -smtCommitPolicy=RoundRobin -instShiftAmt=2 -defer_registration=false -function_trace=false -function_trace_start=0 - -[system.cpu.icache] +[system.cpu.dcache] type=BaseCache -size=131072 +size=262144 assoc=2 block_size=64 latency=1 @@ -283,7 +112,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -322,7 +150,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -351,13 +178,10 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[system.cpu.toL2Bus] -type=Bus -bus_id=0 - [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -396,8 +220,9 @@ print_cpseq=false print_reg_delta=false pc_symbol=true intel_format=false +legion_lockstep=false trace_system=client -[debug] -break_cycles= +[statsreset] +reset_cycle=0 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt index 5d4f9235a..3926b2de9 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,112 +1,67 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 542 # Number of BTB hits -global.BPredUnit.BTBLookups 1938 # Number of BTB lookups -global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted -global.BPredUnit.lookups 2256 # Number of BP lookups -global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 41797 # Simulator instruction rate (inst/s) -host_mem_usage 160344 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 50948 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +host_inst_rate 460435 # Simulator instruction rate (inst/s) +host_mem_usage 178124 # Number of bytes of host memory used +host_seconds 199.60 # Real time elapsed on the host +host_tick_rate 765898 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 6870 # Number of ticks simulated -system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6116 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3908 6389.80% - 1 1064 1739.70% - 2 389 636.04% - 3 210 343.36% - 4 153 250.16% - 5 93 152.06% - 6 76 124.26% - 7 149 243.62% - 8 74 120.99% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - -system.cpu.commit.COM:count 5640 # Number of instructions committed -system.cpu.commit.COM:loads 979 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 1791 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5623 # Number of Instructions Simulated -system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +sim_insts 91900700 # Number of instructions simulated +sim_seconds 0.000153 # Number of seconds simulated +sim_ticks 152870012 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 19995627 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3765.212314 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2765.212314 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 19995156 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1773415 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 471 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 1302415 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 471 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6500813 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3867.178372 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2867.178372 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6499204 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 6222290 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000248 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1609 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 4613290 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000248 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1609 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 12737.673077 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses -system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 26496440 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3844.088942 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2844.088942 # average overall mshr miss latency +system.cpu.dcache.demand_hits 26494360 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 7995705 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2080 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 5915705 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2080 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 26496440 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3844.088942 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2844.088942 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2048 # number of overall hits -system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses -system.cpu.dcache.overall_misses 311 # number of overall misses -system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_hits 26494360 # number of overall hits +system.cpu.dcache.overall_miss_latency 7995705 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2080 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 5915705 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2080 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 103 # number of replacements +system.cpu.dcache.sampled_refs 2080 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use -system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1399.324024 # Cycle average of tags in use +system.cpu.dcache.total_refs 26494360 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched -system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6871 -system.cpu.fetch.rateDist.min_value 0 - 0 4549 6620.58% - 1 174 253.24% - 2 186 270.70% - 3 157 228.50% - 4 211 307.09% - 5 153 222.68% - 6 171 248.87% - 7 105 152.82% - 8 1165 1695.53% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - -system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.dcache.writebacks 74 # number of writebacks +system.cpu.icache.ReadReq_accesses 91900701 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3116.205529 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2116.205529 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 91892201 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 26487747 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000092 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 8500 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 17987747 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000092 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 8500 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 10810.847176 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses -system.cpu.icache.demand_misses 327 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 91900701 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3116.205529 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2116.205529 # average overall mshr miss latency +system.cpu.icache.demand_hits 91892201 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 26487747 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000092 # miss rate for demand accesses +system.cpu.icache.demand_misses 8500 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 17987747 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000092 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 8500 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_accesses 91900701 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3116.205529 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2116.205529 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1255 # number of overall hits -system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses -system.cpu.icache.overall_misses 327 # number of overall misses -system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_hits 91892201 # number of overall hits +system.cpu.icache.overall_miss_latency 26487747 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000092 # miss rate for overall accesses +system.cpu.icache.overall_misses 8500 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 17987747 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000092 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 8500 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,1726 +135,60 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.replacements 6677 # number of replacements +system.cpu.icache.sampled_refs 8500 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use -system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1370.015418 # Cycle average of tags in use +system.cpu.icache.total_refs 91892201 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:insts 7969 # Number of executed instructions -system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed -system.cpu.iew.EXEC:nop 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate -system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute -system.cpu.iew.EXEC:stores 989 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5438 # num instructions consuming a value -system.cpu.iew.WB:count 7722 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4049 # num instructions producing a value -system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle -system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 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-system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5594 66.69% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 1757 20.95% # Type of FU issued - MemWrite 1032 12.30% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 0.87% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 76 66.09% # attempts to use FU when none available - MemWrite 38 33.04% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3753 5462.09% - 1 894 1301.12% - 2 723 1052.25% - 3 614 893.61% - 4 451 656.38% - 5 279 406.05% - 6 104 151.36% - 7 41 59.67% - 8 12 17.46% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - -system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate -system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.l2cache.ReadReq_accesses 10580 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2883.751500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1878.799057 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5912 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 13461352 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.441210 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4668 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 8770234 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.441210 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 4668 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 74 # number of WriteReqNoAck|Writeback accesses(hits+misses) +system.cpu.l2cache.WriteReqNoAck|Writeback_hits 74 # number of WriteReqNoAck|Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.282348 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 10580 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2883.751500 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1878.799057 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 5912 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 13461352 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.441210 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 4668 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 8770234 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.441210 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 4668 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 10654 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2883.751500 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1878.799057 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_hits 5986 # number of overall hits +system.cpu.l2cache.overall_miss_latency 13461352 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.438145 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 4668 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 8770234 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.438145 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 4668 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -1947,28 +201,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 4668 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3056.777484 # Cycle average of tags in use +system.cpu.l2cache.total_refs 5986 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 6871 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.workload.PROG:num_syscalls 17 # Number of system calls +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 152870012 # number of cpu cycles simulated +system.cpu.num_insts 91900700 # Number of instructions executed +system.cpu.num_refs 26536244 # Number of memory references +system.cpu.workload.PROG:num_syscalls 387 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr b/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr index 8893caac8..87866a2a5 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr +++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr @@ -1,3 +1 @@ warn: Entering event queue @ 0. Starting simulation... -warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 -warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout b/tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout index fbb329a2f..f32f0a972 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout +++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout @@ -1,13 +1,14 @@ -Hello world! -M5 Simulator System -Copyright (c) 2001-2006 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:12 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Exiting @ tick 6870 because target called exit() +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 \ No newline at end of file From 54a946604b2fa81c0d58fc41bfe1d82840f44793 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Tue, 5 Dec 2006 11:12:18 -0500 Subject: [PATCH 20/20] Override default SConscript options and only build the SimpleCPUs. --HG-- extra : convert_revision : cfcfb787d8442cb76ed766aa5bc947636f067209 --- build_opts/SPARC_FS | 1 + build_opts/SPARC_SE | 1 + 2 files changed, 2 insertions(+) diff --git a/build_opts/SPARC_FS b/build_opts/SPARC_FS index 59d17eee9..7c8bda0ce 100644 --- a/build_opts/SPARC_FS +++ b/build_opts/SPARC_FS @@ -1,2 +1,3 @@ TARGET_ISA = 'sparc' +CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU' FULL_SYSTEM = 1 diff --git a/build_opts/SPARC_SE b/build_opts/SPARC_SE index 3b256fc34..62b6841ad 100644 --- a/build_opts/SPARC_SE +++ b/build_opts/SPARC_SE @@ -1,2 +1,3 @@ TARGET_ISA = 'sparc' +CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU' FULL_SYSTEM = 0