ruby: Fix RubyPort to properly handle retrys
This commit is contained in:
parent
dedb4fbf05
commit
2da54d1285
5 changed files with 55 additions and 4 deletions
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@ -49,6 +49,8 @@ RubyPort::RubyPort(const Params *p)
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m_request_cnt = 0;
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m_request_cnt = 0;
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pio_port = NULL;
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pio_port = NULL;
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physMemPort = NULL;
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physMemPort = NULL;
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m_usingRubyTester = p->using_ruby_tester;
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}
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}
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void
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void
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@ -108,6 +110,7 @@ RubyPort::M5Port::M5Port(const std::string &_name,
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{
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{
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DPRINTF(Ruby, "creating port from ruby sequcner to cpu %s\n", _name);
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DPRINTF(Ruby, "creating port from ruby sequcner to cpu %s\n", _name);
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ruby_port = _port;
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ruby_port = _port;
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_onRetryList = false;
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}
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}
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Tick
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Tick
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@ -256,9 +259,18 @@ RubyPort::M5Port::recvTiming(PacketPtr pkt)
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// Otherwise, we need to delete the senderStatus we just created and return
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// Otherwise, we need to delete the senderStatus we just created and return
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// false.
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// false.
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if (requestStatus == RequestStatus_Issued) {
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if (requestStatus == RequestStatus_Issued) {
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DPRINTF(MemoryAccess, "Request %x issued\n", pkt->getAddr());
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return true;
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return true;
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}
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}
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//
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// Unless one is using the ruby tester, record the stalled M5 port for
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// later retry when the sequencer becomes free.
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//
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if (!ruby_port->m_usingRubyTester) {
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ruby_port->addToRetryList(this);
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}
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DPRINTF(MemoryAccess,
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DPRINTF(MemoryAccess,
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"Request for address %#x did not issue because %s\n",
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"Request for address %#x did not issue because %s\n",
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pkt->getAddr(), RequestStatus_to_string(requestStatus));
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pkt->getAddr(), RequestStatus_to_string(requestStatus));
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@ -283,6 +295,23 @@ RubyPort::ruby_hit_callback(PacketPtr pkt)
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delete senderState;
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delete senderState;
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port->hitCallback(pkt);
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port->hitCallback(pkt);
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//
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// If we had to stall the M5Ports, wake them up because the sequencer
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// likely has free resources now.
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//
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if (waitingOnSequencer) {
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for (std::list<M5Port*>::iterator i = retryList.begin();
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i != retryList.end(); ++i) {
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(*i)->sendRetry();
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(*i)->onRetryList(false);
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DPRINTF(MemoryAccess,
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"Sequencer may now be free. SendRetry to port %s\n",
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(*i)->name());
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}
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retryList.clear();
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waitingOnSequencer = false;
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}
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}
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}
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void
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void
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@ -50,6 +50,7 @@ class RubyPort : public MemObject
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{
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{
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private:
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private:
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RubyPort *ruby_port;
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RubyPort *ruby_port;
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bool _onRetryList;
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public:
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public:
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M5Port(const std::string &_name, RubyPort *_port);
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M5Port(const std::string &_name, RubyPort *_port);
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@ -57,6 +58,12 @@ class RubyPort : public MemObject
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void hitCallback(PacketPtr pkt);
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void hitCallback(PacketPtr pkt);
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unsigned deviceBlockSize() const;
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unsigned deviceBlockSize() const;
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bool onRetryList()
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{ return _onRetryList; }
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void onRetryList(bool newVal)
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{ _onRetryList = newVal; }
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protected:
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protected:
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virtual bool recvTiming(PacketPtr pkt);
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virtual bool recvTiming(PacketPtr pkt);
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virtual Tick recvAtomic(PacketPtr pkt);
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virtual Tick recvAtomic(PacketPtr pkt);
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@ -118,14 +125,32 @@ class RubyPort : public MemObject
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AbstractController* m_controller;
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AbstractController* m_controller;
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MessageBuffer* m_mandatory_q_ptr;
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MessageBuffer* m_mandatory_q_ptr;
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PioPort* pio_port;
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PioPort* pio_port;
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bool m_usingRubyTester;
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private:
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private:
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void addToRetryList(M5Port * port)
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{
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if (!port->onRetryList()) {
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port->onRetryList(true);
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retryList.push_back(port);
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waitingOnSequencer = true;
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}
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}
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uint16_t m_port_id;
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uint16_t m_port_id;
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uint64_t m_request_cnt;
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uint64_t m_request_cnt;
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M5Port* physMemPort;
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M5Port* physMemPort;
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PhysicalMemory* physmem;
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PhysicalMemory* physmem;
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//
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// Based on similar code in the M5 bus. Stores pointers to those ports
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// that should be called when the Sequencer becomes available after a stall.
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//
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std::list<M5Port*> retryList;
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bool waitingOnSequencer;
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};
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};
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#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
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#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
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@ -72,7 +72,6 @@ Sequencer::Sequencer(const Params *p)
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m_dataCache_ptr = p->dcache;
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m_dataCache_ptr = p->dcache;
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m_max_outstanding_requests = p->max_outstanding_requests;
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m_max_outstanding_requests = p->max_outstanding_requests;
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m_deadlock_threshold = p->deadlock_threshold;
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m_deadlock_threshold = p->deadlock_threshold;
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m_usingRubyTester = p->using_ruby_tester;
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assert(m_max_outstanding_requests > 0);
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assert(m_max_outstanding_requests > 0);
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assert(m_deadlock_threshold > 0);
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assert(m_deadlock_threshold > 0);
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@ -152,8 +152,6 @@ class Sequencer : public RubyPort, public Consumer
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int m_load_waiting_on_store_cycles;
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int m_load_waiting_on_store_cycles;
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int m_load_waiting_on_load_cycles;
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int m_load_waiting_on_load_cycles;
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bool m_usingRubyTester;
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class SequencerWakeupEvent : public Event
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class SequencerWakeupEvent : public Event
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{
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{
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private:
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private:
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@ -39,6 +39,7 @@ class RubyPort(MemObject):
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pio_port = Port("Ruby_pio_port")
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pio_port = Port("Ruby_pio_port")
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physmem = Param.PhysicalMemory("")
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physmem = Param.PhysicalMemory("")
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physMemPort = Port("port to physical memory")
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physMemPort = Port("port to physical memory")
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using_ruby_tester = Param.Bool(False, "")
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class RubySequencer(RubyPort):
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class RubySequencer(RubyPort):
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type = 'RubySequencer'
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type = 'RubySequencer'
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@ -49,7 +50,6 @@ class RubySequencer(RubyPort):
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"max requests (incl. prefetches) outstanding")
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"max requests (incl. prefetches) outstanding")
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deadlock_threshold = Param.Int(500000,
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deadlock_threshold = Param.Int(500000,
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"max outstanding cycles for a request before deadlock/livelock declared")
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"max outstanding cycles for a request before deadlock/livelock declared")
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using_ruby_tester = Param.Bool(False, "")
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class DMASequencer(RubyPort):
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class DMASequencer(RubyPort):
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type = 'DMASequencer'
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type = 'DMASequencer'
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