remove the annotation junk
arch/alpha/isa_desc: remove the annotation junk Move some code to AlphaPseudo where it belongs arch/alpha/pseudo_inst.cc: arch/alpha/pseudo_inst.hh: remove the annotation junk add pseudo instruction code that was previously misplaced --HG-- extra : convert_revision : 97db8402aa34e0bdf044b138c52331fc9e714986
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5 changed files with 25 additions and 22 deletions
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@ -1,7 +1,6 @@
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/* $Id$ */
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/* $Id$ */
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#include "targetarch/alpha_memory.hh"
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#include "targetarch/alpha_memory.hh"
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#include "sim/annotation.hh"
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#ifdef DEBUG
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#ifdef DEBUG
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#include "sim/debug.hh"
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#include "sim/debug.hh"
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#endif
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#endif
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@ -126,8 +125,6 @@ ExecContext::ev5_trap(Fault fault)
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regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
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regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
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regs.npc = regs.pc + sizeof(MachInst);
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regs.npc = regs.pc + sizeof(MachInst);
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Annotate::Ev5Trap(this, fault);
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}
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}
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@ -359,7 +356,6 @@ ExecContext::setIpr(int idx, uint64_t val)
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old = ipr[idx];
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old = ipr[idx];
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ipr[idx] = val;
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ipr[idx] = val;
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kernelStats.context(old, val);
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kernelStats.context(old, val);
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Annotate::Context(this);
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break;
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break;
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case AlphaISA::IPR_DTB_PTE:
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case AlphaISA::IPR_DTB_PTE:
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@ -387,11 +383,9 @@ ExecContext::setIpr(int idx, uint64_t val)
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// only write least significant five bits - interrupt level
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// only write least significant five bits - interrupt level
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ipr[idx] = val & 0x1f;
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ipr[idx] = val & 0x1f;
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kernelStats.swpipl(ipr[idx]);
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kernelStats.swpipl(ipr[idx]);
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Annotate::IPL(this, val & 0x1f);
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break;
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break;
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case AlphaISA::IPR_DTB_CM:
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case AlphaISA::IPR_DTB_CM:
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Annotate::ChangeMode(this, (val & 0x18) != 0);
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kernelStats.mode((val & 0x18) != 0);
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kernelStats.mode((val & 0x18) != 0);
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case AlphaISA::IPR_ICM:
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case AlphaISA::IPR_ICM:
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@ -25,7 +25,6 @@ let {{
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#include "cpu/full_cpu/dyn_inst.hh"
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#include "cpu/full_cpu/dyn_inst.hh"
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#include "cpu/simple_cpu/simple_cpu.hh"
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#include "cpu/simple_cpu/simple_cpu.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/static_inst.hh"
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#include "sim/annotation.hh"
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#include "sim/sim_exit.hh"
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#include "sim/sim_exit.hh"
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#ifdef FULL_SYSTEM
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#ifdef FULL_SYSTEM
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@ -2297,8 +2296,6 @@ decode OPCODE default Unknown::unknown() {
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// on this PAL call (including maybe suppress it)
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// on this PAL call (including maybe suppress it)
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dopal = xc->simPalCheck(palFunc);
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dopal = xc->simPalCheck(palFunc);
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Annotate::Callpal(xc->xcBase(), palFunc);
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if (dopal) {
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if (dopal) {
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AlphaISA::swap_palshadow(&xc->xcBase()->regs, true);
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AlphaISA::swap_palshadow(&xc->xcBase()->regs, true);
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xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC);
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xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC);
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@ -2357,24 +2354,20 @@ decode OPCODE default Unknown::unknown() {
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// M5 special opcodes use the reserved 0x01 opcode space
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// M5 special opcodes use the reserved 0x01 opcode space
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0x01: decode M5FUNC {
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0x01: decode M5FUNC {
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0x00: arm({{
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0x00: arm({{
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if (!xc->misspeculating()) {
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if (!xc->misspeculating())
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Annotate::ARM(xc->xcBase());
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AlphaPseudo::arm(xc->xcBase());
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xc->xcBase()->kernelStats.arm();
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}
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}});
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}});
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0x01: quiesce({{
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0x01: quiesce({{
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if (!xc->misspeculating())
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if (!xc->misspeculating())
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AlphaPseudo::quiesce(xc->xcBase());
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AlphaPseudo::quiesce(xc->xcBase());
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}});
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}});
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0x10: ivlb({{
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0x10: ivlb({{
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if (!xc->misspeculating()) {
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if (!xc->misspeculating())
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Annotate::BeginInterval(xc->xcBase());
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AlphaPseudo::ivlb(xc->xcBase());
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xc->xcBase()->kernelStats.ivlb();
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}
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}}, No_OpClass);
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}}, No_OpClass);
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0x11: ivle({{
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0x11: ivle({{
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if (!xc->misspeculating())
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if (!xc->misspeculating())
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Annotate::EndInterval(xc->xcBase());
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AlphaPseudo::ivle(xc->xcBase());
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}}, No_OpClass);
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}}, No_OpClass);
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0x20: m5exit_old({{
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0x20: m5exit_old({{
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if (!xc->misspeculating())
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if (!xc->misspeculating())
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@ -30,7 +30,6 @@
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#include "arch/alpha/pseudo_inst.hh"
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#include "arch/alpha/pseudo_inst.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/exec_context.hh"
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#include "sim/annotation.hh"
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#include "sim/param.hh"
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#include "sim/param.hh"
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#include "sim/serialize.hh"
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#include "sim/serialize.hh"
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#include "sim/sim_exit.hh"
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#include "sim/sim_exit.hh"
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@ -46,17 +45,33 @@ namespace AlphaPseudo
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bool doCheckpointInsts;
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bool doCheckpointInsts;
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bool doQuiesce;
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bool doQuiesce;
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void
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arm(ExecContext *xc)
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{
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xc->kernelStats.arm();
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}
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void
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void
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quiesce(ExecContext *xc)
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quiesce(ExecContext *xc)
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{
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{
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if (!doQuiesce)
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if (!doQuiesce)
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return;
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return;
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Annotate::QUIESCE(xc);
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xc->suspend();
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xc->suspend();
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xc->kernelStats.quiesce();
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xc->kernelStats.quiesce();
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}
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}
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void
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ivlb(ExecContext *xc)
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{
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xc->kernelStats.ivlb();
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}
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void
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ivle(ExecContext *xc)
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{
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}
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void
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void
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m5exit_old(ExecContext *xc)
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m5exit_old(ExecContext *xc)
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{
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{
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@ -37,7 +37,10 @@ namespace AlphaPseudo
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extern bool doCheckpointInsts;
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extern bool doCheckpointInsts;
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extern bool doQuiesce;
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extern bool doQuiesce;
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void arm(ExecContext *xc);
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void quiesce(ExecContext *xc);
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void quiesce(ExecContext *xc);
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void ivlb(ExecContext *xc);
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void ivle(ExecContext *xc);
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void m5exit(ExecContext *xc);
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void m5exit(ExecContext *xc);
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void m5exit_old(ExecContext *xc);
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void m5exit_old(ExecContext *xc);
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void resetstats(ExecContext *xc);
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void resetstats(ExecContext *xc);
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@ -50,7 +50,6 @@
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#include "cpu/static_inst.hh"
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#include "cpu/static_inst.hh"
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#include "mem/base_mem.hh"
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#include "mem/base_mem.hh"
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#include "mem/mem_interface.hh"
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#include "mem/mem_interface.hh"
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#include "sim/annotation.hh"
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#include "sim/builder.hh"
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#include "sim/builder.hh"
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#include "sim/debug.hh"
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#include "sim/debug.hh"
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#include "sim/host.hh"
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#include "sim/host.hh"
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@ -579,7 +578,6 @@ SimpleCPU::post_interrupt(int int_num, int index)
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if (xc->status() == ExecContext::Suspended) {
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if (xc->status() == ExecContext::Suspended) {
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DPRINTF(IPI,"Suspended Processor awoke\n");
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DPRINTF(IPI,"Suspended Processor awoke\n");
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xc->activate();
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xc->activate();
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Annotate::Resume(xc);
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}
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}
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}
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}
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#endif // FULL_SYSTEM
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#endif // FULL_SYSTEM
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