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config: Fix omission of walker cache in config scripts

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This patch ensures a walker cache is instantiated if specfied.

Change-Id: I2c6b4bf3454d56bb19558c73b406e1875acbd986
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>
This commit is contained in:
Andreas Hansson 2016-06-20 14:39:49 +01:00
parent 37bb0d0fb3
commit 2c91ccfbe8
1 changed files with 20 additions and 11 deletions
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29
configs/common/CacheConfig.py
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@ -1,4 +1,4 @@
# Copyright (c) 2012-2013, 2015 ARM Limited # Copyright (c) 2012-2013, 2015-2016 ARM Limited
# All rights reserved # All rights reserved
# #
# The license below extends only to copyright in the software and shall # The license below extends only to copyright in the software and shall
@ -60,11 +60,15 @@ def config_cache(options, system):
print "arm_detailed is unavailable. Did you compile the O3 model?" print "arm_detailed is unavailable. Did you compile the O3 model?"
sys.exit(1) sys.exit(1)
dcache_class, icache_class, l2_cache_class = \ dcache_class, icache_class, l2_cache_class, walk_cache_class = \
O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2 O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, \
O3_ARM_v7aWalkCache
else: else:
dcache_class, icache_class, l2_cache_class = \ dcache_class, icache_class, l2_cache_class, walk_cache_class = \
L1_DCache, L1_ICache, L2Cache L1_DCache, L1_ICache, L2Cache, None
if buildEnv['TARGET_ISA'] == 'x86':
walk_cache_class = PageTableWalkerCache
# Set the cache line size of the system # Set the cache line size of the system
system.cache_line_size = options.cacheline_size system.cache_line_size = options.cacheline_size
@ -98,6 +102,15 @@ def config_cache(options, system):
dcache = dcache_class(size=options.l1d_size, dcache = dcache_class(size=options.l1d_size,
assoc=options.l1d_assoc) assoc=options.l1d_assoc)
# If we have a walker cache specified, instantiate two
# instances here
if walk_cache_class:
iwalkcache = walk_cache_class()
dwalkcache = walk_cache_class()
else:
iwalkcache = None
dwalkcache = None
if options.memchecker: if options.memchecker:
dcache_mon = MemCheckerMonitor(warn_only=True) dcache_mon = MemCheckerMonitor(warn_only=True)
dcache_real = dcache dcache_real = dcache
@ -115,12 +128,8 @@ def config_cache(options, system):
# When connecting the caches, the clock is also inherited # When connecting the caches, the clock is also inherited
# from the CPU in question # from the CPU in question
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].addPrivateSplitL1Caches(icache, dcache, system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
PageTableWalkerCache(), iwalkcache, dwalkcache)
PageTableWalkerCache())
else:
system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
if options.memchecker: if options.memchecker:
# The mem_side ports of the caches haven't been connected yet. # The mem_side ports of the caches haven't been connected yet.