build: fix compile problems pointed out by gcc 4.4
This commit is contained in:
parent
fbfe92b5b8
commit
2c5fe6f95e
22 changed files with 64 additions and 43 deletions
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@ -29,6 +29,7 @@
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#include "arch/arm/insts/static_inst.hh"
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#include "arch/arm/insts/static_inst.hh"
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#include "base/condcodes.hh"
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#include "base/condcodes.hh"
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#include "base/cprintf.hh"
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#include "base/loader/symtab.hh"
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#include "base/loader/symtab.hh"
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namespace ArmISA
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namespace ArmISA
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@ -62,7 +63,7 @@ ArmStaticInst::shift_rm_imm(uint32_t base, uint32_t shamt,
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else
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else
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return (base << (32 - shamt)) | (base >> shamt);
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return (base << (32 - shamt)) | (base >> shamt);
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default:
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default:
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fprintf(stderr, "Unhandled shift type\n");
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ccprintf(std::cerr, "Unhandled shift type\n");
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exit(1);
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exit(1);
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break;
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break;
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}
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}
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@ -101,7 +102,7 @@ ArmStaticInst::shift_rm_rs(uint32_t base, uint32_t shamt,
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else
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else
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return (base << (32 - shamt)) | (base >> shamt);
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return (base << (32 - shamt)) | (base >> shamt);
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default:
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default:
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fprintf(stderr, "Unhandled shift type\n");
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ccprintf(std::cerr, "Unhandled shift type\n");
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exit(1);
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exit(1);
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break;
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break;
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}
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}
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@ -141,7 +142,7 @@ ArmStaticInst::shift_carry_imm(uint32_t base, uint32_t shamt,
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else
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else
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return (base >> (shamt - 1)) & 1;
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return (base >> (shamt - 1)) & 1;
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default:
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default:
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fprintf(stderr, "Unhandled shift type\n");
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ccprintf(std::cerr, "Unhandled shift type\n");
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exit(1);
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exit(1);
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break;
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break;
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}
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}
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@ -182,7 +183,7 @@ ArmStaticInst::shift_carry_rs(uint32_t base, uint32_t shamt,
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shamt = 32;
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shamt = 32;
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return (base >> (shamt - 1)) & 1;
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return (base >> (shamt - 1)) & 1;
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default:
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default:
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fprintf(stderr, "Unhandled shift type\n");
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ccprintf(std::cerr, "Unhandled shift type\n");
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exit(1);
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exit(1);
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break;
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break;
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}
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}
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@ -463,6 +463,8 @@ MipsISA::dspMuleq(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl)
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uint64_t b_values[SIMD_MAX_VALS];
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uint64_t b_values[SIMD_MAX_VALS];
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uint64_t c_values[SIMD_MAX_VALS];
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uint64_t c_values[SIMD_MAX_VALS];
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memset(c_values, 0, sizeof(c_values));
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simdUnpack(a, a_values, SIMD_FMT_PH, SIGNED);
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simdUnpack(a, a_values, SIMD_FMT_PH, SIGNED);
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simdUnpack(b, b_values, SIMD_FMT_PH, SIGNED);
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simdUnpack(b, b_values, SIMD_FMT_PH, SIGNED);
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@ -743,7 +745,7 @@ MipsISA::dspMulsaq(int64_t dspac, int32_t a, int32_t b, int32_t ac,
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int nvals = SIMD_NVALS[fmt];
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int nvals = SIMD_NVALS[fmt];
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uint64_t a_values[SIMD_MAX_VALS];
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uint64_t a_values[SIMD_MAX_VALS];
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uint64_t b_values[SIMD_MAX_VALS];
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uint64_t b_values[SIMD_MAX_VALS];
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int64_t temp[2];
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int64_t temp[2] = {0, 0};
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uint32_t ouflag = 0;
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uint32_t ouflag = 0;
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simdUnpack(a, a_values, fmt, SIGNED);
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simdUnpack(a, a_values, fmt, SIGNED);
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@ -500,7 +500,7 @@ X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
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InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
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InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
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// Record that an IPI is being sent.
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// Record that an IPI is being sent.
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low.deliveryStatus = 1;
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low.deliveryStatus = 1;
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TriggerIntMessage message;
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TriggerIntMessage message = 0;
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message.destination = high.destination;
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message.destination = high.destination;
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message.vector = low.vector;
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message.vector = low.vector;
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message.deliveryMode = low.deliveryMode;
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message.deliveryMode = low.deliveryMode;
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@ -41,7 +41,7 @@ void
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ISA::updateHandyM5Reg(Efer efer, CR0 cr0,
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ISA::updateHandyM5Reg(Efer efer, CR0 cr0,
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SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags)
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SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags)
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{
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{
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HandyM5Reg m5reg;
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HandyM5Reg m5reg = 0;
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if (efer.lma) {
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if (efer.lma) {
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m5reg.mode = LongMode;
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m5reg.mode = LongMode;
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if (csAttr.longMode)
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if (csAttr.longMode)
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@ -211,7 +211,7 @@ X86System::startup()
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numGDTEntries++;
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numGDTEntries++;
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SegSelector ds;
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SegSelector ds = 0;
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ds.si = numGDTEntries - 1;
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ds.si = numGDTEntries - 1;
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tc->setMiscReg(MISCREG_DS, (MiscReg)ds);
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tc->setMiscReg(MISCREG_DS, (MiscReg)ds);
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@ -28,10 +28,10 @@
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* Authors: Gabe Black
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* Authors: Gabe Black
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*/
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*/
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#include "base/bigint.hh"
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#include <iostream>
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#include <iostream>
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#include "base/bigint.hh"
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using namespace std;
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using namespace std;
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ostream & operator << (ostream & os, const Twin64_t & t)
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ostream & operator << (ostream & os, const Twin64_t & t)
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@ -28,10 +28,11 @@
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* Authors: Ali Saidi
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* Authors: Ali Saidi
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*/
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*/
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#include "base/misc.hh"
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#include <iostream>
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#include <iostream>
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#include "base/misc.hh"
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#include "base/types.hh"
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#ifndef __BASE_BIGINT_HH__
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#ifndef __BASE_BIGINT_HH__
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#define __BASE_BIGINT_HH__
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#define __BASE_BIGINT_HH__
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// Create a couple of large int types for atomic reads
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// Create a couple of large int types for atomic reads
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@ -28,6 +28,7 @@
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* Authors: Nathan Binkert
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* Authors: Nathan Binkert
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*/
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*/
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#include <cstdio>
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#include <sstream>
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#include <sstream>
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#include <string>
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#include <string>
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@ -118,6 +118,7 @@
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#include <sys/signal.h>
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#include <sys/signal.h>
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#include <cstdio>
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#include <string>
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#include <string>
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#include <unistd.h>
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#include <unistd.h>
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@ -55,6 +55,7 @@ typedef int64_t Counter;
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* @note using an unsigned breaks the cache.
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* @note using an unsigned breaks the cache.
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*/
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*/
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typedef int64_t Tick;
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typedef int64_t Tick;
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typedef uint64_t UTick;
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const Tick MaxTick = LL(0x7fffffffffffffff);
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const Tick MaxTick = LL(0x7fffffffffffffff);
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@ -36,6 +36,7 @@
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#include <list>
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#include <list>
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#include <string>
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#include <string>
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#include "base/types.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/inorder/inorder_dyn_inst.hh"
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#include "cpu/inorder/inorder_dyn_inst.hh"
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#include "cpu/inorder/pipeline_traits.hh"
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#include "cpu/inorder/pipeline_traits.hh"
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@ -32,6 +32,8 @@
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#ifndef __STD_TYPES_HH__
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#ifndef __STD_TYPES_HH__
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#define __STD_TYPES_HH__
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#define __STD_TYPES_HH__
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#include "base/types.hh"
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// inst sequence type, used to order instructions in the ready list,
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// inst sequence type, used to order instructions in the ready list,
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// if this rolls over the ready list order temporarily will get messed
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// if this rolls over the ready list order temporarily will get messed
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// up, but execution will continue and complete correctly
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// up, but execution will continue and complete correctly
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@ -41,10 +41,12 @@
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#error Legion tracing only works in full system!
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#error Legion tracing only works in full system!
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#endif
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#endif
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#include <iomanip>
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#include <sys/ipc.h>
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#include <sys/ipc.h>
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#include <sys/shm.h>
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#include <sys/shm.h>
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#include <cstdio>
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#include <iomanip>
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#include "arch/sparc/predecoder.hh"
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#include "arch/sparc/predecoder.hh"
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#include "arch/sparc/registers.hh"
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#include "arch/sparc/registers.hh"
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#include "arch/sparc/utility.hh"
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#include "arch/sparc/utility.hh"
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@ -90,20 +90,18 @@ void
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Iob::readIob(PacketPtr pkt)
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Iob::readIob(PacketPtr pkt)
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{
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{
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Addr accessAddr = pkt->getAddr() - iobManAddr;
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Addr accessAddr = pkt->getAddr() - iobManAddr;
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int index;
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uint64_t data;
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if (accessAddr >= IntManAddr && accessAddr < IntManAddr + IntManSize) {
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if (accessAddr >= IntManAddr && accessAddr < IntManAddr + IntManSize) {
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index = (accessAddr - IntManAddr) >> 3;
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int index = (accessAddr - IntManAddr) >> 3;
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data = intMan[index].cpu << 8 | intMan[index].vector << 0;
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uint64_t data = intMan[index].cpu << 8 | intMan[index].vector << 0;
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pkt->set(data);
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pkt->set(data);
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return;
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return;
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}
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}
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if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) {
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if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) {
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index = (accessAddr - IntManAddr) >> 3;
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int index = (accessAddr - IntCtlAddr) >> 3;
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data = intCtl[index].mask ? 1 << 2 : 0 |
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uint64_t data = intCtl[index].mask ? 1 << 2 : 0 |
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intCtl[index].pend ? 1 << 0 : 0;
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intCtl[index].pend ? 1 << 0 : 0;
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pkt->set(data);
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pkt->set(data);
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return;
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return;
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}
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}
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@ -199,7 +197,7 @@ Iob::writeIob(PacketPtr pkt)
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}
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}
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if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) {
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if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) {
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index = (accessAddr - IntManAddr) >> 3;
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index = (accessAddr - IntCtlAddr) >> 3;
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data = pkt->get<uint64_t>();
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data = pkt->get<uint64_t>();
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intCtl[index].mask = bits(data,2,2);
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intCtl[index].mask = bits(data,2,2);
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if (bits(data,1,1))
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if (bits(data,1,1))
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@ -151,7 +151,7 @@ X86ISA::I82094AA::signalInterrupt(int line)
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DPRINTF(I82094AA, "Entry was masked.\n");
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DPRINTF(I82094AA, "Entry was masked.\n");
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return;
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return;
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} else {
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} else {
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TriggerIntMessage message;
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TriggerIntMessage message = 0;
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message.destination = entry.dest;
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message.destination = entry.dest;
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if (entry.deliveryMode == DeliveryMode::ExtInt) {
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if (entry.deliveryMode == DeliveryMode::ExtInt) {
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assert(extIntPic);
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assert(extIntPic);
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@ -28,6 +28,7 @@
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* Authors: Ali Saidi
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* Authors: Ali Saidi
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*/
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*/
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#include <cstdio>
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#include <string>
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#include <string>
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#include "cpu/thread_context.hh"
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#include "cpu/thread_context.hh"
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#include <unistd.h>
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#include <unistd.h>
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#include <zlib.h>
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#include <zlib.h>
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#include <cstdio>
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#include <iostream>
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#include <iostream>
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#include <string>
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#include <string>
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@ -148,7 +148,7 @@ inline
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physical_address_t Address::bitSelect(int small, int big) const // rips bits inclusive
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physical_address_t Address::bitSelect(int small, int big) const // rips bits inclusive
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{
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{
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physical_address_t mask;
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physical_address_t mask;
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assert(big >= small);
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assert((unsigned)big >= (unsigned)small);
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if (big >= ADDRESS_WIDTH - 1) {
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if (big >= ADDRESS_WIDTH - 1) {
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return (m_address >> small);
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return (m_address >> small);
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@ -30,6 +30,7 @@
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#include <cmath>
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#include <cmath>
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#include <cstdio>
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#include <cstdio>
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#include "base/types.hh"
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#include "mem/ruby/network/orion/parm_technology.hh"
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#include "mem/ruby/network/orion/parm_technology.hh"
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#include "mem/ruby/network/orion/power_utils.hh"
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#include "mem/ruby/network/orion/power_utils.hh"
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static char h_tab[256] = {0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8};
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static char h_tab[256] = {0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8};
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static unsigned SIM_power_Hamming_slow( unsigned long int old_val, unsigned long int new_val, unsigned long int mask )
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static uint32_t SIM_power_Hamming_slow( uint64_t old_val, uint64_t new_val, uint64_t mask )
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{
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{
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/* old slow code, I don't understand the new fast code though */
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/* old slow code, I don't understand the new fast code though */
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/* unsigned long int dist;
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/* uint64_t dist;
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unsigned Hamming = 0;
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uint32_t Hamming = 0;
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dist = ( old_val ^ new_val ) & mask;
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dist = ( old_val ^ new_val ) & mask;
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mask = (mask >> 1) + 1;
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mask = (mask >> 1) + 1;
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@ -58,7 +59,7 @@ static unsigned SIM_power_Hamming_slow( unsigned long int old_val, unsigned long
|
||||||
#define TWO(k) (BIGONE << (k))
|
#define TWO(k) (BIGONE << (k))
|
||||||
#define CYCL(k) (BIGNONE/(1 + (TWO(TWO(k)))))
|
#define CYCL(k) (BIGNONE/(1 + (TWO(TWO(k)))))
|
||||||
#define BSUM(x,k) ((x)+=(x) >> TWO(k), (x) &= CYCL(k))
|
#define BSUM(x,k) ((x)+=(x) >> TWO(k), (x) &= CYCL(k))
|
||||||
unsigned long int x;
|
uint64_t x;
|
||||||
|
|
||||||
x = (old_val ^ new_val) & mask;
|
x = (old_val ^ new_val) & mask;
|
||||||
x = (x & CYCL(0)) + ((x>>TWO(0)) & CYCL(0));
|
x = (x & CYCL(0)) + ((x>>TWO(0)) & CYCL(0));
|
||||||
|
@ -74,7 +75,7 @@ static unsigned SIM_power_Hamming_slow( unsigned long int old_val, unsigned long
|
||||||
|
|
||||||
int SIM_power_init(void)
|
int SIM_power_init(void)
|
||||||
{
|
{
|
||||||
unsigned i;
|
uint32_t i;
|
||||||
|
|
||||||
/* initialize Hamming distance table */
|
/* initialize Hamming distance table */
|
||||||
for (i = 0; i < 256; i++)
|
for (i = 0; i < 256; i++)
|
||||||
|
@ -84,14 +85,16 @@ int SIM_power_init(void)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/* assume unsigned long int is unsigned64_t */
|
|
||||||
unsigned SIM_power_Hamming(unsigned long int old_val, unsigned long int new_val, unsigned long int mask)
|
uint32_t
|
||||||
|
SIM_power_Hamming(uint64_t old_val, uint64_t new_val, uint64_t mask)
|
||||||
{
|
{
|
||||||
union {
|
union {
|
||||||
unsigned long int x;
|
uint64_t x;
|
||||||
char id[8];
|
uint64_t id[8];
|
||||||
} u;
|
} u;
|
||||||
unsigned rval;
|
|
||||||
|
uint32_t rval;
|
||||||
|
|
||||||
u.x = (old_val ^ new_val) & mask;
|
u.x = (old_val ^ new_val) & mask;
|
||||||
|
|
||||||
|
@ -108,10 +111,12 @@ unsigned SIM_power_Hamming(unsigned long int old_val, unsigned long int new_val,
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
unsigned SIM_power_Hamming_group(unsigned long int d1_new, unsigned long int d1_old, unsigned long int d2_new, unsigned long int d2_old, unsigned width, unsigned n_grp)
|
uint32_t
|
||||||
|
SIM_power_Hamming_group(uint64_t d1_new, uint64_t d1_old, uint64_t d2_new,
|
||||||
|
uint64_t d2_old, uint32_t width, uint32_t n_grp)
|
||||||
{
|
{
|
||||||
unsigned rval = 0;
|
uint32_t rval = 0;
|
||||||
unsigned long int g1_new, g1_old, g2_new, g2_old, mask;
|
uint64_t g1_new, g1_old, g2_new, g2_old, mask;
|
||||||
|
|
||||||
mask = HAMM_MASK(width);
|
mask = HAMM_MASK(width);
|
||||||
|
|
||||||
|
@ -146,11 +151,12 @@ double logtwo(double x)
|
||||||
return log10(x)/log10(2);
|
return log10(x)/log10(2);
|
||||||
}
|
}
|
||||||
|
|
||||||
unsigned SIM_power_logtwo(unsigned long int x)
|
uint32_t
|
||||||
|
SIM_power_logtwo(uint64_t x)
|
||||||
{
|
{
|
||||||
unsigned rval = 0;
|
uint32_t rval = 0;
|
||||||
|
|
||||||
while (x >> rval && rval < sizeof(unsigned long int) << 3) rval++;
|
while (x >> rval && rval < sizeof(uint64_t) << 3) rval++;
|
||||||
if (x == (BIGONE << rval - 1)) rval--;
|
if (x == (BIGONE << rval - 1)) rval--;
|
||||||
|
|
||||||
return rval;
|
return rval;
|
||||||
|
|
|
@ -471,7 +471,7 @@ class EventWrapper : public Event
|
||||||
inline void
|
inline void
|
||||||
EventQueue::schedule(Event *event, Tick when)
|
EventQueue::schedule(Event *event, Tick when)
|
||||||
{
|
{
|
||||||
assert(when >= curTick);
|
assert((UTick)when >= (UTick)curTick);
|
||||||
assert(!event->scheduled());
|
assert(!event->scheduled());
|
||||||
#ifdef EVENTQ_DEBUG
|
#ifdef EVENTQ_DEBUG
|
||||||
assert((event->flags & Event::Initialized) == Event::Initialized);
|
assert((event->flags & Event::Initialized) == Event::Initialized);
|
||||||
|
|
|
@ -32,6 +32,8 @@
|
||||||
|
|
||||||
#include <unistd.h>
|
#include <unistd.h>
|
||||||
#include <fcntl.h>
|
#include <fcntl.h>
|
||||||
|
|
||||||
|
#include <cstdio>
|
||||||
#include <string>
|
#include <string>
|
||||||
|
|
||||||
#include "arch/remote_gdb.hh"
|
#include "arch/remote_gdb.hh"
|
||||||
|
|
|
@ -32,8 +32,9 @@
|
||||||
#include <fcntl.h>
|
#include <fcntl.h>
|
||||||
#include <unistd.h>
|
#include <unistd.h>
|
||||||
|
|
||||||
#include <string>
|
#include <cstdio>
|
||||||
#include <iostream>
|
#include <iostream>
|
||||||
|
#include <string>
|
||||||
|
|
||||||
#include "sim/syscall_emul.hh"
|
#include "sim/syscall_emul.hh"
|
||||||
#include "base/chunk_generator.hh"
|
#include "base/chunk_generator.hh"
|
||||||
|
|
Loading…
Reference in a new issue