Shuffle around device names to make things easier to read.

Create EtherDevBase which both Sinic and NSGigE derive from
bump fifos
drop rx max copy size to 1514 bytes to be friendlier with linux
default interrupt delay is 10us

dev/ns_gige.cc:
    Shuffle around parameters to make it easier to find stuff
dev/sinic.cc:
    Shuffle around parameters to make it easier to find stuff
    rename cycleTime -> clock
dev/sinic.hh:
    rename cycleTime -> clock

--HG--
extra : convert_revision : a673bee875e50d083098991aea20972fa8d5b5c7

dev/ns_gige.cc

@@ -2984,69 +2984,77 @@ REGISTER_SIM_OBJECT("NSGigEInt", NSGigEInt)
 
 BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
 
-    Param<Addr> addr;
     Param<Tick> clock;
-    Param<Tick> tx_delay;
+
-    Param<Tick> rx_delay;
+    Param<Addr> addr;
-    Param<Tick> intr_delay;
     SimObjectParam<MemoryController *> mmu;
     SimObjectParam<PhysicalMemory *> physmem;
-    Param<bool> rx_filter;
-    Param<string> hardware_address;
-    SimObjectParam<Bus*> io_bus;
-    SimObjectParam<Bus*> payload_bus;
-    SimObjectParam<HierParams *> hier;
-    Param<Tick> pio_latency;
-    Param<bool> dma_desc_free;
-    Param<bool> dma_data_free;
-    Param<Tick> dma_read_delay;
-    Param<Tick> dma_write_delay;
-    Param<Tick> dma_read_factor;
-    Param<Tick> dma_write_factor;
     SimObjectParam<PciConfigAll *> configspace;
     SimObjectParam<PciConfigData *> configdata;
     SimObjectParam<Platform *> platform;
     Param<uint32_t> pci_bus;
     Param<uint32_t> pci_dev;
     Param<uint32_t> pci_func;
-    Param<uint32_t> tx_fifo_size;
+
-    Param<uint32_t> rx_fifo_size;
+    SimObjectParam<HierParams *> hier;
-    Param<bool> dedicated;
+    SimObjectParam<Bus*> io_bus;
+    SimObjectParam<Bus*> payload_bus;
+    Param<bool> dma_desc_free;
+    Param<bool> dma_data_free;
+    Param<Tick> dma_read_delay;
+    Param<Tick> dma_write_delay;
+    Param<Tick> dma_read_factor;
+    Param<Tick> dma_write_factor;
     Param<bool> dma_no_allocate;
+    Param<Tick> pio_latency;
+    Param<Tick> intr_delay;
+
+    Param<Tick> rx_delay;
+    Param<Tick> tx_delay;
+    Param<uint32_t> rx_fifo_size;
+    Param<uint32_t> tx_fifo_size;
+
+    Param<bool> rx_filter;
+    Param<string> hardware_address;
+    Param<bool> dedicated;
 
 END_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
 
 BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
 
-    INIT_PARAM(addr, "Device Address"),
     INIT_PARAM(clock, "State machine processor frequency"),
-    INIT_PARAM(tx_delay, "Transmit Delay"),
+
-    INIT_PARAM(rx_delay, "Receive Delay"),
+    INIT_PARAM(addr, "Device Address"),
-    INIT_PARAM(intr_delay, "Interrupt Delay in microseconds"),
     INIT_PARAM(mmu, "Memory Controller"),
     INIT_PARAM(physmem, "Physical Memory"),
-    INIT_PARAM_DFLT(rx_filter, "Enable Receive Filter", true),
-    INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
-    INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to for headers", NULL),
-    INIT_PARAM_DFLT(payload_bus, "The IO Bus to attach to for payload", NULL),
-    INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams),
-    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
-    INIT_PARAM_DFLT(dma_desc_free, "DMA of Descriptors is free", false),
-    INIT_PARAM_DFLT(dma_data_free, "DMA of Data is free", false),
-    INIT_PARAM_DFLT(dma_read_delay, "fixed delay for dma reads", 0),
-    INIT_PARAM_DFLT(dma_write_delay, "fixed delay for dma writes", 0),
-    INIT_PARAM_DFLT(dma_read_factor, "multiplier for dma reads", 0),
-    INIT_PARAM_DFLT(dma_write_factor, "multiplier for dma writes", 0),
     INIT_PARAM(configspace, "PCI Configspace"),
     INIT_PARAM(configdata, "PCI Config data"),
     INIT_PARAM(platform, "Platform"),
     INIT_PARAM(pci_bus, "PCI bus"),
     INIT_PARAM(pci_dev, "PCI device number"),
     INIT_PARAM(pci_func, "PCI function code"),
-    INIT_PARAM_DFLT(tx_fifo_size, "max size in bytes of txFifo", 131072),
+
-    INIT_PARAM_DFLT(rx_fifo_size, "max size in bytes of rxFifo", 131072),
+    INIT_PARAM(hier, "Hierarchy global variables"),
-    INIT_PARAM(dedicated, "dedicate a kernel thread to the driver"),
+    INIT_PARAM(io_bus, "The IO Bus to attach to for headers"),
-    INIT_PARAM_DFLT(dma_no_allocate, "Should DMA reads allocate cache lines", true)
+    INIT_PARAM(payload_bus, "The IO Bus to attach to for payload"),
+    INIT_PARAM(dma_desc_free, "DMA of Descriptors is free"),
+    INIT_PARAM(dma_data_free, "DMA of Data is free"),
+    INIT_PARAM(dma_read_delay, "fixed delay for dma reads"),
+    INIT_PARAM(dma_write_delay, "fixed delay for dma writes"),
+    INIT_PARAM(dma_read_factor, "multiplier for dma reads"),
+    INIT_PARAM(dma_write_factor, "multiplier for dma writes"),
+    INIT_PARAM(dma_no_allocate, "Should DMA reads allocate cache lines"),
+    INIT_PARAM(pio_latency, "Programmed IO latency in bus cycles"),
+    INIT_PARAM(intr_delay, "Interrupt Delay in microseconds"),
+
+    INIT_PARAM(rx_delay, "Receive Delay"),
+    INIT_PARAM(tx_delay, "Transmit Delay"),
+    INIT_PARAM(rx_fifo_size, "max size in bytes of rxFifo"),
+    INIT_PARAM(tx_fifo_size, "max size in bytes of txFifo"),
+
+    INIT_PARAM(rx_filter, "Enable Receive Filter"),
+    INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
+    INIT_PARAM(dedicated, "dedicate a kernel thread to the driver")
 
 END_INIT_SIM_OBJECT_PARAMS(NSGigE)
 
@@ -3056,7 +3064,11 @@ CREATE_SIM_OBJECT(NSGigE)
     NSGigE::Params *params = new NSGigE::Params;
 
     params->name = getInstanceName();
+
+    params->clock = clock;
+
     params->mmu = mmu;
+    params->pmem = physmem;
     params->configSpace = configspace;
     params->configData = configdata;
     params->plat = platform;
@@ -3064,27 +3076,28 @@ CREATE_SIM_OBJECT(NSGigE)
     params->deviceNum = pci_dev;
     params->functionNum = pci_func;
 
-    params->clock = clock;
-    params->intr_delay = intr_delay;
-    params->pmem = physmem;
-    params->tx_delay = tx_delay;
-    params->rx_delay = rx_delay;
     params->hier = hier;
     params->header_bus = io_bus;
     params->payload_bus = payload_bus;
-    params->pio_latency = pio_latency;
     params->dma_desc_free = dma_desc_free;
     params->dma_data_free = dma_data_free;
     params->dma_read_delay = dma_read_delay;
     params->dma_write_delay = dma_write_delay;
     params->dma_read_factor = dma_read_factor;
     params->dma_write_factor = dma_write_factor;
+    params->dma_no_allocate = dma_no_allocate;
+    params->pio_latency = pio_latency;
+    params->intr_delay = intr_delay;
+
+    params->rx_delay = rx_delay;
+    params->tx_delay = tx_delay;
+    params->rx_fifo_size = rx_fifo_size;
+    params->tx_fifo_size = tx_fifo_size;
+
     params->rx_filter = rx_filter;
     params->eaddr = hardware_address;
-    params->tx_fifo_size = tx_fifo_size;
-    params->rx_fifo_size = rx_fifo_size;
     params->dedicated = dedicated;
-    params->dma_no_allocate = dma_no_allocate;
+
     return new NSGigE(params);
 }
 

dev/sinic.cc

@@ -77,7 +77,7 @@ const char *TxStateStrings[] =
 // Sinic PCI Device
 //
 Base::Base(Params *p)
-    : PciDev(p), rxEnable(false), txEnable(false), cycleTime(p->cycle_time),
+    : PciDev(p), rxEnable(false), txEnable(false), clock(p->clock),
       intrDelay(p->intr_delay), intrTick(0), cpuIntrEnable(false),
       cpuPendingIntr(false), intrEvent(0), interface(NULL)
 {
@@ -1360,71 +1360,79 @@ REGISTER_SIM_OBJECT("SinicInt", Interface)
 
 BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
 
+    Param<Tick> clock;
+
     Param<Addr> addr;
-    Param<Tick> cycle_time;
-    Param<Tick> tx_delay;
-    Param<Tick> rx_delay;
-    Param<Tick> intr_delay;
     SimObjectParam<MemoryController *> mmu;
     SimObjectParam<PhysicalMemory *> physmem;
-    Param<bool> rx_filter;
-    Param<string> hardware_address;
-    SimObjectParam<Bus*> io_bus;
-    SimObjectParam<Bus*> payload_bus;
-    SimObjectParam<HierParams *> hier;
-    Param<Tick> pio_latency;
     SimObjectParam<PciConfigAll *> configspace;
     SimObjectParam<PciConfigData *> configdata;
     SimObjectParam<Platform *> platform;
     Param<uint32_t> pci_bus;
     Param<uint32_t> pci_dev;
     Param<uint32_t> pci_func;
+
+    SimObjectParam<HierParams *> hier;
+    SimObjectParam<Bus*> io_bus;
+    SimObjectParam<Bus*> payload_bus;
+    Param<Tick> dma_read_delay;
+    Param<Tick> dma_read_factor;
+    Param<Tick> dma_write_delay;
+    Param<Tick> dma_write_factor;
+    Param<bool> dma_no_allocate;
+    Param<Tick> pio_latency;
+    Param<Tick> intr_delay;
+
+    Param<Tick> rx_delay;
+    Param<Tick> tx_delay;
     Param<uint32_t> rx_max_copy;
     Param<uint32_t> tx_max_copy;
     Param<uint32_t> rx_fifo_size;
     Param<uint32_t> tx_fifo_size;
     Param<uint32_t> rx_fifo_threshold;
     Param<uint32_t> tx_fifo_threshold;
-    Param<Tick> dma_read_delay;
+
-    Param<Tick> dma_read_factor;
+    Param<bool> rx_filter;
-    Param<Tick> dma_write_delay;
+    Param<string> hardware_address;
-    Param<Tick> dma_write_factor;
-    Param<bool> dma_no_allocate;
 
 END_DECLARE_SIM_OBJECT_PARAMS(Device)
 
 BEGIN_INIT_SIM_OBJECT_PARAMS(Device)
 
+    INIT_PARAM(clock, "State machine cycle time"),
+
     INIT_PARAM(addr, "Device Address"),
-    INIT_PARAM(cycle_time, "State machine cycle time"),
-    INIT_PARAM_DFLT(tx_delay, "Transmit Delay", 1000),
-    INIT_PARAM_DFLT(rx_delay, "Receive Delay", 1000),
-    INIT_PARAM_DFLT(intr_delay, "Interrupt Delay in microseconds", 0),
     INIT_PARAM(mmu, "Memory Controller"),
     INIT_PARAM(physmem, "Physical Memory"),
-    INIT_PARAM_DFLT(rx_filter, "Enable Receive Filter", true),
-    INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
-    INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to for headers", NULL),
-    INIT_PARAM_DFLT(payload_bus, "The IO Bus to attach to for payload", NULL),
-    INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams),
-    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
     INIT_PARAM(configspace, "PCI Configspace"),
     INIT_PARAM(configdata, "PCI Config data"),
     INIT_PARAM(platform, "Platform"),
     INIT_PARAM(pci_bus, "PCI bus"),
     INIT_PARAM(pci_dev, "PCI device number"),
     INIT_PARAM(pci_func, "PCI function code"),
-    INIT_PARAM_DFLT(rx_max_copy, "rx max copy", 16*1024),
+
-    INIT_PARAM_DFLT(tx_max_copy, "rx max copy", 16*1024),
+    INIT_PARAM(hier, "Hierarchy global variables"),
-    INIT_PARAM_DFLT(rx_fifo_size, "max size in bytes of rxFifo", 64*1024),
+    INIT_PARAM(io_bus, "The IO Bus to attach to for headers"),
-    INIT_PARAM_DFLT(tx_fifo_size, "max size in bytes of txFifo", 64*1024),
+    INIT_PARAM(payload_bus, "The IO Bus to attach to for payload"),
-    INIT_PARAM_DFLT(rx_fifo_threshold, "max size in bytes of rxFifo", 48*1024),
+    INIT_PARAM(dma_read_delay, "fixed delay for dma reads"),
-    INIT_PARAM_DFLT(tx_fifo_threshold, "max size in bytes of txFifo", 16*1024),
+    INIT_PARAM(dma_read_factor, "multiplier for dma reads"),
-    INIT_PARAM_DFLT(dma_read_delay, "fixed delay for dma reads", 0),
+    INIT_PARAM(dma_write_delay, "fixed delay for dma writes"),
-    INIT_PARAM_DFLT(dma_read_factor, "multiplier for dma reads", 0),
+    INIT_PARAM(dma_write_factor, "multiplier for dma writes"),
-    INIT_PARAM_DFLT(dma_write_delay, "fixed delay for dma writes", 0),
+    INIT_PARAM(dma_no_allocate, "Should we allocat on read in cache"),
-    INIT_PARAM_DFLT(dma_write_factor, "multiplier for dma writes", 0),
+    INIT_PARAM(pio_latency, "Programmed IO latency in bus cycles"),
-    INIT_PARAM_DFLT(dma_no_allocate, "Should we allocat on read in cache", true)
+    INIT_PARAM(intr_delay, "Interrupt Delay"),
+
+    INIT_PARAM(rx_delay, "Receive Delay"),
+    INIT_PARAM(tx_delay, "Transmit Delay"),
+    INIT_PARAM(rx_max_copy, "rx max copy"),
+    INIT_PARAM(tx_max_copy, "rx max copy"),
+    INIT_PARAM(rx_fifo_size, "max size in bytes of rxFifo"),
+    INIT_PARAM(tx_fifo_size, "max size in bytes of txFifo"),
+    INIT_PARAM(rx_fifo_threshold, "max size in bytes of rxFifo"),
+    INIT_PARAM(tx_fifo_threshold, "max size in bytes of txFifo"),
+
+    INIT_PARAM(rx_filter, "Enable Receive Filter"),
+    INIT_PARAM(hardware_address, "Ethernet Hardware Address")
 
 END_INIT_SIM_OBJECT_PARAMS(Device)
 
@@ -1432,36 +1440,42 @@ END_INIT_SIM_OBJECT_PARAMS(Device)
 CREATE_SIM_OBJECT(Device)
 {
     Device::Params *params = new Device::Params;
+
     params->name = getInstanceName();
-    params->intr_delay = intr_delay;
+
-    params->physmem = physmem;
+    params->clock = clock;
-    params->cycle_time = cycle_time;
-    params->tx_delay = tx_delay;
-    params->rx_delay = rx_delay;
     params->mmu = mmu;
-    params->hier = hier;
+    params->physmem = physmem;
-    params->io_bus = io_bus;
-    params->payload_bus = payload_bus;
-    params->pio_latency = pio_latency;
     params->configSpace = configspace;
     params->configData = configdata;
     params->plat = platform;
     params->busNum = pci_bus;
     params->deviceNum = pci_dev;
     params->functionNum = pci_func;
-    params->rx_filter = rx_filter;
+
-    params->eaddr = hardware_address;
+    params->hier = hier;
+    params->io_bus = io_bus;
+    params->payload_bus = payload_bus;
+    params->dma_read_delay = dma_read_delay;
+    params->dma_read_factor = dma_read_factor;
+    params->dma_write_delay = dma_write_delay;
+    params->dma_write_factor = dma_write_factor;
+    params->dma_no_allocate = dma_no_allocate;
+    params->pio_latency = pio_latency;
+    params->intr_delay = intr_delay;
+
+    params->tx_delay = tx_delay;
+    params->rx_delay = rx_delay;
     params->rx_max_copy = rx_max_copy;
     params->tx_max_copy = tx_max_copy;
     params->rx_fifo_size = rx_fifo_size;
     params->tx_fifo_size = tx_fifo_size;
     params->rx_fifo_threshold = rx_fifo_threshold;
     params->tx_fifo_threshold = tx_fifo_threshold;
-    params->dma_read_delay = dma_read_delay;
+
-    params->dma_read_factor = dma_read_factor;
+    params->rx_filter = rx_filter;
-    params->dma_write_delay = dma_write_delay;
+    params->eaddr = hardware_address;
-    params->dma_write_factor = dma_write_factor;
+
-    params->dma_no_allocate = dma_no_allocate;
     return new Device(params);
 }
 

dev/sinic.hh

@@ -48,8 +48,8 @@ class Base : public PciDev
   protected:
     bool rxEnable;
     bool txEnable;
-    Tick cycleTime;
+    Tick clock;
-    inline Tick cycles(int numCycles) const { return numCycles * cycleTime; }
+    inline Tick cycles(int numCycles) const { return numCycles * clock; }
 
   protected:
     Tick intrDelay;
@@ -81,7 +81,7 @@ class Base : public PciDev
   public:
     struct Params : public PciDev::Params
     {
-        Tick cycle_time;
+        Tick clock;
         Tick intr_delay;
     };
 

python/m5/objects/Ethernet.py

@@ -60,66 +60,50 @@ if build_env['ALPHA_TLASER']:
         type = 'EtherDevInt'
         device = Param.EtherDev("Ethernet device of this interface")
 
-class NSGigE(PciDevice):
+class EtherDevBase(PciDevice):
-    type = 'NSGigE'
     hardware_address = Param.EthernetAddr(NextEthernetAddr,
         "Ethernet Hardware Address")
 
     clock = Param.Clock('0ns', "State machine processor frequency")
 
-    dma_data_free = Param.Bool(False, "DMA of Data is free")
+    physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
-    dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
+
+    hier = Param.HierParams(Parent.any, "Hierarchy global variables")
+    payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
     dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
     dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
     dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
     dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
     dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
 
-
-    rx_filter = Param.Bool(True, "Enable Receive Filter")
     rx_delay = Param.Latency('1us', "Receive Delay")
     tx_delay = Param.Latency('1us', "Transmit Delay")
+    rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo")
+    tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo")
 
-    rx_fifo_size = Param.MemorySize('128kB', "max size in bytes of rxFifo")
+    rx_filter = Param.Bool(True, "Enable Receive Filter")
-    tx_fifo_size = Param.MemorySize('128kB', "max size in bytes of txFifo")
+    intr_delay = Param.Latency('10us', "Interrupt Propagation Delay")
 
-    dedicated = Param.Bool(False, "dedicated kernel thread for driver")
+class NSGigE(EtherDevBase):
+    type = 'NSGigE'
 
-    intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds")
+    dma_data_free = Param.Bool(False, "DMA of Data is free")
-    payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
+    dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
-    physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
+
+    dedicated = Param.Bool(False, "dedicate a kernel thread to the driver")
 
 class NSGigEInt(EtherInt):
     type = 'NSGigEInt'
     device = Param.NSGigE("Ethernet device of this interface")
 
-class Sinic(PciDevice):
+class Sinic(EtherDevBase):
     type = 'Sinic'
-    hardware_address = Param.EthernetAddr(NextEthernetAddr,
-        "Ethernet Hardware Address")
 
-    clock = Param.Clock('100MHz', "State machine processor frequency")
+    rx_max_copy = Param.MemorySize('1514B', "rx max copy")
-
-    dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
-    dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
-    dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
-    dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
-
-    rx_filter = Param.Bool(True, "Enable Receive Filter")
-    rx_delay = Param.Latency('1us', "Receive Delay")
-    tx_delay = Param.Latency('1us', "Transmit Delay")
-
-    rx_max_copy = Param.MemorySize('16kB', "rx max copy")
     tx_max_copy = Param.MemorySize('16kB', "tx max copy")
-    rx_fifo_size = Param.MemorySize('64kB', "max size of rx fifo")
-    tx_fifo_size = Param.MemorySize('64kB', "max size of tx fifo")
     rx_fifo_threshold = Param.MemorySize('48kB', "rx fifo high threshold")
     tx_fifo_threshold = Param.MemorySize('16kB', "tx fifo low threshold")
 
-    intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds")
-    payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
-    physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
-
 class SinicInt(EtherInt):
     type = 'SinicInt'
     device = Param.Sinic("Ethernet device of this interface")