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have sinic use the new readBar/writeBar stuff that's in the

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pci device base class

dev/sinic.cc:
dev/sinic.hh:
    use the new readBar/writeBar stuff that's in the pci device
    base class

--HG--
extra : convert_revision : 8a0b2bde3cc13597785d6ea75d6e6811680bb01b
This commit is contained in:
Nathan Binkert 2005-11-21 21:52:04 -05:00
parent 48863a1a43
commit 2b76b41b90
2 changed files with 31 additions and 6 deletions
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30
dev/sinic.cc
View file

@ -335,10 +335,21 @@ Fault
Device::read(MemReqPtr &req, uint8_t *data)
{
assert(config.command & PCI_CMD_MSE);
Fault fault = readBar(req, data);
//The mask is to give you only the offset into the device register file
Addr daddr = req->paddr & 0xfff;
if (fault == Machine_Check_Fault) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
req->paddr, req->vaddr, req->size);
return Machine_Check_Fault;
}
return fault;
}
Fault
Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
{
if (!regValid(daddr))
panic("invalid register: da=%#x pa=%#x va=%#x size=%d",
daddr, req->paddr, req->vaddr, req->size);
@ -414,10 +425,21 @@ Fault
Device::write(MemReqPtr &req, const uint8_t *data)
{
assert(config.command & PCI_CMD_MSE);
Fault fault = writeBar(req, data);
//The mask is to give you only the offset into the device register file
Addr daddr = req->paddr & 0xfff;
if (fault == Machine_Check_Fault) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
req->paddr, req->vaddr, req->size);
return Machine_Check_Fault;
}
return fault;
}
Fault
Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
{
if (!regValid(daddr))
panic("invalid address: da=%#x pa=%#x va=%#x size=%d",
daddr, req->paddr, req->vaddr, req->size);

7
dev/sinic.hh
View file

@ -259,10 +259,13 @@ class Device : public Base
* Memory Interface
*/
public:
void prepareRead();
Fault iprRead(Addr daddr, uint64_t &result);
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault write(MemReqPtr &req, const uint8_t *data);
void prepareRead();
Fault iprRead(Addr daddr, uint64_t &result);
Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
Tick cacheAccess(MemReqPtr &req);
/**