tests: Use more representative configs for ARM tests

This patch changes the CPU and cache configurations used in the ARM SE and FS
regressions to make them more representative, and also get better code
coverage by exercising different replacement policies and use an L2
prefetcher.
This commit is contained in:
Andreas Hansson 2014-09-20 17:18:33 -04:00
parent 1f6d5f8f84
commit 2b0438a11e
2 changed files with 37 additions and 3 deletions

View file

@ -43,6 +43,25 @@ m5.util.addToPath('../configs/common')
import FSConfig import FSConfig
from Caches import * from Caches import *
from base_config import * from base_config import *
from O3_ARM_v7a import *
class ArmSESystemUniprocessor(BaseSESystemUniprocessor):
"""Syscall-emulation builder for ARM uniprocessor systems.
A small tweak of the syscall-emulation builder to use more
representative cache configurations.
"""
def __init__(self, **kwargs):
BaseSESystem.__init__(self, **kwargs)
def create_caches_private(self, cpu):
# The atomic SE configurations do not use caches
if self.mem_mode == "timing":
# Use the more representative cache configuration
cpu.addTwoLevelCacheHierarchy(O3_ARM_v7a_ICache(),
O3_ARM_v7a_DCache(),
O3_ARM_v7aL2())
class LinuxArmSystemBuilder(object): class LinuxArmSystemBuilder(object):
"""Mix-in that implements create_system. """Mix-in that implements create_system.
@ -87,6 +106,12 @@ class LinuxArmFSSystem(LinuxArmSystemBuilder,
BaseSystem.__init__(self, **kwargs) BaseSystem.__init__(self, **kwargs)
LinuxArmSystemBuilder.__init__(self, machine_type) LinuxArmSystemBuilder.__init__(self, machine_type)
def create_caches_private(self, cpu):
# Use the more representative cache configuration
cpu.addTwoLevelCacheHierarchy(O3_ARM_v7a_ICache(),
O3_ARM_v7a_DCache(),
O3_ARM_v7aL2())
class LinuxArmFSSystemUniprocessor(LinuxArmSystemBuilder, class LinuxArmFSSystemUniprocessor(LinuxArmSystemBuilder,
BaseFSSystemUniprocessor): BaseFSSystemUniprocessor):
"""Basic ARM full system builder for uniprocessor systems. """Basic ARM full system builder for uniprocessor systems.
@ -100,7 +125,6 @@ class LinuxArmFSSystemUniprocessor(LinuxArmSystemBuilder,
BaseFSSystemUniprocessor.__init__(self, **kwargs) BaseFSSystemUniprocessor.__init__(self, **kwargs)
LinuxArmSystemBuilder.__init__(self, machine_type) LinuxArmSystemBuilder.__init__(self, machine_type)
class LinuxArmFSSwitcheroo(LinuxArmSystemBuilder, BaseFSSwitcheroo): class LinuxArmFSSwitcheroo(LinuxArmSystemBuilder, BaseFSSwitcheroo):
"""Uniprocessor ARM system prepared for CPU switching""" """Uniprocessor ARM system prepared for CPU switching"""

View file

@ -39,7 +39,17 @@
# Authors: Andreas Hansson # Authors: Andreas Hansson
from m5.objects import * from m5.objects import *
from m5.defines import buildEnv
from base_config import * from base_config import *
from arm_generic import *
from O3_ARM_v7a import O3_ARM_v7a_3
root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64, # If we are running ARM regressions, use a more sensible CPU
cpu_class=DerivO3CPU).create_root() # configuration. This makes the results more meaningful, and also
# increases the coverage of the regressions.
if buildEnv['TARGET_ISA'] == "arm":
root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
cpu_class=O3_ARM_v7a_3).create_root()
else:
root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
cpu_class=DerivO3CPU).create_root()