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tests: update EIO ref stats for removed cache stats

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Complaints about changes in EIO tests were due to reference files
that still have removed cache stats from cset 11454:e55afadc4e19.
This commit is contained in:
Steve Reinhardt 2016-05-07 14:43:06 -04:00
parent bb83fa2051
commit 2ae8b365c1
18 changed files with 93 additions and 166 deletions
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3
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16 num_work_ids=16
readfile= readfile=
symbolfile= symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0 work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1 work_begin_cpu_id_exit=-1
work_begin_exit_count=0 work_begin_exit_count=0
@ -141,6 +143,7 @@ clk_domain=system.clk_domain
eventq_index=0 eventq_index=0
forward_latency=4 forward_latency=4
frontend_latency=3 frontend_latency=3
point_of_coherency=true
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=Null
snoop_response_latency=4 snoop_response_latency=4

5
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json
View file

@ -15,6 +15,7 @@
"role": "SLAVE" "role": "SLAVE"
}, },
"name": "membus", "name": "membus",
"point_of_coherency": true,
"snoop_filter": null, "snoop_filter": null,
"forward_latency": 4, "forward_latency": 4,
"clk_domain": "system.clk_domain", "clk_domain": "system.clk_domain",
@ -37,8 +38,10 @@
}, },
"symbolfile": "", "symbolfile": "",
"readfile": "", "readfile": "",
"thermal_model": null,
"cxx_class": "System", "cxx_class": "System",
"load_offset": 0, "load_offset": 0,
"work_begin_exit_count": 0,
"work_end_ckpt_count": 0, "work_end_ckpt_count": 0,
"memories": [ "memories": [
"system.physmem" "system.physmem"
@ -105,7 +108,7 @@
"in_addr_map": true "in_addr_map": true
}, },
"work_cpus_ckpt_count": 0, "work_cpus_ckpt_count": 0,
"work_begin_exit_count": 0, "thermal_components": [],
"path": "system", "path": "system",
"cpu_clk_domain": { "cpu_clk_domain": {
"name": "cpu_clk_domain", "name": "cpu_clk_domain",

6
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 1 2016 02:06:47 gem5 compiled May 7 2016 13:41:33
gem5 started Feb 1 2016 02:07:02 gem5 started May 7 2016 13:42:02
gem5 executing on zizzer, pid 44725 gem5 executing on zizzer, pid 51296
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second

10
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000250 # Nu
sim_ticks 250015500 # Number of ticks simulated sim_ticks 250015500 # Number of ticks simulated
final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1689656 # Simulator instruction rate (inst/s) host_inst_rate 1181428 # Simulator instruction rate (inst/s)
host_op_rate 1689524 # Simulator op (including micro ops) rate (op/s) host_op_rate 1181354 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 844754706 # Simulator tick rate (ticks/s) host_tick_rate 590676886 # Simulator tick rate (ticks/s)
host_mem_usage 219516 # Number of bytes of host memory used host_mem_usage 220296 # Number of bytes of host memory used
host_seconds 0.30 # Real time elapsed on the host host_seconds 0.42 # Real time elapsed on the host
sim_insts 500001 # Number of instructions simulated sim_insts 500001 # Number of instructions simulated
sim_ops 500001 # Number of ops (including micro ops) simulated sim_ops 500001 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts

7
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16 num_work_ids=16
readfile= readfile=
symbolfile= symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0 work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1 work_begin_cpu_id_exit=-1
work_begin_exit_count=0 work_begin_exit_count=0
@ -88,7 +90,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
forward_snoops=true
hit_latency=2 hit_latency=2
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
@ -130,7 +131,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
forward_snoops=true
hit_latency=2 hit_latency=2
is_read_only=true is_read_only=true
max_miss_count=0 max_miss_count=0
@ -181,7 +181,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
forward_snoops=true
hit_latency=20 hit_latency=20
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
@ -216,6 +215,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0 eventq_index=0
forward_latency=0 forward_latency=0
frontend_latency=1 frontend_latency=1
point_of_coherency=false
response_latency=1 response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1 snoop_response_latency=1
@ -271,6 +271,7 @@ clk_domain=system.clk_domain
eventq_index=0 eventq_index=0
forward_latency=4 forward_latency=4
frontend_latency=3 frontend_latency=3
point_of_coherency=true
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=Null
snoop_response_latency=4 snoop_response_latency=4

15
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json
View file

@ -14,6 +14,7 @@
"role": "SLAVE" "role": "SLAVE"
}, },
"name": "membus", "name": "membus",
"point_of_coherency": true,
"snoop_filter": null, "snoop_filter": null,
"forward_latency": 4, "forward_latency": 4,
"clk_domain": "system.clk_domain", "clk_domain": "system.clk_domain",
@ -36,8 +37,10 @@
}, },
"symbolfile": "", "symbolfile": "",
"readfile": "", "readfile": "",
"thermal_model": null,
"cxx_class": "System", "cxx_class": "System",
"load_offset": 0, "load_offset": 0,
"work_begin_exit_count": 0,
"work_end_ckpt_count": 0, "work_end_ckpt_count": 0,
"memories": [ "memories": [
"system.physmem" "system.physmem"
@ -104,7 +107,7 @@
"in_addr_map": true "in_addr_map": true
}, },
"work_cpus_ckpt_count": 0, "work_cpus_ckpt_count": 0,
"work_begin_exit_count": 0, "thermal_components": [],
"path": "system", "path": "system",
"cpu_clk_domain": { "cpu_clk_domain": {
"name": "cpu_clk_domain", "name": "cpu_clk_domain",
@ -158,6 +161,7 @@
"role": "SLAVE" "role": "SLAVE"
}, },
"name": "toL2Bus", "name": "toL2Bus",
"point_of_coherency": false,
"snoop_filter": { "snoop_filter": {
"name": "snoop_filter", "name": "snoop_filter",
"system": "system", "system": "system",
@ -227,11 +231,10 @@
"role": "MASTER" "role": "MASTER"
}, },
"type": "Cache", "type": "Cache",
"forward_snoops": true,
"writeback_clean": true, "writeback_clean": true,
"hit_latency": 2, "hit_latency": 2,
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1, "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [ "addr_ranges": [
"0:18446744073709551615" "0:18446744073709551615"
], ],
@ -291,11 +294,10 @@
"role": "MASTER" "role": "MASTER"
}, },
"type": "Cache", "type": "Cache",
"forward_snoops": true,
"writeback_clean": false, "writeback_clean": false,
"hit_latency": 20, "hit_latency": 20,
"tgts_per_mshr": 12,
"demand_mshr_reserve": 1, "demand_mshr_reserve": 1,
"tgts_per_mshr": 12,
"addr_ranges": [ "addr_ranges": [
"0:18446744073709551615" "0:18446744073709551615"
], ],
@ -374,11 +376,10 @@
"role": "MASTER" "role": "MASTER"
}, },
"type": "Cache", "type": "Cache",
"forward_snoops": true,
"writeback_clean": false, "writeback_clean": false,
"hit_latency": 2, "hit_latency": 2,
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1, "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [ "addr_ranges": [
"0:18446744073709551615" "0:18446744073709551615"
], ],

6
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 1 2016 02:06:47 gem5 compiled May 7 2016 13:41:33
gem5 started Feb 1 2016 02:07:02 gem5 started May 7 2016 13:42:14
gem5 executing on zizzer, pid 44728 gem5 executing on zizzer, pid 51342
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second

19
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000733 # Nu
sim_ticks 733071500 # Number of ticks simulated sim_ticks 733071500 # Number of ticks simulated
final_tick 733071500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 733071500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 728390 # Simulator instruction rate (inst/s) host_inst_rate 558953 # Simulator instruction rate (inst/s)
host_op_rate 728363 # Simulator op (including micro ops) rate (op/s) host_op_rate 558933 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1067851383 # Simulator tick rate (ticks/s) host_tick_rate 819448941 # Simulator tick rate (ticks/s)
host_mem_usage 229580 # Number of bytes of host memory used host_mem_usage 229836 # Number of bytes of host memory used
host_seconds 0.69 # Real time elapsed on the host host_seconds 0.89 # Real time elapsed on the host
sim_insts 500001 # Number of instructions simulated sim_insts 500001 # Number of instructions simulated
sim_ops 500001 # Number of ops (including micro ops) simulated sim_ops 500001 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
@ -191,8 +191,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 139 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 139 # number of WriteReq MSHR misses
@ -225,7 +223,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 264.585152 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 264.585152 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 499617 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 499617 # Total number of references to valid blocks.
@ -282,8 +279,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 403 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::cpu.inst 403 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 403 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 403 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 403 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 403 # number of demand (read+write) MSHR misses
@ -308,7 +303,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61001.240695
system.cpu.icache.demand_avg_mshr_miss_latency::total 61001.240695 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 61001.240695 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61001.240695 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61001.240695 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 61001.240695 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 61001.240695 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 480.680597 # Cycle average of tags in use system.cpu.l2cache.tags.tagsinuse 480.680597 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
@ -393,8 +387,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 139 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 139 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 139 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 139 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 403 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 403 # number of ReadCleanReq MSHR misses
@ -443,7 +435,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.583431
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.240695 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.240695 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.583431 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.583431 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 857 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.tot_requests 857 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

13
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16 num_work_ids=16
readfile= readfile=
symbolfile= symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0 work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1 work_begin_cpu_id_exit=-1
work_begin_exit_count=0 work_begin_exit_count=0
@ -92,7 +94,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
forward_snoops=true
hit_latency=2 hit_latency=2
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
@ -134,7 +135,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
forward_snoops=true
hit_latency=2 hit_latency=2
is_read_only=true is_read_only=true
max_miss_count=0 max_miss_count=0
@ -239,7 +239,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
forward_snoops=true
hit_latency=2 hit_latency=2
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
@ -281,7 +280,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
forward_snoops=true
hit_latency=2 hit_latency=2
is_read_only=true is_read_only=true
max_miss_count=0 max_miss_count=0
@ -386,7 +384,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
forward_snoops=true
hit_latency=2 hit_latency=2
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
@ -428,7 +425,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
forward_snoops=true
hit_latency=2 hit_latency=2
is_read_only=true is_read_only=true
max_miss_count=0 max_miss_count=0
@ -533,7 +529,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
forward_snoops=true
hit_latency=2 hit_latency=2
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
@ -575,7 +570,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
forward_snoops=true
hit_latency=2 hit_latency=2
is_read_only=true is_read_only=true
max_miss_count=0 max_miss_count=0
@ -659,7 +653,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
forward_snoops=true
hit_latency=20 hit_latency=20
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
@ -693,6 +686,7 @@ clk_domain=system.clk_domain
eventq_index=0 eventq_index=0
forward_latency=4 forward_latency=4
frontend_latency=3 frontend_latency=3
point_of_coherency=true
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=Null
snoop_response_latency=4 snoop_response_latency=4
@ -722,6 +716,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0 eventq_index=0
forward_latency=0 forward_latency=0
frontend_latency=1 frontend_latency=1
point_of_coherency=false
response_latency=1 response_latency=1
snoop_filter=system.toL2Bus.snoop_filter snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1 snoop_response_latency=1

33
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.json
View file

@ -14,6 +14,7 @@
"role": "SLAVE" "role": "SLAVE"
}, },
"name": "membus", "name": "membus",
"point_of_coherency": true,
"snoop_filter": null, "snoop_filter": null,
"forward_latency": 4, "forward_latency": 4,
"clk_domain": "system.clk_domain", "clk_domain": "system.clk_domain",
@ -68,11 +69,10 @@
"role": "MASTER" "role": "MASTER"
}, },
"type": "Cache", "type": "Cache",
"forward_snoops": true,
"writeback_clean": false, "writeback_clean": false,
"hit_latency": 20, "hit_latency": 20,
"tgts_per_mshr": 12,
"demand_mshr_reserve": 1, "demand_mshr_reserve": 1,
"tgts_per_mshr": 12,
"addr_ranges": [ "addr_ranges": [
"0:18446744073709551615" "0:18446744073709551615"
], ],
@ -85,8 +85,10 @@
"assoc": 8 "assoc": 8
}, },
"readfile": "", "readfile": "",
"thermal_model": null,
"cxx_class": "System", "cxx_class": "System",
"load_offset": 0, "load_offset": 0,
"work_begin_exit_count": 0,
"work_end_ckpt_count": 0, "work_end_ckpt_count": 0,
"memories": [ "memories": [
"system.physmem" "system.physmem"
@ -153,7 +155,7 @@
"in_addr_map": true "in_addr_map": true
}, },
"work_cpus_ckpt_count": 0, "work_cpus_ckpt_count": 0,
"work_begin_exit_count": 0, "thermal_components": [],
"path": "system", "path": "system",
"cpu_clk_domain": { "cpu_clk_domain": {
"name": "cpu_clk_domain", "name": "cpu_clk_domain",
@ -183,6 +185,7 @@
"role": "SLAVE" "role": "SLAVE"
}, },
"name": "toL2Bus", "name": "toL2Bus",
"point_of_coherency": false,
"snoop_filter": { "snoop_filter": {
"name": "snoop_filter", "name": "snoop_filter",
"system": "system", "system": "system",
@ -285,11 +288,10 @@
"role": "MASTER" "role": "MASTER"
}, },
"type": "Cache", "type": "Cache",
"forward_snoops": true,
"writeback_clean": true, "writeback_clean": true,
"hit_latency": 2, "hit_latency": 2,
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1, "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [ "addr_ranges": [
"0:18446744073709551615" "0:18446744073709551615"
], ],
@ -384,11 +386,10 @@
"role": "MASTER" "role": "MASTER"
}, },
"type": "Cache", "type": "Cache",
"forward_snoops": true,
"writeback_clean": false, "writeback_clean": false,
"hit_latency": 2, "hit_latency": 2,
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1, "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [ "addr_ranges": [
"0:18446744073709551615" "0:18446744073709551615"
], ],
@ -482,11 +483,10 @@
"role": "MASTER" "role": "MASTER"
}, },
"type": "Cache", "type": "Cache",
"forward_snoops": true,
"writeback_clean": true, "writeback_clean": true,
"hit_latency": 2, "hit_latency": 2,
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1, "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [ "addr_ranges": [
"0:18446744073709551615" "0:18446744073709551615"
], ],
@ -581,11 +581,10 @@
"role": "MASTER" "role": "MASTER"
}, },
"type": "Cache", "type": "Cache",
"forward_snoops": true,
"writeback_clean": false, "writeback_clean": false,
"hit_latency": 2, "hit_latency": 2,
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1, "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [ "addr_ranges": [
"0:18446744073709551615" "0:18446744073709551615"
], ],
@ -679,11 +678,10 @@
"role": "MASTER" "role": "MASTER"
}, },
"type": "Cache", "type": "Cache",
"forward_snoops": true,
"writeback_clean": true, "writeback_clean": true,
"hit_latency": 2, "hit_latency": 2,
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1, "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [ "addr_ranges": [
"0:18446744073709551615" "0:18446744073709551615"
], ],
@ -778,11 +776,10 @@
"role": "MASTER" "role": "MASTER"
}, },
"type": "Cache", "type": "Cache",
"forward_snoops": true,
"writeback_clean": false, "writeback_clean": false,
"hit_latency": 2, "hit_latency": 2,
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1, "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [ "addr_ranges": [
"0:18446744073709551615" "0:18446744073709551615"
], ],
@ -876,11 +873,10 @@
"role": "MASTER" "role": "MASTER"
}, },
"type": "Cache", "type": "Cache",
"forward_snoops": true,
"writeback_clean": true, "writeback_clean": true,
"hit_latency": 2, "hit_latency": 2,
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1, "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [ "addr_ranges": [
"0:18446744073709551615" "0:18446744073709551615"
], ],
@ -975,11 +971,10 @@
"role": "MASTER" "role": "MASTER"
}, },
"type": "Cache", "type": "Cache",
"forward_snoops": true,
"writeback_clean": false, "writeback_clean": false,
"hit_latency": 2, "hit_latency": 2,
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1, "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [ "addr_ranges": [
"0:18446744073709551615" "0:18446744073709551615"
], ],

6
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
View file

@ -3,5 +3,7 @@ warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything
gzip: stdout: Broken pipe gzip: stdout: Broken pipe
stdout: Broken pipe
stdout: Broken pipe gzip: stdout: Broken pipe
gzip: stdout: Broken pipe

6
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 1 2016 02:06:47 gem5 compiled May 7 2016 13:41:33
gem5 started Feb 1 2016 02:07:02 gem5 started May 7 2016 13:41:50
gem5 executing on zizzer, pid 44731 gem5 executing on zizzer, pid 51237
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second

37
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000250 # Nu
sim_ticks 250015500 # Number of ticks simulated sim_ticks 250015500 # Number of ticks simulated
final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1345479 # Simulator instruction rate (inst/s) host_inst_rate 1254205 # Simulator instruction rate (inst/s)
host_op_rate 1345456 # Simulator op (including micro ops) rate (op/s) host_op_rate 1254187 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 168189773 # Simulator tick rate (ticks/s) host_tick_rate 156780790 # Simulator tick rate (ticks/s)
host_mem_usage 243396 # Number of bytes of host memory used host_mem_usage 242604 # Number of bytes of host memory used
host_seconds 1.49 # Real time elapsed on the host host_seconds 1.59 # Real time elapsed on the host
sim_insts 2000004 # Number of instructions simulated sim_insts 2000004 # Number of instructions simulated
sim_ops 2000004 # Number of ops (including micro ops) simulated sim_ops 2000004 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
@ -205,11 +205,8 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks
system.cpu0.dcache.writebacks::total 29 # number of writebacks system.cpu0.dcache.writebacks::total 29 # number of writebacks
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 152 # number of replacements system.cpu0.icache.tags.replacements 152 # number of replacements
system.cpu0.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use system.cpu0.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 499556 # Total number of references to valid blocks. system.cpu0.icache.tags.total_refs 499556 # Total number of references to valid blocks.
@ -255,11 +252,8 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.writebacks::writebacks 152 # number of writebacks system.cpu0.icache.writebacks::writebacks 152 # number of writebacks
system.cpu0.icache.writebacks::total 152 # number of writebacks system.cpu0.icache.writebacks::total 152 # number of writebacks
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_acv 0 # ITB acv
@ -405,11 +399,8 @@ system.cpu1.dcache.blocked::no_mshrs 0 # nu
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks
system.cpu1.dcache.writebacks::total 29 # number of writebacks system.cpu1.dcache.writebacks::total 29 # number of writebacks
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 152 # number of replacements system.cpu1.icache.tags.replacements 152 # number of replacements
system.cpu1.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use system.cpu1.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 499556 # Total number of references to valid blocks. system.cpu1.icache.tags.total_refs 499556 # Total number of references to valid blocks.
@ -455,11 +446,8 @@ system.cpu1.icache.blocked::no_mshrs 0 # nu
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.writebacks::writebacks 152 # number of writebacks system.cpu1.icache.writebacks::writebacks 152 # number of writebacks
system.cpu1.icache.writebacks::total 152 # number of writebacks system.cpu1.icache.writebacks::total 152 # number of writebacks
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_acv 0 # ITB acv
@ -605,11 +593,8 @@ system.cpu2.dcache.blocked::no_mshrs 0 # nu
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks
system.cpu2.dcache.writebacks::total 29 # number of writebacks system.cpu2.dcache.writebacks::total 29 # number of writebacks
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.icache.tags.replacements 152 # number of replacements system.cpu2.icache.tags.replacements 152 # number of replacements
system.cpu2.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use system.cpu2.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
system.cpu2.icache.tags.total_refs 499556 # Total number of references to valid blocks. system.cpu2.icache.tags.total_refs 499556 # Total number of references to valid blocks.
@ -655,11 +640,8 @@ system.cpu2.icache.blocked::no_mshrs 0 # nu
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
system.cpu2.icache.writebacks::writebacks 152 # number of writebacks system.cpu2.icache.writebacks::writebacks 152 # number of writebacks
system.cpu2.icache.writebacks::total 152 # number of writebacks system.cpu2.icache.writebacks::total 152 # number of writebacks
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dtb.fetch_hits 0 # ITB hits system.cpu3.dtb.fetch_hits 0 # ITB hits
system.cpu3.dtb.fetch_misses 0 # ITB misses system.cpu3.dtb.fetch_misses 0 # ITB misses
system.cpu3.dtb.fetch_acv 0 # ITB acv system.cpu3.dtb.fetch_acv 0 # ITB acv
@ -805,11 +787,8 @@ system.cpu3.dcache.blocked::no_mshrs 0 # nu
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks
system.cpu3.dcache.writebacks::total 29 # number of writebacks system.cpu3.dcache.writebacks::total 29 # number of writebacks
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.icache.tags.replacements 152 # number of replacements system.cpu3.icache.tags.replacements 152 # number of replacements
system.cpu3.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use system.cpu3.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
system.cpu3.icache.tags.total_refs 499556 # Total number of references to valid blocks. system.cpu3.icache.tags.total_refs 499556 # Total number of references to valid blocks.
@ -855,11 +834,8 @@ system.cpu3.icache.blocked::no_mshrs 0 # nu
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.cache_copies 0 # number of cache copies performed
system.cpu3.icache.writebacks::writebacks 152 # number of writebacks system.cpu3.icache.writebacks::writebacks 152 # number of writebacks
system.cpu3.icache.writebacks::total 152 # number of writebacks system.cpu3.icache.writebacks::total 152 # number of writebacks
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 0 # number of replacements system.l2c.tags.replacements 0 # number of replacements
system.l2c.tags.tagsinuse 1962.780232 # Cycle average of tags in use system.l2c.tags.tagsinuse 1962.780232 # Cycle average of tags in use
system.l2c.tags.total_refs 1068 # Total number of references to valid blocks. system.l2c.tags.total_refs 1068 # Total number of references to valid blocks.
@ -1033,9 +1009,6 @@ system.l2c.blocked::no_mshrs 0 # nu
system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadResp 2872 # Transaction distribution system.membus.trans_dist::ReadResp 2872 # Transaction distribution
system.membus.trans_dist::ReadExReq 556 # Transaction distribution system.membus.trans_dist::ReadExReq 556 # Transaction distribution
system.membus.trans_dist::ReadExResp 556 # Transaction distribution system.membus.trans_dist::ReadExResp 556 # Transaction distribution

13
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16 num_work_ids=16
readfile= readfile=
symbolfile= symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0 work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1 work_begin_cpu_id_exit=-1
work_begin_exit_count=0 work_begin_exit_count=0
@ -88,7 +90,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
forward_snoops=true
hit_latency=2 hit_latency=2
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
@ -130,7 +131,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
forward_snoops=true
hit_latency=2 hit_latency=2
is_read_only=true is_read_only=true
max_miss_count=0 max_miss_count=0
@ -231,7 +231,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
forward_snoops=true
hit_latency=2 hit_latency=2
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
@ -273,7 +272,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
forward_snoops=true
hit_latency=2 hit_latency=2
is_read_only=true is_read_only=true
max_miss_count=0 max_miss_count=0
@ -374,7 +372,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
forward_snoops=true
hit_latency=2 hit_latency=2
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
@ -416,7 +413,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
forward_snoops=true
hit_latency=2 hit_latency=2
is_read_only=true is_read_only=true
max_miss_count=0 max_miss_count=0
@ -517,7 +513,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
forward_snoops=true
hit_latency=2 hit_latency=2
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
@ -559,7 +554,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
forward_snoops=true
hit_latency=2 hit_latency=2
is_read_only=true is_read_only=true
max_miss_count=0 max_miss_count=0
@ -643,7 +637,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl clusivity=mostly_incl
demand_mshr_reserve=1 demand_mshr_reserve=1
eventq_index=0 eventq_index=0
forward_snoops=true
hit_latency=20 hit_latency=20
is_read_only=false is_read_only=false
max_miss_count=0 max_miss_count=0
@ -677,6 +670,7 @@ clk_domain=system.clk_domain
eventq_index=0 eventq_index=0
forward_latency=4 forward_latency=4
frontend_latency=3 frontend_latency=3
point_of_coherency=true
response_latency=2 response_latency=2
snoop_filter=Null snoop_filter=Null
snoop_response_latency=4 snoop_response_latency=4
@ -706,6 +700,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0 eventq_index=0
forward_latency=0 forward_latency=0
frontend_latency=1 frontend_latency=1
point_of_coherency=false
response_latency=1 response_latency=1
snoop_filter=system.toL2Bus.snoop_filter snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1 snoop_response_latency=1

33
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.json
View file

@ -14,6 +14,7 @@
"role": "SLAVE" "role": "SLAVE"
}, },
"name": "membus", "name": "membus",
"point_of_coherency": true,
"snoop_filter": null, "snoop_filter": null,
"forward_latency": 4, "forward_latency": 4,
"clk_domain": "system.clk_domain", "clk_domain": "system.clk_domain",
@ -68,11 +69,10 @@
"role": "MASTER" "role": "MASTER"
}, },
"type": "Cache", "type": "Cache",
"forward_snoops": true,
"writeback_clean": false, "writeback_clean": false,
"hit_latency": 20, "hit_latency": 20,
"tgts_per_mshr": 12,
"demand_mshr_reserve": 1, "demand_mshr_reserve": 1,
"tgts_per_mshr": 12,
"addr_ranges": [ "addr_ranges": [
"0:18446744073709551615" "0:18446744073709551615"
], ],
@ -85,8 +85,10 @@
"assoc": 8 "assoc": 8
}, },
"readfile": "", "readfile": "",
"thermal_model": null,
"cxx_class": "System", "cxx_class": "System",
"load_offset": 0, "load_offset": 0,
"work_begin_exit_count": 0,
"work_end_ckpt_count": 0, "work_end_ckpt_count": 0,
"memories": [ "memories": [
"system.physmem" "system.physmem"
@ -153,7 +155,7 @@
"in_addr_map": true "in_addr_map": true
}, },
"work_cpus_ckpt_count": 0, "work_cpus_ckpt_count": 0,
"work_begin_exit_count": 0, "thermal_components": [],
"path": "system", "path": "system",
"cpu_clk_domain": { "cpu_clk_domain": {
"name": "cpu_clk_domain", "name": "cpu_clk_domain",
@ -183,6 +185,7 @@
"role": "SLAVE" "role": "SLAVE"
}, },
"name": "toL2Bus", "name": "toL2Bus",
"point_of_coherency": false,
"snoop_filter": { "snoop_filter": {
"name": "snoop_filter", "name": "snoop_filter",
"system": "system", "system": "system",
@ -282,11 +285,10 @@
"role": "MASTER" "role": "MASTER"
}, },
"type": "Cache", "type": "Cache",
"forward_snoops": true,
"writeback_clean": true, "writeback_clean": true,
"hit_latency": 2, "hit_latency": 2,
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1, "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [ "addr_ranges": [
"0:18446744073709551615" "0:18446744073709551615"
], ],
@ -380,11 +382,10 @@
"role": "MASTER" "role": "MASTER"
}, },
"type": "Cache", "type": "Cache",
"forward_snoops": true,
"writeback_clean": false, "writeback_clean": false,
"hit_latency": 2, "hit_latency": 2,
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1, "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [ "addr_ranges": [
"0:18446744073709551615" "0:18446744073709551615"
], ],
@ -475,11 +476,10 @@
"role": "MASTER" "role": "MASTER"
}, },
"type": "Cache", "type": "Cache",
"forward_snoops": true,
"writeback_clean": true, "writeback_clean": true,
"hit_latency": 2, "hit_latency": 2,
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1, "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [ "addr_ranges": [
"0:18446744073709551615" "0:18446744073709551615"
], ],
@ -573,11 +573,10 @@
"role": "MASTER" "role": "MASTER"
}, },
"type": "Cache", "type": "Cache",
"forward_snoops": true,
"writeback_clean": false, "writeback_clean": false,
"hit_latency": 2, "hit_latency": 2,
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1, "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [ "addr_ranges": [
"0:18446744073709551615" "0:18446744073709551615"
], ],
@ -668,11 +667,10 @@
"role": "MASTER" "role": "MASTER"
}, },
"type": "Cache", "type": "Cache",
"forward_snoops": true,
"writeback_clean": true, "writeback_clean": true,
"hit_latency": 2, "hit_latency": 2,
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1, "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [ "addr_ranges": [
"0:18446744073709551615" "0:18446744073709551615"
], ],
@ -766,11 +764,10 @@
"role": "MASTER" "role": "MASTER"
}, },
"type": "Cache", "type": "Cache",
"forward_snoops": true,
"writeback_clean": false, "writeback_clean": false,
"hit_latency": 2, "hit_latency": 2,
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1, "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [ "addr_ranges": [
"0:18446744073709551615" "0:18446744073709551615"
], ],
@ -861,11 +858,10 @@
"role": "MASTER" "role": "MASTER"
}, },
"type": "Cache", "type": "Cache",
"forward_snoops": true,
"writeback_clean": true, "writeback_clean": true,
"hit_latency": 2, "hit_latency": 2,
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1, "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [ "addr_ranges": [
"0:18446744073709551615" "0:18446744073709551615"
], ],
@ -959,11 +955,10 @@
"role": "MASTER" "role": "MASTER"
}, },
"type": "Cache", "type": "Cache",
"forward_snoops": true,
"writeback_clean": false, "writeback_clean": false,
"hit_latency": 2, "hit_latency": 2,
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1, "demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [ "addr_ranges": [
"0:18446744073709551615" "0:18446744073709551615"
], ],

4
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
View file

@ -2,7 +2,7 @@ warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything
gzip:
gzip: stdout: Broken pipe gzip: stdout: Broken pipe
stdout: Broken pipe stdout: Broken pipe
stdout: Broken pipe
gzip: stdout: Broken pipe

6
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 1 2016 02:06:47 gem5 compiled May 7 2016 13:41:33
gem5 started Feb 1 2016 02:07:02 gem5 started May 7 2016 13:41:50
gem5 executing on zizzer, pid 44723 gem5 executing on zizzer, pid 51213
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re /z/stever/hg/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second

37
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000734 # Nu
sim_ticks 733914500 # Number of ticks simulated sim_ticks 733914500 # Number of ticks simulated
final_tick 733914500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 733914500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 608165 # Simulator instruction rate (inst/s) host_inst_rate 598517 # Simulator instruction rate (inst/s)
host_op_rate 608160 # Simulator op (including micro ops) rate (op/s) host_op_rate 598513 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 223170099 # Simulator tick rate (ticks/s) host_tick_rate 219630055 # Simulator tick rate (ticks/s)
host_mem_usage 243400 # Number of bytes of host memory used host_mem_usage 242608 # Number of bytes of host memory used
host_seconds 3.29 # Real time elapsed on the host host_seconds 3.34 # Real time elapsed on the host
sim_insts 1999973 # Number of instructions simulated sim_insts 1999973 # Number of instructions simulated
sim_ops 1999973 # Number of ops (including micro ops) simulated sim_ops 1999973 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
@ -221,8 +221,6 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks
system.cpu0.dcache.writebacks::total 29 # number of writebacks system.cpu0.dcache.writebacks::total 29 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 324 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 324 # number of ReadReq MSHR misses
@ -257,7 +255,6 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 60058.315335
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 60058.315335 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 60058.315335 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 60058.315335 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 60058.315335 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 60058.315335 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 60058.315335 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 152 # number of replacements system.cpu0.icache.tags.replacements 152 # number of replacements
system.cpu0.icache.tags.tagsinuse 216.116668 # Cycle average of tags in use system.cpu0.icache.tags.tagsinuse 216.116668 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 499557 # Total number of references to valid blocks. system.cpu0.icache.tags.total_refs 499557 # Total number of references to valid blocks.
@ -314,8 +311,6 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.writebacks::writebacks 152 # number of writebacks system.cpu0.icache.writebacks::writebacks 152 # number of writebacks
system.cpu0.icache.writebacks::total 152 # number of writebacks system.cpu0.icache.writebacks::total 152 # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 463 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 463 # number of ReadReq MSHR misses
@ -342,7 +337,6 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 54672.786177
system.cpu0.icache.demand_avg_mshr_miss_latency::total 54672.786177 # average overall mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::total 54672.786177 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 54672.786177 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 54672.786177 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 54672.786177 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 54672.786177 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_acv 0 # ITB acv
@ -504,8 +498,6 @@ system.cpu1.dcache.blocked::no_mshrs 0 # nu
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks
system.cpu1.dcache.writebacks::total 29 # number of writebacks system.cpu1.dcache.writebacks::total 29 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 324 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 324 # number of ReadReq MSHR misses
@ -540,7 +532,6 @@ system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 60059.395248
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 60059.395248 # average overall mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::total 60059.395248 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 60059.395248 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 60059.395248 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 60059.395248 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 60059.395248 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 152 # number of replacements system.cpu1.icache.tags.replacements 152 # number of replacements
system.cpu1.icache.tags.tagsinuse 216.114546 # Cycle average of tags in use system.cpu1.icache.tags.tagsinuse 216.114546 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 499551 # Total number of references to valid blocks. system.cpu1.icache.tags.total_refs 499551 # Total number of references to valid blocks.
@ -597,8 +588,6 @@ system.cpu1.icache.blocked::no_mshrs 0 # nu
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.writebacks::writebacks 152 # number of writebacks system.cpu1.icache.writebacks::writebacks 152 # number of writebacks
system.cpu1.icache.writebacks::total 152 # number of writebacks system.cpu1.icache.writebacks::total 152 # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463 # number of ReadReq MSHR misses
@ -625,7 +614,6 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 54686.825054
system.cpu1.icache.demand_avg_mshr_miss_latency::total 54686.825054 # average overall mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::total 54686.825054 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 54686.825054 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 54686.825054 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 54686.825054 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 54686.825054 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_acv 0 # ITB acv
@ -787,8 +775,6 @@ system.cpu2.dcache.blocked::no_mshrs 0 # nu
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks
system.cpu2.dcache.writebacks::total 29 # number of writebacks system.cpu2.dcache.writebacks::total 29 # number of writebacks
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 324 # number of ReadReq MSHR misses system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 324 # number of ReadReq MSHR misses
@ -823,7 +809,6 @@ system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 60058.315335
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 60058.315335 # average overall mshr miss latency system.cpu2.dcache.demand_avg_mshr_miss_latency::total 60058.315335 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 60058.315335 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 60058.315335 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 60058.315335 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::total 60058.315335 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.icache.tags.replacements 152 # number of replacements system.cpu2.icache.tags.replacements 152 # number of replacements
system.cpu2.icache.tags.tagsinuse 216.112416 # Cycle average of tags in use system.cpu2.icache.tags.tagsinuse 216.112416 # Cycle average of tags in use
system.cpu2.icache.tags.total_refs 499546 # Total number of references to valid blocks. system.cpu2.icache.tags.total_refs 499546 # Total number of references to valid blocks.
@ -880,8 +865,6 @@ system.cpu2.icache.blocked::no_mshrs 0 # nu
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
system.cpu2.icache.writebacks::writebacks 152 # number of writebacks system.cpu2.icache.writebacks::writebacks 152 # number of writebacks
system.cpu2.icache.writebacks::total 152 # number of writebacks system.cpu2.icache.writebacks::total 152 # number of writebacks
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 463 # number of ReadReq MSHR misses system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 463 # number of ReadReq MSHR misses
@ -908,7 +891,6 @@ system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 54698.704104
system.cpu2.icache.demand_avg_mshr_miss_latency::total 54698.704104 # average overall mshr miss latency system.cpu2.icache.demand_avg_mshr_miss_latency::total 54698.704104 # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 54698.704104 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 54698.704104 # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 54698.704104 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::total 54698.704104 # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dtb.fetch_hits 0 # ITB hits system.cpu3.dtb.fetch_hits 0 # ITB hits
system.cpu3.dtb.fetch_misses 0 # ITB misses system.cpu3.dtb.fetch_misses 0 # ITB misses
system.cpu3.dtb.fetch_acv 0 # ITB acv system.cpu3.dtb.fetch_acv 0 # ITB acv
@ -1070,8 +1052,6 @@ system.cpu3.dcache.blocked::no_mshrs 0 # nu
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks
system.cpu3.dcache.writebacks::total 29 # number of writebacks system.cpu3.dcache.writebacks::total 29 # number of writebacks
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 324 # number of ReadReq MSHR misses system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 324 # number of ReadReq MSHR misses
@ -1106,7 +1086,6 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 60059.395248
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 60059.395248 # average overall mshr miss latency system.cpu3.dcache.demand_avg_mshr_miss_latency::total 60059.395248 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 60059.395248 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 60059.395248 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 60059.395248 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::total 60059.395248 # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.icache.tags.replacements 152 # number of replacements system.cpu3.icache.tags.replacements 152 # number of replacements
system.cpu3.icache.tags.tagsinuse 216.110261 # Cycle average of tags in use system.cpu3.icache.tags.tagsinuse 216.110261 # Cycle average of tags in use
system.cpu3.icache.tags.total_refs 499543 # Total number of references to valid blocks. system.cpu3.icache.tags.total_refs 499543 # Total number of references to valid blocks.
@ -1163,8 +1142,6 @@ system.cpu3.icache.blocked::no_mshrs 0 # nu
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.cache_copies 0 # number of cache copies performed
system.cpu3.icache.writebacks::writebacks 152 # number of writebacks system.cpu3.icache.writebacks::writebacks 152 # number of writebacks
system.cpu3.icache.writebacks::total 152 # number of writebacks system.cpu3.icache.writebacks::total 152 # number of writebacks
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 463 # number of ReadReq MSHR misses system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 463 # number of ReadReq MSHR misses
@ -1191,7 +1168,6 @@ system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 54708.423326
system.cpu3.icache.demand_avg_mshr_miss_latency::total 54708.423326 # average overall mshr miss latency system.cpu3.icache.demand_avg_mshr_miss_latency::total 54708.423326 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 54708.423326 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 54708.423326 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 54708.423326 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::total 54708.423326 # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 0 # number of replacements system.l2c.tags.replacements 0 # number of replacements
system.l2c.tags.tagsinuse 1940.317854 # Cycle average of tags in use system.l2c.tags.tagsinuse 1940.317854 # Cycle average of tags in use
system.l2c.tags.total_refs 1068 # Total number of references to valid blocks. system.l2c.tags.total_refs 1068 # Total number of references to valid blocks.
@ -1431,8 +1407,6 @@ system.l2c.blocked::no_mshrs 0 # nu
system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.ReadExReq_mshr_misses::cpu0.data 139 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 139 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 139 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 139 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 139 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu2.data 139 # number of ReadExReq MSHR misses
@ -1565,7 +1539,6 @@ system.l2c.overall_avg_mshr_miss_latency::cpu2.data 49505.506608
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 49555.831266 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 49555.831266 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49507.709251 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49507.709251 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 49519.690782 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 49519.690782 # average overall mshr miss latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadResp 2872 # Transaction distribution system.membus.trans_dist::ReadResp 2872 # Transaction distribution
system.membus.trans_dist::ReadExReq 556 # Transaction distribution system.membus.trans_dist::ReadExReq 556 # Transaction distribution
system.membus.trans_dist::ReadExResp 556 # Transaction distribution system.membus.trans_dist::ReadExResp 556 # Transaction distribution