sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

page_table.cc is a syscall only kinda thing

Browse source 
fix tlbs for newmem

SConscript:
    page_table.cc is a syscall only kinda thing
arch/alpha/tlb.cc:
arch/alpha/tlb.hh:
    fix tlbs for newmem

--HG--
extra : convert_revision : 0aafcb9698b993a807be883bde1696ee4d33b408
This commit is contained in:
Ali Saidi 2006-03-29 18:42:53 -05:00
parent 3dcb589ea4
commit 2ad1db3fde
3 changed files with 8 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
SConscript
View file

@ -90,7 +90,6 @@ base_sources = Split('''
mem/connector.cc
mem/mem_object.cc
mem/page_table.cc
mem/physical.cc
mem/port.cc
mem/translating_port.cc
@ -255,6 +254,7 @@ turbolaser_sources = Split('''
# Syscall emulation (non-full-system) sources
syscall_emulation_sources = Split('''
kern/linux/linux.cc
mem/page_table.cc
sim/process.cc
sim/syscall_emul.cc
''')

6
arch/alpha/tlb.cc
View file

@ -94,7 +94,7 @@ AlphaTLB::lookup(Addr vpn, uint8_t asn) const
void
AlphaTLB::checkCacheability(MemReqPtr &req)
AlphaTLB::checkCacheability(CpuRequestPtr &req)
{
// in Alpha, cacheability is controlled by upper-level bits of the
// physical address
@ -292,7 +292,7 @@ AlphaITB::regStats()
Fault
AlphaITB::translate(MemReqPtr &req) const
AlphaITB::translate(CpuRequestPtr &req) const
{
ExecContext *xc = req->xc;
@ -451,7 +451,7 @@ AlphaDTB::regStats()
}
Fault
AlphaDTB::translate(MemReqPtr &req, bool write) const
AlphaDTB::translate(CpuRequestPtr &req, bool write) const
{
ExecContext *xc = req->xc;
Addr pc = xc->readPC();

8
arch/alpha/tlb.hh
View file

@ -35,7 +35,7 @@
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/faults.hh"
#include "base/statistics.hh"
#include "mem/mem_req.hh"
#include "mem/request.hh"
#include "sim/sim_object.hh"
class ExecContext;
@ -73,7 +73,7 @@ class AlphaTLB : public SimObject
return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
}
static void checkCacheability(MemReqPtr &req);
static void checkCacheability(CpuRequestPtr &req);
// Checkpointing
virtual void serialize(std::ostream &os);
@ -92,7 +92,7 @@ class AlphaITB : public AlphaTLB
AlphaITB(const std::string &name, int size);
virtual void regStats();
Fault translate(MemReqPtr &req) const;
Fault translate(CpuRequestPtr &req) const;
};
class AlphaDTB : public AlphaTLB
@ -115,7 +115,7 @@ class AlphaDTB : public AlphaTLB
AlphaDTB(const std::string &name, int size);
virtual void regStats();
Fault translate(MemReqPtr &req, bool write) const;
Fault translate(CpuRequestPtr &req, bool write) const;
};
#endif // __ALPHA_MEMORY_HH__