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arm: Fix incorrect TLB permission check in aarch32

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The TLB currently assumes that the pxn bit in an LPAE page descriptor
disables execution from unprivileged mode. However, according to the
architecture manual, this bit should disable execution from privileged
modes. Update the TLB implementation to reflect this behavior.

Change-Id: I7f1bb232d7a94a93fd601a9230223195ac952947
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
This commit is contained in:
Andreas Sandberg 2016-05-26 17:38:15 +01:00
parent e360f4db07
commit 2ace05044c
1 changed files with 2 additions and 2 deletions
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4
src/arch/arm/tlb.cc
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2010-2013 ARM Limited * Copyright (c) 2010-2013, 2016 ARM Limited
* All rights reserved * All rights reserved
* *
* The license below extends only to copyright in the software and shall * The license below extends only to copyright in the software and shall
@ -720,7 +720,7 @@ TLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode)
bool xn = te->xn || (isWritable && sctlr.wxn) || bool xn = te->xn || (isWritable && sctlr.wxn) ||
(ap == 3 && sctlr.uwxn && is_priv); (ap == 3 && sctlr.uwxn && is_priv);
if (is_fetch && (abt || xn || if (is_fetch && (abt || xn ||
(te->longDescFormat && te->pxn && !is_priv) || (te->longDescFormat && te->pxn && is_priv) ||
(isSecure && te->ns && scr.sif))) { (isSecure && te->ns && scr.sif))) {
permsFaults++; permsFaults++;
DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d " DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d "