misc: Add explicit overrides and fix other clang >= 3.5 issues
This patch adds explicit overrides as this is now required when using "-Wall" with clang >= 3.5, the latter now part of the most recent XCode. The patch consequently removes "virtual" for those methods where "override" is added. The latter should be enough of an indication. As part of this patch, a few minor issues that clang >= 3.5 complains about are also resolved (unused methods and variables).
This commit is contained in:
parent
22c04190c6
commit
2ac04c11ac
58 changed files with 307 additions and 305 deletions
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@ -43,16 +43,17 @@ class AlphaLiveProcess : public LiveProcess
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AlphaLiveProcess(LiveProcessParams *params, ObjectFile *objFile);
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AlphaLiveProcess(LiveProcessParams *params, ObjectFile *objFile);
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void loadState(CheckpointIn &cp) override;
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void loadState(CheckpointIn &cp) override;
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void initState();
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void initState() override;
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void argsInit(int intSize, int pageSize);
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void argsInit(int intSize, int pageSize);
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public:
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public:
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AlphaISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
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AlphaISA::IntReg getSyscallArg(ThreadContext *tc, int &i) override;
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/// Explicitly import the otherwise hidden getSyscallArg
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/// Explicitly import the otherwise hidden getSyscallArg
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using LiveProcess::getSyscallArg;
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using LiveProcess::getSyscallArg;
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void setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val);
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void setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val) override;
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void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
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void setSyscallReturn(ThreadContext *tc,
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SyscallReturn return_value) override;
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};
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};
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/* No architectural page table defined for this ISA */
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/* No architectural page table defined for this ISA */
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@ -55,7 +55,7 @@ class AlphaSystem : public System
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/**
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/**
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* Initialise the state of the system.
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* Initialise the state of the system.
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*/
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*/
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virtual void initState();
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void initState() override;
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/**
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/**
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* Serialization stuff
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* Serialization stuff
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@ -65,7 +65,7 @@ class AlphaSystem : public System
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/** Override startup() to provide a path to call setupFuncEvents()
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/** Override startup() to provide a path to call setupFuncEvents()
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*/
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*/
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virtual void startup();
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void startup() override;
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/**
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/**
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* Set the m5AlphaAccess pointer in the console
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* Set the m5AlphaAccess pointer in the console
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@ -121,7 +121,7 @@ class AlphaSystem : public System
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return addFuncEvent<T>(consoleSymtab, lbl);
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return addFuncEvent<T>(consoleSymtab, lbl);
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}
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}
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virtual Addr fixFuncEventAddr(Addr addr);
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Addr fixFuncEventAddr(Addr addr) override;
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public:
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public:
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void setIntrFreq(Tick freq) { intrFreq = freq; }
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void setIntrFreq(Tick freq) { intrFreq = freq; }
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@ -85,21 +85,21 @@ class TLB : public BaseTLB
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TLB(const Params *p);
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TLB(const Params *p);
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virtual ~TLB();
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virtual ~TLB();
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void takeOverFrom(BaseTLB *otlb) {}
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void takeOverFrom(BaseTLB *otlb) override {}
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virtual void regStats();
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void regStats() override;
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int getsize() const { return table.size(); }
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int getsize() const { return table.size(); }
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TlbEntry &index(bool advance = true);
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TlbEntry &index(bool advance = true);
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void insert(Addr vaddr, TlbEntry &entry);
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void insert(Addr vaddr, TlbEntry &entry);
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void flushAll();
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void flushAll() override;
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void flushProcesses();
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void flushProcesses();
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void flushAddr(Addr addr, uint8_t asn);
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void flushAddr(Addr addr, uint8_t asn);
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void
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void
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demapPage(Addr vaddr, uint64_t asn)
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demapPage(Addr vaddr, uint64_t asn) override
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{
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{
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assert(asn < (1 << 8));
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assert(asn < (1 << 8));
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flushAddr(vaddr, asn);
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flushAddr(vaddr, asn);
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@ -884,7 +884,7 @@ class TableWalker : public MemObject
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return dynamic_cast<const Params *>(_params);
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return dynamic_cast<const Params *>(_params);
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}
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}
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virtual void init();
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void init() override;
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bool haveLPAE() const { return _haveLPAE; }
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bool haveLPAE() const { return _haveLPAE; }
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bool haveVirtualization() const { return _haveVirtualization; }
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bool haveVirtualization() const { return _haveVirtualization; }
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@ -892,12 +892,12 @@ class TableWalker : public MemObject
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/** Checks if all state is cleared and if so, completes drain */
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/** Checks if all state is cleared and if so, completes drain */
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void completeDrain();
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void completeDrain();
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DrainState drain() override;
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DrainState drain() override;
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virtual void drainResume() override;
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void drainResume() override;
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virtual BaseMasterPort& getMasterPort(const std::string &if_name,
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BaseMasterPort& getMasterPort(const std::string &if_name,
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PortID idx = InvalidPortID);
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PortID idx = InvalidPortID) override;
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void regStats();
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void regStats() override;
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Fault walk(RequestPtr req, ThreadContext *tc, uint16_t asid, uint8_t _vmid,
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Fault walk(RequestPtr req, ThreadContext *tc, uint16_t asid, uint8_t _vmid,
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bool _isHyp, TLB::Mode mode, TLB::Translation *_trans,
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bool _isHyp, TLB::Mode mode, TLB::Translation *_trans,
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@ -155,10 +155,10 @@ class TLB : public BaseTLB
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virtual ~TLB();
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virtual ~TLB();
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void takeOverFrom(BaseTLB *otlb);
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void takeOverFrom(BaseTLB *otlb) override;
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/// setup all the back pointers
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/// setup all the back pointers
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virtual void init();
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void init() override;
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TableWalker *getTableWalker() { return tableWalker; }
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TableWalker *getTableWalker() { return tableWalker; }
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@ -197,7 +197,7 @@ class TLB : public BaseTLB
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/** Reset the entire TLB. Used for CPU switching to prevent stale
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/** Reset the entire TLB. Used for CPU switching to prevent stale
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* translations after multiple switches
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* translations after multiple switches
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*/
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*/
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void flushAll()
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void flushAll() override
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{
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{
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flushAllSecurity(false, 0, true);
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flushAllSecurity(false, 0, true);
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flushAllSecurity(true, 0, true);
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flushAllSecurity(true, 0, true);
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@ -230,14 +230,12 @@ class TLB : public BaseTLB
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void printTlb() const;
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void printTlb() const;
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void demapPage(Addr vaddr, uint64_t asn)
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void demapPage(Addr vaddr, uint64_t asn) override
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{
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{
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// needed for x86 only
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// needed for x86 only
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panic("demapPage() is not implemented.\n");
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panic("demapPage() is not implemented.\n");
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}
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}
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static bool validVirtualAddress(Addr vaddr);
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/**
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/**
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* Do a functional lookup on the TLB (for debugging)
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* Do a functional lookup on the TLB (for debugging)
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* and don't modify any internal state
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* and don't modify any internal state
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@ -290,7 +288,7 @@ class TLB : public BaseTLB
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void serialize(CheckpointOut &cp) const override;
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void serialize(CheckpointOut &cp) const override;
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void unserialize(CheckpointIn &cp) override;
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void unserialize(CheckpointIn &cp) override;
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void regStats();
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void regStats() override;
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void regProbePoints() override;
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void regProbePoints() override;
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@ -304,7 +302,7 @@ class TLB : public BaseTLB
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*
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*
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* @return A pointer to the walker master port
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* @return A pointer to the walker master port
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*/
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*/
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virtual BaseMasterPort* getMasterPort();
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BaseMasterPort* getMasterPort() override;
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// Caching misc register values here.
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// Caching misc register values here.
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// Writing to misc registers needs to invalidate them.
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// Writing to misc registers needs to invalidate them.
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@ -123,7 +123,7 @@ class GenericTLB : public BaseTLB
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{}
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{}
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public:
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public:
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void demapPage(Addr vaddr, uint64_t asn);
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void demapPage(Addr vaddr, uint64_t asn) override;
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Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
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Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
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void translateTiming(RequestPtr req, ThreadContext *tc,
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void translateTiming(RequestPtr req, ThreadContext *tc,
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@ -189,7 +189,7 @@ class BaseCPU : public MemObject
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* @return a reference to the port with the given name
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* @return a reference to the port with the given name
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*/
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*/
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BaseMasterPort &getMasterPort(const std::string &if_name,
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BaseMasterPort &getMasterPort(const std::string &if_name,
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PortID idx = InvalidPortID);
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PortID idx = InvalidPortID) override;
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/** Get cpu task id */
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/** Get cpu task id */
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uint32_t taskId() const { return _taskId; }
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uint32_t taskId() const { return _taskId; }
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@ -303,9 +303,9 @@ class BaseCPU : public MemObject
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BaseCPU(Params *params, bool is_checker = false);
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BaseCPU(Params *params, bool is_checker = false);
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virtual ~BaseCPU();
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virtual ~BaseCPU();
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virtual void init();
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void init() override;
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virtual void startup();
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void startup() override;
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virtual void regStats();
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void regStats() override;
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void regProbePoints() override;
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void regProbePoints() override;
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@ -98,7 +98,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
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/** id attached to all issued requests */
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/** id attached to all issued requests */
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MasterID masterId;
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MasterID masterId;
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public:
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public:
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virtual void init();
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void init() override;
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typedef CheckerCPUParams Params;
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typedef CheckerCPUParams Params;
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CheckerCPU(Params *p);
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CheckerCPU(Params *p);
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@ -110,7 +110,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
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void setDcachePort(MasterPort *dcache_port);
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void setDcachePort(MasterPort *dcache_port);
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MasterPort &getDataPort()
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MasterPort &getDataPort() override
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{
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{
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// the checker does not have ports on its own so return the
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// the checker does not have ports on its own so return the
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// data port of the actual CPU core
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// data port of the actual CPU core
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@ -118,7 +118,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
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return *dcachePort;
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return *dcachePort;
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}
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}
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MasterPort &getInstPort()
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MasterPort &getInstPort() override
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{
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{
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// the checker does not have ports on its own so return the
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// the checker does not have ports on its own so return the
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// data port of the actual CPU core
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// data port of the actual CPU core
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@ -175,12 +175,12 @@ class CheckerCPU : public BaseCPU, public ExecContext
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TheISA::TLB* getITBPtr() { return itb; }
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TheISA::TLB* getITBPtr() { return itb; }
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TheISA::TLB* getDTBPtr() { return dtb; }
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TheISA::TLB* getDTBPtr() { return dtb; }
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virtual Counter totalInsts() const
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virtual Counter totalInsts() const override
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{
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{
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return 0;
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return 0;
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}
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}
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virtual Counter totalOps() const
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virtual Counter totalOps() const override
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{
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{
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return 0;
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return 0;
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}
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}
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@ -194,8 +194,10 @@ class CheckerCPU : public BaseCPU, public ExecContext
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// These functions are only used in CPU models that split
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// These functions are only used in CPU models that split
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// effective address computation from the actual memory access.
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// effective address computation from the actual memory access.
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void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
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void setEA(Addr EA) override
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Addr getEA() const { panic("SimpleCPU::getEA() not implemented\n"); }
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{ panic("CheckerCPU::setEA() not implemented\n"); }
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Addr getEA() const override
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{ panic("CheckerCPU::getEA() not implemented\n"); }
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// The register accessor methods provide the index of the
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// The register accessor methods provide the index of the
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// instruction's operand (e.g., 0 or 1), not the architectural
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// instruction's operand (e.g., 0 or 1), not the architectural
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// storage (which is pretty hard to imagine they would have reason
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// storage (which is pretty hard to imagine they would have reason
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// to do).
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// to do).
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IntReg readIntRegOperand(const StaticInst *si, int idx)
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IntReg readIntRegOperand(const StaticInst *si, int idx) override
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{
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{
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return thread->readIntReg(si->srcRegIdx(idx));
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return thread->readIntReg(si->srcRegIdx(idx));
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}
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}
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FloatReg readFloatRegOperand(const StaticInst *si, int idx)
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FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
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{
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{
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int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
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int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
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return thread->readFloatReg(reg_idx);
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return thread->readFloatReg(reg_idx);
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}
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}
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FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
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FloatRegBits readFloatRegOperandBits(const StaticInst *si,
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int idx) override
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{
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{
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int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
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int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
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return thread->readFloatRegBits(reg_idx);
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return thread->readFloatRegBits(reg_idx);
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}
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}
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CCReg readCCRegOperand(const StaticInst *si, int idx)
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CCReg readCCRegOperand(const StaticInst *si, int idx) override
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{
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{
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int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
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int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
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return thread->readCCReg(reg_idx);
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return thread->readCCReg(reg_idx);
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result.push(instRes);
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result.push(instRes);
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}
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}
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void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
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void setIntRegOperand(const StaticInst *si, int idx,
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IntReg val) override
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{
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{
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thread->setIntReg(si->destRegIdx(idx), val);
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thread->setIntReg(si->destRegIdx(idx), val);
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setResult<uint64_t>(val);
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setResult<uint64_t>(val);
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}
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}
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void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
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void setFloatRegOperand(const StaticInst *si, int idx,
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FloatReg val) override
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{
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{
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int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
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int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
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thread->setFloatReg(reg_idx, val);
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thread->setFloatReg(reg_idx, val);
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}
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}
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void setFloatRegOperandBits(const StaticInst *si, int idx,
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void setFloatRegOperandBits(const StaticInst *si, int idx,
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FloatRegBits val)
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FloatRegBits val) override
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{
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{
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int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
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int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
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thread->setFloatRegBits(reg_idx, val);
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thread->setFloatRegBits(reg_idx, val);
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setResult<uint64_t>(val);
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setResult<uint64_t>(val);
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}
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}
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void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
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void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
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{
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{
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int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
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int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
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thread->setCCReg(reg_idx, val);
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thread->setCCReg(reg_idx, val);
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setResult<uint64_t>(val);
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setResult<uint64_t>(val);
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}
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}
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bool readPredicate() { return thread->readPredicate(); }
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bool readPredicate() override { return thread->readPredicate(); }
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void setPredicate(bool val)
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void setPredicate(bool val) override
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{
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{
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thread->setPredicate(val);
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thread->setPredicate(val);
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}
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}
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TheISA::PCState pcState() const { return thread->pcState(); }
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TheISA::PCState pcState() const override { return thread->pcState(); }
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void pcState(const TheISA::PCState &val)
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void pcState(const TheISA::PCState &val) override
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{
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{
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DPRINTF(Checker, "Changing PC to %s, old PC %s.\n",
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DPRINTF(Checker, "Changing PC to %s, old PC %s.\n",
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val, thread->pcState());
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val, thread->pcState());
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@ -290,7 +295,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
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return thread->readMiscRegNoEffect(misc_reg);
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return thread->readMiscRegNoEffect(misc_reg);
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}
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}
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MiscReg readMiscReg(int misc_reg)
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MiscReg readMiscReg(int misc_reg) override
|
||||||
{
|
{
|
||||||
return thread->readMiscReg(misc_reg);
|
return thread->readMiscReg(misc_reg);
|
||||||
}
|
}
|
||||||
|
@ -302,21 +307,21 @@ class CheckerCPU : public BaseCPU, public ExecContext
|
||||||
return thread->setMiscRegNoEffect(misc_reg, val);
|
return thread->setMiscRegNoEffect(misc_reg, val);
|
||||||
}
|
}
|
||||||
|
|
||||||
void setMiscReg(int misc_reg, const MiscReg &val)
|
void setMiscReg(int misc_reg, const MiscReg &val) override
|
||||||
{
|
{
|
||||||
DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg);
|
DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg);
|
||||||
miscRegIdxs.push(misc_reg);
|
miscRegIdxs.push(misc_reg);
|
||||||
return thread->setMiscReg(misc_reg, val);
|
return thread->setMiscReg(misc_reg, val);
|
||||||
}
|
}
|
||||||
|
|
||||||
MiscReg readMiscRegOperand(const StaticInst *si, int idx)
|
MiscReg readMiscRegOperand(const StaticInst *si, int idx) override
|
||||||
{
|
{
|
||||||
int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
|
int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
|
||||||
return thread->readMiscReg(reg_idx);
|
return thread->readMiscReg(reg_idx);
|
||||||
}
|
}
|
||||||
|
|
||||||
void setMiscRegOperand(
|
void setMiscRegOperand(const StaticInst *si, int idx,
|
||||||
const StaticInst *si, int idx, const MiscReg &val)
|
const MiscReg &val) override
|
||||||
{
|
{
|
||||||
int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
|
int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
|
||||||
return this->setMiscReg(reg_idx, val);
|
return this->setMiscReg(reg_idx, val);
|
||||||
|
@ -343,18 +348,20 @@ class CheckerCPU : public BaseCPU, public ExecContext
|
||||||
newPCState = val;
|
newPCState = val;
|
||||||
}
|
}
|
||||||
|
|
||||||
void demapPage(Addr vaddr, uint64_t asn)
|
void demapPage(Addr vaddr, uint64_t asn) override
|
||||||
{
|
{
|
||||||
this->itb->demapPage(vaddr, asn);
|
this->itb->demapPage(vaddr, asn);
|
||||||
this->dtb->demapPage(vaddr, asn);
|
this->dtb->demapPage(vaddr, asn);
|
||||||
}
|
}
|
||||||
|
|
||||||
// monitor/mwait funtions
|
// monitor/mwait funtions
|
||||||
virtual void armMonitor(Addr address) { BaseCPU::armMonitor(0, address); }
|
void armMonitor(Addr address) override
|
||||||
bool mwait(PacketPtr pkt) { return BaseCPU::mwait(0, pkt); }
|
{ BaseCPU::armMonitor(0, address); }
|
||||||
void mwaitAtomic(ThreadContext *tc)
|
bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); }
|
||||||
|
void mwaitAtomic(ThreadContext *tc) override
|
||||||
{ return BaseCPU::mwaitAtomic(0, tc, thread->dtb); }
|
{ return BaseCPU::mwaitAtomic(0, tc, thread->dtb); }
|
||||||
AddressMonitor *getAddrMonitor() { return BaseCPU::getCpuAddrMonitor(0); }
|
AddressMonitor *getAddrMonitor() override
|
||||||
|
{ return BaseCPU::getCpuAddrMonitor(0); }
|
||||||
|
|
||||||
void demapInstPage(Addr vaddr, uint64_t asn)
|
void demapInstPage(Addr vaddr, uint64_t asn)
|
||||||
{
|
{
|
||||||
|
@ -366,24 +373,26 @@ class CheckerCPU : public BaseCPU, public ExecContext
|
||||||
this->dtb->demapPage(vaddr, asn);
|
this->dtb->demapPage(vaddr, asn);
|
||||||
}
|
}
|
||||||
|
|
||||||
Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
|
Fault readMem(Addr addr, uint8_t *data, unsigned size,
|
||||||
|
unsigned flags) override;
|
||||||
Fault writeMem(uint8_t *data, unsigned size,
|
Fault writeMem(uint8_t *data, unsigned size,
|
||||||
Addr addr, unsigned flags, uint64_t *res);
|
Addr addr, unsigned flags, uint64_t *res) override;
|
||||||
|
|
||||||
unsigned int readStCondFailures() const {
|
unsigned int readStCondFailures() const override {
|
||||||
return thread->readStCondFailures();
|
return thread->readStCondFailures();
|
||||||
}
|
}
|
||||||
|
|
||||||
void setStCondFailures(unsigned int sc_failures)
|
void setStCondFailures(unsigned int sc_failures) override
|
||||||
{}
|
{}
|
||||||
/////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////
|
||||||
|
|
||||||
Fault hwrei() { return thread->hwrei(); }
|
Fault hwrei() override { return thread->hwrei(); }
|
||||||
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
|
bool simPalCheck(int palFunc) override
|
||||||
|
{ return thread->simPalCheck(palFunc); }
|
||||||
void wakeup(ThreadID tid) override { }
|
void wakeup(ThreadID tid) override { }
|
||||||
// Assume that the normal CPU's call to syscall was successful.
|
// Assume that the normal CPU's call to syscall was successful.
|
||||||
// The checker's state would have already been updated by the syscall.
|
// The checker's state would have already been updated by the syscall.
|
||||||
void syscall(int64_t callnum) { }
|
void syscall(int64_t callnum) override { }
|
||||||
|
|
||||||
void handleError()
|
void handleError()
|
||||||
{
|
{
|
||||||
|
@ -396,7 +405,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
|
||||||
|
|
||||||
void dumpAndExit();
|
void dumpAndExit();
|
||||||
|
|
||||||
ThreadContext *tcBase() { return tc; }
|
ThreadContext *tcBase() override { return tc; }
|
||||||
SimpleThread *threadBase() { return thread; }
|
SimpleThread *threadBase() { return thread; }
|
||||||
|
|
||||||
Result unverifiedResult;
|
Result unverifiedResult;
|
||||||
|
|
|
@ -114,10 +114,10 @@ class MinorCPU : public BaseCPU
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
/** Return a reference to the data port. */
|
/** Return a reference to the data port. */
|
||||||
MasterPort &getDataPort();
|
MasterPort &getDataPort() override;
|
||||||
|
|
||||||
/** Return a reference to the instruction port. */
|
/** Return a reference to the instruction port. */
|
||||||
MasterPort &getInstPort();
|
MasterPort &getInstPort() override;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
MinorCPU(MinorCPUParams *params);
|
MinorCPU(MinorCPUParams *params);
|
||||||
|
@ -126,8 +126,8 @@ class MinorCPU : public BaseCPU
|
||||||
|
|
||||||
public:
|
public:
|
||||||
/** Starting, waking and initialisation */
|
/** Starting, waking and initialisation */
|
||||||
void init();
|
void init() override;
|
||||||
void startup();
|
void startup() override;
|
||||||
void wakeup(ThreadID tid) override;
|
void wakeup(ThreadID tid) override;
|
||||||
|
|
||||||
Addr dbg_vtophys(Addr addr);
|
Addr dbg_vtophys(Addr addr);
|
||||||
|
@ -136,18 +136,18 @@ class MinorCPU : public BaseCPU
|
||||||
Minor::MinorStats stats;
|
Minor::MinorStats stats;
|
||||||
|
|
||||||
/** Stats interface from SimObject (by way of BaseCPU) */
|
/** Stats interface from SimObject (by way of BaseCPU) */
|
||||||
void regStats();
|
void regStats() override;
|
||||||
|
|
||||||
/** Simple inst count interface from BaseCPU */
|
/** Simple inst count interface from BaseCPU */
|
||||||
Counter totalInsts() const;
|
Counter totalInsts() const override;
|
||||||
Counter totalOps() const;
|
Counter totalOps() const override;
|
||||||
|
|
||||||
void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
|
void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
|
||||||
void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
|
void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
|
||||||
|
|
||||||
/** Serialize pipeline data */
|
/** Serialize pipeline data */
|
||||||
void serialize(CheckpointOut &cp) const;
|
void serialize(CheckpointOut &cp) const override;
|
||||||
void unserialize(CheckpointIn &cp);
|
void unserialize(CheckpointIn &cp) override;
|
||||||
|
|
||||||
/** Drain interface */
|
/** Drain interface */
|
||||||
DrainState drain() override;
|
DrainState drain() override;
|
||||||
|
@ -155,15 +155,15 @@ class MinorCPU : public BaseCPU
|
||||||
/** Signal from Pipeline that MinorCPU should signal that a drain
|
/** Signal from Pipeline that MinorCPU should signal that a drain
|
||||||
* is complete and set its drainState */
|
* is complete and set its drainState */
|
||||||
void signalDrainDone();
|
void signalDrainDone();
|
||||||
void memWriteback();
|
void memWriteback() override;
|
||||||
|
|
||||||
/** Switching interface from BaseCPU */
|
/** Switching interface from BaseCPU */
|
||||||
void switchOut();
|
void switchOut() override;
|
||||||
void takeOverFrom(BaseCPU *old_cpu);
|
void takeOverFrom(BaseCPU *old_cpu) override;
|
||||||
|
|
||||||
/** Thread activation interface from BaseCPU. */
|
/** Thread activation interface from BaseCPU. */
|
||||||
void activateContext(ThreadID thread_id);
|
void activateContext(ThreadID thread_id) override;
|
||||||
void suspendContext(ThreadID thread_id);
|
void suspendContext(ThreadID thread_id) override;
|
||||||
|
|
||||||
/** Interface for stages to signal that they have become active after
|
/** Interface for stages to signal that they have become active after
|
||||||
* a callback or eventq event where the pipeline itself may have
|
* a callback or eventq event where the pipeline itself may have
|
||||||
|
|
|
@ -223,7 +223,7 @@ FUPipeline::findTiming(const StaticInstPtr &inst)
|
||||||
"Found extra timing match (pattern %d '%s')"
|
"Found extra timing match (pattern %d '%s')"
|
||||||
" %s %16x (type %s)\n",
|
" %s %16x (type %s)\n",
|
||||||
i, timing.description, inst->disassemble(0), mach_inst,
|
i, timing.description, inst->disassemble(0), mach_inst,
|
||||||
typeid(*inst).name());
|
typeid(inst).name());
|
||||||
|
|
||||||
return &timing;
|
return &timing;
|
||||||
}
|
}
|
||||||
|
|
|
@ -124,7 +124,7 @@ class Pipeline : public Ticked
|
||||||
|
|
||||||
/** A custom evaluate allows report in the right place (between
|
/** A custom evaluate allows report in the right place (between
|
||||||
* stages and pipeline advance) */
|
* stages and pipeline advance) */
|
||||||
void evaluate();
|
void evaluate() override;
|
||||||
|
|
||||||
void countCycles(Cycles delta) override
|
void countCycles(Cycles delta) override
|
||||||
{
|
{
|
||||||
|
|
|
@ -265,13 +265,13 @@ class FullO3CPU : public BaseO3CPU
|
||||||
~FullO3CPU();
|
~FullO3CPU();
|
||||||
|
|
||||||
/** Registers statistics. */
|
/** Registers statistics. */
|
||||||
void regStats();
|
void regStats() override;
|
||||||
|
|
||||||
ProbePointArg<PacketPtr> *ppInstAccessComplete;
|
ProbePointArg<PacketPtr> *ppInstAccessComplete;
|
||||||
ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
|
ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
|
||||||
|
|
||||||
/** Register probe points. */
|
/** Register probe points. */
|
||||||
void regProbePoints();
|
void regProbePoints() override;
|
||||||
|
|
||||||
void demapPage(Addr vaddr, uint64_t asn)
|
void demapPage(Addr vaddr, uint64_t asn)
|
||||||
{
|
{
|
||||||
|
@ -295,9 +295,9 @@ class FullO3CPU : public BaseO3CPU
|
||||||
void tick();
|
void tick();
|
||||||
|
|
||||||
/** Initialize the CPU */
|
/** Initialize the CPU */
|
||||||
void init();
|
void init() override;
|
||||||
|
|
||||||
void startup();
|
void startup() override;
|
||||||
|
|
||||||
/** Returns the Number of Active Threads in the CPU */
|
/** Returns the Number of Active Threads in the CPU */
|
||||||
int numActiveThreads()
|
int numActiveThreads()
|
||||||
|
@ -316,21 +316,21 @@ class FullO3CPU : public BaseO3CPU
|
||||||
void removeThread(ThreadID tid);
|
void removeThread(ThreadID tid);
|
||||||
|
|
||||||
/** Count the Total Instructions Committed in the CPU. */
|
/** Count the Total Instructions Committed in the CPU. */
|
||||||
virtual Counter totalInsts() const;
|
Counter totalInsts() const override;
|
||||||
|
|
||||||
/** Count the Total Ops (including micro ops) committed in the CPU. */
|
/** Count the Total Ops (including micro ops) committed in the CPU. */
|
||||||
virtual Counter totalOps() const;
|
Counter totalOps() const override;
|
||||||
|
|
||||||
/** Add Thread to Active Threads List. */
|
/** Add Thread to Active Threads List. */
|
||||||
void activateContext(ThreadID tid);
|
void activateContext(ThreadID tid) override;
|
||||||
|
|
||||||
/** Remove Thread from Active Threads List */
|
/** Remove Thread from Active Threads List */
|
||||||
void suspendContext(ThreadID tid);
|
void suspendContext(ThreadID tid) override;
|
||||||
|
|
||||||
/** Remove Thread from Active Threads List &&
|
/** Remove Thread from Active Threads List &&
|
||||||
* Remove Thread Context from CPU.
|
* Remove Thread Context from CPU.
|
||||||
*/
|
*/
|
||||||
void haltContext(ThreadID tid);
|
void haltContext(ThreadID tid) override;
|
||||||
|
|
||||||
/** Update The Order In Which We Process Threads. */
|
/** Update The Order In Which We Process Threads. */
|
||||||
void updateThreadPriority();
|
void updateThreadPriority();
|
||||||
|
@ -364,12 +364,12 @@ class FullO3CPU : public BaseO3CPU
|
||||||
void commitDrained(ThreadID tid);
|
void commitDrained(ThreadID tid);
|
||||||
|
|
||||||
/** Switches out this CPU. */
|
/** Switches out this CPU. */
|
||||||
virtual void switchOut();
|
void switchOut() override;
|
||||||
|
|
||||||
/** Takes over from another CPU. */
|
/** Takes over from another CPU. */
|
||||||
virtual void takeOverFrom(BaseCPU *oldCPU);
|
void takeOverFrom(BaseCPU *oldCPU) override;
|
||||||
|
|
||||||
void verifyMemoryMode() const;
|
void verifyMemoryMode() const override;
|
||||||
|
|
||||||
/** Get the current instruction sequence number, and increment it. */
|
/** Get the current instruction sequence number, and increment it. */
|
||||||
InstSeqNum getAndIncrementInstSeq()
|
InstSeqNum getAndIncrementInstSeq()
|
||||||
|
@ -392,12 +392,6 @@ class FullO3CPU : public BaseO3CPU
|
||||||
/** Halts the CPU. */
|
/** Halts the CPU. */
|
||||||
void halt() { panic("Halt not implemented!\n"); }
|
void halt() { panic("Halt not implemented!\n"); }
|
||||||
|
|
||||||
/** Check if this address is a valid instruction address. */
|
|
||||||
bool validInstAddr(Addr addr) { return true; }
|
|
||||||
|
|
||||||
/** Check if this address is a valid data address. */
|
|
||||||
bool validDataAddr(Addr addr) { return true; }
|
|
||||||
|
|
||||||
/** Register accessors. Index refers to the physical register index. */
|
/** Register accessors. Index refers to the physical register index. */
|
||||||
|
|
||||||
/** Reads a miscellaneous register. */
|
/** Reads a miscellaneous register. */
|
||||||
|
@ -699,10 +693,10 @@ class FullO3CPU : public BaseO3CPU
|
||||||
}
|
}
|
||||||
|
|
||||||
/** Used by the fetch unit to get a hold of the instruction port. */
|
/** Used by the fetch unit to get a hold of the instruction port. */
|
||||||
virtual MasterPort &getInstPort() { return icachePort; }
|
MasterPort &getInstPort() override { return icachePort; }
|
||||||
|
|
||||||
/** Get the dcache port (used to find block size for translations). */
|
/** Get the dcache port (used to find block size for translations). */
|
||||||
virtual MasterPort &getDataPort() { return dcachePort; }
|
MasterPort &getDataPort() override { return dcachePort; }
|
||||||
|
|
||||||
/** Stat for total number of times the CPU is descheduled. */
|
/** Stat for total number of times the CPU is descheduled. */
|
||||||
Stats::Scalar timesIdled;
|
Stats::Scalar timesIdled;
|
||||||
|
|
|
@ -75,7 +75,7 @@ class BPredUnit : public SimObject
|
||||||
/**
|
/**
|
||||||
* Registers statistics.
|
* Registers statistics.
|
||||||
*/
|
*/
|
||||||
void regStats();
|
void regStats() override;
|
||||||
|
|
||||||
void regProbePoints() override;
|
void regProbePoints() override;
|
||||||
|
|
||||||
|
|
|
@ -55,7 +55,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU
|
||||||
AtomicSimpleCPU(AtomicSimpleCPUParams *params);
|
AtomicSimpleCPU(AtomicSimpleCPUParams *params);
|
||||||
virtual ~AtomicSimpleCPU();
|
virtual ~AtomicSimpleCPU();
|
||||||
|
|
||||||
virtual void init();
|
void init() override;
|
||||||
|
|
||||||
private:
|
private:
|
||||||
|
|
||||||
|
@ -181,10 +181,10 @@ class AtomicSimpleCPU : public BaseSimpleCPU
|
||||||
protected:
|
protected:
|
||||||
|
|
||||||
/** Return a reference to the data port. */
|
/** Return a reference to the data port. */
|
||||||
virtual MasterPort &getDataPort() { return dcachePort; }
|
MasterPort &getDataPort() override { return dcachePort; }
|
||||||
|
|
||||||
/** Return a reference to the instruction port. */
|
/** Return a reference to the instruction port. */
|
||||||
virtual MasterPort &getInstPort() { return icachePort; }
|
MasterPort &getInstPort() override { return icachePort; }
|
||||||
|
|
||||||
/** Perform snoop for other cpu-local thread contexts. */
|
/** Perform snoop for other cpu-local thread contexts. */
|
||||||
void threadSnoop(PacketPtr pkt, ThreadID sender);
|
void threadSnoop(PacketPtr pkt, ThreadID sender);
|
||||||
|
@ -194,20 +194,21 @@ class AtomicSimpleCPU : public BaseSimpleCPU
|
||||||
DrainState drain() override;
|
DrainState drain() override;
|
||||||
void drainResume() override;
|
void drainResume() override;
|
||||||
|
|
||||||
void switchOut();
|
void switchOut() override;
|
||||||
void takeOverFrom(BaseCPU *oldCPU);
|
void takeOverFrom(BaseCPU *oldCPU) override;
|
||||||
|
|
||||||
void verifyMemoryMode() const;
|
void verifyMemoryMode() const override;
|
||||||
|
|
||||||
virtual void activateContext(ThreadID thread_num);
|
void activateContext(ThreadID thread_num) override;
|
||||||
virtual void suspendContext(ThreadID thread_num);
|
void suspendContext(ThreadID thread_num) override;
|
||||||
|
|
||||||
Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
|
Fault readMem(Addr addr, uint8_t *data, unsigned size,
|
||||||
|
unsigned flags) override;
|
||||||
|
|
||||||
Fault writeMem(uint8_t *data, unsigned size,
|
Fault writeMem(uint8_t *data, unsigned size,
|
||||||
Addr addr, unsigned flags, uint64_t *res);
|
Addr addr, unsigned flags, uint64_t *res) override;
|
||||||
|
|
||||||
virtual void regProbePoints();
|
void regProbePoints() override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Print state of address in memory system via PrintReq (for
|
* Print state of address in memory system via PrintReq (for
|
||||||
|
|
|
@ -94,7 +94,7 @@ class BaseSimpleCPU : public BaseCPU
|
||||||
BaseSimpleCPU(BaseSimpleCPUParams *params);
|
BaseSimpleCPU(BaseSimpleCPUParams *params);
|
||||||
virtual ~BaseSimpleCPU();
|
virtual ~BaseSimpleCPU();
|
||||||
void wakeup(ThreadID tid) override;
|
void wakeup(ThreadID tid) override;
|
||||||
virtual void init();
|
void init() override;
|
||||||
public:
|
public:
|
||||||
Trace::InstRecord *traceData;
|
Trace::InstRecord *traceData;
|
||||||
CheckerCPU *checker;
|
CheckerCPU *checker;
|
||||||
|
@ -134,13 +134,13 @@ class BaseSimpleCPU : public BaseCPU
|
||||||
void postExecute();
|
void postExecute();
|
||||||
void advancePC(const Fault &fault);
|
void advancePC(const Fault &fault);
|
||||||
|
|
||||||
virtual void haltContext(ThreadID thread_num);
|
void haltContext(ThreadID thread_num) override;
|
||||||
|
|
||||||
// statistics
|
// statistics
|
||||||
virtual void regStats();
|
void regStats() override;
|
||||||
virtual void resetStats();
|
void resetStats() override;
|
||||||
|
|
||||||
virtual void startup();
|
void startup() override;
|
||||||
|
|
||||||
virtual Fault readMem(Addr addr, uint8_t* data, unsigned size,
|
virtual Fault readMem(Addr addr, uint8_t* data, unsigned size,
|
||||||
unsigned flags) = 0;
|
unsigned flags) = 0;
|
||||||
|
@ -149,8 +149,8 @@ class BaseSimpleCPU : public BaseCPU
|
||||||
unsigned flags, uint64_t* res) = 0;
|
unsigned flags, uint64_t* res) = 0;
|
||||||
|
|
||||||
void countInst();
|
void countInst();
|
||||||
virtual Counter totalInsts() const;
|
Counter totalInsts() const override;
|
||||||
virtual Counter totalOps() const;
|
Counter totalOps() const override;
|
||||||
|
|
||||||
void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
|
void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
|
||||||
void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
|
void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
|
||||||
|
|
|
@ -55,7 +55,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
|
||||||
TimingSimpleCPU(TimingSimpleCPUParams * params);
|
TimingSimpleCPU(TimingSimpleCPUParams * params);
|
||||||
virtual ~TimingSimpleCPU();
|
virtual ~TimingSimpleCPU();
|
||||||
|
|
||||||
virtual void init();
|
void init() override;
|
||||||
|
|
||||||
private:
|
private:
|
||||||
|
|
||||||
|
@ -265,28 +265,29 @@ class TimingSimpleCPU : public BaseSimpleCPU
|
||||||
protected:
|
protected:
|
||||||
|
|
||||||
/** Return a reference to the data port. */
|
/** Return a reference to the data port. */
|
||||||
virtual MasterPort &getDataPort() { return dcachePort; }
|
MasterPort &getDataPort() override { return dcachePort; }
|
||||||
|
|
||||||
/** Return a reference to the instruction port. */
|
/** Return a reference to the instruction port. */
|
||||||
virtual MasterPort &getInstPort() { return icachePort; }
|
MasterPort &getInstPort() override { return icachePort; }
|
||||||
|
|
||||||
public:
|
public:
|
||||||
|
|
||||||
DrainState drain() override;
|
DrainState drain() override;
|
||||||
void drainResume() override;
|
void drainResume() override;
|
||||||
|
|
||||||
void switchOut();
|
void switchOut() override;
|
||||||
void takeOverFrom(BaseCPU *oldCPU);
|
void takeOverFrom(BaseCPU *oldCPU) override;
|
||||||
|
|
||||||
void verifyMemoryMode() const;
|
void verifyMemoryMode() const override;
|
||||||
|
|
||||||
virtual void activateContext(ThreadID thread_num);
|
void activateContext(ThreadID thread_num) override;
|
||||||
virtual void suspendContext(ThreadID thread_num);
|
void suspendContext(ThreadID thread_num) override;
|
||||||
|
|
||||||
Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
|
Fault readMem(Addr addr, uint8_t *data, unsigned size,
|
||||||
|
unsigned flags) override;
|
||||||
|
|
||||||
Fault writeMem(uint8_t *data, unsigned size,
|
Fault writeMem(uint8_t *data, unsigned size,
|
||||||
Addr addr, unsigned flags, uint64_t *res);
|
Addr addr, unsigned flags, uint64_t *res) override;
|
||||||
|
|
||||||
void fetch();
|
void fetch();
|
||||||
void sendFetch(const Fault &fault, RequestPtr req, ThreadContext *tc);
|
void sendFetch(const Fault &fault, RequestPtr req, ThreadContext *tc);
|
||||||
|
|
|
@ -192,12 +192,12 @@ class TrafficGen : public MemObject
|
||||||
|
|
||||||
~TrafficGen() {}
|
~TrafficGen() {}
|
||||||
|
|
||||||
virtual BaseMasterPort& getMasterPort(const std::string &if_name,
|
BaseMasterPort& getMasterPort(const std::string &if_name,
|
||||||
PortID idx = InvalidPortID);
|
PortID idx = InvalidPortID) override;
|
||||||
|
|
||||||
void init();
|
void init() override;
|
||||||
|
|
||||||
void initState();
|
void initState() override;
|
||||||
|
|
||||||
DrainState drain() override;
|
DrainState drain() override;
|
||||||
|
|
||||||
|
@ -205,7 +205,7 @@ class TrafficGen : public MemObject
|
||||||
void unserialize(CheckpointIn &cp) override;
|
void unserialize(CheckpointIn &cp) override;
|
||||||
|
|
||||||
/** Register statistics */
|
/** Register statistics */
|
||||||
void regStats();
|
void regStats() override;
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -107,13 +107,13 @@ class AlphaBackdoor : public BasicPioDevice
|
||||||
return dynamic_cast<const Params *>(_params);
|
return dynamic_cast<const Params *>(_params);
|
||||||
}
|
}
|
||||||
|
|
||||||
virtual void startup();
|
void startup() override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* memory mapped reads and writes
|
* memory mapped reads and writes
|
||||||
*/
|
*/
|
||||||
virtual Tick read(PacketPtr pkt);
|
Tick read(PacketPtr pkt) override;
|
||||||
virtual Tick write(PacketPtr pkt);
|
Tick write(PacketPtr pkt) override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* standard serialization routines for checkpointing
|
* standard serialization routines for checkpointing
|
||||||
|
|
|
@ -80,7 +80,7 @@ class Tsunami : public Platform
|
||||||
int intr_sum_type[Tsunami::Max_CPUs];
|
int intr_sum_type[Tsunami::Max_CPUs];
|
||||||
int ipi_pending[Tsunami::Max_CPUs];
|
int ipi_pending[Tsunami::Max_CPUs];
|
||||||
|
|
||||||
void init();
|
void init() override;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
typedef TsunamiParams Params;
|
typedef TsunamiParams Params;
|
||||||
|
@ -89,40 +89,40 @@ class Tsunami : public Platform
|
||||||
/**
|
/**
|
||||||
* Cause the cpu to post a serial interrupt to the CPU.
|
* Cause the cpu to post a serial interrupt to the CPU.
|
||||||
*/
|
*/
|
||||||
virtual void postConsoleInt();
|
void postConsoleInt() override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Clear a posted CPU interrupt (id=55)
|
* Clear a posted CPU interrupt (id=55)
|
||||||
*/
|
*/
|
||||||
virtual void clearConsoleInt();
|
void clearConsoleInt() override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Cause the chipset to post a cpi interrupt to the CPU.
|
* Cause the chipset to post a cpi interrupt to the CPU.
|
||||||
*/
|
*/
|
||||||
virtual void postPciInt(int line);
|
void postPciInt(int line) override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Clear a posted PCI->CPU interrupt
|
* Clear a posted PCI->CPU interrupt
|
||||||
*/
|
*/
|
||||||
virtual void clearPciInt(int line);
|
void clearPciInt(int line) override;
|
||||||
|
|
||||||
|
|
||||||
virtual Addr pciToDma(Addr pciAddr) const;
|
Addr pciToDma(Addr pciAddr) const override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Calculate the configuration address given a bus/dev/func.
|
* Calculate the configuration address given a bus/dev/func.
|
||||||
*/
|
*/
|
||||||
virtual Addr calcPciConfigAddr(int bus, int dev, int func);
|
Addr calcPciConfigAddr(int bus, int dev, int func) override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Calculate the address for an IO location on the PCI bus.
|
* Calculate the address for an IO location on the PCI bus.
|
||||||
*/
|
*/
|
||||||
virtual Addr calcPciIOAddr(Addr addr);
|
Addr calcPciIOAddr(Addr addr) override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Calculate the address for a memory location on the PCI bus.
|
* Calculate the address for a memory location on the PCI bus.
|
||||||
*/
|
*/
|
||||||
virtual Addr calcPciMemAddr(Addr addr);
|
Addr calcPciMemAddr(Addr addr) override;
|
||||||
|
|
||||||
void serialize(CheckpointOut &cp) const override;
|
void serialize(CheckpointOut &cp) const override;
|
||||||
void unserialize(CheckpointIn &cp) override;
|
void unserialize(CheckpointIn &cp) override;
|
||||||
|
|
|
@ -92,9 +92,9 @@ class TsunamiCChip : public BasicPioDevice
|
||||||
return dynamic_cast<const Params *>(_params);
|
return dynamic_cast<const Params *>(_params);
|
||||||
}
|
}
|
||||||
|
|
||||||
virtual Tick read(PacketPtr pkt);
|
Tick read(PacketPtr pkt) override;
|
||||||
|
|
||||||
virtual Tick write(PacketPtr pkt);
|
Tick write(PacketPtr pkt) override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* post an RTC interrupt to the CPU
|
* post an RTC interrupt to the CPU
|
||||||
|
|
|
@ -123,8 +123,8 @@ class TsunamiIO : public BasicPioDevice
|
||||||
return dynamic_cast<const Params *>(_params);
|
return dynamic_cast<const Params *>(_params);
|
||||||
}
|
}
|
||||||
|
|
||||||
virtual Tick read(PacketPtr pkt);
|
Tick read(PacketPtr pkt) override;
|
||||||
virtual Tick write(PacketPtr pkt);
|
Tick write(PacketPtr pkt) override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Post an PIC interrupt to the CPU via the CChip
|
* Post an PIC interrupt to the CPU via the CChip
|
||||||
|
@ -144,7 +144,7 @@ class TsunamiIO : public BasicPioDevice
|
||||||
/**
|
/**
|
||||||
* Start running.
|
* Start running.
|
||||||
*/
|
*/
|
||||||
virtual void startup();
|
void startup() override;
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -86,8 +86,8 @@ class TsunamiPChip : public BasicPioDevice
|
||||||
Addr calcIOAddr(Addr addr);
|
Addr calcIOAddr(Addr addr);
|
||||||
Addr calcMemAddr(Addr addr);
|
Addr calcMemAddr(Addr addr);
|
||||||
|
|
||||||
virtual Tick read(PacketPtr pkt);
|
Tick read(PacketPtr pkt) override;
|
||||||
virtual Tick write(PacketPtr pkt);
|
Tick write(PacketPtr pkt) override;
|
||||||
|
|
||||||
void serialize(CheckpointOut &cp) const override;
|
void serialize(CheckpointOut &cp) const override;
|
||||||
void unserialize(CheckpointIn &cp) override;
|
void unserialize(CheckpointIn &cp) override;
|
||||||
|
|
|
@ -196,13 +196,13 @@ class CopyEngine : public PciDevice
|
||||||
CopyEngine(const Params *params);
|
CopyEngine(const Params *params);
|
||||||
~CopyEngine();
|
~CopyEngine();
|
||||||
|
|
||||||
void regStats();
|
void regStats() override;
|
||||||
|
|
||||||
virtual BaseMasterPort &getMasterPort(const std::string &if_name,
|
BaseMasterPort &getMasterPort(const std::string &if_name,
|
||||||
PortID idx = InvalidPortID);
|
PortID idx = InvalidPortID) override;
|
||||||
|
|
||||||
virtual Tick read(PacketPtr pkt);
|
Tick read(PacketPtr pkt) override;
|
||||||
virtual Tick write(PacketPtr pkt);
|
Tick write(PacketPtr pkt) override;
|
||||||
|
|
||||||
void serialize(CheckpointOut &cp) const override;
|
void serialize(CheckpointOut &cp) const override;
|
||||||
void unserialize(CheckpointIn &cp) override;
|
void unserialize(CheckpointIn &cp) override;
|
||||||
|
|
|
@ -132,10 +132,10 @@ class CowDiskImage : public DiskImage
|
||||||
void serialize(CheckpointOut &cp) const override;
|
void serialize(CheckpointOut &cp) const override;
|
||||||
void unserialize(CheckpointIn &cp) override;
|
void unserialize(CheckpointIn &cp) override;
|
||||||
|
|
||||||
virtual std::streampos size() const;
|
std::streampos size() const override;
|
||||||
|
|
||||||
virtual std::streampos read(uint8_t *data, std::streampos offset) const;
|
std::streampos read(uint8_t *data, std::streampos offset) const override;
|
||||||
virtual std::streampos write(const uint8_t *data, std::streampos offset);
|
std::streampos write(const uint8_t *data, std::streampos offset) override;
|
||||||
};
|
};
|
||||||
|
|
||||||
void SafeRead(std::ifstream &stream, void *data, int count);
|
void SafeRead(std::ifstream &stream, void *data, int count);
|
||||||
|
|
|
@ -134,8 +134,8 @@ class DmaPort : public MasterPort, public Drainable
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
|
|
||||||
bool recvTimingResp(PacketPtr pkt);
|
bool recvTimingResp(PacketPtr pkt) override;
|
||||||
void recvReqRetry() ;
|
void recvReqRetry() override;
|
||||||
|
|
||||||
void queueDma(PacketPtr pkt);
|
void queueDma(PacketPtr pkt);
|
||||||
|
|
||||||
|
@ -175,12 +175,12 @@ class DmaDevice : public PioDevice
|
||||||
|
|
||||||
bool dmaPending() const { return dmaPort.dmaPending(); }
|
bool dmaPending() const { return dmaPort.dmaPending(); }
|
||||||
|
|
||||||
virtual void init();
|
void init() override;
|
||||||
|
|
||||||
unsigned int cacheBlockSize() const { return sys->cacheLineSize(); }
|
unsigned int cacheBlockSize() const { return sys->cacheLineSize(); }
|
||||||
|
|
||||||
virtual BaseMasterPort &getMasterPort(const std::string &if_name,
|
BaseMasterPort &getMasterPort(const std::string &if_name,
|
||||||
PortID idx = InvalidPortID);
|
PortID idx = InvalidPortID) override;
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -156,7 +156,7 @@ class EtherLink : public EtherObject
|
||||||
return dynamic_cast<const Params *>(_params);
|
return dynamic_cast<const Params *>(_params);
|
||||||
}
|
}
|
||||||
|
|
||||||
virtual EtherInt *getEthPort(const std::string &if_name, int idx);
|
EtherInt *getEthPort(const std::string &if_name, int idx) override;
|
||||||
|
|
||||||
void serialize(CheckpointOut &cp) const override;
|
void serialize(CheckpointOut &cp) const override;
|
||||||
void unserialize(CheckpointIn &cp) override;
|
void unserialize(CheckpointIn &cp) override;
|
||||||
|
|
|
@ -110,7 +110,7 @@ class EtherTap : public EtherObject
|
||||||
return dynamic_cast<const Params *>(_params);
|
return dynamic_cast<const Params *>(_params);
|
||||||
}
|
}
|
||||||
|
|
||||||
virtual EtherInt *getEthPort(const std::string &if_name, int idx);
|
EtherInt *getEthPort(const std::string &if_name, int idx) override;
|
||||||
|
|
||||||
virtual bool recvPacket(EthPacketPtr packet);
|
virtual bool recvPacket(EthPacketPtr packet);
|
||||||
virtual void sendDone();
|
virtual void sendDone();
|
||||||
|
|
|
@ -143,8 +143,8 @@ class I2CBus : public BasicPioDevice
|
||||||
|
|
||||||
I2CBus(const I2CBusParams* p);
|
I2CBus(const I2CBusParams* p);
|
||||||
|
|
||||||
virtual Tick read(PacketPtr pkt);
|
Tick read(PacketPtr pkt) override;
|
||||||
virtual Tick write(PacketPtr pkt);
|
Tick write(PacketPtr pkt) override;
|
||||||
|
|
||||||
void serialize(CheckpointOut &cp) const override;
|
void serialize(CheckpointOut &cp) const override;
|
||||||
void unserialize(CheckpointIn &cp) override;
|
void unserialize(CheckpointIn &cp) override;
|
||||||
|
|
|
@ -342,13 +342,13 @@ class IGbE : public EtherDevice
|
||||||
class RxDescCache : public DescCache<iGbReg::RxDesc>
|
class RxDescCache : public DescCache<iGbReg::RxDesc>
|
||||||
{
|
{
|
||||||
protected:
|
protected:
|
||||||
virtual Addr descBase() const { return igbe->regs.rdba(); }
|
Addr descBase() const override { return igbe->regs.rdba(); }
|
||||||
virtual long descHead() const { return igbe->regs.rdh(); }
|
long descHead() const override { return igbe->regs.rdh(); }
|
||||||
virtual long descLen() const { return igbe->regs.rdlen() >> 4; }
|
long descLen() const override { return igbe->regs.rdlen() >> 4; }
|
||||||
virtual long descTail() const { return igbe->regs.rdt(); }
|
long descTail() const override { return igbe->regs.rdt(); }
|
||||||
virtual void updateHead(long h) { igbe->regs.rdh(h); }
|
void updateHead(long h) override { igbe->regs.rdh(h); }
|
||||||
virtual void enableSm();
|
void enableSm() override;
|
||||||
virtual void fetchAfterWb() {
|
void fetchAfterWb() override {
|
||||||
if (!igbe->rxTick && igbe->drainState() == DrainState::Running)
|
if (!igbe->rxTick && igbe->drainState() == DrainState::Running)
|
||||||
fetchDescriptors();
|
fetchDescriptors();
|
||||||
}
|
}
|
||||||
|
@ -391,7 +391,7 @@ class IGbE : public EtherDevice
|
||||||
EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktHdrEvent;
|
EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktHdrEvent;
|
||||||
EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktDataEvent;
|
EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktDataEvent;
|
||||||
|
|
||||||
virtual bool hasOutstandingEvents();
|
bool hasOutstandingEvents() override;
|
||||||
|
|
||||||
void serialize(CheckpointOut &cp) const override;
|
void serialize(CheckpointOut &cp) const override;
|
||||||
void unserialize(CheckpointIn &cp) override;
|
void unserialize(CheckpointIn &cp) override;
|
||||||
|
@ -403,14 +403,14 @@ class IGbE : public EtherDevice
|
||||||
class TxDescCache : public DescCache<iGbReg::TxDesc>
|
class TxDescCache : public DescCache<iGbReg::TxDesc>
|
||||||
{
|
{
|
||||||
protected:
|
protected:
|
||||||
virtual Addr descBase() const { return igbe->regs.tdba(); }
|
Addr descBase() const override { return igbe->regs.tdba(); }
|
||||||
virtual long descHead() const { return igbe->regs.tdh(); }
|
long descHead() const override { return igbe->regs.tdh(); }
|
||||||
virtual long descTail() const { return igbe->regs.tdt(); }
|
long descTail() const override { return igbe->regs.tdt(); }
|
||||||
virtual long descLen() const { return igbe->regs.tdlen() >> 4; }
|
long descLen() const override { return igbe->regs.tdlen() >> 4; }
|
||||||
virtual void updateHead(long h) { igbe->regs.tdh(h); }
|
void updateHead(long h) override { igbe->regs.tdh(h); }
|
||||||
virtual void enableSm();
|
void enableSm() override;
|
||||||
virtual void actionAfterWb();
|
void actionAfterWb() override;
|
||||||
virtual void fetchAfterWb() {
|
void fetchAfterWb() override {
|
||||||
if (!igbe->txTick && igbe->drainState() == DrainState::Running)
|
if (!igbe->txTick && igbe->drainState() == DrainState::Running)
|
||||||
fetchDescriptors();
|
fetchDescriptors();
|
||||||
}
|
}
|
||||||
|
@ -497,7 +497,7 @@ class IGbE : public EtherDevice
|
||||||
completionEnabled = enabled;
|
completionEnabled = enabled;
|
||||||
}
|
}
|
||||||
|
|
||||||
virtual bool hasOutstandingEvents();
|
bool hasOutstandingEvents() override;
|
||||||
|
|
||||||
void nullCallback() {
|
void nullCallback() {
|
||||||
DPRINTF(EthernetDesc, "Completion writeback complete\n");
|
DPRINTF(EthernetDesc, "Completion writeback complete\n");
|
||||||
|
@ -521,16 +521,16 @@ class IGbE : public EtherDevice
|
||||||
|
|
||||||
IGbE(const Params *params);
|
IGbE(const Params *params);
|
||||||
~IGbE();
|
~IGbE();
|
||||||
virtual void init();
|
void init() override;
|
||||||
|
|
||||||
virtual EtherInt *getEthPort(const std::string &if_name, int idx);
|
EtherInt *getEthPort(const std::string &if_name, int idx) override;
|
||||||
|
|
||||||
Tick lastInterrupt;
|
Tick lastInterrupt;
|
||||||
|
|
||||||
virtual Tick read(PacketPtr pkt);
|
Tick read(PacketPtr pkt) override;
|
||||||
virtual Tick write(PacketPtr pkt);
|
Tick write(PacketPtr pkt) override;
|
||||||
|
|
||||||
virtual Tick writeConfig(PacketPtr pkt);
|
Tick writeConfig(PacketPtr pkt) override;
|
||||||
|
|
||||||
bool ethRxPkt(EthPacketPtr packet);
|
bool ethRxPkt(EthPacketPtr packet);
|
||||||
void ethTxDone();
|
void ethTxDone();
|
||||||
|
|
|
@ -146,13 +146,13 @@ class IdeController : public PciDevice
|
||||||
|
|
||||||
void intrPost();
|
void intrPost();
|
||||||
|
|
||||||
Tick writeConfig(PacketPtr pkt);
|
Tick writeConfig(PacketPtr pkt) override;
|
||||||
Tick readConfig(PacketPtr pkt);
|
Tick readConfig(PacketPtr pkt) override;
|
||||||
|
|
||||||
void setDmaComplete(IdeDisk *disk);
|
void setDmaComplete(IdeDisk *disk);
|
||||||
|
|
||||||
Tick read(PacketPtr pkt);
|
Tick read(PacketPtr pkt) override;
|
||||||
Tick write(PacketPtr pkt);
|
Tick write(PacketPtr pkt) override;
|
||||||
|
|
||||||
void serialize(CheckpointOut &cp) const override;
|
void serialize(CheckpointOut &cp) const override;
|
||||||
void unserialize(CheckpointIn &cp) override;
|
void unserialize(CheckpointIn &cp) override;
|
||||||
|
|
|
@ -276,7 +276,7 @@ class IdeDisk : public SimObject
|
||||||
/**
|
/**
|
||||||
* Register Statistics
|
* Register Statistics
|
||||||
*/
|
*/
|
||||||
void regStats();
|
void regStats() override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Set the controller for this device
|
* Set the controller for this device
|
||||||
|
|
|
@ -353,12 +353,12 @@ class NSGigE : public EtherDevBase
|
||||||
NSGigE(Params *params);
|
NSGigE(Params *params);
|
||||||
~NSGigE();
|
~NSGigE();
|
||||||
|
|
||||||
virtual EtherInt *getEthPort(const std::string &if_name, int idx);
|
EtherInt *getEthPort(const std::string &if_name, int idx) override;
|
||||||
|
|
||||||
virtual Tick writeConfig(PacketPtr pkt);
|
Tick writeConfig(PacketPtr pkt) override;
|
||||||
|
|
||||||
virtual Tick read(PacketPtr pkt);
|
Tick read(PacketPtr pkt) override;
|
||||||
virtual Tick write(PacketPtr pkt);
|
Tick write(PacketPtr pkt) override;
|
||||||
|
|
||||||
bool cpuIntrPending() const;
|
bool cpuIntrPending() const;
|
||||||
void cpuIntrAck() { cpuIntrClear(); }
|
void cpuIntrAck() { cpuIntrClear(); }
|
||||||
|
|
|
@ -76,9 +76,9 @@ class PciDevice : public DmaDevice
|
||||||
protected:
|
protected:
|
||||||
PciDevice *device;
|
PciDevice *device;
|
||||||
|
|
||||||
virtual Tick recvAtomic(PacketPtr pkt);
|
Tick recvAtomic(PacketPtr pkt) override;
|
||||||
|
|
||||||
virtual AddrRangeList getAddrRanges() const;
|
AddrRangeList getAddrRanges() const override;
|
||||||
|
|
||||||
Platform *platform;
|
Platform *platform;
|
||||||
|
|
||||||
|
@ -234,7 +234,7 @@ class PciDevice : public DmaDevice
|
||||||
*
|
*
|
||||||
* @return a list of non-overlapping address ranges
|
* @return a list of non-overlapping address ranges
|
||||||
*/
|
*/
|
||||||
AddrRangeList getAddrRanges() const;
|
AddrRangeList getAddrRanges() const override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Constructor for PCI Dev. This function copies data from the
|
* Constructor for PCI Dev. This function copies data from the
|
||||||
|
@ -243,7 +243,7 @@ class PciDevice : public DmaDevice
|
||||||
*/
|
*/
|
||||||
PciDevice(const Params *params);
|
PciDevice(const Params *params);
|
||||||
|
|
||||||
virtual void init();
|
void init() override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Serialize this object to the given output stream.
|
* Serialize this object to the given output stream.
|
||||||
|
@ -259,8 +259,8 @@ class PciDevice : public DmaDevice
|
||||||
void unserialize(CheckpointIn &cp) override;
|
void unserialize(CheckpointIn &cp) override;
|
||||||
|
|
||||||
|
|
||||||
virtual BaseSlavePort &getSlavePort(const std::string &if_name,
|
BaseSlavePort &getSlavePort(const std::string &if_name,
|
||||||
PortID idx = InvalidPortID)
|
PortID idx = InvalidPortID) override
|
||||||
{
|
{
|
||||||
if (if_name == "config") {
|
if (if_name == "config") {
|
||||||
return configPort;
|
return configPort;
|
||||||
|
|
|
@ -238,7 +238,7 @@ class Device : public Base
|
||||||
public:
|
public:
|
||||||
bool recvPacket(EthPacketPtr packet);
|
bool recvPacket(EthPacketPtr packet);
|
||||||
void transferDone();
|
void transferDone();
|
||||||
virtual EtherInt *getEthPort(const std::string &if_name, int idx);
|
EtherInt *getEthPort(const std::string &if_name, int idx) override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* DMA parameters
|
* DMA parameters
|
||||||
|
@ -269,8 +269,8 @@ class Device : public Base
|
||||||
* Memory Interface
|
* Memory Interface
|
||||||
*/
|
*/
|
||||||
public:
|
public:
|
||||||
virtual Tick read(PacketPtr pkt);
|
Tick read(PacketPtr pkt) override;
|
||||||
virtual Tick write(PacketPtr pkt);
|
Tick write(PacketPtr pkt) override;
|
||||||
virtual void drainResume() override;
|
virtual void drainResume() override;
|
||||||
|
|
||||||
void prepareIO(ContextID cpu, int index);
|
void prepareIO(ContextID cpu, int index);
|
||||||
|
@ -290,8 +290,8 @@ class Device : public Base
|
||||||
int _maxVnicDistance;
|
int _maxVnicDistance;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
virtual void regStats();
|
void regStats() override;
|
||||||
virtual void resetStats();
|
void resetStats() override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Serialization stuff
|
* Serialization stuff
|
||||||
|
|
|
@ -97,14 +97,14 @@ class Uart8250 : public Uart
|
||||||
}
|
}
|
||||||
Uart8250(const Params *p);
|
Uart8250(const Params *p);
|
||||||
|
|
||||||
virtual Tick read(PacketPtr pkt);
|
Tick read(PacketPtr pkt) override;
|
||||||
virtual Tick write(PacketPtr pkt);
|
Tick write(PacketPtr pkt) override;
|
||||||
virtual AddrRangeList getAddrRanges() const;
|
AddrRangeList getAddrRanges() const override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Inform the uart that there is data available.
|
* Inform the uart that there is data available.
|
||||||
*/
|
*/
|
||||||
virtual void dataAvailable();
|
void dataAvailable() override;
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
|
@ -220,7 +220,8 @@ class VirtIO9PProxy : public VirtIO9PBase
|
||||||
void unserialize(CheckpointIn &cp) override;
|
void unserialize(CheckpointIn &cp) override;
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
void recvTMsg(const P9MsgHeader &header, const uint8_t *data, size_t size);
|
void recvTMsg(const P9MsgHeader &header, const uint8_t *data,
|
||||||
|
size_t size) override;
|
||||||
|
|
||||||
/** Notification of pending data from server */
|
/** Notification of pending data from server */
|
||||||
void serverDataReady();
|
void serverDataReady();
|
||||||
|
|
|
@ -197,7 +197,7 @@ class AbstractMemory : public MemObject
|
||||||
/**
|
/**
|
||||||
* Initialise this memory.
|
* Initialise this memory.
|
||||||
*/
|
*/
|
||||||
void init();
|
void init() override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* See if this is a null memory that should never store data and
|
* See if this is a null memory that should never store data and
|
||||||
|
@ -304,7 +304,7 @@ class AbstractMemory : public MemObject
|
||||||
/**
|
/**
|
||||||
* Register Statistics
|
* Register Statistics
|
||||||
*/
|
*/
|
||||||
virtual void regStats();
|
void regStats() override;
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
12
src/mem/cache/cache.hh
vendored
12
src/mem/cache/cache.hh
vendored
|
@ -334,9 +334,9 @@ class Cache : public BaseCache
|
||||||
PacketPtr cleanEvictBlk(CacheBlk *blk);
|
PacketPtr cleanEvictBlk(CacheBlk *blk);
|
||||||
|
|
||||||
|
|
||||||
void memWriteback();
|
void memWriteback() override;
|
||||||
void memInvalidate();
|
void memInvalidate() override;
|
||||||
bool isDirty() const;
|
bool isDirty() const override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Cache block visitor that writes back dirty cache blocks using
|
* Cache block visitor that writes back dirty cache blocks using
|
||||||
|
@ -410,11 +410,11 @@ class Cache : public BaseCache
|
||||||
return tags->findBlock(addr, is_secure);
|
return tags->findBlock(addr, is_secure);
|
||||||
}
|
}
|
||||||
|
|
||||||
bool inCache(Addr addr, bool is_secure) const {
|
bool inCache(Addr addr, bool is_secure) const override {
|
||||||
return (tags->findBlock(addr, is_secure) != 0);
|
return (tags->findBlock(addr, is_secure) != 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
bool inMissQueue(Addr addr, bool is_secure) const {
|
bool inMissQueue(Addr addr, bool is_secure) const override {
|
||||||
return (mshrQueue.findMatch(addr, is_secure) != 0);
|
return (mshrQueue.findMatch(addr, is_secure) != 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -430,7 +430,7 @@ class Cache : public BaseCache
|
||||||
/** Non-default destructor is needed to deallocate memory. */
|
/** Non-default destructor is needed to deallocate memory. */
|
||||||
virtual ~Cache();
|
virtual ~Cache();
|
||||||
|
|
||||||
void regStats();
|
void regStats() override;
|
||||||
|
|
||||||
/** serialize the state of the caches
|
/** serialize the state of the caches
|
||||||
* We currently don't support checkpointing cache state, so this panics.
|
* We currently don't support checkpointing cache state, so this panics.
|
||||||
|
|
32
src/mem/cache/tags/base_set_assoc.hh
vendored
32
src/mem/cache/tags/base_set_assoc.hh
vendored
|
@ -152,7 +152,7 @@ public:
|
||||||
* @return The number of sets.
|
* @return The number of sets.
|
||||||
*/
|
*/
|
||||||
unsigned
|
unsigned
|
||||||
getNumSets() const
|
getNumSets() const override
|
||||||
{
|
{
|
||||||
return numSets;
|
return numSets;
|
||||||
}
|
}
|
||||||
|
@ -162,7 +162,7 @@ public:
|
||||||
* @return The number of ways.
|
* @return The number of ways.
|
||||||
*/
|
*/
|
||||||
unsigned
|
unsigned
|
||||||
getNumWays() const
|
getNumWays() const override
|
||||||
{
|
{
|
||||||
return assoc;
|
return assoc;
|
||||||
}
|
}
|
||||||
|
@ -173,13 +173,13 @@ public:
|
||||||
* @param way The way of the block.
|
* @param way The way of the block.
|
||||||
* @return The cache block.
|
* @return The cache block.
|
||||||
*/
|
*/
|
||||||
CacheBlk *findBlockBySetAndWay(int set, int way) const;
|
CacheBlk *findBlockBySetAndWay(int set, int way) const override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Invalidate the given block.
|
* Invalidate the given block.
|
||||||
* @param blk The block to invalidate.
|
* @param blk The block to invalidate.
|
||||||
*/
|
*/
|
||||||
void invalidate(CacheBlk *blk)
|
void invalidate(CacheBlk *blk) override
|
||||||
{
|
{
|
||||||
assert(blk);
|
assert(blk);
|
||||||
assert(blk->isValid());
|
assert(blk->isValid());
|
||||||
|
@ -203,7 +203,7 @@ public:
|
||||||
* @return Pointer to the cache block if found.
|
* @return Pointer to the cache block if found.
|
||||||
*/
|
*/
|
||||||
CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
|
CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
|
||||||
int context_src)
|
int context_src) override
|
||||||
{
|
{
|
||||||
Addr tag = extractTag(addr);
|
Addr tag = extractTag(addr);
|
||||||
int set = extractSet(addr);
|
int set = extractSet(addr);
|
||||||
|
@ -242,7 +242,7 @@ public:
|
||||||
* @param asid The address space ID.
|
* @param asid The address space ID.
|
||||||
* @return Pointer to the cache block if found.
|
* @return Pointer to the cache block if found.
|
||||||
*/
|
*/
|
||||||
CacheBlk* findBlock(Addr addr, bool is_secure) const;
|
CacheBlk* findBlock(Addr addr, bool is_secure) const override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Find an invalid block to evict for the address provided.
|
* Find an invalid block to evict for the address provided.
|
||||||
|
@ -251,7 +251,7 @@ public:
|
||||||
* @param addr The addr to a find a replacement candidate for.
|
* @param addr The addr to a find a replacement candidate for.
|
||||||
* @return The candidate block.
|
* @return The candidate block.
|
||||||
*/
|
*/
|
||||||
CacheBlk* findVictim(Addr addr)
|
CacheBlk* findVictim(Addr addr) override
|
||||||
{
|
{
|
||||||
BlkType *blk = NULL;
|
BlkType *blk = NULL;
|
||||||
int set = extractSet(addr);
|
int set = extractSet(addr);
|
||||||
|
@ -271,7 +271,7 @@ public:
|
||||||
* @param pkt Packet holding the address to update
|
* @param pkt Packet holding the address to update
|
||||||
* @param blk The block to update.
|
* @param blk The block to update.
|
||||||
*/
|
*/
|
||||||
void insertBlock(PacketPtr pkt, CacheBlk *blk)
|
void insertBlock(PacketPtr pkt, CacheBlk *blk) override
|
||||||
{
|
{
|
||||||
Addr addr = pkt->getAddr();
|
Addr addr = pkt->getAddr();
|
||||||
MasterID master_id = pkt->req->masterId();
|
MasterID master_id = pkt->req->masterId();
|
||||||
|
@ -324,7 +324,7 @@ public:
|
||||||
* Limit the allocation for the cache ways.
|
* Limit the allocation for the cache ways.
|
||||||
* @param ways The maximum number of ways available for replacement.
|
* @param ways The maximum number of ways available for replacement.
|
||||||
*/
|
*/
|
||||||
virtual void setWayAllocationMax(int ways)
|
virtual void setWayAllocationMax(int ways) override
|
||||||
{
|
{
|
||||||
fatal_if(ways < 1, "Allocation limit must be greater than zero");
|
fatal_if(ways < 1, "Allocation limit must be greater than zero");
|
||||||
allocAssoc = ways;
|
allocAssoc = ways;
|
||||||
|
@ -334,7 +334,7 @@ public:
|
||||||
* Get the way allocation mask limit.
|
* Get the way allocation mask limit.
|
||||||
* @return The maximum number of ways available for replacement.
|
* @return The maximum number of ways available for replacement.
|
||||||
*/
|
*/
|
||||||
virtual int getWayAllocationMax() const
|
virtual int getWayAllocationMax() const override
|
||||||
{
|
{
|
||||||
return allocAssoc;
|
return allocAssoc;
|
||||||
}
|
}
|
||||||
|
@ -344,7 +344,7 @@ public:
|
||||||
* @param addr The address to get the tag from.
|
* @param addr The address to get the tag from.
|
||||||
* @return The tag of the address.
|
* @return The tag of the address.
|
||||||
*/
|
*/
|
||||||
Addr extractTag(Addr addr) const
|
Addr extractTag(Addr addr) const override
|
||||||
{
|
{
|
||||||
return (addr >> tagShift);
|
return (addr >> tagShift);
|
||||||
}
|
}
|
||||||
|
@ -354,7 +354,7 @@ public:
|
||||||
* @param addr The address to get the set from.
|
* @param addr The address to get the set from.
|
||||||
* @return The set index of the address.
|
* @return The set index of the address.
|
||||||
*/
|
*/
|
||||||
int extractSet(Addr addr) const
|
int extractSet(Addr addr) const override
|
||||||
{
|
{
|
||||||
return ((addr >> setShift) & setMask);
|
return ((addr >> setShift) & setMask);
|
||||||
}
|
}
|
||||||
|
@ -375,7 +375,7 @@ public:
|
||||||
* @param set The set of the block.
|
* @param set The set of the block.
|
||||||
* @return The block address.
|
* @return The block address.
|
||||||
*/
|
*/
|
||||||
Addr regenerateBlkAddr(Addr tag, unsigned set) const
|
Addr regenerateBlkAddr(Addr tag, unsigned set) const override
|
||||||
{
|
{
|
||||||
return ((tag << tagShift) | ((Addr)set << setShift));
|
return ((tag << tagShift) | ((Addr)set << setShift));
|
||||||
}
|
}
|
||||||
|
@ -383,17 +383,17 @@ public:
|
||||||
/**
|
/**
|
||||||
* Called at end of simulation to complete average block reference stats.
|
* Called at end of simulation to complete average block reference stats.
|
||||||
*/
|
*/
|
||||||
virtual void cleanupRefs();
|
void cleanupRefs() override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Print all tags used
|
* Print all tags used
|
||||||
*/
|
*/
|
||||||
virtual std::string print() const;
|
std::string print() const override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Called prior to dumping stats to compute task occupancy
|
* Called prior to dumping stats to compute task occupancy
|
||||||
*/
|
*/
|
||||||
virtual void computeStats();
|
void computeStats() override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Visit each block in the tag store and apply a visitor to the
|
* Visit each block in the tag store and apply a visitor to the
|
||||||
|
|
26
src/mem/cache/tags/fa_lru.hh
vendored
26
src/mem/cache/tags/fa_lru.hh
vendored
|
@ -168,13 +168,13 @@ public:
|
||||||
* Register the stats for this object.
|
* Register the stats for this object.
|
||||||
* @param name The name to prepend to the stats name.
|
* @param name The name to prepend to the stats name.
|
||||||
*/
|
*/
|
||||||
void regStats();
|
void regStats() override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Invalidate a cache block.
|
* Invalidate a cache block.
|
||||||
* @param blk The block to invalidate.
|
* @param blk The block to invalidate.
|
||||||
*/
|
*/
|
||||||
void invalidate(CacheBlk *blk);
|
void invalidate(CacheBlk *blk) override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Access block and update replacement data. May not succeed, in which case
|
* Access block and update replacement data. May not succeed, in which case
|
||||||
|
@ -195,7 +195,7 @@ public:
|
||||||
* Just a wrapper of above function to conform with the base interface.
|
* Just a wrapper of above function to conform with the base interface.
|
||||||
*/
|
*/
|
||||||
CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
|
CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
|
||||||
int context_src);
|
int context_src) override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Find the block in the cache, do not update the replacement data.
|
* Find the block in the cache, do not update the replacement data.
|
||||||
|
@ -204,16 +204,16 @@ public:
|
||||||
* @param asid The address space ID.
|
* @param asid The address space ID.
|
||||||
* @return Pointer to the cache block.
|
* @return Pointer to the cache block.
|
||||||
*/
|
*/
|
||||||
CacheBlk* findBlock(Addr addr, bool is_secure) const;
|
CacheBlk* findBlock(Addr addr, bool is_secure) const override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Find a replacement block for the address provided.
|
* Find a replacement block for the address provided.
|
||||||
* @param pkt The request to a find a replacement candidate for.
|
* @param pkt The request to a find a replacement candidate for.
|
||||||
* @return The block to place the replacement in.
|
* @return The block to place the replacement in.
|
||||||
*/
|
*/
|
||||||
CacheBlk* findVictim(Addr addr);
|
CacheBlk* findVictim(Addr addr) override;
|
||||||
|
|
||||||
void insertBlock(PacketPtr pkt, CacheBlk *blk);
|
void insertBlock(PacketPtr pkt, CacheBlk *blk) override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Return the block size of this cache.
|
* Return the block size of this cache.
|
||||||
|
@ -240,7 +240,7 @@ public:
|
||||||
* @return The number of sets.
|
* @return The number of sets.
|
||||||
*/
|
*/
|
||||||
unsigned
|
unsigned
|
||||||
getNumSets() const
|
getNumSets() const override
|
||||||
{
|
{
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
@ -250,7 +250,7 @@ public:
|
||||||
* @return The number of ways.
|
* @return The number of ways.
|
||||||
*/
|
*/
|
||||||
unsigned
|
unsigned
|
||||||
getNumWays() const
|
getNumWays() const override
|
||||||
{
|
{
|
||||||
return numBlocks;
|
return numBlocks;
|
||||||
}
|
}
|
||||||
|
@ -261,7 +261,7 @@ public:
|
||||||
* @param way The way of the block.
|
* @param way The way of the block.
|
||||||
* @return The cache block.
|
* @return The cache block.
|
||||||
*/
|
*/
|
||||||
CacheBlk* findBlockBySetAndWay(int set, int way) const;
|
CacheBlk* findBlockBySetAndWay(int set, int way) const override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Align an address to the block size.
|
* Align an address to the block size.
|
||||||
|
@ -279,7 +279,7 @@ public:
|
||||||
* @param addr The address to get the tag from.
|
* @param addr The address to get the tag from.
|
||||||
* @return The tag.
|
* @return The tag.
|
||||||
*/
|
*/
|
||||||
Addr extractTag(Addr addr) const
|
Addr extractTag(Addr addr) const override
|
||||||
{
|
{
|
||||||
return blkAlign(addr);
|
return blkAlign(addr);
|
||||||
}
|
}
|
||||||
|
@ -289,7 +289,7 @@ public:
|
||||||
* @param addr The address to get the set from.
|
* @param addr The address to get the set from.
|
||||||
* @return 0.
|
* @return 0.
|
||||||
*/
|
*/
|
||||||
int extractSet(Addr addr) const
|
int extractSet(Addr addr) const override
|
||||||
{
|
{
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -300,7 +300,7 @@ public:
|
||||||
* @param set The set the block belongs to.
|
* @param set The set the block belongs to.
|
||||||
* @return the block address.
|
* @return the block address.
|
||||||
*/
|
*/
|
||||||
Addr regenerateBlkAddr(Addr tag, unsigned set) const
|
Addr regenerateBlkAddr(Addr tag, unsigned set) const override
|
||||||
{
|
{
|
||||||
return (tag);
|
return (tag);
|
||||||
}
|
}
|
||||||
|
@ -308,7 +308,7 @@ public:
|
||||||
/**
|
/**
|
||||||
* @todo Implement as in lru. Currently not used
|
* @todo Implement as in lru. Currently not used
|
||||||
*/
|
*/
|
||||||
virtual std::string print() const { return ""; }
|
virtual std::string print() const override { return ""; }
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Visit each block in the tag store and apply a visitor to the
|
* Visit each block in the tag store and apply a visitor to the
|
||||||
|
|
|
@ -868,14 +868,14 @@ class DRAMCtrl : public AbstractMemory
|
||||||
|
|
||||||
public:
|
public:
|
||||||
|
|
||||||
void regStats();
|
void regStats() override;
|
||||||
|
|
||||||
DRAMCtrl(const DRAMCtrlParams* p);
|
DRAMCtrl(const DRAMCtrlParams* p);
|
||||||
|
|
||||||
DrainState drain() override;
|
DrainState drain() override;
|
||||||
|
|
||||||
virtual BaseSlavePort& getSlavePort(const std::string& if_name,
|
virtual BaseSlavePort& getSlavePort(const std::string& if_name,
|
||||||
PortID idx = InvalidPortID);
|
PortID idx = InvalidPortID) override;
|
||||||
|
|
||||||
virtual void init() override;
|
virtual void init() override;
|
||||||
virtual void startup() override;
|
virtual void startup() override;
|
||||||
|
|
|
@ -192,10 +192,10 @@ class DRAMSim2 : public AbstractMemory
|
||||||
DrainState drain() override;
|
DrainState drain() override;
|
||||||
|
|
||||||
virtual BaseSlavePort& getSlavePort(const std::string& if_name,
|
virtual BaseSlavePort& getSlavePort(const std::string& if_name,
|
||||||
PortID idx = InvalidPortID);
|
PortID idx = InvalidPortID) override;
|
||||||
|
|
||||||
virtual void init();
|
void init() override;
|
||||||
virtual void startup();
|
void startup() override;
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
|
|
||||||
|
|
|
@ -211,14 +211,14 @@ class FuncPageTable : public PageTableBase
|
||||||
|
|
||||||
~FuncPageTable();
|
~FuncPageTable();
|
||||||
|
|
||||||
void initState(ThreadContext* tc)
|
void initState(ThreadContext* tc) override
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
void map(Addr vaddr, Addr paddr, int64_t size,
|
void map(Addr vaddr, Addr paddr, int64_t size,
|
||||||
uint64_t flags = 0);
|
uint64_t flags = 0) override;
|
||||||
void remap(Addr vaddr, int64_t size, Addr new_vaddr);
|
void remap(Addr vaddr, int64_t size, Addr new_vaddr) override;
|
||||||
void unmap(Addr vaddr, int64_t size);
|
void unmap(Addr vaddr, int64_t size) override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Check if any pages in a region are already allocated
|
* Check if any pages in a region are already allocated
|
||||||
|
@ -226,14 +226,14 @@ class FuncPageTable : public PageTableBase
|
||||||
* @param size The length of the region.
|
* @param size The length of the region.
|
||||||
* @return True if no pages in the region are mapped.
|
* @return True if no pages in the region are mapped.
|
||||||
*/
|
*/
|
||||||
bool isUnmapped(Addr vaddr, int64_t size);
|
bool isUnmapped(Addr vaddr, int64_t size) override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Lookup function
|
* Lookup function
|
||||||
* @param vaddr The virtual address.
|
* @param vaddr The virtual address.
|
||||||
* @return entry The page table entry corresponding to vaddr.
|
* @return entry The page table entry corresponding to vaddr.
|
||||||
*/
|
*/
|
||||||
bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
|
bool lookup(Addr vaddr, TheISA::TlbEntry &entry) override;
|
||||||
|
|
||||||
void serialize(CheckpointOut &cp) const override;
|
void serialize(CheckpointOut &cp) const override;
|
||||||
void unserialize(CheckpointIn &cp) override;
|
void unserialize(CheckpointIn &cp) override;
|
||||||
|
|
|
@ -42,8 +42,6 @@ class NetworkLink_d(ClockedObject):
|
||||||
"virtual channels per virtual network")
|
"virtual channels per virtual network")
|
||||||
virt_nets = Param.Int(Parent.number_of_virtual_networks,
|
virt_nets = Param.Int(Parent.number_of_virtual_networks,
|
||||||
"number of virtual networks")
|
"number of virtual networks")
|
||||||
channel_width = Param.Int(Parent.bandwidth_factor,
|
|
||||||
"channel width == bw factor")
|
|
||||||
|
|
||||||
class CreditLink_d(NetworkLink_d):
|
class CreditLink_d(NetworkLink_d):
|
||||||
type = 'CreditLink_d'
|
type = 'CreditLink_d'
|
||||||
|
|
|
@ -33,7 +33,7 @@
|
||||||
|
|
||||||
NetworkLink_d::NetworkLink_d(const Params *p)
|
NetworkLink_d::NetworkLink_d(const Params *p)
|
||||||
: ClockedObject(p), Consumer(this), m_id(p->link_id),
|
: ClockedObject(p), Consumer(this), m_id(p->link_id),
|
||||||
m_latency(p->link_latency), channel_width(p->channel_width),
|
m_latency(p->link_latency),
|
||||||
linkBuffer(new flitBuffer_d()), link_consumer(nullptr),
|
linkBuffer(new flitBuffer_d()), link_consumer(nullptr),
|
||||||
link_srcQueue(nullptr), m_link_utilized(0),
|
link_srcQueue(nullptr), m_link_utilized(0),
|
||||||
m_vc_load(p->vcs_per_vnet * p->virt_nets)
|
m_vc_load(p->vcs_per_vnet * p->virt_nets)
|
||||||
|
|
|
@ -69,7 +69,6 @@ class NetworkLink_d : public ClockedObject, public Consumer
|
||||||
private:
|
private:
|
||||||
const int m_id;
|
const int m_id;
|
||||||
const Cycles m_latency;
|
const Cycles m_latency;
|
||||||
const int channel_width;
|
|
||||||
|
|
||||||
flitBuffer_d *linkBuffer;
|
flitBuffer_d *linkBuffer;
|
||||||
Consumer *link_consumer;
|
Consumer *link_consumer;
|
||||||
|
|
|
@ -53,15 +53,15 @@ class RubyMemoryControl : public AbstractMemory, public Consumer
|
||||||
public:
|
public:
|
||||||
typedef RubyMemoryControlParams Params;
|
typedef RubyMemoryControlParams Params;
|
||||||
RubyMemoryControl(const Params *p);
|
RubyMemoryControl(const Params *p);
|
||||||
void init();
|
void init() override;
|
||||||
void reset();
|
void reset();
|
||||||
|
|
||||||
~RubyMemoryControl();
|
~RubyMemoryControl();
|
||||||
|
|
||||||
virtual BaseSlavePort& getSlavePort(const std::string& if_name,
|
virtual BaseSlavePort& getSlavePort(const std::string& if_name,
|
||||||
PortID idx = InvalidPortID);
|
PortID idx = InvalidPortID) override;
|
||||||
DrainState drain() override;
|
DrainState drain() override;
|
||||||
void wakeup();
|
void wakeup() override;
|
||||||
|
|
||||||
void setDescription(const std::string& name) { m_description = name; };
|
void setDescription(const std::string& name) { m_description = name; };
|
||||||
std::string getDescription() { return m_description; };
|
std::string getDescription() { return m_description; };
|
||||||
|
@ -72,8 +72,8 @@ class RubyMemoryControl : public AbstractMemory, public Consumer
|
||||||
void enqueueMemRef(MemoryNode *memRef);
|
void enqueueMemRef(MemoryNode *memRef);
|
||||||
bool areNSlotsAvailable(int n) { return true; }; // infinite queue length
|
bool areNSlotsAvailable(int n) { return true; }; // infinite queue length
|
||||||
|
|
||||||
void print(std::ostream& out) const;
|
void print(std::ostream& out) const override;
|
||||||
void regStats();
|
void regStats() override;
|
||||||
|
|
||||||
const int getBank(const Addr addr) const;
|
const int getBank(const Addr addr) const;
|
||||||
const int getRank(const Addr addr) const;
|
const int getRank(const Addr addr) const;
|
||||||
|
|
|
@ -60,7 +60,7 @@ class DMASequencer : public MemObject
|
||||||
public:
|
public:
|
||||||
typedef DMASequencerParams Params;
|
typedef DMASequencerParams Params;
|
||||||
DMASequencer(const Params *);
|
DMASequencer(const Params *);
|
||||||
void init();
|
void init() override;
|
||||||
RubySystem *m_ruby_system;
|
RubySystem *m_ruby_system;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
|
@ -95,7 +95,7 @@ class DMASequencer : public MemObject
|
||||||
};
|
};
|
||||||
|
|
||||||
BaseSlavePort &getSlavePort(const std::string &if_name,
|
BaseSlavePort &getSlavePort(const std::string &if_name,
|
||||||
PortID idx = InvalidPortID);
|
PortID idx = InvalidPortID) override;
|
||||||
|
|
||||||
/* external interface */
|
/* external interface */
|
||||||
RequestStatus makeRequest(PacketPtr pkt);
|
RequestStatus makeRequest(PacketPtr pkt);
|
||||||
|
|
|
@ -143,12 +143,12 @@ class RubyPort : public MemObject
|
||||||
RubyPort(const Params *p);
|
RubyPort(const Params *p);
|
||||||
virtual ~RubyPort() {}
|
virtual ~RubyPort() {}
|
||||||
|
|
||||||
void init();
|
void init() override;
|
||||||
|
|
||||||
BaseMasterPort &getMasterPort(const std::string &if_name,
|
BaseMasterPort &getMasterPort(const std::string &if_name,
|
||||||
PortID idx = InvalidPortID);
|
PortID idx = InvalidPortID) override;
|
||||||
BaseSlavePort &getSlavePort(const std::string &if_name,
|
BaseSlavePort &getSlavePort(const std::string &if_name,
|
||||||
PortID idx = InvalidPortID);
|
PortID idx = InvalidPortID) override;
|
||||||
|
|
||||||
virtual RequestStatus makeRequest(PacketPtr pkt) = 0;
|
virtual RequestStatus makeRequest(PacketPtr pkt) = 0;
|
||||||
virtual int outstandingCount() const = 0;
|
virtual int outstandingCount() const = 0;
|
||||||
|
|
|
@ -89,16 +89,16 @@ class RubySystem : public ClockedObject
|
||||||
return m_profiler;
|
return m_profiler;
|
||||||
}
|
}
|
||||||
|
|
||||||
void regStats() { m_profiler->regStats(name()); }
|
void regStats() override { m_profiler->regStats(name()); }
|
||||||
void collateStats() { m_profiler->collateStats(); }
|
void collateStats() { m_profiler->collateStats(); }
|
||||||
void resetStats();
|
void resetStats() override;
|
||||||
|
|
||||||
void memWriteback();
|
void memWriteback() override;
|
||||||
void serialize(CheckpointOut &cp) const override;
|
void serialize(CheckpointOut &cp) const override;
|
||||||
void unserialize(CheckpointIn &cp) override;
|
void unserialize(CheckpointIn &cp) override;
|
||||||
void drainResume() override;
|
void drainResume() override;
|
||||||
void process();
|
void process();
|
||||||
void startup();
|
void startup() override;
|
||||||
bool functionalRead(Packet *ptr);
|
bool functionalRead(Packet *ptr);
|
||||||
bool functionalWrite(Packet *ptr);
|
bool functionalWrite(Packet *ptr);
|
||||||
|
|
||||||
|
|
|
@ -188,8 +188,8 @@ class SimpleMemory : public AbstractMemory
|
||||||
DrainState drain() override;
|
DrainState drain() override;
|
||||||
|
|
||||||
BaseSlavePort& getSlavePort(const std::string& if_name,
|
BaseSlavePort& getSlavePort(const std::string& if_name,
|
||||||
PortID idx = InvalidPortID);
|
PortID idx = InvalidPortID) override;
|
||||||
void init();
|
void init() override;
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
|
|
||||||
|
|
|
@ -237,7 +237,7 @@ class SrcClockDomain : public ClockDomain
|
||||||
return freqOpPoints[perf_level];
|
return freqOpPoints[perf_level];
|
||||||
}
|
}
|
||||||
|
|
||||||
void startup();
|
void startup() override;
|
||||||
|
|
||||||
void serialize(CheckpointOut &cp) const override;
|
void serialize(CheckpointOut &cp) const override;
|
||||||
void unserialize(CheckpointIn &cp) override;
|
void unserialize(CheckpointIn &cp) override;
|
||||||
|
|
|
@ -120,7 +120,7 @@ class Process : public SimObject
|
||||||
// constructor
|
// constructor
|
||||||
Process(ProcessParams *params);
|
Process(ProcessParams *params);
|
||||||
|
|
||||||
virtual void initState();
|
void initState() override;
|
||||||
|
|
||||||
DrainState drain() override;
|
DrainState drain() override;
|
||||||
|
|
||||||
|
@ -156,7 +156,7 @@ class Process : public SimObject
|
||||||
void inheritFDArray(Process *p);
|
void inheritFDArray(Process *p);
|
||||||
|
|
||||||
// override of virtual SimObject method: register statistics
|
// override of virtual SimObject method: register statistics
|
||||||
virtual void regStats();
|
void regStats() override;
|
||||||
|
|
||||||
// After getting registered with system object, tell process which
|
// After getting registered with system object, tell process which
|
||||||
// system-wide context id it is assigned.
|
// system-wide context id it is assigned.
|
||||||
|
|
|
@ -110,7 +110,7 @@ class Root : public SimObject
|
||||||
|
|
||||||
/** Schedule the timesync event at initState() when not unserializing
|
/** Schedule the timesync event at initState() when not unserializing
|
||||||
*/
|
*/
|
||||||
void initState();
|
void initState() override;
|
||||||
|
|
||||||
void serialize(CheckpointOut &cp) const override;
|
void serialize(CheckpointOut &cp) const override;
|
||||||
void unserialize(CheckpointIn &cp) override;
|
void unserialize(CheckpointIn &cp) override;
|
||||||
|
|
|
@ -88,9 +88,9 @@ class LocalSimLoopExitEvent : public Event
|
||||||
const std::string getCause() const { return cause; }
|
const std::string getCause() const { return cause; }
|
||||||
const int getCode() const { return code; }
|
const int getCode() const { return code; }
|
||||||
|
|
||||||
void process(); // process event
|
void process() override; // process event
|
||||||
|
|
||||||
virtual const char *description() const;
|
const char *description() const override;
|
||||||
|
|
||||||
void serialize(CheckpointOut &cp) const override;
|
void serialize(CheckpointOut &cp) const override;
|
||||||
void unserialize(CheckpointIn &cp) override;
|
void unserialize(CheckpointIn &cp) override;
|
||||||
|
@ -107,7 +107,7 @@ class CountedDrainEvent : public Event
|
||||||
public:
|
public:
|
||||||
CountedDrainEvent();
|
CountedDrainEvent();
|
||||||
|
|
||||||
void process();
|
void process() override;
|
||||||
|
|
||||||
void setCount(int _count) { count = _count; }
|
void setCount(int _count) { count = _count; }
|
||||||
|
|
||||||
|
@ -128,9 +128,9 @@ class CountedExitEvent : public Event
|
||||||
public:
|
public:
|
||||||
CountedExitEvent(const std::string &_cause, int &_downCounter);
|
CountedExitEvent(const std::string &_cause, int &_downCounter);
|
||||||
|
|
||||||
void process(); // process event
|
void process() override; // process event
|
||||||
|
|
||||||
virtual const char *description() const;
|
const char *description() const override;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -97,9 +97,9 @@ class System : public MemObject
|
||||||
SystemPort(const std::string &_name, MemObject *_owner)
|
SystemPort(const std::string &_name, MemObject *_owner)
|
||||||
: MasterPort(_name, _owner)
|
: MasterPort(_name, _owner)
|
||||||
{ }
|
{ }
|
||||||
bool recvTimingResp(PacketPtr pkt)
|
bool recvTimingResp(PacketPtr pkt) override
|
||||||
{ panic("SystemPort does not receive timing!\n"); return false; }
|
{ panic("SystemPort does not receive timing!\n"); return false; }
|
||||||
void recvReqRetry()
|
void recvReqRetry() override
|
||||||
{ panic("SystemPort does not expect retry!\n"); }
|
{ panic("SystemPort does not expect retry!\n"); }
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -111,7 +111,7 @@ class System : public MemObject
|
||||||
* After all objects have been created and all ports are
|
* After all objects have been created and all ports are
|
||||||
* connected, check that the system port is connected.
|
* connected, check that the system port is connected.
|
||||||
*/
|
*/
|
||||||
virtual void init();
|
void init() override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Get a reference to the system port that can be used by
|
* Get a reference to the system port that can be used by
|
||||||
|
@ -127,7 +127,7 @@ class System : public MemObject
|
||||||
* Additional function to return the Port of a memory object.
|
* Additional function to return the Port of a memory object.
|
||||||
*/
|
*/
|
||||||
BaseMasterPort& getMasterPort(const std::string &if_name,
|
BaseMasterPort& getMasterPort(const std::string &if_name,
|
||||||
PortID idx = InvalidPortID);
|
PortID idx = InvalidPortID) override;
|
||||||
|
|
||||||
/** @{ */
|
/** @{ */
|
||||||
/**
|
/**
|
||||||
|
@ -335,7 +335,7 @@ class System : public MemObject
|
||||||
return masterIds.size();
|
return masterIds.size();
|
||||||
}
|
}
|
||||||
|
|
||||||
virtual void regStats();
|
void regStats() override;
|
||||||
/**
|
/**
|
||||||
* Called by pseudo_inst to track the number of work items started by this
|
* Called by pseudo_inst to track the number of work items started by this
|
||||||
* system.
|
* system.
|
||||||
|
@ -487,7 +487,7 @@ class System : public MemObject
|
||||||
System(Params *p);
|
System(Params *p);
|
||||||
~System();
|
~System();
|
||||||
|
|
||||||
void initState();
|
void initState() override;
|
||||||
|
|
||||||
const Params *params() const { return (const Params *)_params; }
|
const Params *params() const { return (const Params *)_params; }
|
||||||
|
|
||||||
|
|
|
@ -198,7 +198,7 @@ class TickedObject : public ClockedObject, public Ticked
|
||||||
using ClockedObject::unserialize;
|
using ClockedObject::unserialize;
|
||||||
|
|
||||||
/** Pass on regStats, serialize etc. onto Ticked */
|
/** Pass on regStats, serialize etc. onto Ticked */
|
||||||
void regStats();
|
void regStats() override;
|
||||||
void serialize(CheckpointOut &cp) const override;
|
void serialize(CheckpointOut &cp) const override;
|
||||||
void unserialize(CheckpointIn &cp) override;
|
void unserialize(CheckpointIn &cp) override;
|
||||||
};
|
};
|
||||||
|
|
|
@ -111,7 +111,7 @@ class VoltageDomain : public SimObject
|
||||||
* Startup has all SrcClockDomains registered with this voltage domain, so
|
* Startup has all SrcClockDomains registered with this voltage domain, so
|
||||||
* try to make sure that all perf level requests from them are met.
|
* try to make sure that all perf level requests from them are met.
|
||||||
*/
|
*/
|
||||||
void startup();
|
void startup() override;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Recomputes the highest (fastest, i.e., numerically lowest) requested
|
* Recomputes the highest (fastest, i.e., numerically lowest) requested
|
||||||
|
@ -126,7 +126,7 @@ class VoltageDomain : public SimObject
|
||||||
*/
|
*/
|
||||||
bool sanitiseVoltages();
|
bool sanitiseVoltages();
|
||||||
|
|
||||||
void regStats();
|
void regStats() override;
|
||||||
|
|
||||||
void serialize(CheckpointOut &cp) const override;
|
void serialize(CheckpointOut &cp) const override;
|
||||||
void unserialize(CheckpointIn &cp) override;
|
void unserialize(CheckpointIn &cp) override;
|
||||||
|
|
Loading…
Reference in a new issue