ARM: Decode the unsigned saturating instructions.
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be888e67e7
commit
29acf9516c
1 changed files with 16 additions and 16 deletions
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@ -301,17 +301,17 @@ def format ArmParallelAddSubtract() {{
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case 0x2:
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switch (op2) {
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case 0x0:
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return new WarnUnimplemented("uqadd16", machInst);
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return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL);
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case 0x1:
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return new WarnUnimplemented("uqasx", machInst);
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return new UqasxReg(machInst, rd, rn, rm, 0, LSL);
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case 0x2:
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return new WarnUnimplemented("uqsax", machInst);
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return new UqsaxReg(machInst, rd, rn, rm, 0, LSL);
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case 0x3:
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return new WarnUnimplemented("uqsub16", machInst);
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return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL);
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case 0x4:
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return new WarnUnimplemented("uqadd8", machInst);
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return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL);
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case 0x7:
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return new WarnUnimplemented("uqsub8", machInst);
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return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL);
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}
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break;
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case 0x3:
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@ -539,13 +539,13 @@ def format Thumb32DataProcReg() {{
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}
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} else {
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if (bits(op2, 3) == 0) {
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if (bits(op2, 2) == 0x0) {
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const uint32_t op1 = bits(machInst, 22, 20);
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const uint32_t op2 = bits(machInst, 5, 4);
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const IntRegIndex rd =
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(IntRegIndex)(uint32_t)bits(machInst, 11, 8);
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const IntRegIndex rm =
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(IntRegIndex)(uint32_t)bits(machInst, 3, 0);
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if (bits(op2, 2) == 0x0) {
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const uint32_t op1 = bits(machInst, 22, 20);
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const uint32_t op2 = bits(machInst, 5, 4);
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switch (op2) {
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case 0x0:
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switch (op1) {
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@ -623,17 +623,17 @@ def format Thumb32DataProcReg() {{
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case 0x1:
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switch (op1) {
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case 0x1:
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return new WarnUnimplemented("uqadd16", machInst);
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return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL);
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case 0x2:
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return new WarnUnimplemented("uqasx", machInst);
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return new UqasxReg(machInst, rd, rn, rm, 0, LSL);
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case 0x6:
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return new WarnUnimplemented("uqsax", machInst);
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return new UqsaxReg(machInst, rd, rn, rm, 0, LSL);
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case 0x5:
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return new WarnUnimplemented("uqsub16", machInst);
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return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL);
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case 0x0:
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return new WarnUnimplemented("uqadd8", machInst);
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return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL);
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case 0x4:
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return new WarnUnimplemented("uqsub8", machInst);
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return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL);
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}
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break;
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case 0x2:
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