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ISA: Simplify various implementations of completeAcc.

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This commit is contained in:
Gabe Black 2010-10-22 00:23:19 -07:00
parent bc49381287
commit 29676286c8
6 changed files with 11 additions and 106 deletions
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15
src/arch/alpha/isa/mem.isa
View file

@ -354,20 +354,7 @@ def template StoreCompleteAcc {{
%(CPU_exec_context)s *xc, %(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const Trace::InstRecord *traceData) const
{ {
Fault fault = NoFault; return NoFault;
%(fp_enable_check)s;
%(op_dest_decl)s;
if (fault == NoFault) {
%(postacc_code)s;
}
if (fault == NoFault) {
%(op_wb)s;
}
return fault;
} }
}}; }};

36
src/arch/arm/isa/templates/mem.isa
View file

@ -595,23 +595,11 @@ def template StoreCompleteAcc {{
%(CPU_exec_context)s *xc, %(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const Trace::InstRecord *traceData) const
{ {
Fault fault = NoFault; if (machInst.itstateMask != 0) {
warn_once("Complete acc isn't called on normal stores in O3.");
%(op_decl)s;
%(op_rd)s;
if (%(predicate_test)s)
{
if (fault == NoFault) {
%(op_wb)s;
}
}
if (fault == NoFault && machInst.itstateMask != 0) {
xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
} }
return NoFault;
return fault;
} }
}}; }};
@ -621,23 +609,11 @@ def template NeonStoreCompleteAcc {{
PacketPtr pkt, %(CPU_exec_context)s *xc, PacketPtr pkt, %(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const Trace::InstRecord *traceData) const
{ {
Fault fault = NoFault; if (machInst.itstateMask != 0) {
warn_once("Complete acc isn't called on normal stores in O3.");
%(op_decl)s;
%(op_rd)s;
if (%(predicate_test)s)
{
if (fault == NoFault) {
%(op_wb)s;
}
}
if (fault == NoFault && machInst.itstateMask != 0) {
xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
} }
return NoFault;
return fault;
} }
}}; }};

10
src/arch/arm/isa/templates/misc.isa
View file

@ -387,17 +387,11 @@ def template ClrexCompleteAcc {{
%(CPU_exec_context)s *xc, %(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const Trace::InstRecord *traceData) const
{ {
Fault fault = NoFault; if (machInst.itstateMask != 0) {
%(op_decl)s;
%(op_rd)s;
if (fault == NoFault && machInst.itstateMask != 0) {
xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
} }
return fault; return NoFault;
} }
}}; }};

37
src/arch/mips/isa/formats/mem.isa
View file

@ -420,42 +420,7 @@ def template StoreCompleteAcc {{
%(CPU_exec_context)s *xc, %(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const Trace::InstRecord *traceData) const
{ {
Fault fault = NoFault; return NoFault;
%(fp_enable_check)s;
%(op_dest_decl)s;
if (fault == NoFault) {
%(postacc_code)s;
}
if (fault == NoFault) {
%(op_wb)s;
}
return fault;
}
}};
def template StoreCompleteAcc {{
Fault %(class_name)s::completeAcc(Packet *pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_dest_decl)s;
if (fault == NoFault) {
%(postacc_code)s;
}
if (fault == NoFault) {
%(op_wb)s;
}
return fault;
} }
}}; }};

10
src/arch/power/isa/formats/mem.isa
View file

@ -212,15 +212,7 @@ def template StoreCompleteAcc {{
%(CPU_exec_context)s *xc, %(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const Trace::InstRecord *traceData) const
{ {
Fault fault = NoFault; return NoFault;
%(op_dest_decl)s;
if (fault == NoFault) {
%(op_wb)s;
}
return fault;
} }
}}; }};

9
src/arch/sparc/isa/formats/mem/util.isa
View file

@ -272,15 +272,6 @@ def template StoreCompleteAcc {{
Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc, Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc,
Trace::InstRecord * traceData) const Trace::InstRecord * traceData) const
{ {
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
%(postacc_code)s;
if (fault == NoFault)
{
%(op_wb)s;
}
return NoFault; return NoFault;
} }
}}; }};