Make Sparc traceflag even more chatty
some fixes to fp instructions to use the single precision registers if this is an fp op emit fp check code add fpregs to m5legion struct src/arch/sparc/floatregfile.cc: Make Sparc traceflag even more chatty src/arch/sparc/isa/base.isa: add code to check if the fpu is enabled src/arch/sparc/isa/decoder.isa: some fixes to fp instructions to use the single precision registers fix smul again fix subc/subcc/subccc condition code setting src/arch/sparc/isa/formats/basic.isa: src/arch/sparc/isa/formats/mem/util.isa: if this is an fp op emit fp check code src/cpu/exetrace.cc: check fp regs as well as int regs src/cpu/m5legion_interface.h: add fpregs to m5legion struct --HG-- extra : convert_revision : e7d26d10fb8ce88f96e3a51f84b48c3b3ad2f232
This commit is contained in:
parent
8561c8366c
commit
2939d7d061
7 changed files with 82 additions and 43 deletions
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@ -72,16 +72,19 @@ FloatReg FloatRegFile::readReg(int floatReg, int width)
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float32_t result32;
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memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32));
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result = htog(result32);
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DPRINTF(Sparc, "Read FP32 register %d = 0x%x\n", floatReg, result);
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break;
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case DoubleWidth:
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float64_t result64;
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memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64));
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result = htog(result64);
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DPRINTF(Sparc, "Read FP64 register %d = 0x%x\n", floatReg, result);
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break;
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case QuadWidth:
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float128_t result128;
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memcpy(&result128, regSpace + 4 * floatReg, sizeof(result128));
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result = htog(result128);
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DPRINTF(Sparc, "Read FP128 register %d = 0x%x\n", floatReg, result);
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break;
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default:
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panic("Attempted to read a %d bit floating point register!", width);
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@ -101,16 +104,19 @@ FloatRegBits FloatRegFile::readRegBits(int floatReg, int width)
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uint32_t result32;
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memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32));
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result = htog(result32);
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DPRINTF(Sparc, "Read FP32 bits register %d = 0x%x\n", floatReg, result);
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break;
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case DoubleWidth:
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uint64_t result64;
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memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64));
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result = htog(result64);
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DPRINTF(Sparc, "Read FP64 bits register %d = 0x%x\n", floatReg, result);
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break;
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case QuadWidth:
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uint64_t result128;
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memcpy(&result128, regSpace + 4 * floatReg, sizeof(result128));
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result = htog(result128);
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DPRINTF(Sparc, "Read FP128 bits register %d = 0x%x\n", floatReg, result);
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break;
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default:
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panic("Attempted to read a %d bit floating point register!", width);
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@ -1,4 +1,4 @@
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// Copyright (c) 2006 The Regents of The University of Michigan
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// Copyright (c) 2006-2007 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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@ -290,3 +290,27 @@ output decoder {{
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}
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}};
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output exec {{
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/// Check "FP enabled" machine status bit. Called when executing any FP
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/// instruction in full-system mode.
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/// @retval Full-system mode: NoFault if FP is enabled, FpDisabled
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/// if not. Non-full-system mode: always returns NoFault.
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#if FULL_SYSTEM
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inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
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{
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Fault fault = NoFault; // dummy... this ipr access should not fault
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if (xc->readMiscRegWithEffect(MISCREG_PSTATE) & PSTATE::pef &&
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xc->readMiscRegWithEffect(MISCREG_FPRS) & 0x4)
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return NoFault;
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else
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return new FpDisabled;
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}
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#else
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inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
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{
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return NoFault;
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}
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#endif
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}};
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@ -186,7 +186,7 @@ decode OP default Unknown::unknown()
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Y = Rd<63:32>;
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}});
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0x0B: smul({{
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Rd.sdw = sext<32>(Rs1.sdw) * sext<32>(Rs2_or_imm13);
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Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
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Y = Rd.sdw<63:32>;
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}});
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0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
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@ -246,8 +246,7 @@ decode OP default Unknown::unknown()
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Rd = resTemp = Rs1 + val2 + carryin;}},
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{{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
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{{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
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{{(Rs1<63:1> + val2<63:1> +
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((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
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{{((Rs1 & val2) | (~resTemp & (Rs1 | val2)))<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
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);
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0x1A: umulcc({{
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@ -257,16 +256,16 @@ decode OP default Unknown::unknown()
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{{0}},{{0}},{{0}},{{0}});
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0x1B: smulcc({{
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int64_t resTemp;
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Rd = resTemp = sext<32>(Rs1.sdw) * sext<32>(Rs2_or_imm13);
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Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
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Y = resTemp<63:32>;}},
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{{0}},{{0}},{{0}},{{0}});
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0x1C: subccc({{
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int64_t resTemp, val2 = Rs2_or_imm13;
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int64_t carryin = Ccr<0:0>;
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Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
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{{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
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{{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<31:>}},
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{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
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{{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
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{{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<63:>}},
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{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
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);
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0x1D: udivxcc({{
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Fsr &= ~(7 << 14);
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Fsr &= ~(0x1F);
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}});
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0x03: Trap::fmovq({{fault = new FpDisabled;}});
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0x03: Trap::fmovq({{fault = new FpExceptionOther;}});
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0x05: fnegs({{
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Frds.uw = Frs2s.uw ^ (1UL << 31);
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//fsr.ftt = fsr.cexc = 0
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@ -860,11 +859,11 @@ decode OP default Unknown::unknown()
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0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
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0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
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0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
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0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}});
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0x75: BasicOperate::fsrc1s({{Frds.uw = Frs1s.uw;}});
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0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
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0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
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0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
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0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}});
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0x79: BasicOperate::fsrc2s({{Frds.uw = Frs2s.uw;}});
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0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
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0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
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0x7C: Trap::for({{fault = new IllegalInstruction;}});
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@ -1130,14 +1129,14 @@ decode OP default Unknown::unknown()
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{{ Mem.uw = Rd.uw;
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Rd.uw = uReg0;}}, {{EXT_ASI}});
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format Trap {
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0x20: Load::ldf({{Frd.uw = Mem.uw;}});
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0x20: Load::ldf({{Frds.uw = Mem.uw;}});
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0x21: decode X {
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0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
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0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
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}
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0x22: ldqf({{fault = new FpDisabled;}});
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0x23: Load::lddf({{Frd.udw = Mem.udw;}});
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0x24: Store::stf({{Mem.uw = Frd.uw;}});
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0x24: Store::stf({{Mem.uw = Frds.uw;}});
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0x25: decode X {
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0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}});
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0x1: Store::stxfsr({{Mem.udw = Fsr;}});
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@ -1145,7 +1144,7 @@ decode OP default Unknown::unknown()
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0x26: stqf({{fault = new FpDisabled;}});
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0x27: Store::stdf({{Mem.udw = Frd.udw;}});
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0x2D: Nop::prefetch({{ }});
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0x30: LoadAlt::ldfa({{Frd.uw = Mem.uw;}}, {{EXT_ASI}});
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0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}});
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0x32: ldqfa({{fault = new FpDisabled;}});
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format LoadAlt {
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0x33: decode EXT_ASI {
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{{fault = new DataAccessException;}});
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}
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}
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0x34: Store::stfa({{Mem.uw = Frd.uw;}});
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0x34: Store::stfa({{Mem.uw = Frds.uw;}});
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0x36: stqfa({{fault = new FpDisabled;}});
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format StoreAlt {
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0x37: decode EXT_ASI {
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@ -1,4 +1,4 @@
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// Copyright (c) 2006 The Regents of The University of Michigan
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// Copyright (c) 2006-2007 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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@ -71,6 +71,7 @@ def template BasicExecute {{
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{
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Fault fault = NoFault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(code)s;
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@ -1,4 +1,4 @@
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// Copyright (c) 2006 The Regents of The University of Michigan
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// Copyright (c) 2006-2007 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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{
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Fault fault = NoFault;
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Addr EA;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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Fault fault = NoFault;
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Addr EA;
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uint%(mem_acc_size)s_t Mem;
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%(fp_enable_check)s;
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%(ea_decl)s;
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%(ea_rd)s;
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%(ea_code)s;
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//It should be optomized out in all the others
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bool storeCond = true;
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Addr EA;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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Fault fault = NoFault;
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bool storeCond = true;
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Addr EA;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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@ -293,7 +293,8 @@ Trace::InstRecord::dump(ostream &outs)
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bool diffPC = false;
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bool diffCC = false;
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bool diffInst = false;
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bool diffRegs = false;
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bool diffIntRegs = false;
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bool diffFpRegs = false;
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bool diffTpc = false;
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bool diffTnpc = false;
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bool diffTstate = false;
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}
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for (int i = 0; i < TheISA::NumIntArchRegs; i++) {
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if (thread->readIntReg(i) != shared_data->intregs[i]) {
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diffRegs = true;
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diffIntRegs = true;
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}
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}
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for (int i = 0; i < TheISA::NumFloatRegs/2; i++) {
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if (thread->readFloatRegBits(i,FloatRegFile::DoubleWidth) != shared_data->fpregs[i]) {
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diffFpRegs = true;
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}
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}
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uint64_t oldTl = thread->readMiscReg(MISCREG_TL);
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diffTlb = true;
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}
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if ((diffPC || diffCC || diffInst || diffRegs || diffTpc ||
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diffTnpc || diffTstate || diffTt || diffHpstate ||
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diffHtstate || diffHtba || diffPstate || diffY ||
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diffCcr || diffTl || diffGl || diffAsi || diffPil ||
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diffCwp || diffCansave || diffCanrestore ||
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diffOtherwin || diffCleanwin || diffTlb)
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if ((diffPC || diffCC || diffInst || diffIntRegs ||
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diffFpRegs || diffTpc || diffTnpc || diffTstate ||
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diffTt || diffHpstate || diffHtstate || diffHtba ||
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diffPstate || diffY || diffCcr || diffTl || diffGl ||
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diffAsi || diffPil || diffCwp || diffCansave ||
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diffCanrestore || diffOtherwin || diffCleanwin || diffTlb)
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&& !((staticInst->machInst & 0xC1F80000) == 0x81D00000)
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&& !(((staticInst->machInst & 0xC0000000) == 0xC0000000)
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&& shared_data->tl == thread->readMiscReg(MISCREG_TL) + 1)
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@ -444,8 +450,10 @@ Trace::InstRecord::dump(ostream &outs)
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outs << " [CC]";
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if (diffInst)
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outs << " [Instruction]";
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if (diffRegs)
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if (diffIntRegs)
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outs << " [IntRegs]";
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if (diffFpRegs)
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outs << " [FpRegs]";
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if (diffTpc)
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outs << " [Tpc]";
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if (diffTnpc)
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@ -588,26 +596,22 @@ Trace::InstRecord::dump(ostream &outs)
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printSectionHeader(outs, "General Purpose Registers");
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static const char * regtypes[4] = {"%g", "%o", "%l", "%i"};
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for(int y = 0; y < 4; y++)
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{
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for(int x = 0; x < 8; x++)
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{
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for(int y = 0; y < 4; y++) {
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for(int x = 0; x < 8; x++) {
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char label[8];
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sprintf(label, "%s%d", regtypes[y], x);
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printRegPair(outs, label,
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thread->readIntReg(y*8+x),
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shared_data->intregs[y*8+x]);
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/*outs << regtypes[y] << x << " " ;
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outs << "0x" << hex << setw(16)
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<< thread->readIntReg(y*8+x);
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if (thread->readIntReg(y*8 + x)
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!= shared_data->intregs[y*8+x])
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outs << " X ";
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else
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outs << " | ";
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outs << "0x" << setw(16) << hex
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<< shared_data->intregs[y*8+x]
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<< endl;*/
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}
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}
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if (diffFpRegs) {
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for (int x = 0; x < 32; x++) {
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char label[8];
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sprintf(label, "%%f%d", x);
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printRegPair(outs, label,
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thread->readFloatRegBits(x,FloatRegFile::DoubleWidth),
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shared_data->fpregs[x]);
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}
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}
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if (diffTlb) {
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* Copyright (c) 2006-2007 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -30,7 +30,7 @@
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#include <unistd.h>
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#define VERSION 0xA1000007
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#define VERSION 0xA1000008
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#define OWN_M5 0x000000AA
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#define OWN_LEGION 0x00000055
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@ -47,6 +47,7 @@ typedef struct {
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uint32_t instruction;
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uint32_t new_instruction;
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uint64_t intregs[32];
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uint64_t fpregs[32];
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uint64_t tpc[8];
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uint64_t tnpc[8];
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