quiet/remove some warnings
fix implementation of cwp manipulation implement PS0 and PS1 IMMU asis src/arch/sparc/miscregfile.cc: get rid of some warnings fix implementation of setting cwp to saturate cwp since it appears the os sets it to a large value to see how many there actually are src/arch/sparc/tlb.cc: implement PS0 and PS1 IMMU access ASIs src/arch/sparc/ua2005.cc: make warning less verbose --HG-- extra : convert_revision : 442b65dfc41ebc32b2ef0e6b80da94eee3be9cd3
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7933aade85
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28a83c6d1c
3 changed files with 39 additions and 7 deletions
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@ -326,7 +326,6 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
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return mbits(tc->getCpuPtr()->instCount() + (int64_t)stick,62,2) |
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return mbits(tc->getCpuPtr()->instCount() + (int64_t)stick,62,2) |
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mbits(tick,63,63);
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mbits(tick,63,63);
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case MISCREG_FPRS:
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case MISCREG_FPRS:
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warn("FPRS register read and FPU stuff not really implemented\n");
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// in legion if fp is enabled du and dl are set
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// in legion if fp is enabled du and dl are set
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if (fprs & 0x4)
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if (fprs & 0x4)
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return 0x7;
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return 0x7;
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@ -389,7 +388,6 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
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asi = val;
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asi = val;
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break;
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break;
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case MISCREG_FPRS:
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case MISCREG_FPRS:
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warn("FPU not really implemented writing %#X to FPRS\n", val);
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fprs = val;
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fprs = val;
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break;
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break;
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case MISCREG_TICK:
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case MISCREG_TICK:
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@ -612,6 +610,8 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
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void MiscRegFile::setRegWithEffect(int miscReg,
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void MiscRegFile::setRegWithEffect(int miscReg,
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const MiscReg &val, ThreadContext * tc)
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const MiscReg &val, ThreadContext * tc)
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{
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{
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MiscReg new_val = val;
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switch (miscReg) {
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switch (miscReg) {
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case MISCREG_STICK:
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case MISCREG_STICK:
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case MISCREG_TICK:
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case MISCREG_TICK:
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@ -634,7 +634,8 @@ void MiscRegFile::setRegWithEffect(int miscReg,
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tl = val;
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tl = val;
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return;
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return;
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case MISCREG_CWP:
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case MISCREG_CWP:
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tc->changeRegFileContext(CONTEXT_CWP, val);
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new_val = val > NWindows ? NWindows - 1 : val;
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tc->changeRegFileContext(CONTEXT_CWP, new_val);
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break;
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break;
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case MISCREG_GL:
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case MISCREG_GL:
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tc->changeRegFileContext(CONTEXT_GLOBALS, val);
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tc->changeRegFileContext(CONTEXT_GLOBALS, val);
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@ -671,7 +672,7 @@ void MiscRegFile::setRegWithEffect(int miscReg,
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panic("Accessing Fullsystem register %s to %#x in SE mode\n", getMiscRegName(miscReg), val);
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panic("Accessing Fullsystem register %s to %#x in SE mode\n", getMiscRegName(miscReg), val);
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#endif
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#endif
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}
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}
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setReg(miscReg, val);
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setReg(miscReg, new_val);
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}
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}
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void MiscRegFile::serialize(std::ostream & os)
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void MiscRegFile::serialize(std::ostream & os)
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@ -625,13 +625,13 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
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return new DataAccessException;
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return new DataAccessException;
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}
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}
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} else if (hpriv) {
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} /*else if (hpriv) {*/
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if (asi == ASI_P) {
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if (asi == ASI_P) {
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ct = Primary;
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ct = Primary;
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context = pri_context;
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context = pri_context;
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goto continueDtbFlow;
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goto continueDtbFlow;
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}
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}
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}
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//}
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if (!implicit) {
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if (!implicit) {
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if (AsiIsLittle(asi))
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if (AsiIsLittle(asi))
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@ -933,6 +933,36 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
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mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
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mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
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pkt->set(data);
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pkt->set(data);
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break;
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break;
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case ASI_IMMU_TSB_PS0_PTR_REG:
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temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
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if (bits(temp,12,0) == 0) {
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tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0);
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cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
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} else {
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tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0);
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cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
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}
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data = mbits(tsbtemp,63,13);
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data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
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mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
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pkt->set(data);
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break;
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case ASI_IMMU_TSB_PS1_PTR_REG:
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temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
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if (bits(temp,12,0) == 0) {
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tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1);
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cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
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} else {
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tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1);
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cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
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}
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data = mbits(tsbtemp,63,13);
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if (bits(tsbtemp,12,12))
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data |= ULL(1) << (13+bits(tsbtemp,3,0));
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data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
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mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
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pkt->set(data);
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break;
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default:
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default:
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doMmuReadError:
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doMmuReadError:
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@ -47,6 +47,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
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// Check if we are going to interrupt because of something
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// Check if we are going to interrupt because of something
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setReg(miscReg, val);
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setReg(miscReg, val);
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tc->getCpuPtr()->checkInterrupts = true;
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tc->getCpuPtr()->checkInterrupts = true;
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if (val != 0x10000 && val != 0)
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warn("Writing to softint not really supported, writing: %#x\n", val);
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warn("Writing to softint not really supported, writing: %#x\n", val);
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break;
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break;
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