config: Add XOR hashing to the DRAM channel interleaving

This patch uses the recently added XOR hashing capabilities for the
DRAM channel interleaving. This avoids channel biasing due to strided
access patterns.
This commit is contained in:
Andreas Hansson 2015-02-03 14:25:55 -05:00
parent ccb512ecc1
commit 28a7cea2b3

View file

@ -137,6 +137,13 @@ def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
import math import math
intlv_low_bit = int(math.log(intlv_size, 2)) intlv_low_bit = int(math.log(intlv_size, 2))
# Use basic hashing for the channel selection, and preferably use
# the lower tag bits from the last level cache. As we do not know
# the details of the caches here, make an educated guess. 4 MByte
# 4-way associative with 64 byte cache lines is 6 offset bits and
# 14 index bits.
xor_low_bit = 20
# Create an instance so we can figure out the address # Create an instance so we can figure out the address
# mapping and row-buffer size # mapping and row-buffer size
ctrl = cls() ctrl = cls()
@ -165,6 +172,8 @@ def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
ctrl.range = m5.objects.AddrRange(r.start, size = r.size(), ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
intlvHighBit = \ intlvHighBit = \
intlv_low_bit + intlv_bits - 1, intlv_low_bit + intlv_bits - 1,
xorHighBit = \
xor_low_bit + intlv_bits - 1,
intlvBits = intlv_bits, intlvBits = intlv_bits,
intlvMatch = i) intlvMatch = i)
return ctrl return ctrl