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ARM: Align the PC when using it as the base for a load.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:04 -05:00
parent d63f748b53
commit 28227440a7
1 changed files with 5 additions and 1 deletions
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6
src/arch/arm/isa/operands.isa
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@ -56,6 +56,10 @@ let {{
((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) : ((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) :
xc->%(func)s(this, %(op_idx)s)) xc->%(func)s(this, %(op_idx)s))
''' '''
maybeAlignedPCRead = '''
((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc) & ~PcModeMask, 4)) :
xc->%(func)s(this, %(op_idx)s))
'''
maybePCWrite = ''' maybePCWrite = '''
((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) : ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
xc->%(func)s(this, %(op_idx)s, %(final_val)s)) xc->%(func)s(this, %(op_idx)s, %(final_val)s))
@ -91,7 +95,7 @@ def operands {{
'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
maybePCRead, maybeAIWPCWrite), maybePCRead, maybeAIWPCWrite),
'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1, 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
maybePCRead, maybePCWrite), maybeAlignedPCRead, maybePCWrite),
'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2, 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
maybePCRead, maybePCWrite), maybePCRead, maybePCWrite),
'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3, 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,