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Merge IGNORE_STYLE change and my change.

Browse source 
--HG--
extra : convert_revision : 13880ec6df17b0317d4097243bb24add753a098a
This commit is contained in:
Ali Saidi 2007-08-13 23:44:26 -04:00
parent b069b81acf 9b4be65327
commit 27ddf0b40e
120 changed files with 5898 additions and 4926 deletions
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2
SConstruct
View file

@ -118,7 +118,7 @@ pretxncommit.style = python:style.check_whitespace
""" % (ROOT)
sys.exit(1)
if isdir(joinpath(ROOT, '.hg')):
if ARGUMENTS.get('IGNORE_STYLE') != 'True' and isdir(joinpath(ROOT, '.hg')):
try:
from mercurial import ui
check_style_hook(ui.ui())

7
configs/common/Caches.py
View file

@ -43,3 +43,10 @@ class L2Cache(BaseCache):
mshrs = 20
tgts_per_mshr = 12
class IOCache(BaseCache):
assoc = 8
block_size = 64
latency = '10ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12

4
configs/common/FSConfig.py
View file

@ -53,7 +53,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
self.readfile = mdesc.script()
self.iobus = Bus(bus_id=0)
self.membus = Bus(bus_id=1)
self.bridge = Bridge(fix_partial_write_b=True, delay='50ns', nack_delay='4ns')
self.bridge = Bridge(delay='50ns', nack_delay='4ns')
self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
self.bridge.side_a = self.iobus.port
self.bridge.side_b = self.membus.port
@ -93,7 +93,7 @@ def makeSparcSystem(mem_mode, mdesc = None):
self.readfile = mdesc.script()
self.iobus = Bus(bus_id=0)
self.membus = Bus(bus_id=1)
self.bridge = Bridge(fix_partial_write_b=True, delay='50ns', nack_delay='4ns')
self.bridge = Bridge(delay='50ns', nack_delay='4ns')
self.t1000 = T1000()
self.t1000.attachOnChipIO(self.membus)
self.t1000.attachIO(self.iobus)

1
configs/common/Options.py
View file

@ -32,6 +32,7 @@ parser.add_option("-t", "--timing", action="store_true")
parser.add_option("-n", "--num_cpus", type="int", default=1)
parser.add_option("--caches", action="store_true")
parser.add_option("--l2cache", action="store_true")
parser.add_option("--fastmem", action="store_true")
# Run duration options
parser.add_option("-m", "--maxtick", type="int")

12
configs/example/fs.py
View file

@ -121,12 +121,20 @@ for i in xrange(np):
if options.caches:
test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
test_sys.iocache = IOCache(mem_side_filter_ranges=[AddrRange(0, Addr.max)],
cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)])
test_sys.iocache.cpu_side = test_sys.iobus.port
test_sys.iocache.mem_side = test_sys.membus.port
if options.l2cache:
test_sys.cpu[i].connectMemPorts(test_sys.tol2bus)
else:
test_sys.cpu[i].connectMemPorts(test_sys.membus)
if options.fastmem:
test_sys.cpu[i].physmem_port = test_sys.physmem.port
if len(bm) == 2:
if m5.build_env['TARGET_ISA'] == 'alpha':
drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
@ -134,6 +142,8 @@ if len(bm) == 2:
drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
drive_sys.cpu = DriveCPUClass(cpu_id=0)
drive_sys.cpu.connectMemPorts(drive_sys.membus)
if options.fastmem:
drive_sys.cpu.physmem_port = drive_sys.physmem.port
if options.kernel is not None:
drive_sys.kernel = binary(options.kernel)

3
configs/example/se.py
View file

@ -114,6 +114,9 @@ for i in xrange(np):
system.cpu[i].connectMemPorts(system.membus)
system.cpu[i].workload = process
if options.fastmem:
system.cpu[0].physmem_port = system.physmem.port
root = Root(system = system)
Simulation.run(options, root, system, FutureClass)

33
src/arch/alpha/tlb.cc
View file

@ -75,21 +75,26 @@ TLB::~TLB()
// look up an entry in the TLB
PTE *
TLB::lookup(Addr vpn, uint8_t asn) const
TLB::lookup(Addr vpn, uint8_t asn)
{
// assume not found...
PTE *retval = NULL;
if (PTECache[0] && vpn == PTECache[0]->tag &&
(PTECache[0]->asma || PTECache[0]->asn == asn))
retval = PTECache[0];
else if (PTECache[1] && vpn == PTECache[1]->tag &&
(PTECache[1]->asma || PTECache[1]->asn == asn))
retval = PTECache[1];
else if (PTECache[2] && vpn == PTECache[2]->tag &&
(PTECache[2]->asma || PTECache[2]->asn == asn))
retval = PTECache[2];
else {
if (PTECache[0]) {
if (vpn == PTECache[0]->tag &&
(PTECache[0]->asma || PTECache[0]->asn == asn))
retval = PTECache[0];
else if (PTECache[1]) {
if (vpn == PTECache[1]->tag &&
(PTECache[1]->asma || PTECache[1]->asn == asn))
retval = PTECache[1];
else if (PTECache[2] && vpn == PTECache[2]->tag &&
(PTECache[2]->asma || PTECache[2]->asn == asn))
retval = PTECache[2];
}
}
if (retval == NULL) {
PageTable::const_iterator i = lookupTable.find(vpn);
if (i != lookupTable.end()) {
while (i->first == vpn) {
@ -97,7 +102,7 @@ TLB::lookup(Addr vpn, uint8_t asn) const
PTE *pte = &table[index];
assert(pte->valid);
if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
retval = pte;
retval = updateCache(pte);
break;
}
@ -307,7 +312,7 @@ ITB::regStats()
Fault
ITB::translate(RequestPtr &req, ThreadContext *tc) const
ITB::translate(RequestPtr &req, ThreadContext *tc)
{
//If this is a pal pc, then set PHYSICAL
if(FULL_SYSTEM && PcPAL(req->getPC()))
@ -469,7 +474,7 @@ DTB::regStats()
}
Fault
DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
{
Addr pc = tc->readPC();

12
src/arch/alpha/tlb.hh
View file

@ -61,7 +61,7 @@ namespace AlphaISA
int nlu; // not last used entry (for replacement)
void nextnlu() { if (++nlu >= size) nlu = 0; }
PTE *lookup(Addr vpn, uint8_t asn) const;
PTE *lookup(Addr vpn, uint8_t asn);
public:
TLB(const std::string &name, int size);
@ -92,6 +92,12 @@ namespace AlphaISA
// Most recently used page table entries
PTE *PTECache[3];
inline void flushCache() { memset(PTECache, 0, 3 * sizeof(PTE*)); }
inline PTE* updateCache(PTE *pte) {
PTECache[2] = PTECache[1];
PTECache[1] = PTECache[0];
PTECache[0] = pte;
return pte;
}
};
class ITB : public TLB
@ -106,7 +112,7 @@ namespace AlphaISA
ITB(const std::string &name, int size);
virtual void regStats();
Fault translate(RequestPtr &req, ThreadContext *tc) const;
Fault translate(RequestPtr &req, ThreadContext *tc);
};
class DTB : public TLB
@ -129,7 +135,7 @@ namespace AlphaISA
DTB(const std::string &name, int size);
virtual void regStats();
Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const;
Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
};
}

2
src/base/compiler.hh
View file

@ -40,11 +40,13 @@
#define M5_ATTR_NORETURN __attribute__((noreturn))
#define M5_PRAGMA_NORETURN(x)
#define M5_DUMMY_RETURN
#define M5_VAR_USED __attribute__((unused))
#elif defined(__SUNPRO_CC)
// this doesn't do anything with sun cc, but why not
#define M5_ATTR_NORETURN __sun_attr__((__noreturn__))
#define M5_DUMMY_RETURN return (0);
#define DO_PRAGMA(x) _Pragma(#x)
#define M5_VAR_USED
#define M5_PRAGMA_NORETURN(x) DO_PRAGMA(does_not_return(x))
#else
#error "Need to define compiler options in base/compiler.hh"

55
src/base/range_ops.hh Normal file
View file

@ -0,0 +1,55 @@
/*
* Copyright (c) 2007 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Ali Saidi
*/
#ifndef __BASE_RANGE_OPS_HH__
#define __BASE_RANGE_OPS_HH__
#include <list>
#include <vector>
#include "base/range.hh"
template <class T>
inline void
FilterRangeList(std::vector<Range<T> > filter_list, std::list<Range<T> >
&range_list) {
typename std::list<Range<T> >::iterator i;
for (int x = 0; x < filter_list.size(); x++) {
for (i = range_list.begin(); i != range_list.end(); ) {
// Is the range within one of our filter ranges?
if (filter_list[x] == i->start || filter_list[x] == i->end)
range_list.erase(i++);
else
i++;
}
}
}
#endif //__BASE_RANGE_OPS_HH__

5
src/cpu/BaseCPU.py
View file

@ -93,10 +93,11 @@ class BaseCPU(SimObject):
def connectMemPorts(self, bus):
for p in self._mem_ports:
exec('self.%s = bus.port' % p)
if p != 'physmem_port':
exec('self.%s = bus.port' % p)
def addPrivateSplitL1Caches(self, ic, dc):
assert(len(self._mem_ports) == 2)
assert(len(self._mem_ports) == 2 or len(self._mem_ports) == 3)
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side

3
src/cpu/simple/AtomicSimpleCPU.py
View file

@ -40,4 +40,5 @@ class AtomicSimpleCPU(BaseCPU):
profile = Param.Latency('0ns', "trace the kernel stack")
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
_mem_ports = ['icache_port', 'dcache_port']
physmem_port = Port("Physical Memory Port")
_mem_ports = ['icache_port', 'dcache_port', 'physmem_port']

33
src/cpu/simple/atomic.cc
View file

@ -67,6 +67,10 @@ AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
return &dcachePort;
else if (if_name == "icache_port")
return &icachePort;
else if (if_name == "physmem_port") {
hasPhysMemPort = true;
return &physmemPort;
}
else
panic("No Such Port\n");
}
@ -83,6 +87,12 @@ AtomicSimpleCPU::init()
TheISA::initCPU(tc, tc->readCpuId());
}
#endif
if (hasPhysMemPort) {
bool snoop = false;
AddrRangeList pmAddrList;
physmemPort.getPeerAddressRanges(pmAddrList, snoop);
physMemAddr = *pmAddrList.begin();
}
}
bool
@ -141,7 +151,8 @@ AtomicSimpleCPU::DcachePort::setPeer(Port *port)
AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
: BaseSimpleCPU(p), tickEvent(this),
width(p->width), simulate_stalls(p->simulate_stalls),
icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
physmemPort(name() + "-iport", this), hasPhysMemPort(false)
{
_status = Idle;
@ -293,8 +304,12 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
if (req->isMmapedIpr())
dcache_latency = TheISA::handleIprRead(thread->getTC(), &pkt);
else
dcache_latency = dcachePort.sendAtomic(&pkt);
else {
if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
dcache_latency = physmemPort.sendAtomic(&pkt);
else
dcache_latency = dcachePort.sendAtomic(&pkt);
}
dcache_access = true;
assert(!pkt.isError());
@ -402,7 +417,10 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
dcache_latency = TheISA::handleIprWrite(thread->getTC(), &pkt);
} else {
data = htog(data);
dcache_latency = dcachePort.sendAtomic(&pkt);
if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
dcache_latency = physmemPort.sendAtomic(&pkt);
else
dcache_latency = dcachePort.sendAtomic(&pkt);
}
dcache_access = true;
assert(!pkt.isError());
@ -513,7 +531,12 @@ AtomicSimpleCPU::tick()
Packet::Broadcast);
ifetch_pkt.dataStatic(&inst);
icache_latency = icachePort.sendAtomic(&ifetch_pkt);
if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
else
icache_latency = icachePort.sendAtomic(&ifetch_pkt);
// ifetch_req is initialized to read the instruction directly
// into the CPU object's inst field.
//}

4
src/cpu/simple/atomic.hh
View file

@ -121,6 +121,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
};
DcachePort dcachePort;
CpuPort physmemPort;
bool hasPhysMemPort;
Request ifetch_req;
Request data_read_req;
Request data_write_req;
@ -128,6 +130,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
bool dcache_access;
Tick dcache_latency;
Range<Addr> physMemAddr;
public:
virtual Port *getPort(const std::string &if_name, int idx = -1);

3
src/dev/io_device.hh
View file

@ -266,8 +266,7 @@ class DmaDevice : public PioDevice
void dmaWrite(Addr addr, int size, Event *event, uint8_t *data)
{
dmaPort->dmaAction(MemCmd::WriteInvalidateReq,
addr, size, event, data);
dmaPort->dmaAction(MemCmd::WriteReq, addr, size, event, data);
}
void dmaRead(Addr addr, int size, Event *event, uint8_t *data)

6
src/mem/Bridge.py
View file

@ -40,5 +40,7 @@ class Bridge(MemObject):
delay = Param.Latency('0ns', "The latency of this bridge")
nack_delay = Param.Latency('0ns', "The latency of this bridge")
write_ack = Param.Bool(False, "Should this bridge ack writes")
fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes")
fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes")
filter_ranges_a = VectorParam.AddrRange([],
"What addresses shouldn't be passed through the side of the bridge")
filter_ranges_b = VectorParam.AddrRange([],
"What addresses shouldn't be passed through the side of the bridge")

33
src/mem/bridge.cc
View file

@ -37,6 +37,7 @@
#include <algorithm>
#include "base/range_ops.hh"
#include "base/trace.hh"
#include "mem/bridge.hh"
#include "params/Bridge.hh"
@ -44,9 +45,10 @@
Bridge::BridgePort::BridgePort(const std::string &_name,
Bridge *_bridge, BridgePort *_otherPort,
int _delay, int _nack_delay, int _req_limit,
int _resp_limit, bool fix_partial_write)
int _resp_limit,
std::vector<Range<Addr> > filter_ranges)
: Port(_name), bridge(_bridge), otherPort(_otherPort),
delay(_delay), nackDelay(_nack_delay), fixPartialWrite(fix_partial_write),
delay(_delay), nackDelay(_nack_delay), filterRanges(filter_ranges),
outstandingResponses(0), queuedRequests(0), inRetry(false),
reqQueueLimit(_req_limit), respQueueLimit(_resp_limit), sendEvent(this)
{
@ -55,9 +57,9 @@ Bridge::BridgePort::BridgePort(const std::string &_name,
Bridge::Bridge(Params *p)
: MemObject(p->name),
portA(p->name + "-portA", this, &portB, p->delay, p->nack_delay,
p->req_size_a, p->resp_size_a, p->fix_partial_write_a),
p->req_size_a, p->resp_size_a, p->filter_ranges_a),
portB(p->name + "-portB", this, &portA, p->delay, p->nack_delay,
p->req_size_b, p->resp_size_b, p->fix_partial_write_b),
p->req_size_b, p->resp_size_b, p->filter_ranges_b),
ackWrites(p->write_ack), _params(p)
{
if (ackWrites)
@ -243,17 +245,6 @@ Bridge::BridgePort::trySend()
PacketPtr pkt = buf->pkt;
// Ugly! @todo When multilevel coherence works this will be removed
if (pkt->cmd == MemCmd::WriteInvalidateReq && fixPartialWrite &&
!pkt->wasNacked()) {
PacketPtr funcPkt = new Packet(pkt->req, MemCmd::WriteReq,
Packet::Broadcast);
funcPkt->dataStatic(pkt->getPtr<uint8_t>());
sendFunctional(funcPkt);
pkt->cmd = MemCmd::WriteReq;
delete funcPkt;
}
DPRINTF(BusBridge, "trySend: origSrc %d dest %d addr 0x%x\n",
buf->origSrc, pkt->getDest(), pkt->getAddr());
@ -313,17 +304,6 @@ Bridge::BridgePort::recvRetry()
Tick
Bridge::BridgePort::recvAtomic(PacketPtr pkt)
{
// fix partial atomic writes... similar to the timing code that does the
// same... will be removed once our code gets this right
if (pkt->cmd == MemCmd::WriteInvalidateReq && fixPartialWrite) {
PacketPtr funcPkt = new Packet(pkt->req, MemCmd::WriteReq,
Packet::Broadcast);
funcPkt->dataStatic(pkt->getPtr<uint8_t>());
otherPort->sendFunctional(funcPkt);
delete funcPkt;
pkt->cmd = MemCmd::WriteReq;
}
return delay + otherPort->sendAtomic(pkt);
}
@ -355,6 +335,7 @@ Bridge::BridgePort::getDeviceAddressRanges(AddrRangeList &resp,
bool &snoop)
{
otherPort->getPeerAddressRanges(resp, snoop);
FilterRangeList(filterRanges, resp);
// we don't allow snooping across bridges
snoop = false;
}

6
src/mem/bridge.hh
View file

@ -70,7 +70,8 @@ class Bridge : public MemObject
/** Min delay to respond to a nack. */
Tick nackDelay;
bool fixPartialWrite;
/** Pass ranges from one side of the bridge to the other? */
std::vector<Range<Addr> > filterRanges;
class PacketBuffer : public Packet::SenderState {
@ -156,7 +157,8 @@ class Bridge : public MemObject
/** Constructor for the BusPort.*/
BridgePort(const std::string &_name, Bridge *_bridge,
BridgePort *_otherPort, int _delay, int _nack_delay,
int _req_limit, int _resp_limit, bool fix_partial_write);
int _req_limit, int _resp_limit,
std::vector<Range<Addr> > filter_ranges);
protected:

43
src/mem/bus.cc
View file

@ -148,10 +148,7 @@ void Bus::occupyBus(PacketPtr pkt)
// The first word will be delivered after the current tick, the delivery
// of the address if any, and one bus cycle to deliver the data
pkt->firstWordTime =
tickNextIdle +
pkt->isRequest() ? clock : 0 +
clock;
pkt->firstWordTime = tickNextIdle + (pkt->isRequest() ? clock : 0) + clock;
//Advance it numCycles bus cycles.
//XXX Should this use the repeated addition trick as well?
@ -211,19 +208,13 @@ Bus::recvTiming(PacketPtr pkt)
dest_port_id = findPort(pkt->getAddr());
dest_port = (dest_port_id == defaultId) ?
defaultPort : interfaces[dest_port_id];
for (SnoopIter s_iter = snoopPorts.begin();
s_iter != snoopPorts.end();
s_iter++) {
SnoopIter s_end = snoopPorts.end();
for (SnoopIter s_iter = snoopPorts.begin(); s_iter != s_end; s_iter++) {
BusPort *p = *s_iter;
if (p != dest_port && p != src_port) {
#ifndef NDEBUG
// cache is not allowed to refuse snoop
bool success = p->sendTiming(pkt);
bool success M5_VAR_USED = p->sendTiming(pkt);
assert(success);
#else
// avoid unused variable warning
p->sendTiming(pkt);
#endif
}
}
} else {
@ -320,9 +311,9 @@ Bus::findPort(Addr addr)
// Check if this matches the default range
if (dest_id == -1) {
for (AddrRangeIter iter = defaultRange.begin();
iter != defaultRange.end(); iter++) {
if (*iter == addr) {
AddrRangeIter a_end = defaultRange.end();
for (AddrRangeIter i = defaultRange.begin(); i != a_end; i++) {
if (*i == addr) {
DPRINTF(Bus, " found addr %#llx on default\n", addr);
return defaultId;
}
@ -437,9 +428,8 @@ Bus::recvFunctional(PacketPtr pkt)
assert(pkt->isRequest()); // hasn't already been satisfied
for (SnoopIter s_iter = snoopPorts.begin();
s_iter != snoopPorts.end();
s_iter++) {
SnoopIter s_end = snoopPorts.end();
for (SnoopIter s_iter = snoopPorts.begin(); s_iter != s_end; s_iter++) {
BusPort *p = *s_iter;
if (p != port && p->getId() != src_id) {
p->sendFunctional(pkt);
@ -464,6 +454,10 @@ Bus::recvStatusChange(Port::Status status, int id)
bool snoops;
AddrRangeIter iter;
if (inRecvStatusChange.count(id))
return;
inRecvStatusChange.insert(id);
assert(status == Port::RangeChange &&
"The other statuses need to be implemented.");
@ -531,6 +525,7 @@ Bus::recvStatusChange(Port::Status status, int id)
if (id != defaultId && defaultPort)
defaultPort->sendStatusChange(Port::RangeChange);
inRecvStatusChange.erase(id);
}
void
@ -589,14 +584,14 @@ Bus::findBlockSize(int id)
int max_bs = -1;
for (PortIter portIter = portMap.begin();
portIter != portMap.end(); portIter++) {
int tmp_bs = interfaces[portIter->second]->peerBlockSize();
PortIter p_end = portMap.end();
for (PortIter p_iter = portMap.begin(); p_iter != p_end; p_iter++) {
int tmp_bs = interfaces[p_iter->second]->peerBlockSize();
if (tmp_bs > max_bs)
max_bs = tmp_bs;
}
for (SnoopIter s_iter = snoopPorts.begin();
s_iter != snoopPorts.end(); s_iter++) {
SnoopIter s_end = snoopPorts.end();
for (SnoopIter s_iter = snoopPorts.begin(); s_iter != s_end; s_iter++) {
int tmp_bs = (*s_iter)->peerBlockSize();
if (tmp_bs > max_bs)
max_bs = tmp_bs;

17
src/mem/bus.hh
View file

@ -38,6 +38,7 @@
#define __MEM_BUS_HH__
#include <string>
#include <set>
#include <list>
#include <inttypes.h>
@ -196,11 +197,13 @@ class Bus : public MemObject
if (portCache[0].valid && addr >= portCache[0].start &&
addr < portCache[0].end) {
return portCache[0].id;
} else if (portCache[1].valid && addr >= portCache[1].start &&
}
if (portCache[1].valid && addr >= portCache[1].start &&
addr < portCache[1].end) {
return portCache[1].id;
} else if (portCache[2].valid && addr >= portCache[2].start &&
addr < portCache[2].end) {
}
if (portCache[2].valid && addr >= portCache[2].start &&
addr < portCache[2].end) {
return portCache[2].id;
}
@ -251,6 +254,7 @@ class Bus : public MemObject
BusFreeEvent busIdle;
bool inRetry;
std::set<int> inRecvStatusChange;
/** max number of bus ids we've handed out so far */
short maxId;
@ -312,9 +316,11 @@ class Bus : public MemObject
inline BusPort* checkBusCache(short id) {
if (busCache[0].valid && id == busCache[0].id) {
return busCache[0].port;
} else if (busCache[1].valid && id == busCache[1].id) {
}
if (busCache[1].valid && id == busCache[1].id) {
return busCache[1].port;
} else if (busCache[2].valid && id == busCache[2].id) {
}
if (busCache[2].valid && id == busCache[2].id) {
return busCache[2].port;
}
@ -338,7 +344,6 @@ class Bus : public MemObject
// Invalidates the cache. Needs to be called in constructor.
inline void clearBusCache() {
// memset(busCache, 0, 3 * sizeof(BusCache));
busCache[2].valid = false;
busCache[1].valid = false;
busCache[0].valid = false;

4
src/mem/cache/BaseCache.py vendored
View file

@ -81,4 +81,8 @@ class BaseCache(MemObject):
"Only prefetch on data not on instruction accesses")
cpu_side = Port("Port on side closer to CPU")
mem_side = Port("Port on side closer to MEM")
cpu_side_filter_ranges = VectorParam.AddrRange([],
"What addresses shouldn't be passed through the side of the bridge")
mem_side_filter_ranges = VectorParam.AddrRange([],
"What addresses shouldn't be passed through the side of the bridge")
addr_range = VectorParam.AddrRange(AllMemory, "The address range in bytes")

5
src/mem/cache/base_cache.cc vendored
View file

@ -40,9 +40,10 @@
using namespace std;
BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache)
BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
std::vector<Range<Addr> > filter_ranges)
: SimpleTimingPort(_name, _cache), cache(_cache), otherPort(NULL),
blocked(false), mustSendRetry(false)
blocked(false), mustSendRetry(false), filterRanges(filter_ranges)
{
}

16
src/mem/cache/base_cache.hh vendored
View file

@ -98,7 +98,8 @@ class BaseCache : public MemObject
BaseCache *cache;
protected:
CachePort(const std::string &_name, BaseCache *_cache);
CachePort(const std::string &_name, BaseCache *_cache,
std::vector<Range<Addr> > filter_ranges);
virtual void recvStatusChange(Status status);
@ -124,6 +125,9 @@ class BaseCache : public MemObject
bool mustSendRetry;
/** filter ranges */
std::vector<Range<Addr> > filterRanges;
void requestBus(RequestCause cause, Tick time)
{
DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
@ -367,15 +371,21 @@ class BaseCache : public MemObject
*/
Counter maxMisses;
std::vector<Range<Addr> > cpuSideFilterRanges;
std::vector<Range<Addr> > memSideFilterRanges;
/**
* Construct an instance of this parameter class.
*/
Params(int _hitLatency, int _blkSize,
int _numMSHRs, int _numTargets, int _numWriteBuffers,
Counter _maxMisses)
Counter _maxMisses,
std::vector<Range<Addr> > cpu_side_filter_ranges,
std::vector<Range<Addr> > mem_side_filter_ranges)
: hitLatency(_hitLatency), blkSize(_blkSize),
numMSHRs(_numMSHRs), numTargets(_numTargets),
numWriteBuffers(_numWriteBuffers), maxMisses(_maxMisses)
numWriteBuffers(_numWriteBuffers), maxMisses(_maxMisses),
cpuSideFilterRanges(cpu_side_filter_ranges),
memSideFilterRanges(mem_side_filter_ranges)
{
}
};

6
src/mem/cache/cache.hh vendored
View file

@ -72,7 +72,8 @@ class Cache : public BaseCache
{
public:
CpuSidePort(const std::string &_name,
Cache<TagStore> *_cache);
Cache<TagStore> *_cache,
std::vector<Range<Addr> > filterRanges);
// BaseCache::CachePort just has a BaseCache *; this function
// lets us get back the type info we lost when we stored the
@ -95,7 +96,8 @@ class Cache : public BaseCache
{
public:
MemSidePort(const std::string &_name,
Cache<TagStore> *_cache);
Cache<TagStore> *_cache,
std::vector<Range<Addr> > filterRanges);
// BaseCache::CachePort just has a BaseCache *; this function
// lets us get back the type info we lost when we stored the

3
src/mem/cache/cache_builder.cc vendored
View file

@ -241,7 +241,8 @@ BaseCacheParams::create()
// Build BaseCache param object
BaseCache::Params base_params(latency, block_size,
mshrs, tgts_per_mshr, write_buffers,
max_miss_count);
max_miss_count, cpu_side_filter_ranges,
mem_side_filter_ranges);
//Warnings about prefetcher policy
if (prefetch_policy == Enums::none) {

25
src/mem/cache/cache_impl.hh vendored
View file

@ -39,6 +39,7 @@
#include "sim/host.hh"
#include "base/misc.hh"
#include "base/range_ops.hh"
#include "mem/cache/cache.hh"
#include "mem/cache/cache_blk.hh"
@ -61,8 +62,10 @@ Cache<TagStore>::Cache(const std::string &_name,
tempBlock = new BlkType();
tempBlock->data = new uint8_t[blkSize];
cpuSidePort = new CpuSidePort(_name + "-cpu_side_port", this);
memSidePort = new MemSidePort(_name + "-mem_side_port", this);
cpuSidePort = new CpuSidePort(_name + "-cpu_side_port", this,
params.baseParams.cpuSideFilterRanges);
memSidePort = new MemSidePort(_name + "-mem_side_port", this,
params.baseParams.memSideFilterRanges);
cpuSidePort->setOtherPort(memSidePort);
memSidePort->setOtherPort(cpuSidePort);
@ -88,7 +91,8 @@ Cache<TagStore>::getPort(const std::string &if_name, int idx)
} else if (if_name == "mem_side") {
return memSidePort;
} else if (if_name == "functional") {
return new CpuSidePort(name() + "-cpu_side_funcport", this);
return new CpuSidePort(name() + "-cpu_side_funcport", this,
std::vector<Range<Addr> >());
} else {
panic("Port name %s unrecognized\n", if_name);
}
@ -732,7 +736,7 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
// If critical word (no offset) return first word time
completion_time = tags->getHitLatency() +
transfer_offset ? pkt->finishTime : pkt->firstWordTime;
(transfer_offset ? pkt->finishTime : pkt->firstWordTime);
assert(!target->pkt->req->isUncacheable());
missLatency[target->pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] +=
@ -1221,6 +1225,7 @@ getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
// CPU side port doesn't snoop; it's a target only.
bool dummy;
otherPort->getPeerAddressRanges(resp, dummy);
FilterRangeList(filterRanges, resp);
snoop = false;
}
@ -1262,8 +1267,9 @@ Cache<TagStore>::CpuSidePort::recvFunctional(PacketPtr pkt)
template<class TagStore>
Cache<TagStore>::
CpuSidePort::CpuSidePort(const std::string &_name,
Cache<TagStore> *_cache)
: BaseCache::CachePort(_name, _cache)
Cache<TagStore> *_cache, std::vector<Range<Addr> >
filterRanges)
: BaseCache::CachePort(_name, _cache, filterRanges)
{
}
@ -1279,6 +1285,8 @@ Cache<TagStore>::MemSidePort::
getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
{
otherPort->getPeerAddressRanges(resp, snoop);
FilterRangeList(filterRanges, resp);
// Memory-side port always snoops, so unconditionally set flag for
// caller.
snoop = true;
@ -1416,8 +1424,9 @@ Cache<TagStore>::MemSidePort::processSendEvent()
template<class TagStore>
Cache<TagStore>::
MemSidePort::MemSidePort(const std::string &_name, Cache<TagStore> *_cache)
: BaseCache::CachePort(_name, _cache)
MemSidePort::MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
std::vector<Range<Addr> > filterRanges)
: BaseCache::CachePort(_name, _cache, filterRanges)
{
// override default send event from SimpleTimingPort
delete sendEvent;

2
src/mem/cache/miss/mshr.cc vendored
View file

@ -263,7 +263,7 @@ MSHR::handleSnoop(PacketPtr pkt, Counter _order)
if (targets->needsExclusive || pkt->needsExclusive()) {
// actual target device (typ. PhysicalMemory) will delete the
// packet on reception, so we need to save a copy here
PacketPtr cp_pkt = new Packet(pkt);
PacketPtr cp_pkt = new Packet(pkt, true);
targets->add(cp_pkt, curTick, _order, false);
++ntargets;

1
src/mem/tport.cc
View file

@ -95,6 +95,7 @@ void
SimpleTimingPort::schedSendTiming(PacketPtr pkt, Tick when)
{
assert(when > curTick);
assert(when < curTick + Clock::Int::ms);
// Nothing is on the list: add it and schedule an event
if (transmitList.empty() || when < transmitList.front().tick) {

2
src/python/generate.py
View file

@ -46,8 +46,10 @@ class DictImporter(object):
self.unload()
def unload(self):
import sys
for module in self.installed:
del sys.modules[module]
self.installed = set()
def find_module(self, fullname, path):
if fullname == '__scons':

18
tests/configs/tsunami-simple-atomic-dual.py
View file

@ -52,10 +52,28 @@ class L2(BaseCache):
tgts_per_mshr = 16
write_buffers = 8
# ---------------------
# I/O Cache
# ---------------------
class IOCache(BaseCache):
assoc = 8
block_size = 64
latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
mem_side_filter_ranges=[AddrRange(0, Addr.max)]
cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
#cpu
cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
#the system
system = FSConfig.makeLinuxAlphaSystem('atomic')
system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.port
system.iocache.mem_side = system.membus.port
system.cpu = cpus
#create the l1/l2 bus

18
tests/configs/tsunami-simple-atomic.py
View file

@ -52,10 +52,28 @@ class L2(BaseCache):
tgts_per_mshr = 16
write_buffers = 8
# ---------------------
# I/O Cache
# ---------------------
class IOCache(BaseCache):
assoc = 8
block_size = 64
latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
mem_side_filter_ranges=[AddrRange(0, Addr.max)]
cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
#cpu
cpu = AtomicSimpleCPU(cpu_id=0)
#the system
system = FSConfig.makeLinuxAlphaSystem('atomic')
system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.port
system.iocache.mem_side = system.membus.port
system.cpu = cpu
#create the l1/l2 bus

18
tests/configs/tsunami-simple-timing-dual.py
View file

@ -52,10 +52,28 @@ class L2(BaseCache):
tgts_per_mshr = 16
write_buffers = 8
# ---------------------
# I/O Cache
# ---------------------
class IOCache(BaseCache):
assoc = 8
block_size = 64
latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
mem_side_filter_ranges=[AddrRange(0, Addr.max)]
cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
#cpu
cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
#the system
system = FSConfig.makeLinuxAlphaSystem('timing')
system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.port
system.iocache.mem_side = system.membus.port
system.cpu = cpus
#create the l1/l2 bus

19
tests/configs/tsunami-simple-timing.py
View file

@ -53,6 +53,19 @@ class L2(BaseCache):
tgts_per_mshr = 16
write_buffers = 8
# ---------------------
# I/O Cache
# ---------------------
class IOCache(BaseCache):
assoc = 8
block_size = 64
latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
mem_side_filter_ranges=[AddrRange(0, Addr.max)]
cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
#cpu
cpu = TimingSimpleCPU(cpu_id=0)
#the system
@ -61,6 +74,12 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
system.cpu = cpu
#create the l1/l2 bus
system.toL2Bus = Bus()
system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.port
system.iocache.mem_side = system.membus.port
#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)

38
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus workload
children=dcache icache l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
@ -24,27 +24,28 @@ max_loads_any_thread=0
phase=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -52,12 +53,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -68,21 +67,21 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -90,12 +89,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -106,21 +103,21 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -128,12 +125,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -151,6 +146,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
@ -174,7 +172,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory

193
tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 494073 # Simulator instruction rate (inst/s)
host_mem_usage 153964 # Number of bytes of host memory used
host_seconds 1218.16 # Real time elapsed on the host
host_tick_rate 624626994 # Simulator tick rate (ticks/s)
host_inst_rate 1799420 # Simulator instruction rate (inst/s)
host_mem_usage 199568 # Number of bytes of host memory used
host_seconds 334.47 # Real time elapsed on the host
host_tick_rate 2297009943 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856965 # Number of instructions simulated
sim_seconds 0.760893 # Number of seconds simulated
sim_ticks 760892614000 # Number of ticks simulated
sim_seconds 0.768288 # Number of seconds simulated
sim_ticks 768287940000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 12040.967639 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11040.967639 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 23626.361612 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21626.361612 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 2423028000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 4754380000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 2221796000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 4351916000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 12166.766996 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11166.766996 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 3092342000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 2838179000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 39122430 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 8222275000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.008337 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 328891 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 7564493000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.008337 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 328891 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
@ -37,31 +37,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 12111.178208 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 11111.178208 # average overall mshr miss latency
system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 5515370000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses
system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 24478.573840 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 22478.573840 # average overall mshr miss latency
system.cpu.dcache.demand_hits 153435240 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 12976655000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.003443 # miss rate for demand accesses
system.cpu.dcache.demand_misses 530123 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 5059975000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 11916409000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.003443 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 530123 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 12111.178208 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 11111.178208 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 24478.573840 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 22478.573840 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 153509968 # number of overall hits
system.cpu.dcache.overall_miss_latency 5515370000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses
system.cpu.dcache.overall_misses 455395 # number of overall misses
system.cpu.dcache.overall_hits 153435240 # number of overall hits
system.cpu.dcache.overall_miss_latency 12976655000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.003443 # miss rate for overall accesses
system.cpu.dcache.overall_misses 530123 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 5059975000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 11916409000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.003443 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 530123 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 451299 # number of replacements
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.250869 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4094.970134 # Cycle average of tags in use
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 257148000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.warmup_cycle 342925000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 325723 # number of writebacks
system.cpu.icache.ReadReq_accesses 601856966 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 13969.811321 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12969.811321 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 601856171 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 11106000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 19875000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 10311000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 18285000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 601856966 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 13969.811321 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12969.811321 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.icache.demand_hits 601856171 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 11106000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 19875000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_misses 795 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 10311000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 18285000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 601856966 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 13969.811321 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12969.811321 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 601856171 # number of overall hits
system.cpu.icache.overall_miss_latency 11106000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 19875000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_misses 795 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 10311000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 18285000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -138,57 +138,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 673.943506 # Cycle average of tags in use
system.cpu.icache.tagsinuse 673.685789 # Cycle average of tags in use
system.cpu.icache.total_refs 601856171 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 456190 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 5591586000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 254163 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2795793000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 254163 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 430092 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 339274000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.057209 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 26098 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 287078000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.057209 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 26098 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_hits 23035 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 3937824000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.885981 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 178992 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1968912000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.885981 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 178992 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 74728 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 1644016000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 74728 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 822008000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 74728 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 325723 # number of Writeback hits
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 325723 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 325723 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 28.960648 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 3.500034 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 430092 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 339274000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.057209 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 26098 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 23035 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 9529410000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.949506 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 433155 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 287078000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.057209 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 26098 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 4764705000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.949506 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 433155 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 781913 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 755815 # number of overall hits
system.cpu.l2cache.overall_miss_latency 339274000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.033377 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 26098 # number of overall misses
system.cpu.l2cache.overall_hits 23035 # number of overall hits
system.cpu.l2cache.overall_miss_latency 9529410000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.949506 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 433155 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 287078000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.033377 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 26098 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 4764705000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.949506 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 433155 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -200,15 +221,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 903 # number of replacements
system.cpu.l2cache.sampled_refs 26098 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 13394 # number of replacements
system.cpu.l2cache.sampled_refs 14881 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 24875.090462 # Cycle average of tags in use
system.cpu.l2cache.total_refs 755815 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 8423.446687 # Cycle average of tags in use
system.cpu.l2cache.total_refs 52084 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 883 # number of writebacks
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 760892614000 # number of cpu cycles simulated
system.cpu.numCycles 768287940000 # number of cpu cycles simulated
system.cpu.num_insts 601856965 # Number of instructions executed
system.cpu.num_refs 154862034 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls

51
tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=DerivO3CPU
children=dcache fuPool icache l2cache toL2Bus workload
children=dcache fuPool icache l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -86,6 +86,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
@ -95,16 +96,15 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@ -118,12 +118,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -139,11 +137,11 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList0
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList0
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList0]
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
@ -217,11 +215,11 @@ opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList0
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList0]
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
@ -229,11 +227,11 @@ opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList0
children=opList
count=0
opList=system.cpu.fuPool.FUList5.opList0
opList=system.cpu.fuPool.FUList5.opList
[system.cpu.fuPool.FUList5.opList0]
[system.cpu.fuPool.FUList5.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
@ -259,11 +257,11 @@ opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0
children=opList
count=1
opList=system.cpu.fuPool.FUList7.opList0
opList=system.cpu.fuPool.FUList7.opList
[system.cpu.fuPool.FUList7.opList0]
[system.cpu.fuPool.FUList7.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
@ -271,16 +269,15 @@ opLat=3
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@ -294,12 +291,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -310,16 +305,15 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@ -333,12 +327,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -356,6 +348,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1

578
tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt
View file

@ -1,122 +1,122 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 155497873 # Number of BTB hits
global.BPredUnit.BTBLookups 176569029 # Number of BTB lookups
global.BPredUnit.BTBHits 183168209 # Number of BTB hits
global.BPredUnit.BTBLookups 207693172 # Number of BTB lookups
global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 90327270 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 223339092 # Number of conditional branches predicted
global.BPredUnit.lookups 223339092 # Number of BP lookups
global.BPredUnit.condIncorrect 83686538 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 256168234 # Number of conditional branches predicted
global.BPredUnit.lookups 256168234 # Number of BP lookups
global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
host_inst_rate 54106 # Simulator instruction rate (inst/s)
host_mem_usage 156124 # Number of bytes of host memory used
host_seconds 27529.37 # Real time elapsed on the host
host_tick_rate 45674334 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 464625781 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 155659586 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 751805606 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 305482201 # Number of stores inserted to the mem dependence unit.
host_inst_rate 108517 # Simulator instruction rate (inst/s)
host_mem_usage 202532 # Number of bytes of host memory used
host_seconds 13726.13 # Real time elapsed on the host
host_tick_rate 80131991 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 457134527 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 154100032 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 745124340 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 301027499 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489514762 # Number of instructions simulated
sim_seconds 1.257386 # Number of seconds simulated
sim_ticks 1257385552000 # Number of ticks simulated
sim_insts 1489514761 # Number of instructions simulated
sim_seconds 1.099902 # Number of seconds simulated
sim_ticks 1099901861500 # Number of ticks simulated
system.cpu.commit.COM:branches 86246390 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 9313657 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 9028629 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 2273477268
system.cpu.commit.COM:committed_per_cycle.samples 1956850179
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 1413600532 6217.79%
1 557883273 2453.88%
2 123364539 542.62%
3 120963543 532.06%
4 18884040 83.06%
5 12171132 53.54%
6 9965158 43.83%
7 7331394 32.25%
8 9313657 40.97%
0 1082285235 5530.75%
1 575067444 2938.74%
2 119112331 608.69%
3 121687931 621.86%
4 26918285 137.56%
5 9398970 48.03%
6 9197638 47.00%
7 4153716 21.23%
8 9028629 46.14%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:count 1489514762 # Number of instructions committed
system.cpu.commit.COM:loads 402511689 # Number of loads committed
system.cpu.commit.COM:count 1489514761 # Number of instructions committed
system.cpu.commit.COM:loads 402511688 # Number of loads committed
system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
system.cpu.commit.COM:refs 569359657 # Number of memory references committed
system.cpu.commit.COM:refs 569359656 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 90327270 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1489514762 # The number of committed instructions
system.cpu.commit.branchMispredicts 83686538 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1489514761 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 2243499 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 1399513618 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1489514762 # Number of Instructions Simulated
system.cpu.committedInsts_total 1489514762 # Number of Instructions Simulated
system.cpu.cpi 1.688316 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.688316 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 431095835 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 2842.252413 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2392.500580 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 430168385 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 2636047000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002151 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 927450 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 694672 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 556921500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000540 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 232778 # number of ReadReq MSHR misses
system.cpu.commit.commitSquashedInsts 1386494932 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1489514761 # Number of Instructions Simulated
system.cpu.committedInsts_total 1489514761 # Number of Instructions Simulated
system.cpu.cpi 1.476859 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.476859 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 432423106 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 21577.217813 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4456.675710 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 432175035 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 5352682000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000574 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 248071 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 707847 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1105572000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000574 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 248071 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 3500 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2500 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 24500 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 17500 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 3889.592412 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3171.120393 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 165155866 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 6576429500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.010134 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1690776 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1420478 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 857147500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001620 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 270298 # number of WriteReq MSHR misses
system.cpu.dcache.SwapReq_avg_miss_latency 7012.500000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 5012.500000 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 280500 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 200500 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 165036365 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 45516.173877 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5913.886312 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 164687129 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 15895886500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.002116 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 349236 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1810277 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2065342000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002116 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 349236 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 1183.354576 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 1139.085750 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 597942477 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 3518.594842 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 2810.845677 # average overall mshr miss latency
system.cpu.dcache.demand_hits 595324251 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 9212476500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.004379 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2618226 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 2115150 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 1414069000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000841 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 503076 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 597459471 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 35573.948573 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 5308.683809 # average overall mshr miss latency
system.cpu.dcache.demand_hits 596862164 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 21248568500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.001000 # miss rate for demand accesses
system.cpu.dcache.demand_misses 597307 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 2518124 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 3170914000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.001000 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 597307 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 597942477 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 3518.594842 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 2810.845677 # average overall mshr miss latency
system.cpu.dcache.overall_accesses 597459471 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 35573.948573 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 5308.683809 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 595324251 # number of overall hits
system.cpu.dcache.overall_miss_latency 9212476500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.004379 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2618226 # number of overall misses
system.cpu.dcache.overall_mshr_hits 2115150 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 1414069000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000841 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 503076 # number of overall MSHR misses
system.cpu.dcache.overall_hits 596862164 # number of overall hits
system.cpu.dcache.overall_miss_latency 21248568500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.001000 # miss rate for overall accesses
system.cpu.dcache.overall_misses 597307 # number of overall misses
system.cpu.dcache.overall_mshr_hits 2518124 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 3170914000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.001000 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 597307 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -128,89 +128,89 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 498987 # number of replacements
system.cpu.dcache.sampled_refs 503083 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 519953 # number of replacements
system.cpu.dcache.sampled_refs 524049 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.797134 # Cycle average of tags in use
system.cpu.dcache.total_refs 595325570 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 77974000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 335737 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 435745843 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 3276032607 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 1073744654 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 761619600 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 241293837 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 2367171 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 223339092 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 355860305 # Number of cache lines fetched
system.cpu.fetch.Cycles 1166695920 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 14770227 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 3591774268 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 93734364 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.088811 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 355860305 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 155497873 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.428271 # Number of inst fetches per cycle
system.cpu.dcache.tagsinuse 4095.788106 # Cycle average of tags in use
system.cpu.dcache.total_refs 596936748 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 72857000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 346070 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 407153301 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 3453639261 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 763587746 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 783418811 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 242953531 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 2690321 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 256168234 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 355186488 # Number of cache lines fetched
system.cpu.fetch.Cycles 1201174807 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 10202313 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 3743631874 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 91259594 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.116450 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 355186488 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 183168209 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.701803 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 2514771105
system.cpu.fetch.rateDist.samples 2199803710
system.cpu.fetch.rateDist.min_value 0
0 1703935491 6775.71%
1 252157679 1002.71%
2 75632424 300.75%
3 38096592 151.49%
4 76680653 304.92%
5 30840750 122.64%
6 33076966 131.53%
7 20130593 80.05%
8 284219957 1130.20%
0 1353815392 6154.26%
1 255570605 1161.79%
2 82946121 377.06%
3 38413739 174.62%
4 83998079 381.84%
5 40983172 186.30%
6 33041033 150.20%
7 20511116 93.24%
8 290524453 1320.68%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 355860305 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 5111.111111 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4198.640483 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 355858946 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 6946000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_accesses 355186427 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 7448.556625 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5296.447076 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 355185076 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 10063000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1359 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 5559000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_misses 1351 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 61 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 7155500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 1324 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses 1351 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 268775.638973 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 262905.311621 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 355860305 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 5111.111111 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 4198.640483 # average overall mshr miss latency
system.cpu.icache.demand_hits 355858946 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 6946000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_accesses 355186427 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 7448.556625 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 5296.447076 # average overall mshr miss latency
system.cpu.icache.demand_hits 355185076 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 10063000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_misses 1359 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 35 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 5559000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_misses 1351 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 61 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 7155500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 1324 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses 1351 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 355860305 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 5111.111111 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 4198.640483 # average overall mshr miss latency
system.cpu.icache.overall_accesses 355186427 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 7448.556625 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 5296.447076 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 355858946 # number of overall hits
system.cpu.icache.overall_miss_latency 6946000 # number of overall miss cycles
system.cpu.icache.overall_hits 355185076 # number of overall hits
system.cpu.icache.overall_miss_latency 10063000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_misses 1359 # number of overall misses
system.cpu.icache.overall_mshr_hits 35 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 5559000 # number of overall MSHR miss cycles
system.cpu.icache.overall_misses 1351 # number of overall misses
system.cpu.icache.overall_mshr_hits 61 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 7155500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 1324 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses 1351 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -222,166 +222,183 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 198 # number of replacements
system.cpu.icache.sampled_refs 1324 # Sample count of references to valid blocks.
system.cpu.icache.replacements 207 # number of replacements
system.cpu.icache.sampled_refs 1351 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1026.431065 # Cycle average of tags in use
system.cpu.icache.total_refs 355858946 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1040.211796 # Cycle average of tags in use
system.cpu.icache.total_refs 355185076 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 1497 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 128998684 # Number of branches executed
system.cpu.idleCycles 8497 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 126707080 # Number of branches executed
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.879999 # Inst execution rate
system.cpu.iew.EXEC:refs 756340485 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 208683785 # Number of stores executed
system.cpu.iew.EXEC:rate 1.003361 # Inst execution rate
system.cpu.iew.EXEC:refs 760962527 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 208093186 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 1511846593 # num instructions consuming a value
system.cpu.iew.WB:count 2184193190 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.964010 # average fanout of values written-back
system.cpu.iew.WB:consumers 1493645383 # num instructions consuming a value
system.cpu.iew.WB:count 2165444744 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.962819 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1457435157 # num instructions producing a value
system.cpu.iew.WB:rate 0.868546 # insts written-back per cycle
system.cpu.iew.WB:sent 2194556483 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 93921260 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 242324 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 751805606 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 21112863 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 6967923 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 305482201 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2889028359 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 547656700 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 155922171 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 2212995141 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 1438109572 # num instructions producing a value
system.cpu.iew.WB:rate 0.984381 # insts written-back per cycle
system.cpu.iew.WB:sent 2178310152 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 91514542 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 458290 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 745124340 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 21362312 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 17090675 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 301027499 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2876000922 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 552869341 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 140121943 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 2207196457 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 56098 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 241293837 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 1173 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 8365 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 242953531 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 87287 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 116560202 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 586068 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.forwLoads 119737756 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 85786 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 3827981 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 59 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 349293917 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 138634233 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 3827981 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 1127857 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 92793403 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.592306 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.592306 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 2368917312 # Type of FU issued
system.cpu.iew.lsq.thread.0.memOrderViolation 10100571 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 31 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 342612652 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 134179531 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 10100571 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 1514083 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 90000459 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.677113 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.677113 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 2347318400 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 351375247 14.83% # Type of FU issued
IntAlu 1188705257 50.18% # Type of FU issued
No_OpClass 351441317 14.97% # Type of FU issued
IntAlu 1181231771 50.32% # Type of FU issued
IntMult 0 0.00% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 2951238 0.12% # Type of FU issued
FloatAdd 3000185 0.13% # Type of FU issued
FloatCmp 0 0.00% # Type of FU issued
FloatCvt 0 0.00% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 592531661 25.01% # Type of FU issued
MemWrite 233353909 9.85% # Type of FU issued
MemRead 586473179 24.98% # Type of FU issued
MemWrite 225171948 9.59% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 6622922 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.002796 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_busy_cnt 3997880 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.001703 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 3150287 47.57% # attempts to use FU when none available
IntAlu 155579 3.89% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 202242 3.05% # attempts to use FU when none available
FloatAdd 244024 6.10% # attempts to use FU when none available
FloatCmp 0 0.00% # attempts to use FU when none available
FloatCvt 0 0.00% # attempts to use FU when none available
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 2975364 44.93% # attempts to use FU when none available
MemWrite 295029 4.45% # attempts to use FU when none available
MemRead 3267233 81.72% # attempts to use FU when none available
MemWrite 331044 8.28% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 2514771105
system.cpu.iq.ISSUE:issued_per_cycle.samples 2199803710
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 1264571415 5028.57%
1 618163663 2458.13%
2 318214573 1265.38%
3 195947630 779.19%
4 78232851 311.09%
5 28085074 111.68%
6 8167595 32.48%
7 2987163 11.88%
8 401141 1.60%
0 993478594 4516.21%
1 570157916 2591.86%
2 321116547 1459.75%
3 178901320 813.26%
4 92584833 420.88%
5 34984610 159.04%
6 7286511 33.12%
7 1105050 5.02%
8 188329 0.86%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 0.942001 # Inst issue rate
system.cpu.iq.iqInstsAdded 2867645475 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 2368917312 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 21382884 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 1368214032 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 461256 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 19139385 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 1296493196 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 504406 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4393.799833 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2267.430007 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 476939 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 120684500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.054454 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 27467 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 62279500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054454 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 27467 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 335737 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 335720 # number of Writeback hits
system.cpu.l2cache.Writeback_miss_rate 0.000051 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 17 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 0.000051 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 17 # number of Writeback MSHR misses
system.cpu.iq.ISSUE:rate 1.067058 # Inst issue rate
system.cpu.iq.iqInstsAdded 2854330173 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 2347318400 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 21670749 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 1311892803 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 993660 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 19427250 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 1293606933 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 275979 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 4897.575540 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2897.575540 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 1351628000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 275979 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 799670000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 275979 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 249421 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4201.208939 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2201.208939 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 64300 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 777732000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.742203 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 185121 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 407490000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.742203 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 185121 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 73301 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4221.136137 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2221.136137 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 309413500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 73301 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 162811500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 73301 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 346070 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 346070 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 346070 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 29.586740 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 4.935065 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 504406 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4393.799833 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2267.430007 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 476939 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 120684500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.054454 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 27467 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 525400 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4618.000434 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2618.000434 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 64300 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 2129360000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.877617 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 461100 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 62279500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.054454 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 27467 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 1207160000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.877617 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 461100 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 840143 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4391.082084 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2267.430007 # average overall mshr miss latency
system.cpu.l2cache.overall_accesses 525400 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4618.000434 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2618.000434 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 812659 # number of overall hits
system.cpu.l2cache.overall_miss_latency 120684500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.032713 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 27484 # number of overall misses
system.cpu.l2cache.overall_hits 64300 # number of overall hits
system.cpu.l2cache.overall_miss_latency 2129360000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.877617 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 461100 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 62279500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.032693 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 27467 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 1207160000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.877617 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 461100 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -393,30 +410,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 2692 # number of replacements
system.cpu.l2cache.sampled_refs 27467 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 19390 # number of replacements
system.cpu.l2cache.sampled_refs 20790 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 24466.224839 # Cycle average of tags in use
system.cpu.l2cache.total_refs 812659 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 8555.838166 # Cycle average of tags in use
system.cpu.l2cache.total_refs 102600 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 2555 # number of writebacks
system.cpu.numCycles 2514771105 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 14153952 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1244762263 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 845 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 1122858502 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 18964355 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 4974059876 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 3105364972 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2435580679 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 713636177 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 241293837 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 24303898 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 1190818416 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 398524739 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 21495577 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 149561373 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 21338548 # count of temporary serializing insts renamed
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 2199803710 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 12980165 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1244762261 # Number of HB maps that are committed
system.cpu.rename.RENAME:FullRegisterEvents 11 # Number of times there has been no free registers
system.cpu.rename.RENAME:IQFullEvents 40711 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 826156851 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 20049545 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 4942866473 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 3108910588 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2431469653 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 720639508 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 242953531 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 28416809 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 1186707392 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 368656846 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 21929426 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 159084902 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 21683995 # count of temporary serializing insts renamed
system.cpu.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 19 # Number of system calls

8
tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout
View file

@ -36,9 +36,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jun 21 2007 21:15:48
M5 started Fri Jun 22 01:01:27 2007
M5 executing on zizzer.eecs.umich.edu
M5 compiled Aug 12 2007 12:23:15
M5 started Sun Aug 12 12:23:18 2007
M5 executing on zeep
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 1257385552000 because target called exit()
Exiting @ tick 1099901861500 because target called exit()

38
tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus workload
children=dcache icache l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
@ -24,27 +24,28 @@ max_loads_any_thread=0
phase=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -52,12 +53,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -68,21 +67,21 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -90,12 +89,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -106,21 +103,21 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -128,12 +125,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -151,6 +146,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
@ -174,7 +172,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory

215
tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt
View file

@ -1,43 +1,43 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 529254 # Simulator instruction rate (inst/s)
host_mem_usage 154916 # Number of bytes of host memory used
host_seconds 2814.36 # Real time elapsed on the host
host_tick_rate 733354350 # Simulator tick rate (ticks/s)
host_inst_rate 1190065 # Simulator instruction rate (inst/s)
host_mem_usage 201788 # Number of bytes of host memory used
host_seconds 1251.63 # Real time elapsed on the host
host_tick_rate 1654548560 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489514860 # Number of instructions simulated
sim_seconds 2.063927 # Number of seconds simulated
sim_ticks 2063926516000 # Number of ticks simulated
sim_seconds 2.070875 # Number of seconds simulated
sim_ticks 2070875212000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 12044.273310 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11044.273310 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 23237.213149 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21237.213149 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 402318208 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 2330326000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 4495936000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 193480 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 2136846000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 4108976000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 193480 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 12285.714286 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 11285.714286 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 86000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 79000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 1000000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 920000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 12168.472925 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11168.472925 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 166586897 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 3160700000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.001557 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 259745 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 2900955000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001557 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 259745 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 166527019 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 7990575000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.001916 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 319623 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 7351329000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001916 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 319623 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 1255.221220 # Average number of references to valid blocks.
@ -47,31 +47,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 12115.452590 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 11115.452590 # average overall mshr miss latency
system.cpu.dcache.demand_hits 568905105 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 5491026000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000796 # miss rate for demand accesses
system.cpu.dcache.demand_misses 453225 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 24335.291355 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 22335.291355 # average overall mshr miss latency
system.cpu.dcache.demand_hits 568845227 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 12486511000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses
system.cpu.dcache.demand_misses 513103 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 5037801000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 453225 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 11460305000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 513103 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 12115.452590 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 11115.452590 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 24335.291355 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 22335.291355 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 568905105 # number of overall hits
system.cpu.dcache.overall_miss_latency 5491026000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000796 # miss rate for overall accesses
system.cpu.dcache.overall_misses 453225 # number of overall misses
system.cpu.dcache.overall_hits 568845227 # number of overall hits
system.cpu.dcache.overall_miss_latency 12486511000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses
system.cpu.dcache.overall_misses 513103 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 5037801000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 453225 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 11460305000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 513103 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 449136 # number of replacements
system.cpu.dcache.sampled_refs 453232 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.630445 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4095.520244 # Cycle average of tags in use
system.cpu.dcache.total_refs 568906424 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 274426000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.warmup_cycle 358125000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 316447 # number of writebacks
system.cpu.icache.ReadReq_accesses 1489514861 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 13859.744991 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12859.744991 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 24978.142077 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22978.142077 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1489513763 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 15218000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 27426000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 14120000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 25230000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1489514861 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 13859.744991 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12859.744991 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 24978.142077 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 22978.142077 # average overall mshr miss latency
system.cpu.icache.demand_hits 1489513763 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 15218000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 27426000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 14120000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 25230000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 1098 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 1489514861 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 13859.744991 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12859.744991 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 24978.142077 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 22978.142077 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1489513763 # number of overall hits
system.cpu.icache.overall_miss_latency 15218000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 27426000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_misses 1098 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 14120000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 25230000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 1098 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -148,61 +148,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 115 # number of replacements
system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 891.684170 # Cycle average of tags in use
system.cpu.icache.tagsinuse 891.566276 # Cycle average of tags in use
system.cpu.icache.total_refs 1489513763 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 454330 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_accesses 259752 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 5714544000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 259752 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2857272000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 259752 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 194578 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 427145 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 353405000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.059835 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 27185 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 299035000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.059835 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 27185 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_hits 28424 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 3655388000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.853920 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 166154 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1827694000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.853920 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 166154 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 59911 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 1318042000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 59911 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 659021000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 59911 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 316447 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 316438 # number of Writeback hits
system.cpu.l2cache.Writeback_miss_rate 0.000028 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 9 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 0.000028 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 9 # number of Writeback MSHR misses
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 316447 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 316447 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 27.352695 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 3.182232 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 454330 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 427145 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 353405000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.059835 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 27185 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 28424 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 9369932000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.937438 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 425906 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 299035000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.059835 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 27185 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 4684966000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.937438 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 425906 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 770777 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 12995.697580 # average overall miss latency
system.cpu.l2cache.overall_accesses 454330 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 743583 # number of overall hits
system.cpu.l2cache.overall_miss_latency 353405000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.035281 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 27194 # number of overall misses
system.cpu.l2cache.overall_hits 28424 # number of overall hits
system.cpu.l2cache.overall_miss_latency 9369932000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.937438 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 425906 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 299035000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.035270 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 27185 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 4684966000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.937438 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 425906 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -214,15 +231,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 2632 # number of replacements
system.cpu.l2cache.sampled_refs 27185 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 18201 # number of replacements
system.cpu.l2cache.sampled_refs 19574 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 24267.041661 # Cycle average of tags in use
system.cpu.l2cache.total_refs 743583 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 8449.172652 # Cycle average of tags in use
system.cpu.l2cache.total_refs 62289 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 2531 # number of writebacks
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 2063926516000 # number of cpu cycles simulated
system.cpu.numCycles 2070875212000 # number of cpu cycles simulated
system.cpu.num_insts 1489514860 # Number of instructions executed
system.cpu.num_refs 569359656 # Number of memory references
system.cpu.workload.PROG:num_syscalls 19 # Number of system calls

8
tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout
View file

@ -36,9 +36,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 15 2007 13:02:31
M5 started Tue May 15 13:36:53 2007
M5 executing on zizzer.eecs.umich.edu
M5 compiled Aug 12 2007 12:23:15
M5 started Sun Aug 12 16:24:16 2007
M5 executing on zeep
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 2063926516000 because target called exit()
Exiting @ tick 2070875212000 because target called exit()

27
tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus workload
children=dcache icache l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
@ -24,22 +24,22 @@ max_loads_any_thread=0
phase=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@ -53,12 +53,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -69,16 +67,15 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@ -92,12 +89,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -108,16 +103,15 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@ -131,12 +125,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -154,6 +146,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in

211
tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt
View file

@ -1,43 +1,43 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 697152 # Simulator instruction rate (inst/s)
host_mem_usage 155896 # Number of bytes of host memory used
host_seconds 349.77 # Real time elapsed on the host
host_tick_rate 1027373651 # Simulator tick rate (ticks/s)
host_inst_rate 1064489 # Simulator instruction rate (inst/s)
host_mem_usage 202188 # Number of bytes of host memory used
host_seconds 229.07 # Real time elapsed on the host
host_tick_rate 1583716497 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243840172 # Number of instructions simulated
sim_seconds 0.359341 # Number of seconds simulated
sim_ticks 359340764000 # Number of ticks simulated
sim_seconds 0.362779 # Number of seconds simulated
sim_ticks 362778959000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 82219469 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 12000.343864 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11000.343864 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 13897.517462 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11897.517462 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 81326673 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 10713859000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 12407648000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 892796 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 9821063000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 10622056000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 892796 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 12500 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 11500 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 3882 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 50000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.001029 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 4 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 46000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.001029 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 4 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 3878 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 200000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.002059 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 8 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 184000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.002059 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 8 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 22901836 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 12623.899964 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11623.899964 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 22855133 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 589574000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.002039 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 46703 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 542871000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002039 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 46703 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 22806941 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 2372375000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.004144 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 94895 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 2182585000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.004144 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 94895 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 110.894471 # Average number of references to valid blocks.
@ -47,31 +47,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 105121305 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 12031.341172 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 11031.341172 # average overall mshr miss latency
system.cpu.dcache.demand_hits 104181806 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 11303433000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.008937 # miss rate for demand accesses
system.cpu.dcache.demand_misses 939499 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 14964.217554 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12964.217554 # average overall mshr miss latency
system.cpu.dcache.demand_hits 104133614 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 14780023000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.009396 # miss rate for demand accesses
system.cpu.dcache.demand_misses 987691 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 10363934000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.008937 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 939499 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 12804641000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.009396 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 987691 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 105121305 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 12031.341172 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 11031.341172 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 14964.217554 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12964.217554 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 104181806 # number of overall hits
system.cpu.dcache.overall_miss_latency 11303433000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.008937 # miss rate for overall accesses
system.cpu.dcache.overall_misses 939499 # number of overall misses
system.cpu.dcache.overall_hits 104133614 # number of overall hits
system.cpu.dcache.overall_miss_latency 14780023000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.009396 # miss rate for overall accesses
system.cpu.dcache.overall_misses 987691 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 10363934000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.008937 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 939499 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 12804641000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.009396 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 987691 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 935407 # number of replacements
system.cpu.dcache.sampled_refs 939503 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3560.887601 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 3565.606162 # Cycle average of tags in use
system.cpu.dcache.total_refs 104185688 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 134116230000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.warmup_cycle 134193588000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 94807 # number of writebacks
system.cpu.icache.ReadReq_accesses 243840173 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 13993.174061 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12993.174061 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 24972.696246 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22972.696246 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 243839294 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 12300000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 21951000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 879 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 11421000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 20193000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 879 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 243840173 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 13993.174061 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12993.174061 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 24972.696246 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 22972.696246 # average overall mshr miss latency
system.cpu.icache.demand_hits 243839294 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 12300000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 21951000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_misses 879 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 11421000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 20193000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 879 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 243840173 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 13993.174061 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12993.174061 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 24972.696246 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 22972.696246 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 243839294 # number of overall hits
system.cpu.icache.overall_miss_latency 12300000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 21951000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_misses 879 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 11421000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 20193000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 879 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -148,57 +148,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 25 # number of replacements
system.cpu.icache.sampled_refs 879 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 716.200092 # Cycle average of tags in use
system.cpu.icache.tagsinuse 716.749422 # Cycle average of tags in use
system.cpu.icache.total_refs 243839294 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 940381 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_accesses 46707 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 1027554000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 46707 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 513777000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 46707 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 893675 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 924777 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 202852000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.016593 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 15604 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 171644000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.016593 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 15604 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_hits 826023 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1488344000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.075701 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 67652 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 744172000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.075701 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 67652 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 48196 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 1060312000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 48196 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 530156000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 48196 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 94807 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 94807 # number of Writeback hits
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 94807 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 94807 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 65.341195 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 48.779815 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 940381 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.demand_accesses 940382 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 924777 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 202852000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.016593 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 15604 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 826023 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 2515898000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.121609 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 114359 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 171644000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.016593 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 15604 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 1257949000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.121609 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 114359 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 1035188 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.overall_accesses 940382 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1019584 # number of overall hits
system.cpu.l2cache.overall_miss_latency 202852000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.015074 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 15604 # number of overall misses
system.cpu.l2cache.overall_hits 826023 # number of overall hits
system.cpu.l2cache.overall_miss_latency 2515898000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.121609 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 114359 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 171644000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.015074 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 15604 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 1257949000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.121609 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 114359 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -210,15 +231,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 15604 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 829 # number of replacements
system.cpu.l2cache.sampled_refs 11345 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 10833.027960 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1019584 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 8098.685225 # Cycle average of tags in use
system.cpu.l2cache.total_refs 553407 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 359340764000 # number of cpu cycles simulated
system.cpu.numCycles 362778959000 # number of cpu cycles simulated
system.cpu.num_insts 243840172 # Number of instructions executed
system.cpu.num_refs 105125191 # Number of memory references
system.cpu.workload.PROG:num_syscalls 428 # Number of system calls

8
tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
View file

@ -21,9 +21,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jun 21 2007 21:15:48
M5 started Fri Jun 22 02:01:52 2007
M5 executing on zizzer.eecs.umich.edu
M5 compiled Aug 12 2007 12:23:15
M5 started Sun Aug 12 16:47:12 2007
M5 executing on zeep
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 359340764000 because target called exit()
Exiting @ tick 362778959000 because target called exit()

72
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=DerivO3CPU
children=dcache fuPool icache l2cache toL2Bus workload
children=dcache fuPool icache l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -21,6 +21,7 @@ SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
choiceCtrBits=2
choicePredictorSize=8192
clock=500
@ -74,8 +75,18 @@ renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
@ -85,21 +96,21 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -107,12 +118,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -128,11 +137,11 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList0
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList0
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList0]
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
@ -206,11 +215,11 @@ opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList0
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList0]
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
@ -218,11 +227,11 @@ opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList0
children=opList
count=0
opList=system.cpu.fuPool.FUList5.opList0
opList=system.cpu.fuPool.FUList5.opList
[system.cpu.fuPool.FUList5.opList0]
[system.cpu.fuPool.FUList5.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
@ -248,11 +257,11 @@ opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0
children=opList
count=1
opList=system.cpu.fuPool.FUList7.opList0
opList=system.cpu.fuPool.FUList7.opList
[system.cpu.fuPool.FUList7.opList0]
[system.cpu.fuPool.FUList7.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
@ -260,21 +269,21 @@ opLat=3
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -282,12 +291,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -298,21 +305,21 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -320,12 +327,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -343,6 +348,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
@ -366,7 +374,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory

593
tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -1,112 +1,114 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 36408912 # Number of BTB hits
global.BPredUnit.BTBLookups 43706931 # Number of BTB lookups
global.BPredUnit.RASInCorrect 1105 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 5391565 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 33884568 # Number of conditional branches predicted
global.BPredUnit.lookups 59377619 # Number of BP lookups
global.BPredUnit.usedRAS 11768977 # Number of times the RAS was used to get a target.
host_inst_rate 72337 # Simulator instruction rate (inst/s)
host_mem_usage 157124 # Number of bytes of host memory used
host_seconds 5192.02 # Real time elapsed on the host
host_tick_rate 28301038 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 55015552 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 43012918 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 120933927 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 90962569 # Number of stores inserted to the mem dependence unit.
global.BPredUnit.BTBHits 38073438 # Number of BTB hits
global.BPredUnit.BTBLookups 45542237 # Number of BTB lookups
global.BPredUnit.RASInCorrect 1066 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 5897861 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 35152227 # Number of conditional branches predicted
global.BPredUnit.lookups 62262084 # Number of BP lookups
global.BPredUnit.usedRAS 12565322 # Number of times the RAS was used to get a target.
host_inst_rate 169929 # Simulator instruction rate (inst/s)
host_mem_usage 207944 # Number of bytes of host memory used
host_seconds 2210.19 # Real time elapsed on the host
host_tick_rate 59827386 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 71764383 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 51661369 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 124318593 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 91863744 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 375574819 # Number of instructions simulated
sim_seconds 0.146939 # Number of seconds simulated
sim_ticks 146939447000 # Number of ticks simulated
system.cpu.commit.COM:branches 44587532 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 12019969 # number cycles where commit BW limit reached
sim_insts 375574833 # Number of instructions simulated
sim_seconds 0.132230 # Number of seconds simulated
sim_ticks 132229900500 # Number of ticks simulated
system.cpu.commit.COM:branches 44587535 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 12177812 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 280687503
system.cpu.commit.COM:committed_per_cycle.samples 249309209
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 153383398 5464.56%
1 43042738 1533.48%
2 19983570 711.95%
3 20747693 739.17%
4 12078292 430.31%
5 11042042 393.39%
6 5000100 178.14%
7 3389701 120.76%
8 12019969 428.23%
0 114305349 4584.88%
1 51380693 2060.92%
2 21363734 856.92%
3 20883024 837.64%
4 12699516 509.39%
5 8486510 340.40%
6 4833732 193.89%
7 3178839 127.51%
8 12177812 488.46%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:count 398664594 # Number of instructions committed
system.cpu.commit.COM:loads 100651995 # Number of loads committed
system.cpu.commit.COM:count 398664608 # Number of instructions committed
system.cpu.commit.COM:loads 100651996 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 174183397 # Number of memory references committed
system.cpu.commit.COM:refs 174183399 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 5387368 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions
system.cpu.commit.branchMispredicts 5893662 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 398664608 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 80492961 # The number of squashed insts skipped by commit
system.cpu.committedInsts 375574819 # Number of Instructions Simulated
system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated
system.cpu.cpi 0.782478 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.782478 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 96341397 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 5402.232747 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4689.672802 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 96339919 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 7984500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000015 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1478 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 500 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 4586500 # number of ReadReq MSHR miss cycles
system.cpu.commit.commitSquashedInsts 93436434 # The number of squashed insts skipped by commit
system.cpu.committedInsts 375574833 # Number of Instructions Simulated
system.cpu.committedInsts_total 375574833 # Number of Instructions Simulated
system.cpu.cpi 0.704145 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.704145 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 96516428 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 11350.662589 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5775.739042 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 96515447 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 11135000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 981 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 512 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 5666000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 978 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 5858.789942 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4984.052533 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 73511622 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 53356000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000124 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 9107 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 5909 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 15939000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 3198 # number of WriteReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses 981 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 73513288 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 23676.737160 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6083.836858 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 73509978 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 78370000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 3310 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 7442 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 20137500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 3310 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 40673.261734 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 40714.928400 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 169862126 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 5795.040151 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 4915.110153 # average overall mshr miss latency
system.cpu.dcache.demand_hits 169851541 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 61340500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000062 # miss rate for demand accesses
system.cpu.dcache.demand_misses 10585 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 6409 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 20525500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_accesses 170029716 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 20858.774179 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 6013.400140 # average overall mshr miss latency
system.cpu.dcache.demand_hits 170025425 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 89505000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
system.cpu.dcache.demand_misses 4291 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 7954 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 25803500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 4176 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses 4291 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 169862126 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 5795.040151 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 4915.110153 # average overall mshr miss latency
system.cpu.dcache.overall_accesses 170029716 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 20858.774179 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 6013.400140 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 169851541 # number of overall hits
system.cpu.dcache.overall_miss_latency 61340500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000062 # miss rate for overall accesses
system.cpu.dcache.overall_misses 10585 # number of overall misses
system.cpu.dcache.overall_mshr_hits 6409 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 20525500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_hits 170025425 # number of overall hits
system.cpu.dcache.overall_miss_latency 89505000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
system.cpu.dcache.overall_misses 4291 # number of overall misses
system.cpu.dcache.overall_mshr_hits 7954 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 25803500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 4176 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses 4291 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -118,92 +120,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 781 # number of replacements
system.cpu.dcache.replacements 780 # number of replacements
system.cpu.dcache.sampled_refs 4176 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3294.483088 # Cycle average of tags in use
system.cpu.dcache.total_refs 169851541 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 3294.806600 # Cycle average of tags in use
system.cpu.dcache.total_refs 170025541 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 637 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 7091571 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 4262 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 10528111 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 508290393 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 182764130 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 90473414 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 13191511 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 12840 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 358389 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 59377619 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 61063139 # Number of cache lines fetched
system.cpu.fetch.Cycles 154416855 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 2298760 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 522129068 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 5723447 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.202048 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 61063139 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 48177889 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.776680 # Number of inst fetches per cycle
system.cpu.dcache.writebacks 635 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 14093330 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 4329 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 11426166 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 530907169 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 132358480 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 102072460 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 15149848 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 12784 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 784940 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 62262084 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 64149519 # Number of cache lines fetched
system.cpu.fetch.Cycles 169628877 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 1267942 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 544672632 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 6256256 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.235432 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 64149519 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 50638760 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.059573 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 293879015
system.cpu.fetch.rateDist.samples 264459058
system.cpu.fetch.rateDist.min_value 0
0 200525300 6823.40%
1 7846897 267.01%
2 7291722 248.12%
3 6200462 210.99%
4 13845529 471.13%
5 7438768 253.12%
6 7492914 254.97%
7 2335483 79.47%
8 40901940 1391.80%
0 158979701 6011.51%
1 11898103 449.90%
2 12511338 473.09%
3 6558243 247.99%
4 15951093 603.16%
5 8933216 337.79%
6 6667977 252.14%
7 4076286 154.14%
8 38883101 1470.29%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 61063139 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 5151.654640 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4230.492813 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 61059120 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 20704500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000066 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 4019 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 123 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 16482000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 3896 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_accesses 64149331 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 7193.164363 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5001.152074 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 64145425 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 28096500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000061 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 3906 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 188 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 19534500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 3906 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 15672.258727 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 16422.279826 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 61063139 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 5151.654640 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 4230.492813 # average overall mshr miss latency
system.cpu.icache.demand_hits 61059120 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 20704500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000066 # miss rate for demand accesses
system.cpu.icache.demand_misses 4019 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 123 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 16482000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 3896 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_accesses 64149331 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 7193.164363 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 5001.152074 # average overall mshr miss latency
system.cpu.icache.demand_hits 64145425 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 28096500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000061 # miss rate for demand accesses
system.cpu.icache.demand_misses 3906 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 188 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 19534500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 3906 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 61063139 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 5151.654640 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 4230.492813 # average overall mshr miss latency
system.cpu.icache.overall_accesses 64149331 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 7193.164363 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 5001.152074 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 61059120 # number of overall hits
system.cpu.icache.overall_miss_latency 20704500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000066 # miss rate for overall accesses
system.cpu.icache.overall_misses 4019 # number of overall misses
system.cpu.icache.overall_mshr_hits 123 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 16482000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 3896 # number of overall MSHR misses
system.cpu.icache.overall_hits 64145425 # number of overall hits
system.cpu.icache.overall_miss_latency 28096500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000061 # miss rate for overall accesses
system.cpu.icache.overall_misses 3906 # number of overall misses
system.cpu.icache.overall_mshr_hits 188 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 19534500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 3906 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -215,162 +217,183 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 1976 # number of replacements
system.cpu.icache.sampled_refs 3896 # Sample count of references to valid blocks.
system.cpu.icache.replacements 1984 # number of replacements
system.cpu.icache.sampled_refs 3906 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1822.947356 # Cycle average of tags in use
system.cpu.icache.total_refs 61059120 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1827.150129 # Cycle average of tags in use
system.cpu.icache.total_refs 64145425 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 6367 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 50329288 # Number of branches executed
system.cpu.iew.EXEC:nop 26718868 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.409679 # Inst execution rate
system.cpu.iew.EXEC:refs 190324589 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 79889528 # Number of stores executed
system.cpu.idleCycles 557628 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 51104102 # Number of branches executed
system.cpu.iew.EXEC:nop 27319155 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.584545 # Inst execution rate
system.cpu.iew.EXEC:refs 191326029 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 79588041 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 266244037 # num instructions consuming a value
system.cpu.iew.WB:count 411128901 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.717332 # average fanout of values written-back
system.cpu.iew.WB:consumers 282498519 # num instructions consuming a value
system.cpu.iew.WB:count 414521159 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.706139 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 190985280 # num instructions producing a value
system.cpu.iew.WB:rate 1.398973 # insts written-back per cycle
system.cpu.iew.WB:sent 411485990 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 6032644 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 1137801 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 120933927 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 222 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 6771454 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 90962569 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 479157588 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 110435061 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 10298797 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 414275208 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 67 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 199483248 # num instructions producing a value
system.cpu.iew.WB:rate 1.567430 # insts written-back per cycle
system.cpu.iew.WB:sent 415435713 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 6236762 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 2781988 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 124318593 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 240 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 6814163 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 91863744 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 492099709 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 111737988 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 8739319 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 419047233 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 168412 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 21083 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 13191511 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 115109 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 50946 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 15149848 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 506738 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 7097511 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 3223 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.forwLoads 8219638 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 31016 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 404889 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 176320 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 20281932 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 17431167 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 404889 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 802823 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 5229821 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.277991 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.277991 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 424574005 # Type of FU issued
system.cpu.iew.lsq.thread.0.memOrderViolation 502753 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 178119 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 23666597 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 18332341 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 502753 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 955669 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 5281093 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.420162 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.420162 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 427786552 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 33581 0.01% # Type of FU issued
IntAlu 163144501 38.43% # Type of FU issued
IntMult 2125088 0.50% # Type of FU issued
No_OpClass 33581 0.01% # Type of FU issued
IntAlu 166519693 38.93% # Type of FU issued
IntMult 2147905 0.50% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 34659405 8.16% # Type of FU issued
FloatCmp 7790033 1.83% # Type of FU issued
FloatCvt 2881594 0.68% # Type of FU issued
FloatMult 16618307 3.91% # Type of FU issued
FloatDiv 1566111 0.37% # Type of FU issued
FloatAdd 35254026 8.24% # Type of FU issued
FloatCmp 7817685 1.83% # Type of FU issued
FloatCvt 2969947 0.69% # Type of FU issued
FloatMult 16787400 3.92% # Type of FU issued
FloatDiv 1570522 0.37% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 113765764 26.80% # Type of FU issued
MemWrite 81989621 19.31% # Type of FU issued
MemRead 113248293 26.47% # Type of FU issued
MemWrite 81437500 19.04% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 9576176 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.022555 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_busy_cnt 9448608 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.022087 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
IntAlu 12415 0.13% # attempts to use FU when none available
No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 17181 0.18% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 46832 0.49% # attempts to use FU when none available
FloatCmp 11338 0.12% # attempts to use FU when none available
FloatCvt 25702 0.27% # attempts to use FU when none available
FloatMult 2984764 31.17% # attempts to use FU when none available
FloatDiv 331535 3.46% # attempts to use FU when none available
FloatAdd 604 0.01% # attempts to use FU when none available
FloatCmp 32516 0.34% # attempts to use FU when none available
FloatCvt 8012 0.08% # attempts to use FU when none available
FloatMult 2137313 22.62% # attempts to use FU when none available
FloatDiv 917798 9.71% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 4942933 51.62% # attempts to use FU when none available
MemWrite 1220657 12.75% # attempts to use FU when none available
MemRead 5261958 55.69% # attempts to use FU when none available
MemWrite 1073226 11.36% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 293879015
system.cpu.iq.ISSUE:issued_per_cycle.samples 264459058
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 129735390 4414.59%
1 52072154 1771.89%
2 39787134 1353.86%
3 29621395 1007.95%
4 21763636 740.56%
5 12600620 428.77%
6 4911147 167.11%
7 2561440 87.16%
8 826099 28.11%
0 94473273 3572.32%
1 57538428 2175.70%
2 41283183 1561.04%
3 28951087 1094.73%
4 22152944 837.67%
5 11939207 451.46%
6 5137200 194.25%
7 2172402 82.15%
8 811334 30.68%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 1.444724 # Inst issue rate
system.cpu.iq.iqInstsAdded 452438498 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 424574005 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 222 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 75756994 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 1109878 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 55099010 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 8070 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4677.770224 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2436.233855 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 715 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 34405000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.911400 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 7355 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 17918500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.911400 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 7355 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 637 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 637 # number of Writeback hits
system.cpu.iq.ISSUE:rate 1.617591 # Inst issue rate
system.cpu.iq.iqInstsAdded 464780314 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 427786552 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 240 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 88460147 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 742026 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 25 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 67499517 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 3199 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 4646.764614 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2646.764614 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 14865000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 3199 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 8467000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 3199 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 4883 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4356.375525 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2356.375525 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 601 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 18654000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.876920 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 4282 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 10090000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.876920 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 4282 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 117 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4482.905983 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2482.905983 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 524500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 117 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 290500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 117 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 635 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 635 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 635 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.183821 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.139496 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 8070 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4677.770224 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2436.233855 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 715 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 34405000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.911400 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 7355 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 8082 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4480.550729 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2480.550729 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 601 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 33519000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.925637 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 7481 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 17918500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.911400 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 7355 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 18557000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.925637 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 7481 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 8707 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4677.770224 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2436.233855 # average overall mshr miss latency
system.cpu.l2cache.overall_accesses 8082 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4480.550729 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2480.550729 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1352 # number of overall hits
system.cpu.l2cache.overall_miss_latency 34405000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.844723 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 7355 # number of overall misses
system.cpu.l2cache.overall_hits 601 # number of overall hits
system.cpu.l2cache.overall_miss_latency 33519000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.925637 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 7481 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 17918500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.844723 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 7355 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 18557000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.925637 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 7481 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -382,31 +405,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 7355 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 6 # number of replacements
system.cpu.l2cache.sampled_refs 4165 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 6644.823451 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1352 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 3521.188558 # Cycle average of tags in use
system.cpu.l2cache.total_refs 581 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 293879015 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 3715266 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 115195 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 185747540 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 2602652 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 654991501 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 496454048 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 320284080 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 87805227 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 13191511 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 3048084 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 60751739 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 371387 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 37057 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 7965999 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 243 # count of temporary serializing insts renamed
system.cpu.timesIdled 133 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.numCycles 264459058 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 6942912 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 259532351 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 1128496 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 136398173 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 4996172 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 682131973 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 517993086 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 334891535 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 98637930 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 15149848 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 6975590 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 75359184 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 354605 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 37909 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 15667924 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 253 # count of temporary serializing insts renamed
system.cpu.timesIdled 375 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout
View file

@ -1,2 +1,2 @@
Eon, Version 1.1
OO-style eon Time= 0.133333
OO-style eon Time= 0.116667

38
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus workload
children=dcache icache l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
@ -24,27 +24,28 @@ max_loads_any_thread=0
phase=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -52,12 +53,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -68,21 +67,21 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -90,12 +89,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -106,21 +103,21 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -128,12 +125,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -151,6 +146,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
@ -174,7 +172,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory

181
tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 579996 # Simulator instruction rate (inst/s)
host_mem_usage 156556 # Number of bytes of host memory used
host_seconds 687.36 # Real time elapsed on the host
host_tick_rate 824955659 # Simulator tick rate (ticks/s)
host_inst_rate 1477024 # Simulator instruction rate (inst/s)
host_mem_usage 207136 # Number of bytes of host memory used
host_seconds 269.91 # Real time elapsed on the host
host_tick_rate 2101151515 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664611 # Number of instructions simulated
sim_seconds 0.567040 # Number of seconds simulated
sim_ticks 567040254000 # Number of ticks simulated
sim_seconds 0.567124 # Number of seconds simulated
sim_ticks 567123959000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 13741.052632 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12741.052632 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 24216.842105 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22216.842105 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 13054000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 23006000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 12104000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 21106000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 13962.523423 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12962.523423 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 73517528 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 44708000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 41506000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 73517416 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 82850000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 3314 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 76222000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 3314 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks.
@ -37,31 +37,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 13911.849711 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12911.849711 # average overall mshr miss latency
system.cpu.dcache.demand_hits 168271068 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 57762000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_avg_miss_latency 24825.515947 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 22825.515947 # average overall mshr miss latency
system.cpu.dcache.demand_hits 168270956 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 105856000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses
system.cpu.dcache.demand_misses 4264 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 53610000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 97328000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses 4264 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 13911.849711 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12911.849711 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 24825.515947 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 22825.515947 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 168271068 # number of overall hits
system.cpu.dcache.overall_miss_latency 57762000 # number of overall miss cycles
system.cpu.dcache.overall_hits 168270956 # number of overall hits
system.cpu.dcache.overall_miss_latency 105856000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
system.cpu.dcache.overall_misses 4152 # number of overall misses
system.cpu.dcache.overall_misses 4264 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 53610000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 97328000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses 4264 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 764 # number of replacements
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3289.654807 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 3289.454030 # Cycle average of tags in use
system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 625 # number of writebacks
system.cpu.icache.ReadReq_accesses 398664612 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 13745.167438 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12745.167438 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 23471.004628 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 21471.004628 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 398660939 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 50486000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 86209000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 46813000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 78863000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 398664612 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 13745.167438 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12745.167438 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 23471.004628 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 21471.004628 # average overall mshr miss latency
system.cpu.icache.demand_hits 398660939 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 50486000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 86209000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 46813000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 78863000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 398664612 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 13745.167438 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12745.167438 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 23471.004628 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 21471.004628 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 398660939 # number of overall hits
system.cpu.icache.overall_miss_latency 50486000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 86209000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
system.cpu.icache.overall_misses 3673 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 46813000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 78863000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -138,57 +138,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 1769 # number of replacements
system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1795.458615 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1795.369888 # Cycle average of tags in use
system.cpu.icache.total_refs 398660939 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 7825 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 70444000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 3202 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 35222000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 3202 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 651 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 93262000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.916805 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 7174 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 78914000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916805 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 7174 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_hits 530 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 90046000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.885356 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 4093 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 45023000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.885356 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 4093 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 112 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 2464000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 112 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1232000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 112 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 625 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 625 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.177865 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.128109 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 651 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 93262000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.916805 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 7174 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 530 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 160490000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.932268 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 7295 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 78914000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.916805 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 7174 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 80245000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.932268 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 7295 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 8450 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1276 # number of overall hits
system.cpu.l2cache.overall_miss_latency 93262000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.848994 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 7174 # number of overall misses
system.cpu.l2cache.overall_hits 530 # number of overall hits
system.cpu.l2cache.overall_miss_latency 160490000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.932268 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 7295 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 78914000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.848994 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 7174 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 80245000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.932268 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 7295 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -200,15 +221,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 7174 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 6 # number of replacements
system.cpu.l2cache.sampled_refs 3981 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 6483.455048 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1276 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 3355.056948 # Cycle average of tags in use
system.cpu.l2cache.total_refs 510 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 567040254000 # number of cpu cycles simulated
system.cpu.numCycles 567123959000 # number of cpu cycles simulated
system.cpu.num_insts 398664611 # Number of instructions executed
system.cpu.num_refs 174183401 # Number of memory references
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls

38
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus workload
children=dcache icache l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
@ -24,27 +24,28 @@ max_loads_any_thread=0
phase=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -52,12 +53,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -68,21 +67,21 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -90,12 +89,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -106,21 +103,21 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -128,12 +125,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -151,6 +146,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
@ -174,7 +172,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory

199
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 622738 # Simulator instruction rate (inst/s)
host_mem_usage 156744 # Number of bytes of host memory used
host_seconds 3226.05 # Real time elapsed on the host
host_tick_rate 852686846 # Simulator tick rate (ticks/s)
host_inst_rate 1536320 # Simulator instruction rate (inst/s)
host_mem_usage 206288 # Number of bytes of host memory used
host_seconds 1307.66 # Real time elapsed on the host
host_tick_rate 2116487900 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987607 # Number of instructions simulated
sim_seconds 2.750814 # Number of seconds simulated
sim_ticks 2750814393000 # Number of ticks simulated
sim_seconds 2.767652 # Number of seconds simulated
sim_ticks 2767652365000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 13971.031250 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12971.031250 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 24898.959808 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22898.959808 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 20372446000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 36307464000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 18914254000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 33391080000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 13873.860351 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12873.860351 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 210722944 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 998252000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000341 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 71952 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 926300000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000341 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 71952 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 210720109 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 1869675000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000355 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 74787 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 1720101000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 74787 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks.
@ -37,31 +37,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 13966.461980 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12966.461980 # average overall mshr miss latency
system.cpu.dcache.demand_hits 720334778 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 21370698000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002120 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1530144 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 24903.889094 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 22903.889094 # average overall mshr miss latency
system.cpu.dcache.demand_hits 720331943 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 38177139000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002124 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1532979 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 19840554000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002120 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1530144 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 35111181000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002124 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1532979 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 13966.461980 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12966.461980 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 24903.889094 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 22903.889094 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 720334778 # number of overall hits
system.cpu.dcache.overall_miss_latency 21370698000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002120 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1530144 # number of overall misses
system.cpu.dcache.overall_hits 720331943 # number of overall hits
system.cpu.dcache.overall_miss_latency 38177139000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002124 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1532979 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 19840554000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002120 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1530144 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 35111181000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002124 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1532979 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 1526048 # number of replacements
system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.422371 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4095.361611 # Cycle average of tags in use
system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 702832000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.warmup_cycle 795826000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 74589 # number of writebacks
system.cpu.icache.ReadReq_accesses 2008987608 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 12448.659872 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11448.659872 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 15691.959230 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 13691.959230 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 2008977012 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 131906000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 166272000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 121310000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 145080000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 2008987608 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 12448.659872 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11448.659872 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 15691.959230 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 13691.959230 # average overall mshr miss latency
system.cpu.icache.demand_hits 2008977012 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 131906000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 166272000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses
system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 121310000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 145080000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 2008987608 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 12448.659872 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11448.659872 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 15691.959230 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 13691.959230 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 2008977012 # number of overall hits
system.cpu.icache.overall_miss_latency 131906000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 166272000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses
system.cpu.icache.overall_misses 10596 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 121310000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 145080000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -138,61 +138,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 9046 # number of replacements
system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1478.610505 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1478.559322 # Cycle average of tags in use
system.cpu.icache.total_refs 2008977012 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 1540740 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_accesses 71952 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 1582944000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 71952 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 791472000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 71952 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 1468788 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 33878 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 19589206000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.978012 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1506862 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 16575482000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.978012 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1506862 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_hits 20497 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 31862402000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.986045 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1448291 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 15931201000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.986045 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1448291 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 2835 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 21821.516755 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 61864000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 2835 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31185000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 2835 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 73515 # number of Writeback hits
system.cpu.l2cache.Writeback_miss_rate 0.014399 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 1074 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 0.014399 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 1074 # number of Writeback MSHR misses
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 74589 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 74589 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.071269 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.015643 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 33878 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 19589206000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.978012 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 1506862 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 20497 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 33445346000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.986697 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 1520243 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 16575482000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.978012 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 1506862 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 16722673000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.986697 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 1520243 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 1615329 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 12990.740986 # average overall miss latency
system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 107393 # number of overall hits
system.cpu.l2cache.overall_miss_latency 19589206000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.933516 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 1507936 # number of overall misses
system.cpu.l2cache.overall_hits 20497 # number of overall hits
system.cpu.l2cache.overall_miss_latency 33445346000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.986697 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 1520243 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 16575482000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.932851 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 1506862 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 16722673000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.986697 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 1520243 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -204,15 +221,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 1474094 # number of replacements
system.cpu.l2cache.sampled_refs 1506862 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 1412930 # number of replacements
system.cpu.l2cache.sampled_refs 1445479 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 32753.638584 # Cycle average of tags in use
system.cpu.l2cache.total_refs 107393 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 2394479000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 66804 # number of writebacks
system.cpu.l2cache.tagsinuse 31165.183060 # Cycle average of tags in use
system.cpu.l2cache.total_refs 22612 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 2750814393000 # number of cpu cycles simulated
system.cpu.numCycles 2767652365000 # number of cpu cycles simulated
system.cpu.num_insts 2008987607 # Number of instructions executed
system.cpu.num_refs 722390435 # Number of memory references
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls

72
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=DerivO3CPU
children=dcache fuPool icache l2cache toL2Bus workload
children=dcache fuPool icache l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -21,6 +21,7 @@ SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
choiceCtrBits=2
choicePredictorSize=8192
clock=500
@ -74,8 +75,18 @@ renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
@ -85,21 +96,21 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -107,12 +118,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -128,11 +137,11 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList0
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList0
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList0]
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
@ -206,11 +215,11 @@ opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList0
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList0]
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
@ -218,11 +227,11 @@ opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList0
children=opList
count=0
opList=system.cpu.fuPool.FUList5.opList0
opList=system.cpu.fuPool.FUList5.opList
[system.cpu.fuPool.FUList5.opList0]
[system.cpu.fuPool.FUList5.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
@ -248,11 +257,11 @@ opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0
children=opList
count=1
opList=system.cpu.fuPool.FUList7.opList0
opList=system.cpu.fuPool.FUList7.opList
[system.cpu.fuPool.FUList7.opList0]
[system.cpu.fuPool.FUList7.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
@ -260,21 +269,21 @@ opLat=3
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -282,12 +291,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -298,21 +305,21 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -320,12 +327,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -343,6 +348,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
@ -366,7 +374,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory

583
tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 7411086 # Number of BTB hits
global.BPredUnit.BTBLookups 13158968 # Number of BTB lookups
global.BPredUnit.RASInCorrect 32147 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 450892 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 9746581 # Number of conditional branches predicted
global.BPredUnit.lookups 14988034 # Number of BP lookups
global.BPredUnit.usedRAS 1776543 # Number of times the RAS was used to get a target.
host_inst_rate 99683 # Simulator instruction rate (inst/s)
host_mem_usage 159476 # Number of bytes of host memory used
host_seconds 798.45 # Real time elapsed on the host
host_tick_rate 35303213 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 9747985 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 9298064 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 21418262 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 15459606 # Number of stores inserted to the mem dependence unit.
global.BPredUnit.BTBHits 7542290 # Number of BTB hits
global.BPredUnit.BTBLookups 13308941 # Number of BTB lookups
global.BPredUnit.RASInCorrect 34250 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 454073 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 9847799 # Number of conditional branches predicted
global.BPredUnit.lookups 15155323 # Number of BP lookups
global.BPredUnit.usedRAS 1795531 # Number of times the RAS was used to get a target.
host_inst_rate 196409 # Simulator instruction rate (inst/s)
host_mem_usage 211144 # Number of bytes of host memory used
host_seconds 405.24 # Real time elapsed on the host
host_tick_rate 57107000 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 11563356 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 10718994 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 21578903 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 15738647 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 79591756 # Number of instructions simulated
sim_seconds 0.028188 # Number of seconds simulated
sim_ticks 28187684500 # Number of ticks simulated
sim_seconds 0.023142 # Number of seconds simulated
sim_ticks 23141799000 # Number of ticks simulated
system.cpu.commit.COM:branches 13754477 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 3230574 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 3510282 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 55590975
system.cpu.commit.COM:committed_per_cycle.samples 45393667
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 26501535 4767.24%
1 10970497 1973.43%
2 5466463 983.34%
3 3506601 630.79%
4 2372940 426.86%
5 1558557 280.36%
6 1098347 197.58%
7 885461 159.28%
8 3230574 581.13%
0 16854505 3712.96%
1 10816662 2382.86%
2 5010201 1103.72%
3 3353080 738.67%
4 2515867 554.23%
5 1511689 333.02%
6 1009468 222.38%
7 811913 178.86%
8 3510282 773.30%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@ -43,70 +43,72 @@ system.cpu.commit.COM:loads 20379399 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 35224018 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 355366 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 357583 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 4551161 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 5444219 # The number of squashed insts skipped by commit
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
system.cpu.cpi 0.708309 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.708309 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 20049834 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 4729.134904 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3349.390829 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 19907503 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 673102500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.007099 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 142331 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 80854 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 205910500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003066 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 61477 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 3029.723364 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4119.889460 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 14053363 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 1696687500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.038322 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 560014 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 416536 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 591113500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009818 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 143478 # number of WriteReq MSHR misses
system.cpu.cpi 0.581499 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.581499 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 19849413 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 15478.106634 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4237.239017 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 19787819 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 953358500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.003103 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 61594 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 85223 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 260988500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003103 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 61594 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 13805554 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 30519.673214 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5295.405245 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 13655731 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 4572549000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.010852 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 149823 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 807823 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 793373500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010852 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 149823 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 165.699134 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 163.116342 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 34663211 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 3374.111014 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3888.775585 # average overall mshr miss latency
system.cpu.dcache.demand_hits 33960866 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 2369790000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.020262 # miss rate for demand accesses
system.cpu.dcache.demand_misses 702345 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 497390 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 797024000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005913 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 204955 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 33654967 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 26137.479484 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 4987.120241 # average overall mshr miss latency
system.cpu.dcache.demand_hits 33443550 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 5525907500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.006282 # miss rate for demand accesses
system.cpu.dcache.demand_misses 211417 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 893046 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 1054362000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.006282 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 211417 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 34663211 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 3374.111014 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3888.775585 # average overall mshr miss latency
system.cpu.dcache.overall_accesses 33654967 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 26137.479484 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 4987.120241 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 33960866 # number of overall hits
system.cpu.dcache.overall_miss_latency 2369790000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.020262 # miss rate for overall accesses
system.cpu.dcache.overall_misses 702345 # number of overall misses
system.cpu.dcache.overall_mshr_hits 497390 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 797024000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005913 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 204955 # number of overall MSHR misses
system.cpu.dcache.overall_hits 33443550 # number of overall hits
system.cpu.dcache.overall_miss_latency 5525907500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.006282 # miss rate for overall accesses
system.cpu.dcache.overall_misses 211417 # number of overall misses
system.cpu.dcache.overall_mshr_hits 893046 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 1054362000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.006282 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 211417 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -118,92 +120,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 200859 # number of replacements
system.cpu.dcache.sampled_refs 204955 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 200972 # number of replacements
system.cpu.dcache.sampled_refs 205068 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4080.110580 # Cycle average of tags in use
system.cpu.dcache.total_refs 33960866 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 144827000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 147753 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 583473 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 97307 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 3380270 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 95203508 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 37386702 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 17614461 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 784542 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 292514 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 6340 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 14988034 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 12416477 # Number of cache lines fetched
system.cpu.fetch.Cycles 30119953 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 260035 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 96279919 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 467393 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.265861 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 12416477 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 9187629 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.707832 # Number of inst fetches per cycle
system.cpu.dcache.tagsinuse 4079.963353 # Cycle average of tags in use
system.cpu.dcache.total_refs 33449942 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 119008000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 147761 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 971695 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 97371 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 3417858 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 96162354 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 25952342 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 18439987 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 888885 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 288762 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 29644 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 15155323 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 12535185 # Number of cache lines fetched
system.cpu.fetch.Cycles 31179449 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 131701 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 97686537 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 470452 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.327452 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 12535185 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 9337821 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.110656 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 56375518
system.cpu.fetch.rateDist.samples 46282553
system.cpu.fetch.rateDist.min_value 0
0 38672046 6859.72%
1 1321940 234.49%
2 1201428 213.11%
3 1338454 237.42%
4 3789980 672.27%
5 1624217 288.11%
6 592859 105.16%
7 975150 172.97%
8 6859444 1216.74%
0 27638291 5971.64%
1 1733920 374.64%
2 1408099 304.24%
3 1707036 368.83%
4 3689148 797.09%
5 1739866 375.92%
6 655334 141.59%
7 1059487 228.92%
8 6651372 1437.12%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 12416477 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 3477.694454 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2488.876340 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 12330467 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 299116500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.006927 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 86010 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 1011 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 211552000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.006846 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 84999 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_accesses 12534294 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 4593.252212 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2552.911039 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 12448414 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 394468500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.006852 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 85880 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 891 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 219244000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.006852 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 85880 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 145.066024 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 144.958009 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 12416477 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 3477.694454 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 2488.876340 # average overall mshr miss latency
system.cpu.icache.demand_hits 12330467 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 299116500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.006927 # miss rate for demand accesses
system.cpu.icache.demand_misses 86010 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 1011 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 211552000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.006846 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 84999 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_accesses 12534294 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 4593.252212 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 2552.911039 # average overall mshr miss latency
system.cpu.icache.demand_hits 12448414 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 394468500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.006852 # miss rate for demand accesses
system.cpu.icache.demand_misses 85880 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 891 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 219244000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.006852 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 85880 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 12416477 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 3477.694454 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2488.876340 # average overall mshr miss latency
system.cpu.icache.overall_accesses 12534294 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 4593.252212 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2552.911039 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 12330467 # number of overall hits
system.cpu.icache.overall_miss_latency 299116500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.006927 # miss rate for overall accesses
system.cpu.icache.overall_misses 86010 # number of overall misses
system.cpu.icache.overall_mshr_hits 1011 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 211552000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.006846 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 84999 # number of overall MSHR misses
system.cpu.icache.overall_hits 12448414 # number of overall hits
system.cpu.icache.overall_miss_latency 394468500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.006852 # miss rate for overall accesses
system.cpu.icache.overall_misses 85880 # number of overall misses
system.cpu.icache.overall_mshr_hits 891 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 219244000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.006852 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 85880 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -215,80 +217,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 82951 # number of replacements
system.cpu.icache.sampled_refs 84999 # Sample count of references to valid blocks.
system.cpu.icache.replacements 83828 # number of replacements
system.cpu.icache.sampled_refs 85876 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1918.432617 # Cycle average of tags in use
system.cpu.icache.total_refs 12330467 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 24669337000 # Cycle when the warmup percentage was hit.
system.cpu.icache.tagsinuse 1919.939531 # Cycle average of tags in use
system.cpu.icache.total_refs 12448414 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 20180672000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 25301 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 14196900 # Number of branches executed
system.cpu.iew.EXEC:nop 9006488 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.455602 # Inst execution rate
system.cpu.iew.EXEC:refs 36045074 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 15052480 # Number of stores executed
system.cpu.idleCycles 779486 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 14215317 # Number of branches executed
system.cpu.iew.EXEC:nop 9054056 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.776804 # Inst execution rate
system.cpu.iew.EXEC:refs 36085022 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 15098216 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 39431808 # num instructions consuming a value
system.cpu.iew.WB:count 81784655 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.769564 # average fanout of values written-back
system.cpu.iew.WB:consumers 41423091 # num instructions consuming a value
system.cpu.iew.WB:count 81970056 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.763712 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 30345313 # num instructions producing a value
system.cpu.iew.WB:rate 1.450712 # insts written-back per cycle
system.cpu.iew.WB:sent 81828309 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 387091 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 10156 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 21418262 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 4652 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 597409 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 15459606 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 92891480 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 20992594 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 333391 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 82060341 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 141 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 31635305 # num instructions producing a value
system.cpu.iew.WB:rate 1.771079 # insts written-back per cycle
system.cpu.iew.WB:sent 82027383 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 388269 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 17461 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 21578903 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 4692 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 341214 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 15738647 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 93782111 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 20986806 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 455724 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 82235016 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 2252 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 37 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 784542 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 478 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 122 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 888885 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 3197 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 828061 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 554 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 937737 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 950 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 19340 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1425 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 1038863 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 614987 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 19340 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 103732 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 283359 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.411814 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.411814 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 82393732 # Type of FU issued
system.cpu.iew.lsq.thread.0.memOrderViolation 19015 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1226 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 1199504 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 894028 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 19015 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 105591 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 282678 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.719692 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.719692 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 82690740 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 0 0.00% # Type of FU issued
IntAlu 45892607 55.70% # Type of FU issued
IntMult 44107 0.05% # Type of FU issued
No_OpClass 0 0.00% # Type of FU issued
IntAlu 46107608 55.76% # Type of FU issued
IntMult 43061 0.05% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 116900 0.14% # Type of FU issued
FloatAdd 119602 0.14% # Type of FU issued
FloatCmp 87 0.00% # Type of FU issued
FloatCvt 120453 0.15% # Type of FU issued
FloatCvt 120853 0.15% # Type of FU issued
FloatMult 50 0.00% # Type of FU issued
FloatDiv 37768 0.05% # Type of FU issued
FloatDiv 37774 0.05% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 21065064 25.57% # Type of FU issued
MemWrite 15116696 18.35% # Type of FU issued
MemRead 21079728 25.49% # Type of FU issued
MemWrite 15181977 18.36% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 898002 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.010899 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_busy_cnt 974009 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.011779 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
IntAlu 168043 18.71% # attempts to use FU when none available
No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 90058 9.25% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
@ -297,84 +299,101 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 309725 34.49% # attempts to use FU when none available
MemWrite 420234 46.80% # attempts to use FU when none available
MemRead 437339 44.90% # attempts to use FU when none available
MemWrite 446612 45.85% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 56375518
system.cpu.iq.ISSUE:issued_per_cycle.samples 46282553
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 22612550 4011.06%
1 13769796 2442.51%
2 7834961 1389.78%
3 4029672 714.79%
4 3712649 658.56%
5 1993297 353.57%
6 1449259 257.07%
7 434309 77.04%
8 539025 95.61%
0 12550048 2711.62%
1 12875827 2782.00%
2 7785024 1682.06%
3 4673558 1009.79%
4 4500672 972.43%
5 2074677 448.26%
6 1137561 245.79%
7 458736 99.12%
8 226450 48.93%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 1.461516 # Inst issue rate
system.cpu.iq.iqInstsAdded 83880340 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 82393732 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 4652 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 4104955 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 35761 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 69 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 2730801 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 289883 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4226.385671 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2218.670959 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 120272 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 716841500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.585102 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 169611 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 376311000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.585102 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 169611 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 147753 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 147292 # number of Writeback hits
system.cpu.l2cache.Writeback_miss_rate 0.003120 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 461 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 0.003120 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 461 # number of Writeback MSHR misses
system.cpu.iq.ISSUE:rate 1.786650 # Inst issue rate
system.cpu.iq.iqInstsAdded 84723363 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 82690740 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 4692 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 4940751 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 53730 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 109 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 3594449 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 143476 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 4086.446514 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2086.446514 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 586307000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 143476 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 299355000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 143476 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 147467 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4144.894478 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2144.894478 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 98804 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 201703000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.329992 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 48663 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 104377000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.329992 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 48663 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 6368 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4226.366206 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2231.626884 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 26913500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 6368 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14211000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 6368 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 147761 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 147761 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 147761 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 1.577516 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 2.459748 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 289883 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4226.385671 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2218.670959 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 120272 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 716841500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.585102 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 169611 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 290943 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4101.249616 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2101.249616 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 98804 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 788010000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.660401 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 192139 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 376311000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.585102 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 169611 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 403732000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.660401 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 192139 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 437636 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4214.929559 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2218.670959 # average overall mshr miss latency
system.cpu.l2cache.overall_accesses 290943 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4101.249616 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2101.249616 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 267564 # number of overall hits
system.cpu.l2cache.overall_miss_latency 716841500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.388615 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 170072 # number of overall misses
system.cpu.l2cache.overall_hits 98804 # number of overall hits
system.cpu.l2cache.overall_miss_latency 788010000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.660401 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 192139 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 376311000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.387562 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 169611 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 403732000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.660401 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 192139 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -386,31 +405,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 136843 # number of replacements
system.cpu.l2cache.sampled_refs 169611 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 25941 # number of replacements
system.cpu.l2cache.sampled_refs 41849 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 32058.525051 # Cycle average of tags in use
system.cpu.l2cache.total_refs 267564 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 13792867000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 115936 # number of writebacks
system.cpu.numCycles 56375518 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 238131 # Number of cycles rename is blocking
system.cpu.l2cache.tagsinuse 4585.524484 # Cycle average of tags in use
system.cpu.l2cache.total_refs 102938 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 46282553 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 249890 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 31030 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 37626801 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 240022 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 113729051 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 94390828 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 56605918 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 17378620 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 784542 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 281505 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 4059037 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 65919 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 4656 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 641192 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 4654 # count of temporary serializing insts renamed
system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:IQFullEvents 36341 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 26244762 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 565515 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 115161809 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 95469817 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 57208765 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 18176186 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 888885 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 649163 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 4661884 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 73667 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 4695 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 1420326 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 4693 # count of temporary serializing insts renamed
system.cpu.timesIdled 518 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ----------

38
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus workload
children=dcache icache l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
@ -24,27 +24,28 @@ max_loads_any_thread=0
phase=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -52,12 +53,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -68,21 +67,21 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -90,12 +89,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -106,21 +103,21 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -128,12 +125,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -151,6 +146,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
@ -174,7 +172,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory

205
tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 585395 # Simulator instruction rate (inst/s)
host_mem_usage 158604 # Number of bytes of host memory used
host_seconds 150.91 # Real time elapsed on the host
host_tick_rate 839295251 # Simulator tick rate (ticks/s)
host_inst_rate 1495977 # Simulator instruction rate (inst/s)
host_mem_usage 209700 # Number of bytes of host memory used
host_seconds 59.05 # Real time elapsed on the host
host_tick_rate 2185213288 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340674 # Number of instructions simulated
sim_seconds 0.126657 # Number of seconds simulated
sim_ticks 126656575000 # Number of ticks simulated
sim_seconds 0.129042 # Number of seconds simulated
sim_ticks 129042205000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 12987.854851 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11987.854851 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 20958.331276 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18958.331276 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 789207000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 1273533000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 728442000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 1152003000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 13826.199000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12826.199000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 1985138000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 1841560000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 3744825000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 3445239000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 169.742404 # Average number of references to valid blocks.
@ -37,31 +37,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 13576.902561 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12576.902561 # average overall mshr miss latency
system.cpu.dcache.demand_hits 34685672 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 2774345000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses
system.cpu.dcache.demand_misses 204343 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 23833.613541 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 21833.613541 # average overall mshr miss latency
system.cpu.dcache.demand_hits 34679457 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 5018358000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses
system.cpu.dcache.demand_misses 210558 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 2570002000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 204343 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 4597242000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 210558 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 13576.902561 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12576.902561 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 23833.613541 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 21833.613541 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 34685672 # number of overall hits
system.cpu.dcache.overall_miss_latency 2774345000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses
system.cpu.dcache.overall_misses 204343 # number of overall misses
system.cpu.dcache.overall_hits 34679457 # number of overall hits
system.cpu.dcache.overall_miss_latency 5018358000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses
system.cpu.dcache.overall_misses 210558 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 2570002000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 204343 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 4597242000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 210558 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 200247 # number of replacements
system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4081.697925 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4080.920336 # Cycle average of tags in use
system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 661090000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.warmup_cycle 737102000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 147714 # number of writebacks
system.cpu.icache.ReadReq_accesses 88340675 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 12197.393898 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11197.393898 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 14131.456382 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12131.456382 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 88264239 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 932320000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 1080152000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000865 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 855884000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 927280000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000865 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 88340675 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 12197.393898 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11197.393898 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 14131.456382 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12131.456382 # average overall mshr miss latency
system.cpu.icache.demand_hits 88264239 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 932320000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 1080152000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000865 # miss rate for demand accesses
system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 855884000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 927280000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000865 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 88340675 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 12197.393898 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11197.393898 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 14131.456382 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12131.456382 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 88264239 # number of overall hits
system.cpu.icache.overall_miss_latency 932320000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 1080152000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000865 # miss rate for overall accesses
system.cpu.icache.overall_misses 76436 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 855884000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 927280000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000865 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -138,61 +138,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 74391 # number of replacements
system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1878.885583 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1876.903920 # Cycle average of tags in use
system.cpu.icache.total_refs 88264239 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 280779 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 12999.768790 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.768790 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 112101 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 2192775000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.600750 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 168678 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1855419000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.600750 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 168678 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 3158716000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1579358000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 137201 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 89695 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1045132000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.346251 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 47506 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 522566000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.346251 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 47506 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 21989.380531 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 136664000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 68365000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 147276 # number of Writeback hits
system.cpu.l2cache.Writeback_miss_rate 0.002965 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 438 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 0.002965 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 438 # number of Writeback MSHR misses
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 147714 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 147714 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 1.537705 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 2.294067 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 12999.768790 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.768790 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 112101 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 2192775000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.600750 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 168678 # number of demand (read+write) misses
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 89695 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 4203848000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.680549 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 191084 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 1855419000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.600750 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 168678 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 2101924000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.680549 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 191084 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 428493 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 12966.100192 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.768790 # average overall mshr miss latency
system.cpu.l2cache.overall_accesses 280779 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 259377 # number of overall hits
system.cpu.l2cache.overall_miss_latency 2192775000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.394676 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 169116 # number of overall misses
system.cpu.l2cache.overall_hits 89695 # number of overall hits
system.cpu.l2cache.overall_miss_latency 4203848000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.680549 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 191084 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 1855419000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.393654 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 168678 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 2101924000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.680549 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 191084 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -204,15 +221,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 135910 # number of replacements
system.cpu.l2cache.sampled_refs 168678 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 24953 # number of replacements
system.cpu.l2cache.sampled_refs 40841 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 31979.717205 # Cycle average of tags in use
system.cpu.l2cache.total_refs 259377 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 61925078000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 115911 # number of writebacks
system.cpu.l2cache.tagsinuse 4393.051484 # Cycle average of tags in use
system.cpu.l2cache.total_refs 93692 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 126656575000 # number of cpu cycles simulated
system.cpu.numCycles 129042205000 # number of cpu cycles simulated
system.cpu.num_insts 88340674 # Number of instructions executed
system.cpu.num_refs 35224019 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls

2
tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.msg
View file

@ -134,7 +134,7 @@
DB Handle Chunk's StackPtr = 20797
DB[ 1] LOADED; Handles= 20797
KERNEL in CORE[ 1] Restored @ 40054800
KERNEL in CORE[ 1] Restored @ 4005c800
OPEN File ./input/lendian.wnv
*Status = 0

38
tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus workload
children=dcache icache l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
@ -24,27 +24,28 @@ max_loads_any_thread=0
phase=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -52,12 +53,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -68,21 +67,21 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -90,12 +89,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -106,21 +103,21 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -128,12 +125,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -151,6 +146,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex bendian.raw
@ -174,7 +172,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory

227
tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt
View file

@ -1,43 +1,43 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 480067 # Simulator instruction rate (inst/s)
host_mem_usage 157016 # Number of bytes of host memory used
host_seconds 283.81 # Real time elapsed on the host
host_tick_rate 698858124 # Simulator tick rate (ticks/s)
host_inst_rate 1128502 # Simulator instruction rate (inst/s)
host_mem_usage 210664 # Number of bytes of host memory used
host_seconds 120.73 # Real time elapsed on the host
host_tick_rate 1658768570 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 136246936 # Number of instructions simulated
sim_seconds 0.198342 # Number of seconds simulated
sim_ticks 198341876000 # Number of ticks simulated
sim_seconds 0.200268 # Number of seconds simulated
sim_ticks 200267857000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 13005.210051 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12005.210051 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 21199.169030 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19199.169030 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 37185812 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 591594000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 964329000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 45489 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 546105000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 873351000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 45489 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 12800 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 11800 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 15901 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 192000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.000942 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 15 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 177000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.000942 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 15 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 15876 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 1000000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.002513 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 920000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.002513 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 13928.024036 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12928.024036 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 20759130 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 1464866000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.005041 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 105174 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 1359692000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005041 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 105174 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 20754892 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 2735300000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.005244 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 109412 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 2516476000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005244 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 109412 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks.
@ -47,31 +47,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 13649.402972 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12649.402972 # average overall mshr miss latency
system.cpu.dcache.demand_hits 57944942 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 2056460000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002593 # miss rate for demand accesses
system.cpu.dcache.demand_misses 150663 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 23883.829026 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 21883.829026 # average overall mshr miss latency
system.cpu.dcache.demand_hits 57940704 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 3699629000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002666 # miss rate for demand accesses
system.cpu.dcache.demand_misses 154901 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 1905797000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002593 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 150663 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 3389827000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002666 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 154901 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 13649.402972 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12649.402972 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 23883.829026 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 21883.829026 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 57944942 # number of overall hits
system.cpu.dcache.overall_miss_latency 2056460000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002593 # miss rate for overall accesses
system.cpu.dcache.overall_misses 150663 # number of overall misses
system.cpu.dcache.overall_hits 57940704 # number of overall hits
system.cpu.dcache.overall_miss_latency 3699629000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002666 # miss rate for overall accesses
system.cpu.dcache.overall_misses 154901 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 1905797000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002593 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 150663 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 3389827000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002666 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 154901 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 146582 # number of replacements
system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4089.719370 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4089.106244 # Cycle average of tags in use
system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 500116000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.warmup_cycle 584597000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 107279 # number of writebacks
system.cpu.icache.ReadReq_accesses 136246937 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 12107.905937 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11107.905937 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 13638.549063 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.549063 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 136059913 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 2264469000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 2550736000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.001373 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 2077445000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 2176688000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.001373 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 136246937 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 12107.905937 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11107.905937 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 13638.549063 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11638.549063 # average overall mshr miss latency
system.cpu.icache.demand_hits 136059913 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 2264469000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 2550736000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.001373 # miss rate for demand accesses
system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 2077445000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 2176688000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.001373 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 136246937 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 12107.905937 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11107.905937 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 13638.549063 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11638.549063 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 136059913 # number of overall hits
system.cpu.icache.overall_miss_latency 2264469000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 2550736000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.001373 # miss rate for overall accesses
system.cpu.icache.overall_misses 187024 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 2077445000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 2176688000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.001373 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -148,61 +148,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 184976 # number of replacements
system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 2007.901723 # Cycle average of tags in use
system.cpu.icache.tagsinuse 2006.859894 # Cycle average of tags in use
system.cpu.icache.total_refs 136059913 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 141263674000 # Cycle when the warmup percentage was hit.
system.cpu.icache.warmup_cycle 142624255000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 337636 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 12999.502521 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.502521 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 202957 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1750760000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.398888 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 134679 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1481402000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.398888 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 134679 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_accesses 105189 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 2314158000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 105189 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1157079000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 105189 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 232513 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 191480 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 902726000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.176476 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 41033 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 451363000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.176476 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 41033 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 4263 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 21963.875205 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 93632000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 4263 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 46893000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 4263 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 107279 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 106771 # number of Writeback hits
system.cpu.l2cache.Writeback_miss_rate 0.004735 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 508 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 0.004735 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 508 # number of Writeback MSHR misses
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 107279 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 107279 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 2.299750 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 5.315911 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 337636 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 12999.502521 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.502521 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 202957 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 1750760000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.398888 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 134679 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 191480 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 3216884000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.432991 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 146222 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 1481402000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.398888 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 134679 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 1608442000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.432991 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 146222 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 444915 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 12950.653539 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.502521 # average overall mshr miss latency
system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 309728 # number of overall hits
system.cpu.l2cache.overall_miss_latency 1750760000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.303849 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 135187 # number of overall misses
system.cpu.l2cache.overall_hits 191480 # number of overall hits
system.cpu.l2cache.overall_miss_latency 3216884000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.432991 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 146222 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 1481402000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.302707 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 134679 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 1608442000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.432991 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 146222 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -214,15 +231,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 101911 # number of replacements
system.cpu.l2cache.sampled_refs 134679 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 22010 # number of replacements
system.cpu.l2cache.sampled_refs 36485 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 32127.015431 # Cycle average of tags in use
system.cpu.l2cache.total_refs 309728 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 41711518000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 82918 # number of writebacks
system.cpu.l2cache.tagsinuse 6146.860431 # Cycle average of tags in use
system.cpu.l2cache.total_refs 193951 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 198341876000 # number of cpu cycles simulated
system.cpu.numCycles 200267857000 # number of cpu cycles simulated
system.cpu.num_insts 136246936 # Number of instructions executed
system.cpu.num_refs 58111522 # Number of memory references
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls

8
tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 15 2007 13:02:31
M5 started Tue May 15 16:44:06 2007
M5 executing on zizzer.eecs.umich.edu
M5 compiled Aug 12 2007 12:23:15
M5 started Sun Aug 12 16:52:13 2007
M5 executing on zeep
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 198341876000 because target called exit()
Exiting @ tick 200267857000 because target called exit()

38
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus workload
children=dcache icache l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
@ -24,27 +24,28 @@ max_loads_any_thread=0
phase=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -52,12 +53,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -68,21 +67,21 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -90,12 +89,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -106,21 +103,21 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -128,12 +125,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -151,6 +146,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
@ -174,7 +172,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory

205
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 637714 # Simulator instruction rate (inst/s)
host_mem_usage 154060 # Number of bytes of host memory used
host_seconds 2853.60 # Real time elapsed on the host
host_tick_rate 886477792 # Simulator tick rate (ticks/s)
host_inst_rate 1593285 # Simulator instruction rate (inst/s)
host_mem_usage 199472 # Number of bytes of host memory used
host_seconds 1142.16 # Real time elapsed on the host
host_tick_rate 2268225007 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1819780129 # Number of instructions simulated
sim_seconds 2.529655 # Number of seconds simulated
sim_ticks 2529654621000 # Number of ticks simulated
sim_seconds 2.590667 # Number of seconds simulated
sim_ticks 2590666806000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 12378.042992 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11378.042992 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 16451.345769 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 14451.345769 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 89399351000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 118818430000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 82176937000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 104373602000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 12836.520018 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11836.520018 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 24252294000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 22362974000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 158480700 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 56195050000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.013985 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 2247802 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 51699446000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.013985 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 2247802 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
@ -37,31 +37,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 12473.108302 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 11473.108302 # average overall mshr miss latency
system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 113651645000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses
system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 18480.410584 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 16480.410584 # average overall mshr miss latency
system.cpu.dcache.demand_hits 595853949 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 175013480000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.015645 # miss rate for demand accesses
system.cpu.dcache.demand_misses 9470216 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 104539911000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 156073048000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.015645 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 9470216 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 12473.108302 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 11473.108302 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 18480.410584 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 16480.410584 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 596212431 # number of overall hits
system.cpu.dcache.overall_miss_latency 113651645000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses
system.cpu.dcache.overall_misses 9111734 # number of overall misses
system.cpu.dcache.overall_hits 595853949 # number of overall hits
system.cpu.dcache.overall_miss_latency 175013480000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.015645 # miss rate for overall accesses
system.cpu.dcache.overall_misses 9470216 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 104539911000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 156073048000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.015645 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 9470216 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 9107638 # number of replacements
system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4078.970916 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4079.283777 # Cycle average of tags in use
system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 40631938000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.warmup_cycle 40727264000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2244708 # number of writebacks
system.cpu.icache.ReadReq_accesses 1819780130 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 13987.531172 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12987.531172 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1819779328 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 11218000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 20050000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 10416000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 18446000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1819780130 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 13987.531172 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12987.531172 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.icache.demand_hits 1819779328 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 11218000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 20050000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
system.cpu.icache.demand_misses 802 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 10416000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 18446000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 1819780130 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 13987.531172 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12987.531172 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1819779328 # number of overall hits
system.cpu.icache.overall_miss_latency 11218000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 20050000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
system.cpu.icache.overall_misses 802 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 10416000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 18446000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -138,61 +138,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 611.364745 # Cycle average of tags in use
system.cpu.icache.tagsinuse 611.417495 # Cycle average of tags in use
system.cpu.icache.total_refs 1819779328 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 9112536 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 12996.354425 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10996.354425 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 6952383 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 28074114000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.237053 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 2160153 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 23753808000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.237053 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 2160153 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 41565040000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1889320 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 20782520000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1889320 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 5145160 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 45717232000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.287691 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 2078056 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 22858616000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.287691 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 2078056 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 358482 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 21999.018082 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 7886252000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 358482 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3943302000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 358482 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 2215611 # number of Writeback hits
system.cpu.l2cache.Writeback_miss_rate 0.012962 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 29097 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 0.012962 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 29097 # number of Writeback MSHR misses
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 2244708 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 2244708 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 4.244141 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 4.187898 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 12996.354425 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 10996.354425 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 6952383 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 28074114000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.237053 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 2160153 # number of demand (read+write) misses
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 5145160 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 87282272000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.435376 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 3967376 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 23753808000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.237053 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 2160153 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 43641136000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.435376 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 3967376 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 11357244 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 12823.621788 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 10996.354425 # average overall mshr miss latency
system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 9167994 # number of overall hits
system.cpu.l2cache.overall_miss_latency 28074114000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.192762 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 2189250 # number of overall misses
system.cpu.l2cache.overall_hits 5145160 # number of overall hits
system.cpu.l2cache.overall_miss_latency 87282272000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.435376 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 3967376 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 23753808000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.190200 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 2160153 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 43641136000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.435376 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 3967376 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -204,15 +221,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 2127385 # number of replacements
system.cpu.l2cache.sampled_refs 2160153 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 1367767 # number of replacements
system.cpu.l2cache.sampled_refs 1390767 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 31194.155037 # Cycle average of tags in use
system.cpu.l2cache.total_refs 9167994 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 245730069000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 1038202 # number of writebacks
system.cpu.l2cache.tagsinuse 18546.386002 # Cycle average of tags in use
system.cpu.l2cache.total_refs 5824390 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 2030116907000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 2529654621000 # number of cpu cycles simulated
system.cpu.numCycles 2590666806000 # number of cpu cycles simulated
system.cpu.num_insts 1819780129 # Number of instructions executed
system.cpu.num_refs 606571345 # Number of memory references
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls

72
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=DerivO3CPU
children=dcache fuPool icache l2cache toL2Bus workload
children=dcache fuPool icache l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -21,6 +21,7 @@ SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
choiceCtrBits=2
choicePredictorSize=8192
clock=500
@ -74,8 +75,18 @@ renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
@ -85,21 +96,21 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -107,12 +118,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -128,11 +137,11 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList0
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList0
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList0]
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
@ -206,11 +215,11 @@ opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList0
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList0]
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
@ -218,11 +227,11 @@ opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList0
children=opList
count=0
opList=system.cpu.fuPool.FUList5.opList0
opList=system.cpu.fuPool.FUList5.opList
[system.cpu.fuPool.FUList5.opList0]
[system.cpu.fuPool.FUList5.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
@ -248,11 +257,11 @@ opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0
children=opList
count=1
opList=system.cpu.fuPool.FUList7.opList0
opList=system.cpu.fuPool.FUList7.opList
[system.cpu.fuPool.FUList7.opList0]
[system.cpu.fuPool.FUList7.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
@ -260,21 +269,21 @@ opLat=3
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -282,12 +291,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -298,21 +305,21 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -320,12 +327,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -343,6 +348,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
@ -366,7 +374,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory

581
tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 11874522 # Number of BTB hits
global.BPredUnit.BTBLookups 15445749 # Number of BTB lookups
global.BPredUnit.RASInCorrect 1158 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 1931947 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 13190559 # Number of conditional branches predicted
global.BPredUnit.lookups 17824174 # Number of BP lookups
global.BPredUnit.usedRAS 1655464 # Number of times the RAS was used to get a target.
host_inst_rate 74830 # Simulator instruction rate (inst/s)
host_mem_usage 156844 # Number of bytes of host memory used
host_seconds 1124.95 # Real time elapsed on the host
host_tick_rate 39347975 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 14674251 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 4294265 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 31675298 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 10012759 # Number of stores inserted to the mem dependence unit.
global.BPredUnit.BTBHits 13022932 # Number of BTB hits
global.BPredUnit.BTBLookups 16938031 # Number of BTB lookups
global.BPredUnit.RASInCorrect 1193 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 1944645 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 14588431 # Number of conditional branches predicted
global.BPredUnit.lookups 19441115 # Number of BP lookups
global.BPredUnit.usedRAS 1715741 # Number of times the RAS was used to get a target.
host_inst_rate 140839 # Simulator instruction rate (inst/s)
host_mem_usage 205524 # Number of bytes of host memory used
host_seconds 597.70 # Real time elapsed on the host
host_tick_rate 68085854 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 17320747 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 5158870 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 33916617 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 10592327 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 84179709 # Number of instructions simulated
sim_seconds 0.044264 # Number of seconds simulated
sim_ticks 44264420500 # Number of ticks simulated
sim_seconds 0.040695 # Number of seconds simulated
sim_ticks 40694900000 # Number of ticks simulated
system.cpu.commit.COM:branches 10240685 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 2948022 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 2814383 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 81602250
system.cpu.commit.COM:committed_per_cycle.samples 73372540
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 44887304 5500.74%
1 17052684 2089.73%
2 8186225 1003.19%
3 3991011 489.08%
4 1764745 216.26%
5 1325913 162.48%
6 892255 109.34%
7 554091 67.90%
8 2948022 361.27%
0 36054158 4913.85%
1 18224800 2483.87%
2 7501822 1022.43%
3 3901009 531.67%
4 2128189 290.05%
5 1274528 173.71%
6 744433 101.46%
7 729218 99.39%
8 2814383 383.57%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@ -43,70 +43,72 @@ system.cpu.commit.COM:loads 20034413 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 26537108 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 1919652 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 1932230 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 46410426 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 55717434 # The number of squashed insts skipped by commit
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
system.cpu.cpi 1.051666 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.051666 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 23047695 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 5314.424635 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4545.725646 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 23047078 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 3279000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 617 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 114 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 2286500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 503 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 3836.081210 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4946.808511 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 6493764 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 28153000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.001129 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 7339 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 5600 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 8602500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1739 # number of WriteReq MSHR misses
system.cpu.cpi 0.966851 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.966851 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 23356209 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 9066 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5569 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 23355709 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 4533000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000021 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 500 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 123 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 2784500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 500 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6495002 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 24564.959569 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5850.134771 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 6493147 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 45568000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1855 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 6101 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 10852000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1855 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 13176.111508 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 13325.436607 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 29548798 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 3950.729010 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 4856.824264 # average overall mshr miss latency
system.cpu.dcache.demand_hits 29540842 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 31432000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000269 # miss rate for demand accesses
system.cpu.dcache.demand_misses 7956 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 5714 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 10889000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000076 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2242 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 29851211 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 21274.309979 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 5790.445860 # average overall mshr miss latency
system.cpu.dcache.demand_hits 29848856 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 50101000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2355 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 6224 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 13636500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2355 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 29548798 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 3950.729010 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 4856.824264 # average overall mshr miss latency
system.cpu.dcache.overall_accesses 29851211 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 21274.309979 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 5790.445860 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 29540842 # number of overall hits
system.cpu.dcache.overall_miss_latency 31432000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000269 # miss rate for overall accesses
system.cpu.dcache.overall_misses 7956 # number of overall misses
system.cpu.dcache.overall_mshr_hits 5714 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 10889000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000076 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2242 # number of overall MSHR misses
system.cpu.dcache.overall_hits 29848856 # number of overall hits
system.cpu.dcache.overall_miss_latency 50101000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2355 # number of overall misses
system.cpu.dcache.overall_mshr_hits 6224 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 13636500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2355 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -118,92 +120,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 163 # number of replacements
system.cpu.dcache.sampled_refs 2242 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 160 # number of replacements
system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 1457.683096 # Cycle average of tags in use
system.cpu.dcache.total_refs 29540842 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 1458.130010 # Cycle average of tags in use
system.cpu.dcache.total_refs 29848978 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 107 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 2294607 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 12777 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 2890400 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 151561971 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 53136009 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 26139582 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 6926673 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 40541 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 32053 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 17824174 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 18016265 # Number of cache lines fetched
system.cpu.fetch.Cycles 44691424 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 975254 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 154588435 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 2011658 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.201337 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 18016265 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 13529986 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.746191 # Number of inst fetches per cycle
system.cpu.dcache.writebacks 106 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 3820626 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 12575 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 3037417 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 162462210 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 39463165 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 29936850 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 8016661 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 44953 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 151900 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 19441115 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 19217268 # Number of cache lines fetched
system.cpu.fetch.Cycles 50163624 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 510483 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 167309935 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 2078673 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.238866 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 19217268 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 14738673 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.055677 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 88528924
system.cpu.fetch.rateDist.samples 81389202
system.cpu.fetch.rateDist.min_value 0
0 61853767 6986.84%
1 2838595 320.64%
2 1299355 146.77%
3 1865057 210.67%
4 3537974 399.64%
5 1231942 139.16%
6 1400771 158.23%
7 1171977 132.38%
8 13329486 1505.66%
0 50442849 6197.73%
1 3127409 384.25%
2 2013333 247.37%
3 3501649 430.24%
4 4585592 563.42%
5 1499931 184.29%
6 2042041 250.90%
7 1854540 227.86%
8 12321858 1513.94%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 18016265 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 3877.692156 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2918.898279 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 18006143 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 39250000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000562 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 10122 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 301 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 28666500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000545 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 9821 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_accesses 19216915 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 5291.898608 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3156.958250 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 19206855 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 53236500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000523 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 10060 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 353 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 31759000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000523 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 10060 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 1833.432746 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 1909.230119 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 18016265 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 3877.692156 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 2918.898279 # average overall mshr miss latency
system.cpu.icache.demand_hits 18006143 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 39250000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000562 # miss rate for demand accesses
system.cpu.icache.demand_misses 10122 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 28666500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000545 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 9821 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_accesses 19216915 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 5291.898608 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 3156.958250 # average overall mshr miss latency
system.cpu.icache.demand_hits 19206855 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 53236500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000523 # miss rate for demand accesses
system.cpu.icache.demand_misses 10060 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 353 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 31759000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000523 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 10060 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 18016265 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 3877.692156 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2918.898279 # average overall mshr miss latency
system.cpu.icache.overall_accesses 19216915 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 5291.898608 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 3156.958250 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 18006143 # number of overall hits
system.cpu.icache.overall_miss_latency 39250000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000562 # miss rate for overall accesses
system.cpu.icache.overall_misses 10122 # number of overall misses
system.cpu.icache.overall_mshr_hits 301 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 28666500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000545 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 9821 # number of overall MSHR misses
system.cpu.icache.overall_hits 19206855 # number of overall hits
system.cpu.icache.overall_miss_latency 53236500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000523 # miss rate for overall accesses
system.cpu.icache.overall_misses 10060 # number of overall misses
system.cpu.icache.overall_mshr_hits 353 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 31759000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000523 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 10060 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -215,162 +217,183 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 7904 # number of replacements
system.cpu.icache.sampled_refs 9821 # Sample count of references to valid blocks.
system.cpu.icache.replacements 8146 # number of replacements
system.cpu.icache.sampled_refs 10060 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1549.418815 # Cycle average of tags in use
system.cpu.icache.total_refs 18006143 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1551.624399 # Cycle average of tags in use
system.cpu.icache.total_refs 19206855 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 7902 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 12543861 # Number of branches executed
system.cpu.iew.EXEC:nop 11949352 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.130385 # Inst execution rate
system.cpu.iew.EXEC:refs 31528912 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 7145648 # Number of stores executed
system.cpu.idleCycles 435727 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 12761226 # Number of branches executed
system.cpu.iew.EXEC:nop 12552336 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.247935 # Inst execution rate
system.cpu.iew.EXEC:refs 31899012 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 7188094 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 87529341 # num instructions consuming a value
system.cpu.iew.WB:count 98214425 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.729574 # average fanout of values written-back
system.cpu.iew.WB:consumers 90808493 # num instructions consuming a value
system.cpu.iew.WB:count 99646578 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.722903 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 63859133 # num instructions producing a value
system.cpu.iew.WB:rate 1.109405 # insts written-back per cycle
system.cpu.iew.WB:sent 99107976 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 2078247 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 190251 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 31675298 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 411 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 2578287 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 10012759 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 138313092 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 24383264 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1412890 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 100071797 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 38223 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 65645732 # num instructions producing a value
system.cpu.iew.WB:rate 1.224322 # insts written-back per cycle
system.cpu.iew.WB:sent 100573545 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 2105709 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 285403 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 33916617 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 429 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 1714541 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 10592327 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 147619094 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 24710918 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2203361 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 101568426 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 132795 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 20 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 6926673 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 64568 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 9 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 8016661 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 165683 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 828690 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 779 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.forwLoads 838013 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 1487 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 84249 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 9673 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 11640885 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 3510064 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 84249 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 193948 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 1884299 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.950872 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.950872 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 101484687 # Type of FU issued
system.cpu.iew.lsq.thread.0.memOrderViolation 249026 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 9801 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 13882204 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 4089632 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 249026 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 202527 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 1903182 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.034286 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.034286 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 103771787 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 7 0.00% # Type of FU issued
IntAlu 62609480 61.69% # Type of FU issued
IntMult 467679 0.46% # Type of FU issued
No_OpClass 7 0.00% # Type of FU issued
IntAlu 64228940 61.89% # Type of FU issued
IntMult 473017 0.46% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 2780950 2.74% # Type of FU issued
FloatCmp 115557 0.11% # Type of FU issued
FloatCvt 2364134 2.33% # Type of FU issued
FloatMult 305451 0.30% # Type of FU issued
FloatDiv 755050 0.74% # Type of FU issued
FloatSqrt 320 0.00% # Type of FU issued
MemRead 24826231 24.46% # Type of FU issued
MemWrite 7259828 7.15% # Type of FU issued
FloatAdd 2790055 2.69% # Type of FU issued
FloatCmp 115633 0.11% # Type of FU issued
FloatCvt 2376207 2.29% # Type of FU issued
FloatMult 305676 0.29% # Type of FU issued
FloatDiv 755062 0.73% # Type of FU issued
FloatSqrt 323 0.00% # Type of FU issued
MemRead 25409003 24.49% # Type of FU issued
MemWrite 7317864 7.05% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 1739512 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.017141 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_busy_cnt 1978136 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.019062 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
IntAlu 236478 13.59% # attempts to use FU when none available
No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 311313 15.74% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 1 0.00% # attempts to use FU when none available
FloatAdd 546 0.03% # attempts to use FU when none available
FloatCmp 0 0.00% # attempts to use FU when none available
FloatCvt 223 0.01% # attempts to use FU when none available
FloatMult 1629 0.09% # attempts to use FU when none available
FloatDiv 705159 40.54% # attempts to use FU when none available
FloatCvt 3483 0.18% # attempts to use FU when none available
FloatMult 2460 0.12% # attempts to use FU when none available
FloatDiv 833660 42.14% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 710061 40.82% # attempts to use FU when none available
MemWrite 85961 4.94% # attempts to use FU when none available
MemRead 753551 38.09% # attempts to use FU when none available
MemWrite 73123 3.70% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 88528924
system.cpu.iq.ISSUE:issued_per_cycle.samples 81389202
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 43673541 4933.25%
1 18286123 2065.55%
2 11155754 1260.13%
3 6962814 786.50%
4 4628513 522.82%
5 2073707 234.24%
6 1255435 141.81%
7 360879 40.76%
8 132158 14.93%
0 35308856 4338.27%
1 18677963 2294.89%
2 11652538 1431.71%
3 6999702 860.03%
4 4887440 600.50%
5 2229546 273.94%
6 1377818 169.29%
7 217468 26.72%
8 37871 4.65%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 1.146345 # Inst issue rate
system.cpu.iq.iqInstsAdded 126363329 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 101484687 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 411 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 41115515 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 151595 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 22 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 37587907 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 12063 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4597.386006 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2450.176887 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 6975 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 23391500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.421786 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 5088 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 12466500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.421786 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 5088 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits
system.cpu.iq.ISSUE:rate 1.275007 # Inst issue rate
system.cpu.iq.iqInstsAdded 135066329 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 103771787 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 429 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 50270340 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 231965 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 47066497 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 1741 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 4485.353245 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2485.353245 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 7809000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1741 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4327000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1741 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 10559 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4274.193548 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2274.193548 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 7149 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 14575000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.322947 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 3410 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 7755000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.322947 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3410 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 118 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4500 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2500 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 531000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 118 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 295000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 118 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 106 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 106 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 1.391903 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 2.172948 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 12063 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4597.386006 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2450.176887 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 6975 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 23391500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.421786 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 5088 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 12300 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4345.563968 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2345.563968 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 7149 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 22384000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.418780 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 5151 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 12466500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.421786 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 5088 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 12082000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.418780 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 5151 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 12170 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4597.386006 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2450.176887 # average overall mshr miss latency
system.cpu.l2cache.overall_accesses 12300 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4345.563968 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2345.563968 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 7082 # number of overall hits
system.cpu.l2cache.overall_miss_latency 23391500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.418077 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 5088 # number of overall misses
system.cpu.l2cache.overall_hits 7149 # number of overall hits
system.cpu.l2cache.overall_miss_latency 22384000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.418780 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 5151 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 12466500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.418077 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 5088 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 12082000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.418780 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 5151 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -383,30 +406,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 5088 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 3290 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 3405.740601 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7082 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 2252.890734 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7149 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 88528924 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 1217757 # Number of cycles rename is blocking
system.cpu.numCycles 81389202 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 1683934 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 511469 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 54000366 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 581686 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 190129267 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 147303303 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 108348051 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 25314451 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 6926673 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 1065045 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 39920690 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 4632 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 447 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 2624388 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 437 # count of temporary serializing insts renamed
system.cpu.timesIdled 98 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:IQFullEvents 1032549 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 40751116 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 970163 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 202965992 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 157380306 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 115963922 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 28805465 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 8016661 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 2127274 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 47536561 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 4752 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 464 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 4689522 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 453 # count of temporary serializing insts renamed
system.cpu.timesIdled 283 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
---------- End Simulation Statistics ----------

38
tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus workload
children=dcache icache l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
@ -24,27 +24,28 @@ max_loads_any_thread=0
phase=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -52,12 +53,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -68,21 +67,21 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -90,12 +89,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -106,21 +103,21 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -128,12 +125,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -151,6 +146,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
@ -174,7 +172,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory

187
tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 651405 # Simulator instruction rate (inst/s)
host_mem_usage 156232 # Number of bytes of host memory used
host_seconds 141.08 # Real time elapsed on the host
host_tick_rate 840119018 # Simulator tick rate (ticks/s)
host_inst_rate 1713530 # Simulator instruction rate (inst/s)
host_mem_usage 204416 # Number of bytes of host memory used
host_seconds 53.63 # Real time elapsed on the host
host_tick_rate 2211088665 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903057 # Number of instructions simulated
sim_seconds 0.118528 # Number of seconds simulated
sim_ticks 118527938000 # Number of ticks simulated
sim_seconds 0.118590 # Number of seconds simulated
sim_ticks 118589598000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 13776.371308 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12776.371308 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 24316.455696 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22316.455696 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 6530000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 11526000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 6056000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 10578000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 13970.251716 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12970.251716 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 24420000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 22672000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 46475000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 42757000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 11923.977948 # Average number of references to valid blocks.
@ -37,31 +37,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 13928.892889 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12928.892889 # average overall mshr miss latency
system.cpu.dcache.demand_hits 26495079 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 30950000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2222 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 24861.123018 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 22861.123018 # average overall mshr miss latency
system.cpu.dcache.demand_hits 26494968 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 58001000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2333 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 28728000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2222 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 53335000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2333 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 13928.892889 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12928.892889 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 24861.123018 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 22861.123018 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 26495079 # number of overall hits
system.cpu.dcache.overall_miss_latency 30950000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2222 # number of overall misses
system.cpu.dcache.overall_hits 26494968 # number of overall hits
system.cpu.dcache.overall_miss_latency 58001000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2333 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 28728000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2222 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 53335000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2333 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 157 # number of replacements
system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 1441.614290 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 1441.457790 # Cycle average of tags in use
system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 104 # number of writebacks
system.cpu.icache.ReadReq_accesses 91903058 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 12615.981199 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11615.981199 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 16695.887192 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 14695.887192 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 91894548 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 107362000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 142082000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 98852000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 125062000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 91903058 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 12615.981199 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11615.981199 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 16695.887192 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 14695.887192 # average overall mshr miss latency
system.cpu.icache.demand_hits 91894548 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 107362000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 142082000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses
system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 98852000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 125062000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 91903058 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 12615.981199 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11615.981199 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 16695.887192 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 14695.887192 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 91894548 # number of overall hits
system.cpu.icache.overall_miss_latency 107362000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 142082000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses
system.cpu.icache.overall_misses 8510 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 98852000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 125062000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -138,57 +138,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 6681 # number of replacements
system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1418.637331 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1418.474486 # Cycle average of tags in use
system.cpu.icache.total_refs 91894548 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 10732 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 38456000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 19228000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 8984 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 5968 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 61932000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.443906 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 4764 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 52404000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.443906 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 4764 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_hits 5916 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 67496000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.341496 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 3068 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 33748000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.341496 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3068 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 2442000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1221000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 111 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 104 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 104 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 1.274559 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 2.002030 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 61932000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.443906 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 4764 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 5916 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 105952000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.448751 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 4816 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 52404000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.443906 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 4764 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 52976000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.448751 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 4816 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 10836 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.overall_accesses 10732 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 6072 # number of overall hits
system.cpu.l2cache.overall_miss_latency 61932000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.439646 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 4764 # number of overall misses
system.cpu.l2cache.overall_hits 5916 # number of overall hits
system.cpu.l2cache.overall_miss_latency 105952000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.448751 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 4816 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 52404000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.439646 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 4764 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 52976000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.448751 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 4816 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -201,14 +222,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 4764 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 2955 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 3172.809799 # Cycle average of tags in use
system.cpu.l2cache.total_refs 6072 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 2014.752255 # Cycle average of tags in use
system.cpu.l2cache.total_refs 5916 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 118527938000 # number of cpu cycles simulated
system.cpu.numCycles 118589598000 # number of cpu cycles simulated
system.cpu.num_insts 91903057 # Number of instructions executed
system.cpu.num_refs 26537109 # Number of memory references
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls

38
tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus workload
children=dcache icache l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
@ -24,27 +24,28 @@ max_loads_any_thread=0
phase=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -52,12 +53,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -68,21 +67,21 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -90,12 +89,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -106,21 +103,21 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -128,12 +125,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -151,6 +146,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
@ -174,7 +172,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory

199
tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt
View file

@ -1,43 +1,43 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 500598 # Simulator instruction rate (inst/s)
host_mem_usage 156000 # Number of bytes of host memory used
host_seconds 386.41 # Real time elapsed on the host
host_tick_rate 699597163 # Simulator tick rate (ticks/s)
host_inst_rate 1154889 # Simulator instruction rate (inst/s)
host_mem_usage 206344 # Number of bytes of host memory used
host_seconds 167.49 # Real time elapsed on the host
host_tick_rate 1614378740 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 193435973 # Number of instructions simulated
sim_seconds 0.270332 # Number of seconds simulated
sim_ticks 270331639000 # Number of ticks simulated
sim_seconds 0.270398 # Number of seconds simulated
sim_ticks 270397855000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 57734138 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 57733640 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 6972000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 12450000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 6474000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 11454000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 14000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 13000 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 22405 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 14000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.000045 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 1 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 13000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.000045 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 1 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 22404 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 50000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.000089 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 2 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 46000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.000089 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 2 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 18976414 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 13987.108656 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12987.108656 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 18975328 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 15190000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000057 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1086 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 14104000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000057 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1086 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 18975304 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 27750000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000058 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1110 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 25530000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000058 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1110 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 48410.960883 # Average number of references to valid blocks.
@ -47,31 +47,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 76710552 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 13991.161616 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12991.161616 # average overall mshr miss latency
system.cpu.dcache.demand_hits 76708968 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 22162000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_avg_miss_latency 25000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.dcache.demand_hits 76708944 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 40200000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1584 # number of demand (read+write) misses
system.cpu.dcache.demand_misses 1608 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 20578000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 36984000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1584 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses 1608 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 76710552 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 13991.161616 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12991.161616 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 25000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 76708968 # number of overall hits
system.cpu.dcache.overall_miss_latency 22162000 # number of overall miss cycles
system.cpu.dcache.overall_hits 76708944 # number of overall hits
system.cpu.dcache.overall_miss_latency 40200000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1584 # number of overall misses
system.cpu.dcache.overall_misses 1608 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 20578000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 36984000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1584 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses 1608 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 26 # number of replacements
system.cpu.dcache.sampled_refs 1585 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 1237.473868 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 1237.402461 # Cycle average of tags in use
system.cpu.dcache.total_refs 76731373 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 23 # number of writebacks
system.cpu.icache.ReadReq_accesses 193435974 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 12584.365830 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11584.365830 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 16510.596674 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 14510.596674 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 193423706 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 154385000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 202552000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 12268 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 142117000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 178016000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000063 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 12268 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 193435974 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 12584.365830 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11584.365830 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 16510.596674 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 14510.596674 # average overall mshr miss latency
system.cpu.icache.demand_hits 193423706 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 154385000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 202552000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses
system.cpu.icache.demand_misses 12268 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 142117000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 178016000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000063 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 12268 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 193435974 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 12584.365830 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11584.365830 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 16510.596674 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 14510.596674 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 193423706 # number of overall hits
system.cpu.icache.overall_miss_latency 154385000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 202552000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses
system.cpu.icache.overall_misses 12268 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 142117000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 178016000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000063 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 12268 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -148,57 +148,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 10342 # number of replacements
system.cpu.icache.sampled_refs 12268 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1591.809550 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1591.726914 # Cycle average of tags in use
system.cpu.icache.total_refs 193423706 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 13852 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_accesses 1087 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 23914000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1087 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 11957000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1087 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 12766 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 8685 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 67171000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.373015 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 5167 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 56837000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.373015 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 5167 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_hits 8679 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 89914000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.320147 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 4087 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 44957000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320147 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 4087 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 25 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 550000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 25 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 275000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 25 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 23 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 23 # number of Writeback hits
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 23 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 23 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 1.685311 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 2.136632 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 13852 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.demand_accesses 13853 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 8685 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 67171000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.373015 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 5167 # number of demand (read+write) misses
system.cpu.l2cache.demand_hits 8679 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 113828000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.373493 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 5174 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 56837000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.373015 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 5167 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 56914000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.373493 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 5174 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 13875 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.overall_accesses 13853 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 8708 # number of overall hits
system.cpu.l2cache.overall_miss_latency 67171000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.372396 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 5167 # number of overall misses
system.cpu.l2cache.overall_hits 8679 # number of overall hits
system.cpu.l2cache.overall_miss_latency 113828000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.373493 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 5174 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 56837000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.372396 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 5167 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 56914000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.373493 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 5174 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -211,14 +232,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 5167 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 4062 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 3507.169610 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8708 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 2649.703709 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8679 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 270331639000 # number of cpu cycles simulated
system.cpu.numCycles 270397855000 # number of cpu cycles simulated
system.cpu.num_insts 193435973 # Number of instructions executed
system.cpu.num_refs 76732959 # Number of memory references
system.cpu.workload.PROG:num_syscalls 396 # Number of system calls

8
tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
View file

@ -18,11 +18,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 15 2007 13:02:31
M5 started Tue May 15 16:53:38 2007
M5 executing on zizzer.eecs.umich.edu
M5 compiled Aug 12 2007 12:23:15
M5 started Sun Aug 12 16:55:52 2007
M5 executing on zeep
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing
Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav
Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 270331639000 because target called exit()
Exiting @ tick 270397855000 because target called exit()

6
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
View file

@ -99,10 +99,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@ -270,10 +272,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@ -304,10 +308,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true

482
tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 543 # Number of BTB hits
global.BPredUnit.BTBLookups 1720 # Number of BTB lookups
global.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 423 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 1175 # Number of conditional branches predicted
global.BPredUnit.lookups 2025 # Number of BP lookups
global.BPredUnit.usedRAS 277 # Number of times the RAS was used to get a target.
host_inst_rate 29843 # Simulator instruction rate (inst/s)
host_mem_usage 154572 # Number of bytes of host memory used
host_seconds 0.19 # Real time elapsed on the host
host_tick_rate 22095832 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 31 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 133 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 1967 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 1200 # Number of stores inserted to the mem dependence unit.
global.BPredUnit.BTBHits 538 # Number of BTB hits
global.BPredUnit.BTBLookups 1681 # Number of BTB lookups
global.BPredUnit.RASInCorrect 51 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 412 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 1149 # Number of conditional branches predicted
global.BPredUnit.lookups 1984 # Number of BP lookups
global.BPredUnit.usedRAS 275 # Number of times the RAS was used to get a target.
host_inst_rate 62494 # Simulator instruction rate (inst/s)
host_mem_usage 196896 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
host_tick_rate 50069310 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 10 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 121 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 1979 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 1190 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5623 # Number of instructions simulated
sim_seconds 0.000004 # Number of seconds simulated
sim_ticks 4170500 # Number of ticks simulated
sim_seconds 0.000005 # Number of seconds simulated
sim_ticks 4515000 # Number of ticks simulated
system.cpu.commit.COM:branches 862 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 105 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 81 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 7614
system.cpu.commit.COM:committed_per_cycle.samples 8177
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 5315 6980.56%
1 1182 1552.40%
2 399 524.03%
3 192 252.17%
4 125 164.17%
5 99 130.02%
6 130 170.74%
7 67 88.00%
8 105 137.90%
0 5854 7159.10%
1 1205 1473.65%
2 403 492.85%
3 188 229.91%
4 133 162.65%
5 98 119.85%
6 110 134.52%
7 105 128.41%
8 81 99.06%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 979 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 1791 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 349 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 3957 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 4015 # The number of squashed insts skipped by commit
system.cpu.committedInsts 5623 # Number of Instructions Simulated
system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
system.cpu.cpi 1.483372 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.483372 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 1487 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 8188.118812 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5495.049505 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1386 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 827000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.067922 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 101 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 34 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 555000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.067922 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 561 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 18316.091954 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5068.965517 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 474 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 1593500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.155080 # miss rate for WriteReq accesses
system.cpu.cpi 1.584030 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.584030 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 1516 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 10550 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6350 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1416 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 1055000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.065963 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 100 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 32 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 635000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.065963 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 533 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 26660.919540 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5781.609195 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 446 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 2319500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.163227 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 251 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 441000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.155080 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_hits 279 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 503000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.163227 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 10.770115 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 10.843931 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 2048 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 12875 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 5297.872340 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1860 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 2420500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.091797 # miss rate for demand accesses
system.cpu.dcache.demand_misses 188 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 285 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 996000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.091797 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 188 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 2049 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 18045.454545 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 6085.561497 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1862 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 3374500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.091264 # miss rate for demand accesses
system.cpu.dcache.demand_misses 187 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 311 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 1138000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.091264 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 187 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 2048 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 12875 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 5297.872340 # average overall mshr miss latency
system.cpu.dcache.overall_accesses 2049 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 18045.454545 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 6085.561497 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1860 # number of overall hits
system.cpu.dcache.overall_miss_latency 2420500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.091797 # miss rate for overall accesses
system.cpu.dcache.overall_misses 188 # number of overall misses
system.cpu.dcache.overall_mshr_hits 285 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 996000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.091797 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses
system.cpu.dcache.overall_hits 1862 # number of overall hits
system.cpu.dcache.overall_miss_latency 3374500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.091264 # miss rate for overall accesses
system.cpu.dcache.overall_misses 187 # number of overall misses
system.cpu.dcache.overall_mshr_hits 311 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 1138000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.091264 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 187 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -119,90 +119,90 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks.
system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 112.600183 # Cycle average of tags in use
system.cpu.dcache.total_refs 1874 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 111.683956 # Cycle average of tags in use
system.cpu.dcache.total_refs 1876 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 391 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 82 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BlockedCycles 428 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 164 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 11387 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 5174 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 2002 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 726 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 244 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 48 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 2025 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 1529 # Number of cache lines fetched
system.cpu.fetch.Cycles 3690 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 212 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 12463 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 457 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.242777 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 1529 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 820 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.494185 # Number of inst fetches per cycle
system.cpu.decode.DECODE:DecodedInsts 11204 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 5725 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 1989 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 729 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 235 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 36 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 1984 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 1520 # Number of cache lines fetched
system.cpu.fetch.Cycles 3641 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 230 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 12195 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 444 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.222746 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 1520 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 813 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.369148 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 8341
system.cpu.fetch.rateDist.samples 8907
system.cpu.fetch.rateDist.min_value 0
0 6181 7410.38%
1 173 207.41%
2 174 208.61%
3 151 181.03%
4 219 262.56%
5 157 188.23%
6 179 214.60%
7 102 122.29%
8 1005 1204.89%
0 6787 7619.85%
1 178 199.84%
2 167 187.49%
3 149 167.28%
4 210 235.77%
5 157 176.27%
6 180 202.09%
7 101 113.39%
8 978 1098.01%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 1511 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 5621.019108 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4464.968153 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1197 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 1765000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.207809 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_accesses 1497 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 7812.101911 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5500 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1183 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 2453000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.209753 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 314 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 1402000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.207809 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_hits 23 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 1727000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.209753 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 314 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 3.812102 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 3.767516 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1511 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 5621.019108 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 4464.968153 # average overall mshr miss latency
system.cpu.icache.demand_hits 1197 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 1765000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.207809 # miss rate for demand accesses
system.cpu.icache.demand_accesses 1497 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 7812.101911 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 5500 # average overall mshr miss latency
system.cpu.icache.demand_hits 1183 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 2453000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.209753 # miss rate for demand accesses
system.cpu.icache.demand_misses 314 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 18 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 1402000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.207809 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_hits 23 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 1727000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.209753 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 314 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 1511 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 5621.019108 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 4464.968153 # average overall mshr miss latency
system.cpu.icache.overall_accesses 1497 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 7812.101911 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 5500 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1197 # number of overall hits
system.cpu.icache.overall_miss_latency 1765000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.207809 # miss rate for overall accesses
system.cpu.icache.overall_hits 1183 # number of overall hits
system.cpu.icache.overall_miss_latency 2453000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.209753 # miss rate for overall accesses
system.cpu.icache.overall_misses 314 # number of overall misses
system.cpu.icache.overall_mshr_hits 18 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 1402000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.207809 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_hits 23 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 1727000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.209753 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 314 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
@ -218,59 +218,59 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 167.838424 # Cycle average of tags in use
system.cpu.icache.total_refs 1197 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 165.376334 # Cycle average of tags in use
system.cpu.icache.total_refs 1183 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 1997 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 1159 # Number of branches executed
system.cpu.iew.EXEC:nop 43 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.933581 # Inst execution rate
system.cpu.iew.EXEC:refs 2561 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 971 # Number of stores executed
system.cpu.idleCycles 88946 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 1172 # Number of branches executed
system.cpu.iew.EXEC:nop 45 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.880207 # Inst execution rate
system.cpu.iew.EXEC:refs 2591 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 974 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 5329 # num instructions consuming a value
system.cpu.iew.WB:count 7480 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.739351 # average fanout of values written-back
system.cpu.iew.WB:consumers 5292 # num instructions consuming a value
system.cpu.iew.WB:count 7505 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.745276 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 3940 # num instructions producing a value
system.cpu.iew.WB:rate 0.896775 # insts written-back per cycle
system.cpu.iew.WB:sent 7559 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 402 # Number of branch mispredicts detected at execute
system.cpu.iew.WB:producers 3944 # num instructions producing a value
system.cpu.iew.WB:rate 0.842596 # insts written-back per cycle
system.cpu.iew.WB:sent 7591 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 401 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 1967 # Number of dispatched load instructions
system.cpu.iew.iewDispLoadInsts 1979 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 240 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 1200 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 9614 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 1590 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 364 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 7787 # Number of executed instructions
system.cpu.iew.iewDispSquashedInsts 194 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 1190 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 9672 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 1617 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 358 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 7840 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 726 # Number of cycles IEW is squashing
system.cpu.iew.iewSquashCycles 729 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 48 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.forwLoads 47 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 70 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.memOrderViolation 66 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 988 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 388 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 70 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 287 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 115 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.674140 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.674140 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 8151 # Type of FU issued
system.cpu.iew.lsq.thread.0.squashedLoads 1000 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 378 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 66 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.631301 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.631301 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 8198 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 2 0.02% # Type of FU issued
IntAlu 5422 66.52% # Type of FU issued
IntAlu 5452 66.50% # Type of FU issued
IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 2 0.02% # Type of FU issued
@ -279,13 +279,13 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 1720 21.10% # Type of FU issued
MemWrite 1004 12.32% # Type of FU issued
MemRead 1744 21.27% # Type of FU issued
MemWrite 997 12.16% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 104 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.012759 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_busy_cnt 102 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.012442 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 0 0.00% # attempts to use FU when none available
@ -297,96 +297,96 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 70 67.31% # attempts to use FU when none available
MemWrite 34 32.69% # attempts to use FU when none available
MemRead 67 65.69% # attempts to use FU when none available
MemWrite 35 34.31% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 8341
system.cpu.iq.ISSUE:issued_per_cycle.samples 8907
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 5104 6119.17%
1 1084 1299.60%
2 829 993.89%
3 533 639.01%
4 366 438.80%
5 258 309.32%
6 126 151.06%
7 28 33.57%
8 13 15.59%
0 5630 6320.87%
1 1096 1230.49%
2 792 889.19%
3 582 653.42%
4 464 520.94%
5 200 224.54%
6 99 111.15%
7 30 33.68%
8 14 15.72%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 0.977221 # Inst issue rate
system.cpu.iq.iqInstsAdded 9548 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 8151 # Number of instructions issued
system.cpu.iq.ISSUE:rate 0.920400 # Inst issue rate
system.cpu.iq.iqInstsAdded 9604 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 8198 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 3578 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsExamined 3664 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 22 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 2360 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedOperandsExamined 2365 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 3643.835616 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2643.835616 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 266000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_avg_miss_latency 4486.301370 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2486.301370 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 327500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 193000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 181500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 3406.779661 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2406.779661 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_accesses 414 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4450.242718 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2450.242718 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1407000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.995181 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 413 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 994000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995181 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 413 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_miss_latency 1833500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.995169 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 412 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1009500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995169 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 412 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 3392.857143 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2392.857143 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 47500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4214.285714 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2214.285714 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 59000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 33500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.005013 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.005025 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 488 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 3442.386831 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2442.386831 # average overall mshr miss latency
system.cpu.l2cache.demand_accesses 487 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4455.670103 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2455.670103 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 1673000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.995902 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 486 # number of demand (read+write) misses
system.cpu.l2cache.demand_miss_latency 2161000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.995893 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 485 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 1187000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.995902 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 486 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 1191000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.995893 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 485 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 488 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 3442.386831 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2442.386831 # average overall mshr miss latency
system.cpu.l2cache.overall_accesses 487 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4455.670103 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2455.670103 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits
system.cpu.l2cache.overall_miss_latency 1673000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.995902 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 486 # number of overall misses
system.cpu.l2cache.overall_miss_latency 2161000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.995893 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 485 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 1187000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.995902 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 486 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 1191000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.995893 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 485 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -399,29 +399,29 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 398 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 223.758944 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 221.319862 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 8341 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 14 # Number of cycles rename is blocking
system.cpu.numCycles 8907 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 50 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
system.cpu.rename.RENAME:IdleCycles 5339 # Number of cycles rename is idle
system.cpu.rename.RENAME:IdleCycles 5884 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 71 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 13891 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 10852 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 8114 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 1888 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 726 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 102 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 4063 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 272 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:RenameLookups 13715 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 10735 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 8030 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 1846 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 729 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 122 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 3979 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 276 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 382 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
system.cpu.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:skidInsts 532 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed
system.cpu.timesIdled 54 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------

8
tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 3 2007 03:56:47
M5 started Fri Aug 3 04:17:12 2007
M5 executing on zizzer.eecs.umich.edu
M5 compiled Aug 12 2007 00:26:55
M5 started Sun Aug 12 00:29:40 2007
M5 executing on zeep
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 4170500 because target called exit()
Exiting @ tick 4515000 because target called exit()

6
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
View file

@ -34,10 +34,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@ -68,10 +70,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@ -102,10 +106,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true

96
tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
View file

@ -1,31 +1,31 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 65923 # Simulator instruction rate (inst/s)
host_mem_usage 154180 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
host_tick_rate 155349854 # Simulator tick rate (ticks/s)
host_inst_rate 334797 # Simulator instruction rate (inst/s)
host_mem_usage 196348 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
host_tick_rate 1064082508 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5642 # Number of instructions simulated
sim_seconds 0.000013 # Number of seconds simulated
sim_ticks 13359000 # Number of ticks simulated
sim_seconds 0.000018 # Number of seconds simulated
sim_ticks 18365000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 1288000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 2300000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1196000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 2116000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 725 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 1218000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 2175000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.107143 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 1131000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2001000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.107143 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency
system.cpu.dcache.demand_avg_miss_latency 25000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1612 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 2506000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency 4475000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.099944 # miss rate for demand accesses
system.cpu.dcache.demand_misses 179 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 2327000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 4117000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.099944 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 179 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 25000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1612 # number of overall hits
system.cpu.dcache.overall_miss_latency 2506000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency 4475000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.099944 # miss rate for overall accesses
system.cpu.dcache.overall_misses 179 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 2327000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 4117000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.099944 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 179 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 103.895955 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 102.396682 # Cycle average of tags in use
system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 13992.779783 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12992.779783 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 24956.678700 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22956.678700 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 5366 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 3876000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 6913000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.049087 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 3599000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 6359000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.049087 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 5643 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 13992.779783 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12992.779783 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 24956.678700 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 22956.678700 # average overall mshr miss latency
system.cpu.icache.demand_hits 5366 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 3876000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 6913000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.049087 # miss rate for demand accesses
system.cpu.icache.demand_misses 277 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 3599000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 6359000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.049087 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 5643 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 13992.779783 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12992.779783 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 24956.678700 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 22956.678700 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 5366 # number of overall hits
system.cpu.icache.overall_miss_latency 3876000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 6913000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.049087 # miss rate for overall accesses
system.cpu.icache.overall_misses 277 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 3599000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 6359000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.049087 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -138,34 +138,34 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 129.745202 # Cycle average of tags in use
system.cpu.icache.tagsinuse 128.096333 # Cycle average of tags in use
system.cpu.icache.total_refs 5366 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 12000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 876000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 1606000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 803000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 369 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 12000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 4416000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency 8096000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.997290 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 368 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 4048000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997290 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 368 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 12000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 168000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency 308000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154000 # number of UpgradeReq MSHR miss cycles
@ -180,10 +180,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 442 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 5292000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency 9702000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.997738 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
@ -194,11 +194,11 @@ system.cpu.l2cache.fast_writes 0 # nu
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 442 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1 # number of overall hits
system.cpu.l2cache.overall_miss_latency 5292000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency 9702000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.997738 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 441 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
@ -219,12 +219,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 354 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 179.464793 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 177.517189 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 13359000 # number of cpu cycles simulated
system.cpu.numCycles 18365000 # number of cpu cycles simulated
system.cpu.num_insts 5642 # Number of instructions executed
system.cpu.num_refs 1792 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls

8
tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 3 2007 03:56:47
M5 started Fri Aug 3 04:17:13 2007
M5 executing on zizzer.eecs.umich.edu
M5 compiled Aug 12 2007 00:26:55
M5 started Sun Aug 12 00:29:41 2007
M5 executing on zeep
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 13359000 because target called exit()
Exiting @ tick 18365000 because target called exit()

6
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
View file

@ -99,10 +99,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@ -270,10 +272,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@ -304,10 +308,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true

432
tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 146 # Number of BTB hits
global.BPredUnit.BTBLookups 613 # Number of BTB lookups
global.BPredUnit.BTBHits 143 # Number of BTB hits
global.BPredUnit.BTBLookups 610 # Number of BTB lookups
global.BPredUnit.RASInCorrect 32 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 212 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 393 # Number of conditional branches predicted
global.BPredUnit.lookups 777 # Number of BP lookups
global.BPredUnit.usedRAS 153 # Number of times the RAS was used to get a target.
host_inst_rate 24407 # Simulator instruction rate (inst/s)
host_mem_usage 153952 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
host_tick_rate 19202153 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads.
global.BPredUnit.condPredicted 394 # Number of conditional branches predicted
global.BPredUnit.lookups 779 # Number of BP lookups
global.BPredUnit.usedRAS 155 # Number of times the RAS was used to get a target.
host_inst_rate 72558 # Simulator instruction rate (inst/s)
host_mem_usage 196048 # Number of bytes of host memory used
host_seconds 0.03 # Real time elapsed on the host
host_tick_rate 63572637 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 8 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 635 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 367 # Number of stores inserted to the mem dependence unit.
memdepunit.memDep.insertedLoads 636 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 369 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2387 # Number of instructions simulated
sim_seconds 0.000002 # Number of seconds simulated
sim_ticks 1884000 # Number of ticks simulated
sim_ticks 2104000 # Number of ticks simulated
system.cpu.commit.COM:branches 396 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 33 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 35 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 3543
system.cpu.commit.COM:committed_per_cycle.samples 3945
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 2580 7281.96%
1 265 747.95%
2 337 951.17%
3 138 389.50%
4 67 189.11%
5 69 194.75%
6 32 90.32%
7 22 62.09%
8 33 93.14%
0 2992 7584.28%
1 255 646.39%
2 335 849.18%
3 139 352.34%
4 66 167.30%
5 69 174.90%
6 33 83.65%
7 21 53.23%
8 35 88.72%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@ -46,67 +46,67 @@ system.cpu.commit.COM:swp_count 0 # Nu
system.cpu.commit.branchMispredicts 131 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 1118 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 1134 # The number of squashed insts skipped by commit
system.cpu.committedInsts 2387 # Number of Instructions Simulated
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
system.cpu.cpi 1.578969 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.578969 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 518 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 6583.333333 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4891.666667 # average ReadReq mshr miss latency
system.cpu.cpi 1.747382 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.747382 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 519 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 8729.508197 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5745.901639 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 458 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 395000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.115830 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 60 # number of ReadReq misses
system.cpu.dcache.ReadReq_miss_latency 532500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.117534 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 61 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 293500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.115830 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 60 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 239 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 14216.216216 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5202.702703 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 202 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 526000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.154812 # miss rate for WriteReq accesses
system.cpu.dcache.ReadReq_mshr_miss_latency 350500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.117534 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 240 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 18810.810811 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6202.702703 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 203 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 696000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.154167 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 37 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 55 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 192500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.154812 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_hits 54 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 229500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.154167 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 7.905882 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 7.929412 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 757 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 9494.845361 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 5010.309278 # average overall mshr miss latency
system.cpu.dcache.demand_hits 660 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 921000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.128137 # miss rate for demand accesses
system.cpu.dcache.demand_misses 97 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 65 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 486000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.128137 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 97 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 759 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 12535.714286 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 5918.367347 # average overall mshr miss latency
system.cpu.dcache.demand_hits 661 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 1228500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.129117 # miss rate for demand accesses
system.cpu.dcache.demand_misses 98 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 64 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 580000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.129117 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 757 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 9494.845361 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 5010.309278 # average overall mshr miss latency
system.cpu.dcache.overall_accesses 759 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 12535.714286 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 5918.367347 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 660 # number of overall hits
system.cpu.dcache.overall_miss_latency 921000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.128137 # miss rate for overall accesses
system.cpu.dcache.overall_misses 97 # number of overall misses
system.cpu.dcache.overall_mshr_hits 65 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 486000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.128137 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 97 # number of overall MSHR misses
system.cpu.dcache.overall_hits 661 # number of overall hits
system.cpu.dcache.overall_miss_latency 1228500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.129117 # miss rate for overall accesses
system.cpu.dcache.overall_misses 98 # number of overall misses
system.cpu.dcache.overall_mshr_hits 64 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 580000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.129117 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -121,88 +121,88 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 51.399169 # Cycle average of tags in use
system.cpu.dcache.total_refs 672 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 50.690606 # Cycle average of tags in use
system.cpu.dcache.total_refs 674 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 87 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BlockedCycles 91 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 83 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 125 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 4218 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 2648 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 808 # Number of cycles decode is running
system.cpu.decode.DECODE:BranchResolved 126 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 4236 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 3045 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 809 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 225 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 304 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 777 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 686 # Number of cache lines fetched
system.cpu.fetch.Cycles 1528 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 107 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 4951 # Number of instructions fetch has processed
system.cpu.fetch.Branches 779 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 691 # Number of cache lines fetched
system.cpu.fetch.Cycles 1534 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 112 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 4961 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 223 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.206155 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 686 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 299 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.313611 # Number of inst fetches per cycle
system.cpu.fetch.branchRate 0.186766 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 691 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 298 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.189403 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 3769
system.cpu.fetch.rateDist.samples 4171
system.cpu.fetch.rateDist.min_value 0
0 2929 7771.29%
1 36 95.52%
2 88 233.48%
3 54 143.27%
4 108 286.55%
5 55 145.93%
6 40 106.13%
7 42 111.44%
8 417 1106.39%
0 3330 7983.70%
1 36 86.31%
2 85 203.79%
3 57 136.66%
4 109 261.33%
5 54 129.47%
6 40 95.90%
7 42 100.70%
8 418 1002.16%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 676 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 5629.032258 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4489.247312 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 490 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 1047000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.275148 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_accesses 674 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 7774.193548 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5451.612903 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 488 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 1446000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.275964 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 186 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 835000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.275148 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 1014000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.275964 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 186 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 2.634409 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 2.623656 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 676 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 5629.032258 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 4489.247312 # average overall mshr miss latency
system.cpu.icache.demand_hits 490 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 1047000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.275148 # miss rate for demand accesses
system.cpu.icache.demand_accesses 674 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 7774.193548 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 5451.612903 # average overall mshr miss latency
system.cpu.icache.demand_hits 488 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 1446000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.275964 # miss rate for demand accesses
system.cpu.icache.demand_misses 186 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 835000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.275148 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_hits 17 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 1014000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.275964 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 676 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 5629.032258 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 4489.247312 # average overall mshr miss latency
system.cpu.icache.overall_accesses 674 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 7774.193548 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 5451.612903 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 490 # number of overall hits
system.cpu.icache.overall_miss_latency 1047000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.275148 # miss rate for overall accesses
system.cpu.icache.overall_hits 488 # number of overall hits
system.cpu.icache.overall_miss_latency 1446000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.275964 # miss rate for overall accesses
system.cpu.icache.overall_misses 186 # number of overall misses
system.cpu.icache.overall_mshr_hits 10 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 835000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.275148 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_hits 17 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 1014000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.275964 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 186 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
@ -218,35 +218,35 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 186 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 104.691657 # Cycle average of tags in use
system.cpu.icache.total_refs 490 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 102.643576 # Cycle average of tags in use
system.cpu.icache.total_refs 488 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 998 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 516 # Number of branches executed
system.cpu.idleCycles 26984 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 522 # Number of branches executed
system.cpu.iew.EXEC:nop 242 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.810295 # Inst execution rate
system.cpu.iew.EXEC:refs 894 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 334 # Number of stores executed
system.cpu.iew.EXEC:rate 0.736514 # Inst execution rate
system.cpu.iew.EXEC:refs 896 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 333 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 1725 # num instructions consuming a value
system.cpu.iew.WB:count 2987 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.794203 # average fanout of values written-back
system.cpu.iew.WB:consumers 1736 # num instructions consuming a value
system.cpu.iew.WB:count 3002 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.793779 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1370 # num instructions producing a value
system.cpu.iew.WB:rate 0.792518 # insts written-back per cycle
system.cpu.iew.WB:sent 3007 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 146 # Number of branch mispredicts detected at execute
system.cpu.iew.WB:producers 1378 # num instructions producing a value
system.cpu.iew.WB:rate 0.719731 # insts written-back per cycle
system.cpu.iew.WB:sent 3020 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 147 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 635 # Number of dispatched load instructions
system.cpu.iew.iewDispLoadInsts 636 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 92 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 367 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 3711 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 560 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 3054 # Number of executed instructions
system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 369 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 3727 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 563 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 108 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 3072 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
@ -254,23 +254,23 @@ system.cpu.iew.iewSquashCycles 225 # Nu
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 24 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.forwLoads 25 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 12 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.memOrderViolation 13 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 220 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 73 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 98 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.lsq.thread.0.squashedLoads 221 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 75 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 99 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 48 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.633324 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.633324 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 3165 # Type of FU issued
system.cpu.ipc 0.572285 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.572285 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 3180 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 0 0.00% # Type of FU issued
IntAlu 2243 70.87% # Type of FU issued
IntAlu 2258 71.01% # Type of FU issued
IntMult 1 0.03% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 0 0.00% # Type of FU issued
@ -279,16 +279,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 581 18.36% # Type of FU issued
MemWrite 340 10.74% # Type of FU issued
MemRead 581 18.27% # Type of FU issued
MemWrite 340 10.69% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.011058 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_busy_cnt 36 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.011321 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 1 2.86% # attempts to use FU when none available
IntAlu 2 5.56% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
@ -297,61 +297,61 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 12 34.29% # attempts to use FU when none available
MemWrite 22 62.86% # attempts to use FU when none available
MemRead 12 33.33% # attempts to use FU when none available
MemWrite 22 61.11% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 3769
system.cpu.iq.ISSUE:issued_per_cycle.samples 4171
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 2469 6550.81%
1 494 1310.69%
2 274 726.98%
3 234 620.85%
4 152 403.29%
5 87 230.83%
6 40 106.13%
7 14 37.15%
8 5 13.27%
0 2877 6897.63%
1 465 1114.84%
2 300 719.25%
3 228 546.63%
4 154 369.22%
5 89 213.38%
6 40 95.90%
7 14 33.57%
8 4 9.59%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 0.839745 # Inst issue rate
system.cpu.iq.iqInstsAdded 3463 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 3165 # Number of instructions issued
system.cpu.iq.ISSUE:rate 0.762407 # Inst issue rate
system.cpu.iq.iqInstsAdded 3479 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 3180 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 947 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsExamined 944 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 468 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 25 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 3720 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2720 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 93000 # number of ReadExReq miss cycles
system.cpu.iq.iqSquashedOperandsExamined 473 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 4750 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2750 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 114000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 25 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 68000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 66000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 25 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 246 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 3357.723577 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2357.723577 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_miss_latency 826000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 247 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4354.251012 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2354.251012 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_miss_latency 1075500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 246 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 580000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_misses 247 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 581500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 246 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 13 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 3230.769231 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2230.769231 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 42000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadReq_mshr_misses 247 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4250 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2250 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 59500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 13 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 29000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 13 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
@ -361,29 +361,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 271 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 3391.143911 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2391.143911 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_miss_latency 4389.298893 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2389.298893 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 919000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency 1189500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 271 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 648000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 647500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 271 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 271 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 3391.143911 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2391.143911 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_miss_latency 4389.298893 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2389.298893 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
system.cpu.l2cache.overall_miss_latency 919000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency 1189500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 271 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 648000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 647500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 271 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -400,26 +400,26 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 233 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 129.636467 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 127.304233 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 3769 # number of cpu cycles simulated
system.cpu.numCycles 4171 # number of cpu cycles simulated
system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed
system.cpu.rename.RENAME:IdleCycles 2724 # Number of cycles rename is idle
system.cpu.rename.RENAME:IdleCycles 3117 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 4613 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 4068 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2909 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 733 # Number of cycles rename is running
system.cpu.rename.RENAME:RenameLookups 4657 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 4106 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2936 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 738 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 225 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 7 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 1141 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 80 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:UndoneMaps 1168 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 84 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 52 # count of insts added to the skid buffer
system.cpu.rename.RENAME:skidInsts 50 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed
system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.timesIdled 16 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ----------

8
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 3 2007 03:56:47
M5 started Fri Aug 3 04:17:13 2007
M5 executing on zizzer.eecs.umich.edu
M5 compiled Aug 12 2007 00:26:55
M5 started Sun Aug 12 00:29:41 2007
M5 executing on zeep
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 1884000 because target called exit()
Exiting @ tick 2104000 because target called exit()

6
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
View file

@ -34,10 +34,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@ -68,10 +70,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@ -102,10 +106,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true

96
tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,31 +1,31 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 43962 # Simulator instruction rate (inst/s)
host_mem_usage 153564 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
host_tick_rate 112042683 # Simulator tick rate (ticks/s)
host_inst_rate 196854 # Simulator instruction rate (inst/s)
host_mem_usage 195480 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
host_tick_rate 706389035 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated
sim_seconds 0.000007 # Number of seconds simulated
sim_ticks 6615000 # Number of ticks simulated
sim_seconds 0.000009 # Number of seconds simulated
sim_ticks 9431000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 770000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 1375000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 715000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 1265000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 256 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 532000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 950000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.129252 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 38 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 494000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 874000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency
system.cpu.dcache.demand_avg_miss_latency 25000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.dcache.demand_hits 616 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 1302000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency 2325000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.131171 # miss rate for demand accesses
system.cpu.dcache.demand_misses 93 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 1209000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 2139000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.131171 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 93 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 25000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 616 # number of overall hits
system.cpu.dcache.overall_miss_latency 1302000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency 2325000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.131171 # miss rate for overall accesses
system.cpu.dcache.overall_misses 93 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 1209000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 2139000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.131171 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 50.044147 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 48.863963 # Cycle average of tags in use
system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 2416 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 2282000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 4075000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.063203 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 2119000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 3749000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.063203 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 2579 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 14000 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.icache.demand_hits 2416 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 2282000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 4075000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.063203 # miss rate for demand accesses
system.cpu.icache.demand_misses 163 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 2119000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 3749000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.063203 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 2579 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 14000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 2416 # number of overall hits
system.cpu.icache.overall_miss_latency 2282000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 4075000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.063203 # miss rate for overall accesses
system.cpu.icache.overall_misses 163 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 2119000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 3749000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.063203 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -138,33 +138,33 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 86.205303 # Cycle average of tags in use
system.cpu.icache.tagsinuse 83.443652 # Cycle average of tags in use
system.cpu.icache.total_refs 2416 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 12000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 324000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 594000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 27 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 297000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 27 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 218 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 12000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_miss_latency 2616000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency 4796000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 218 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 2398000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 12000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 132000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency 242000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 11 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 121000 # number of UpgradeReq MSHR miss cycles
@ -179,10 +179,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 2940000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency 5390000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
@ -193,11 +193,11 @@ system.cpu.l2cache.fast_writes 0 # nu
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
system.cpu.l2cache.overall_miss_latency 2940000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency 5390000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 245 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
@ -218,12 +218,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 109.774164 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 106.620093 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 6615000 # number of cpu cycles simulated
system.cpu.numCycles 9431000 # number of cpu cycles simulated
system.cpu.num_insts 2578 # Number of instructions executed
system.cpu.num_refs 710 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls

8
tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 3 2007 03:56:47
M5 started Fri Aug 3 04:17:14 2007
M5 executing on zizzer.eecs.umich.edu
M5 compiled Aug 12 2007 00:26:55
M5 started Sun Aug 12 00:29:42 2007
M5 executing on zeep
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 6615000 because target called exit()
Exiting @ tick 9431000 because target called exit()

6
tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
View file

@ -34,10 +34,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@ -68,10 +70,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@ -102,10 +106,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true

96
tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
View file

@ -1,31 +1,31 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 45085 # Simulator instruction rate (inst/s)
host_mem_usage 155088 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
host_tick_rate 101545982 # Simulator tick rate (ticks/s)
host_inst_rate 269189 # Simulator instruction rate (inst/s)
host_mem_usage 197500 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
host_tick_rate 866482072 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5657 # Number of instructions simulated
sim_seconds 0.000014 # Number of seconds simulated
sim_ticks 13544000 # Number of ticks simulated
sim_seconds 0.000018 # Number of seconds simulated
sim_ticks 18463000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 1148000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 2050000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1066000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 1886000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 860 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 896000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 1600000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.069264 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 832000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 1472000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency
system.cpu.dcache.demand_avg_miss_latency 25000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1908 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 2044000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency 3650000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.071081 # miss rate for demand accesses
system.cpu.dcache.demand_misses 146 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 1898000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 3358000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.071081 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 25000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1908 # number of overall hits
system.cpu.dcache.overall_miss_latency 2044000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency 3650000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.071081 # miss rate for overall accesses
system.cpu.dcache.overall_misses 146 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 1898000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 3358000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.071081 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 85.440937 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 84.706280 # Cycle average of tags in use
system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 13986.798680 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12986.798680 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 24920.792079 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22920.792079 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 4238000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 7551000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 3935000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 6945000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 13986.798680 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12986.798680 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 24920.792079 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 22920.792079 # average overall mshr miss latency
system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 4238000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 7551000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses
system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 3935000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 6945000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 13986.798680 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12986.798680 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 24920.792079 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 22920.792079 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 5355 # number of overall hits
system.cpu.icache.overall_miss_latency 4238000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 7551000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses
system.cpu.icache.overall_misses 303 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 3935000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 6945000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -138,34 +138,34 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 13 # number of replacements
system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 136.727640 # Cycle average of tags in use
system.cpu.icache.tagsinuse 135.936693 # Cycle average of tags in use
system.cpu.icache.total_refs 5355 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 50 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 12000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 600000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 1100000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 50 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 550000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 385 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 12000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 4596000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency 8426000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.994805 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 383 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 4213000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994805 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 383 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 12000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 168000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency 308000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154000 # number of UpgradeReq MSHR miss cycles
@ -180,10 +180,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 5196000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency 9526000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
@ -194,11 +194,11 @@ system.cpu.l2cache.fast_writes 0 # nu
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits
system.cpu.l2cache.overall_miss_latency 5196000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency 9526000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 433 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
@ -219,12 +219,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 369 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 184.077317 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 183.281817 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 13544000 # number of cpu cycles simulated
system.cpu.numCycles 18463000 # number of cpu cycles simulated
system.cpu.num_insts 5657 # Number of instructions executed
system.cpu.num_refs 2055 # Number of memory references
system.cpu.workload.PROG:num_syscalls 13 # Number of system calls

8
tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 3 2007 04:06:41
M5 started Fri Aug 3 04:31:10 2007
M5 executing on zizzer.eecs.umich.edu
M5 compiled Aug 12 2007 17:11:48
M5 started Sun Aug 12 17:11:50 2007
M5 executing on zeep
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 13544000 because target called exit()
Exiting @ tick 18463000 because target called exit()

6
tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
View file

@ -34,10 +34,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@ -68,10 +70,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@ -102,10 +106,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true

96
tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt
View file

@ -1,31 +1,31 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 36222 # Simulator instruction rate (inst/s)
host_mem_usage 155556 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
host_tick_rate 84966253 # Simulator tick rate (ticks/s)
host_inst_rate 277220 # Simulator instruction rate (inst/s)
host_mem_usage 197684 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
host_tick_rate 892278360 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4863 # Number of instructions simulated
sim_seconds 0.000011 # Number of seconds simulated
sim_ticks 11443000 # Number of ticks simulated
sim_seconds 0.000016 # Number of seconds simulated
sim_ticks 15912000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 13962.962963 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12962.962963 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 24777.777778 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22777.777778 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 554 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 754000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 1338000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.088816 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 700000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 1230000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.088816 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 661 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 562 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 1386000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 2475000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.149773 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 99 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 1287000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2277000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.149773 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 99 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 1269 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 13986.928105 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12986.928105 # average overall mshr miss latency
system.cpu.dcache.demand_avg_miss_latency 24921.568627 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 22921.568627 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1116 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 2140000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency 3813000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.120567 # miss rate for demand accesses
system.cpu.dcache.demand_misses 153 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 1987000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 3507000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.120567 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 153 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 13986.928105 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12986.928105 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 24921.568627 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 22921.568627 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1116 # number of overall hits
system.cpu.dcache.overall_miss_latency 2140000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency 3813000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.120567 # miss rate for overall accesses
system.cpu.dcache.overall_misses 153 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 1987000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 3507000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.120567 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 153 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 83.865949 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 83.464621 # Cycle average of tags in use
system.cpu.dcache.total_refs 1131 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 4864 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 13984.375000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12984.375000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 24906.250000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22906.250000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 4608 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 3580000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 6376000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.052632 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 3324000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 5864000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.052632 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 4864 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 13984.375000 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12984.375000 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 24906.250000 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 22906.250000 # average overall mshr miss latency
system.cpu.icache.demand_hits 4608 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 3580000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 6376000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.052632 # miss rate for demand accesses
system.cpu.icache.demand_misses 256 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 3324000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 5864000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.052632 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 4864 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 13984.375000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12984.375000 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 24906.250000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 22906.250000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 4608 # number of overall hits
system.cpu.icache.overall_miss_latency 3580000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 6376000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.052632 # miss rate for overall accesses
system.cpu.icache.overall_misses 256 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 3324000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 5864000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.052632 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -138,34 +138,34 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 114.646434 # Cycle average of tags in use
system.cpu.icache.tagsinuse 114.953503 # Cycle average of tags in use
system.cpu.icache.total_refs 4608 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 84 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 12000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 1008000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 1848000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 84 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 924000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 84 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 310 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 12000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 3684000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency 6754000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.990323 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 307 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 3377000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990323 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 12000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 180000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency 330000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 165000 # number of UpgradeReq MSHR miss cycles
@ -180,10 +180,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 394 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 4692000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency 8602000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.992386 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 391 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
@ -194,11 +194,11 @@ system.cpu.l2cache.fast_writes 0 # nu
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 394 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 3 # number of overall hits
system.cpu.l2cache.overall_miss_latency 4692000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency 8602000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.992386 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 391 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
@ -219,12 +219,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 292 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 133.135118 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 133.743977 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 11443000 # number of cpu cycles simulated
system.cpu.numCycles 15912000 # number of cpu cycles simulated
system.cpu.num_insts 4863 # Number of instructions executed
system.cpu.num_refs 1269 # Number of memory references
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls

8
tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 3 2007 04:11:25
M5 started Fri Aug 3 04:31:19 2007
M5 executing on zizzer.eecs.umich.edu
M5 compiled Aug 12 2007 12:23:15
M5 started Sun Aug 12 16:58:40 2007
M5 executing on zeep
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 11443000 because target called exit()
Exiting @ tick 15912000 because target called exit()

6
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
View file

@ -99,10 +99,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@ -270,10 +272,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@ -304,10 +308,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=2
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true

724
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
View file

File diff suppressed because it is too large Load diff

8
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
View file

@ -7,9 +7,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 3 2007 03:56:47
M5 started Fri Aug 3 04:17:15 2007
M5 executing on zizzer.eecs.umich.edu
M5 compiled Aug 12 2007 00:26:55
M5 started Sun Aug 12 00:29:42 2007
M5 executing on zeep
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 5126000 because target called exit()
Exiting @ tick 5506000 because target called exit()

66
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
View file

@ -5,7 +5,7 @@ dummy=0
[system]
type=LinuxAlphaSystem
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
console=/dist/m5/system/binaries/console
@ -22,8 +22,8 @@ system_type=34
[system.bridge]
type=Bridge
delay=50000
fix_partial_write_a=false
fix_partial_write_b=true
filter_ranges_a=0:18446744073709551615
filter_ranges_b=0:8589934591
nack_delay=4000
req_size_a=16
req_size_b=16
@ -65,10 +65,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=4
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
@ -103,10 +105,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=1
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
@ -171,10 +175,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=4
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
@ -209,10 +215,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=1
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
@ -295,17 +303,55 @@ clock=1000
responder_set=true
width=64
default=system.tsunami.pciconfig.pio
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
[system.iocache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=8
block_size=64
cpu_side_filter_ranges=549755813888:18446744073709551615
hash_delay=1
latency=50000
lifo=false
max_miss_count=0
mem_side_filter_ranges=0:18446744073709551615
mshrs=20
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=500000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=1024
split=false
split_size=0
subblock_size=0
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.port[28]
mem_side=system.membus.port[2]
[system.l2c]
type=BaseCache
addr_range=0:18446744073709551615
assoc=8
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=92
prefetch_access=false
prefetch_cache_check_push=true
@ -329,7 +375,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
mem_side=system.membus.port[2]
mem_side=system.membus.port[3]
[system.membus]
type=Bus
@ -340,7 +386,7 @@ clock=1000
responder_set=false
width=64
default=system.membus.responder.pio
port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side
port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
[system.membus.responder]
type=IsaFake
@ -474,8 +520,8 @@ system=system
tx_delay=1000000
tx_fifo_size=524288
tx_thread=false
config=system.iobus.port[28]
dma=system.iobus.port[29]
config=system.iobus.port[29]
dma=system.iobus.port[30]
pio=system.iobus.port[27]
[system.tsunami.ethernet.configdata]
@ -840,8 +886,8 @@ pci_func=0
pio_latency=1000
platform=system.tsunami
system=system
config=system.iobus.port[30]
dma=system.iobus.port[31]
config=system.iobus.port[31]
dma=system.iobus.port[32]
pio=system.iobus.port[26]
[system.tsunami.ide.configdata]

11
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console
View file

@ -38,7 +38,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
Mount-cache hash table entries: 512
SMP starting up secondaries.
Slave CPU 1 console command START
Slave CPU 1 console command START
SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400
Brought up 2 CPUs
SMP: Total of 2 processors activated (8000.15 BogoMIPS).
@ -77,7 +77,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
hdb: M5 IDE Disk, ATA DISK drive
ide0 at 0x8410-0x8417,0x8422 on irq 31
hda: max request size: 128KiB
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
hda: cache flushes not supported
hda: hda1
hdb: max request size: 128KiB
@ -104,6 +104,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
All bugs added by David S. Miller <davem@redhat.com>
VFS: Mounted root (ext2 filesystem) readonly.
Freeing unused kernel memory: 224k freed
init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
mounting filesystems...
loading script...
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
mounting filesystems...
EXT2-fs warning: checktime reached, running e2fsck is recommended
loading script...

66
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1258571 # Simulator instruction rate (inst/s)
host_mem_usage 256444 # Number of bytes of host memory used
host_seconds 50.16 # Real time elapsed on the host
host_tick_rate 37289409683 # Simulator tick rate (ticks/s)
host_inst_rate 2271343 # Simulator instruction rate (inst/s)
host_mem_usage 326380 # Number of bytes of host memory used
host_seconds 27.79 # Real time elapsed on the host
host_tick_rate 67296173797 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 63125943 # Number of instructions simulated
sim_seconds 1.870335 # Number of seconds simulated
@ -471,6 +471,64 @@ system.disk2.dma_read_txs 0 # Nu
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.iocache.ReadReq_accesses 175 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_misses 175 # number of ReadReq misses
system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_misses 41552 # number of WriteReq misses
system.iocache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.blocked_no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_no_targets 0 # number of cycles access was blocked
system.iocache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_accesses 41727 # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency 0 # average overall miss latency
system.iocache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.iocache.demand_hits 0 # number of demand (read+write) hits
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate 1 # miss rate for demand accesses
system.iocache.demand_misses 41727 # number of demand (read+write) misses
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.overall_accesses 41727 # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency 0 # average overall miss latency
system.iocache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.iocache.overall_hits 0 # number of overall hits
system.iocache.overall_miss_latency 0 # number of overall miss cycles
system.iocache.overall_miss_rate 1 # miss rate for overall accesses
system.iocache.overall_misses 41727 # number of overall misses
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.iocache.replacements 41695 # number of replacements
system.iocache.sampled_refs 41711 # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.iocache.tagsinuse 0.435433 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 41520 # number of writebacks
system.l2c.ReadExReq_accesses 306246 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses 306246 # number of ReadExReq misses

4
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
View file

@ -1,5 +1,5 @@
Listening for system connection on port 3457
Listening for system connection on port 3456
0: system.remote_gdb.listener: listening for remote gdb on port 7000
0: system.remote_gdb.listener: listening for remote gdb on port 7001
0: system.remote_gdb.listener: listening for remote gdb on port 7002
warn: Entering event queue @ 0. Starting simulation...
warn: 97861500: Trying to launch CPU number 1!

6
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 3 2007 04:02:11
M5 started Fri Aug 3 04:22:43 2007
M5 executing on zizzer.eecs.umich.edu
M5 compiled Aug 10 2007 16:03:34
M5 started Fri Aug 10 16:04:07 2007
M5 executing on zeep
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 1870335101500 because m5_exit instruction encountered

62
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
View file

@ -5,7 +5,7 @@ dummy=0
[system]
type=LinuxAlphaSystem
children=bridge cpu disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
console=/dist/m5/system/binaries/console
@ -22,8 +22,8 @@ system_type=34
[system.bridge]
type=Bridge
delay=50000
fix_partial_write_a=false
fix_partial_write_b=true
filter_ranges_a=0:18446744073709551615
filter_ranges_b=0:8589934591
nack_delay=4000
req_size_a=16
req_size_b=16
@ -65,10 +65,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=4
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
@ -103,10 +105,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=1
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
@ -189,17 +193,55 @@ clock=1000
responder_set=true
width=64
default=system.tsunami.pciconfig.pio
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
[system.iocache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=8
block_size=64
cpu_side_filter_ranges=549755813888:18446744073709551615
hash_delay=1
latency=50000
lifo=false
max_miss_count=0
mem_side_filter_ranges=0:18446744073709551615
mshrs=20
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=500000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=1024
split=false
split_size=0
subblock_size=0
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.port[28]
mem_side=system.membus.port[2]
[system.l2c]
type=BaseCache
addr_range=0:18446744073709551615
assoc=8
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=92
prefetch_access=false
prefetch_cache_check_push=true
@ -223,7 +265,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
mem_side=system.membus.port[2]
mem_side=system.membus.port[3]
[system.membus]
type=Bus
@ -234,7 +276,7 @@ clock=1000
responder_set=false
width=64
default=system.membus.responder.pio
port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side
port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
[system.membus.responder]
type=IsaFake
@ -368,8 +410,8 @@ system=system
tx_delay=1000000
tx_fifo_size=524288
tx_thread=false
config=system.iobus.port[28]
dma=system.iobus.port[29]
config=system.iobus.port[29]
dma=system.iobus.port[30]
pio=system.iobus.port[27]
[system.tsunami.ethernet.configdata]
@ -734,8 +776,8 @@ pci_func=0
pio_latency=1000
platform=system.tsunami
system=system
config=system.iobus.port[30]
dma=system.iobus.port[31]
config=system.iobus.port[31]
dma=system.iobus.port[32]
pio=system.iobus.port[26]
[system.tsunami.ide.configdata]

9
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console
View file

@ -72,7 +72,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
hdb: M5 IDE Disk, ATA DISK drive
ide0 at 0x8410-0x8417,0x8422 on irq 31
hda: max request size: 128KiB
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
hda: cache flushes not supported
hda: hda1
hdb: max request size: 128KiB
@ -99,6 +99,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
All bugs added by David S. Miller <davem@redhat.com>
VFS: Mounted root (ext2 filesystem) readonly.
Freeing unused kernel memory: 224k freed
init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
mounting filesystems...
loading script...
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
mounting filesystems...
EXT2-fs warning: checktime reached, running e2fsck is recommended
loading script...

66
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1294756 # Simulator instruction rate (inst/s)
host_mem_usage 255900 # Number of bytes of host memory used
host_seconds 46.35 # Real time elapsed on the host
host_tick_rate 39449403667 # Simulator tick rate (ticks/s)
host_inst_rate 2322212 # Simulator instruction rate (inst/s)
host_mem_usage 325356 # Number of bytes of host memory used
host_seconds 25.84 # Real time elapsed on the host
host_tick_rate 70754225205 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 60007317 # Number of instructions simulated
sim_seconds 1.828355 # Number of seconds simulated
@ -249,6 +249,64 @@ system.disk2.dma_read_txs 0 # Nu
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.iocache.ReadReq_accesses 174 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_misses 174 # number of ReadReq misses
system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_misses 41552 # number of WriteReq misses
system.iocache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.blocked_no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_no_targets 0 # number of cycles access was blocked
system.iocache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_accesses 41726 # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency 0 # average overall miss latency
system.iocache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.iocache.demand_hits 0 # number of demand (read+write) hits
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate 1 # miss rate for demand accesses
system.iocache.demand_misses 41726 # number of demand (read+write) misses
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.overall_accesses 41726 # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency 0 # average overall miss latency
system.iocache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.iocache.overall_hits 0 # number of overall hits
system.iocache.overall_miss_latency 0 # number of overall miss cycles
system.iocache.overall_miss_rate 1 # miss rate for overall accesses
system.iocache.overall_misses 41726 # number of overall misses
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.iocache.replacements 41686 # number of replacements
system.iocache.sampled_refs 41702 # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.iocache.tagsinuse 1.226223 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.warmup_cycle 1684804097017 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 41512 # number of writebacks
system.l2c.ReadExReq_accesses 304342 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses 304342 # number of ReadExReq misses

4
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
View file

@ -1,3 +1,3 @@
Listening for system connection on port 3457
0: system.remote_gdb.listener: listening for remote gdb on port 7001
Listening for system connection on port 3456
0: system.remote_gdb.listener: listening for remote gdb on port 7000
warn: Entering event queue @ 0. Starting simulation...

6
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 3 2007 04:02:11
M5 started Fri Aug 3 04:21:55 2007
M5 executing on zizzer.eecs.umich.edu
M5 compiled Aug 10 2007 16:03:34
M5 started Fri Aug 10 16:03:39 2007
M5 executing on zeep
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 1828355476000 because m5_exit instruction encountered

66
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
View file

@ -5,7 +5,7 @@ dummy=0
[system]
type=LinuxAlphaSystem
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
console=/dist/m5/system/binaries/console
@ -22,8 +22,8 @@ system_type=34
[system.bridge]
type=Bridge
delay=50000
fix_partial_write_a=false
fix_partial_write_b=true
filter_ranges_a=0:18446744073709551615
filter_ranges_b=0:8589934591
nack_delay=4000
req_size_a=16
req_size_b=16
@ -63,10 +63,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=4
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
@ -101,10 +103,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=1
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
@ -167,10 +171,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=4
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
@ -205,10 +211,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=1
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
@ -291,17 +299,55 @@ clock=1000
responder_set=true
width=64
default=system.tsunami.pciconfig.pio
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
[system.iocache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=8
block_size=64
cpu_side_filter_ranges=549755813888:18446744073709551615
hash_delay=1
latency=50000
lifo=false
max_miss_count=0
mem_side_filter_ranges=0:18446744073709551615
mshrs=20
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=500000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=1024
split=false
split_size=0
subblock_size=0
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.port[28]
mem_side=system.membus.port[2]
[system.l2c]
type=BaseCache
addr_range=0:18446744073709551615
assoc=8
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=92
prefetch_access=false
prefetch_cache_check_push=true
@ -325,7 +371,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
mem_side=system.membus.port[2]
mem_side=system.membus.port[3]
[system.membus]
type=Bus
@ -336,7 +382,7 @@ clock=1000
responder_set=false
width=64
default=system.membus.responder.pio
port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side
port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
[system.membus.responder]
type=IsaFake
@ -470,8 +516,8 @@ system=system
tx_delay=1000000
tx_fifo_size=524288
tx_thread=false
config=system.iobus.port[28]
dma=system.iobus.port[29]
config=system.iobus.port[29]
dma=system.iobus.port[30]
pio=system.iobus.port[27]
[system.tsunami.ethernet.configdata]
@ -836,8 +882,8 @@ pci_func=0
pio_latency=1000
platform=system.tsunami
system=system
config=system.iobus.port[30]
dma=system.iobus.port[31]
config=system.iobus.port[31]
dma=system.iobus.port[32]
pio=system.iobus.port[26]
[system.tsunami.ide.configdata]

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