SE/FS: Pull FULL_SYSTEM out of the build_opts files
--HG-- rename : build_opts/ALPHA_FS => build_opts/ALPHA rename : build_opts/ALPHA_SE_MESI_CMP_directory => build_opts/ALPHA_MESI_CMP_directory rename : build_opts/ALPHA_SE_MOESI_CMP_directory => build_opts/ALPHA_MOESI_CMP_directory rename : build_opts/ALPHA_SE_MOESI_CMP_token => build_opts/ALPHA_MOESI_CMP_token rename : build_opts/ALPHA_SE_MOESI_hammer => build_opts/ALPHA_MOESI_hammer rename : build_opts/ALPHA_SE_Network_test => build_opts/ALPHA_Network_test rename : build_opts/ARM_FS => build_opts/ARM rename : build_opts/MIPS_SE => build_opts/MIPS rename : build_opts/POWER_SE => build_opts/POWER rename : build_opts/SPARC_FS => build_opts/SPARC rename : build_opts/X86_FS => build_opts/X86
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15 changed files with 1 additions and 27 deletions
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@ -1,4 +1,4 @@
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TARGET_ISA = 'alpha'
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FULL_SYSTEM = 1
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SS_COMPATIBLE_FP = 1
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CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
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PROTOCOL = 'MI_example'
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@ -1,4 +1,3 @@
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FULL_SYSTEM = 0
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SS_COMPATIBLE_FP = 1
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CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
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PROTOCOL = 'MESI_CMP_directory'
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FULL_SYSTEM = 0
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SS_COMPATIBLE_FP = 1
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CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
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PROTOCOL = 'MOESI_CMP_directory'
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FULL_SYSTEM = 0
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SS_COMPATIBLE_FP = 1
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CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
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PROTOCOL = 'MOESI_CMP_token'
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FULL_SYSTEM = 0
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SS_COMPATIBLE_FP = 1
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CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
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PROTOCOL = 'MOESI_hammer'
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FULL_SYSTEM = 0
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SS_COMPATIBLE_FP = 1
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CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
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PROTOCOL = 'Network_test'
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@ -1,4 +0,0 @@
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FULL_SYSTEM = 0
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SS_COMPATIBLE_FP = 1
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CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
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PROTOCOL = 'MI_example'
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TARGET_ISA = 'arm'
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CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
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FULL_SYSTEM = 1
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PROTOCOL = 'MI_example'
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@ -1,4 +0,0 @@
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TARGET_ISA = 'arm'
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FULL_SYSTEM = 0
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CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
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PROTOCOL = 'MI_example'
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@ -1,4 +1,3 @@
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TARGET_ISA = 'mips'
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FULL_SYSTEM = 0
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CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
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PROTOCOL = 'MI_example'
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TARGET_ISA = 'power'
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FULL_SYSTEM = 0
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CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
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PROTOCOL = 'MI_example'
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TARGET_ISA = 'sparc'
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CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
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FULL_SYSTEM = 0
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PROTOCOL = 'MI_example'
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@ -1,4 +0,0 @@
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TARGET_ISA = 'sparc'
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CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU'
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FULL_SYSTEM = 1
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PROTOCOL = 'MI_example'
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TARGET_ISA = 'x86'
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CPU_MODELS = 'AtomicSimpleCPU,O3CPU,TimingSimpleCPU'
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FULL_SYSTEM = 1
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PROTOCOL = 'MI_example'
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TARGET_ISA = 'x86'
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CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
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FULL_SYSTEM = 0
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PROTOCOL = 'MI_example'
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