X86: Change the I8259 from a subdevice into a real SimObject.
--HG-- rename : src/dev/x86/south_bridge/i8259.cc => src/dev/x86/i8259.cc rename : src/dev/x86/south_bridge/i8259.hh => src/dev/x86/i8259.hh
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8 changed files with 81 additions and 30 deletions
37
src/dev/x86/I8259.py
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37
src/dev/x86/I8259.py
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# Copyright (c) 2008 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Gabe Black
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from m5.params import *
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from m5.proxy import *
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from Device import BasicPioDevice
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class I8259(BasicPioDevice):
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type = 'I8259'
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cxx_class='X86ISA::I8259'
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pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
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master = Param.Bool(True, 'If this PIC is the master or slave')
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@ -32,6 +32,7 @@ from m5.proxy import *
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from Cmos import Cmos
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from Device import IsaFake
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from Pci import PciConfigAll
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from I8259 import I8259
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from Platform import Platform
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from SouthBridge import SouthBridge
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from Terminal import Terminal
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@ -49,6 +50,8 @@ class PC(Platform):
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south_bridge = SouthBridge()
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cmos = Cmos(pio_addr=x86IOAddress(0x70))
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pic1 = I8259(pio_addr=x86IOAddress(0x20), master=True)
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pic2 = I8259(pio_addr=x86IOAddress(0xA0), master=False)
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# "Non-existant" port used for timing purposes by the linux kernel
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i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
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@ -66,6 +69,8 @@ class PC(Platform):
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def attachIO(self, bus):
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self.south_bridge.pio = bus.port
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self.cmos.pio = bus.port
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self.pic1.pio = bus.port
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self.pic2.pio = bus.port
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self.i_dont_exist.pio = bus.port
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self.behind_pci.pio = bus.port
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self.com_1.pio = bus.port
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@ -37,3 +37,7 @@ if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
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SimObject('Cmos.py')
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Source('cmos.cc')
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TraceFlag('CMOS', 'Accesses to CMOS devices')
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SimObject('I8259.py')
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Source('i8259.cc')
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TraceFlag('I8259', 'Accesses to the I8259 PIC devices')
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@ -28,18 +28,24 @@
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* Authors: Gabe Black
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*/
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#include "dev/x86/south_bridge/i8259.hh"
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#include "dev/x86/i8259.hh"
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Tick
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X86ISA::I8259::read(PacketPtr pkt)
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{
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warn("Reading from PIC device.\n");
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return SubDevice::read(pkt);
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DPRINTF(I8259, "Reading from PIC device.\n");
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return latency;
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}
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Tick
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X86ISA::I8259::write(PacketPtr pkt)
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{
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warn("Writing to PIC device.\n");
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return SubDevice::write(pkt);
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DPRINTF(I8259, "Writing to PIC device.\n");
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return latency;
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}
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X86ISA::I8259 *
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I8259Params::create()
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{
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return new X86ISA::I8259(this);
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}
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@ -28,27 +28,36 @@
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* Authors: Gabe Black
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*/
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#ifndef __DEV_X86_SOUTH_BRIDGE_I8259_HH__
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#define __DEV_X86_SOUTH_BRIDGE_I8259_HH__
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#ifndef __DEV_X86_I8259_HH__
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#define __DEV_X86_I8259_HH__
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#include "arch/x86/x86_traits.hh"
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#include "base/range.hh"
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#include "dev/x86/south_bridge/sub_device.hh"
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#include "dev/io_device.hh"
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#include "params/I8259.hh"
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namespace X86ISA
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{
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class I8259 : public SubDevice
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class I8259 : public BasicPioDevice
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{
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public:
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protected:
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Tick latency;
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bool master;
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I8259()
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{}
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I8259(Tick _latency) : SubDevice(_latency)
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{}
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I8259(Addr start, Addr size, Tick _latency) :
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SubDevice(start, size, _latency)
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{}
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public:
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typedef I8259Params Params;
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const Params *
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params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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I8259(Params * p) : BasicPioDevice(p)
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{
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pioSize = 2;
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latency = p->pio_latency;
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master = p->master;
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}
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Tick read(PacketPtr pkt);
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@ -57,4 +66,4 @@ class I8259 : public SubDevice
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}; // namespace X86ISA
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#endif //__DEV_X86_SOUTH_BRIDGE_I8259_HH__
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#endif //__DEV_X86_I8259_HH__
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@ -37,7 +37,6 @@ if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
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# Sub devices
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Source('i8254.cc')
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Source('i8259.cc')
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Source('speaker.cc')
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TraceFlag('PCSpeaker')
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@ -67,13 +67,9 @@ SouthBridge::write(PacketPtr pkt)
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}
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SouthBridge::SouthBridge(const Params *p) : PioDevice(p),
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pic1(0x20, 2, p->pio_latency),
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pic2(0xA0, 2, p->pio_latency),
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pit(this, p->name + ".pit", 0x40, 4, p->pio_latency),
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speaker(&pit, 0x61, 1, p->pio_latency)
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{
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addDevice(pic1);
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addDevice(pic2);
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addDevice(pit);
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addDevice(speaker);
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#include "base/range_map.hh"
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#include "dev/io_device.hh"
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#include "dev/x86/south_bridge/i8254.hh"
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#include "dev/x86/south_bridge/i8259.hh"
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#include "dev/x86/south_bridge/speaker.hh"
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#include "dev/x86/south_bridge/sub_device.hh"
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#include "params/SouthBridge.hh"
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void addDevice(X86ISA::SubDevice &);
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public:
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// PICs
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X86ISA::I8259 pic1;
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X86ISA::I8259 pic2;
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// I8254 Programmable Interval Timer
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X86ISA::I8254 pit;
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