Add reference outputs for SPARC on the atomic timing cpu model
--HG-- extra : convert_revision : b64ff7c05504da6112631baaae8f0d927469e16f
This commit is contained in:
parent
20208d00e6
commit
274d2670a1
236
tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
Normal file
236
tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
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[root]
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type=Root
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children=system
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checkpoint=
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clock=1000000000000
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max_tick=0
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output_file=cout
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progress_interval=0
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[debug]
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break_cycles=
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[exetrace]
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intel_format=false
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pc_symbol=true
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print_cpseq=false
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print_cycle=true
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print_data=true
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print_effaddr=true
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print_fetchseq=false
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print_iregs=false
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print_opclass=true
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print_reg_delta=false
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print_thread=true
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speculative=true
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trace_system=client
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[serialize]
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count=10
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cycle=0
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dir=cpt.%012d
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period=0
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[stats]
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descriptions=true
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dump_cycle=0
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dump_period=0
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dump_reset=false
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ignore_events=
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mysql_db=
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mysql_host=
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mysql_password=
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mysql_user=
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project_name=test
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simulation_name=test
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simulation_sample=0
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text_compat=true
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text_file=m5stats.txt
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[system]
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type=System
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children=cpu membus physmem
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mem_mode=atomic
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physmem=system.physmem
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[system.cpu]
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type=TimingSimpleCPU
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children=dcache icache l2cache toL2Bus workload
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clock=1
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cpu_id=0
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defer_registration=false
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function_trace=false
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function_trace_start=0
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max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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mem=system.cpu.dcache
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progress_interval=0
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system=system
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workload=system.cpu.workload
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dcache_port=system.cpu.dcache.cpu_side
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icache_port=system.cpu.icache.cpu_side
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[system.cpu.dcache]
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type=BaseCache
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adaptive_compression=false
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assoc=2
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block_size=64
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compressed_bus=false
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compression_latency=0
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hash_delay=1
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hit_latency=1
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latency=1
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lifo=false
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max_miss_count=0
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mshrs=10
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prefetch_access=false
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10
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prefetch_miss=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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protocol=Null
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repl=Null
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size=262144
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split=false
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split_size=0
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store_compressed=false
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subblock_size=0
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tgts_per_mshr=5
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.dcache_port
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mem_side=system.cpu.toL2Bus.port[1]
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[system.cpu.icache]
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type=BaseCache
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adaptive_compression=false
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assoc=2
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block_size=64
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compressed_bus=false
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compression_latency=0
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hash_delay=1
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hit_latency=1
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latency=1
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lifo=false
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max_miss_count=0
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mshrs=10
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prefetch_access=false
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10
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prefetch_miss=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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protocol=Null
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repl=Null
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size=131072
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split=false
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split_size=0
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store_compressed=false
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subblock_size=0
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tgts_per_mshr=5
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.icache_port
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mem_side=system.cpu.toL2Bus.port[0]
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[system.cpu.l2cache]
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type=BaseCache
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adaptive_compression=false
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assoc=2
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block_size=64
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compressed_bus=false
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compression_latency=0
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hash_delay=1
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hit_latency=1
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latency=1
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lifo=false
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max_miss_count=0
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mshrs=10
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prefetch_access=false
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10
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prefetch_miss=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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protocol=Null
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repl=Null
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size=2097152
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split=false
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split_size=0
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store_compressed=false
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subblock_size=0
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tgts_per_mshr=5
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.toL2Bus.port[2]
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mem_side=system.membus.port[1]
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[system.cpu.toL2Bus]
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type=Bus
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bus_id=0
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clock=1000
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width=64
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port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
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[system.cpu.workload]
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type=LiveProcess
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cmd=hello
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egid=100
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env=
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euid=100
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executable=tests/test-progs/hello/bin/sparc/linux/hello
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gid=100
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input=cin
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output=cout
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pid=100
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ppid=99
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system=system
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uid=100
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[system.membus]
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type=Bus
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bus_id=0
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clock=1000
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width=64
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port=system.physmem.port system.cpu.l2cache.mem_side
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[system.physmem]
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type=PhysicalMemory
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file=
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latency=1
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range=0:134217727
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port=system.membus.port[0]
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[trace]
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bufsize=0
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cycle=0
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dump_on_exit=false
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file=cout
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flags=
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ignore=
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start=0
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227
tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out
Normal file
227
tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out
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@ -0,0 +1,227 @@
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[root]
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type=Root
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clock=1000000000000
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max_tick=0
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progress_interval=0
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output_file=cout
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[system.physmem]
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type=PhysicalMemory
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file=
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range=[0,134217727]
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latency=1
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[system]
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type=System
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physmem=system.physmem
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mem_mode=atomic
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[system.membus]
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type=Bus
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bus_id=0
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clock=1000
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width=64
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[system.cpu.dcache]
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type=BaseCache
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size=262144
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assoc=2
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block_size=64
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latency=1
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mshrs=10
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tgts_per_mshr=5
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write_buffers=8
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prioritizeRequests=false
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protocol=null
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trace_addr=0
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hash_delay=1
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repl=null
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compressed_bus=false
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store_compressed=false
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adaptive_compression=false
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compression_latency=0
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block_size=64
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max_miss_count=0
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addr_range=[0,18446744073709551615]
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split=false
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split_size=0
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lifo=false
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two_queue=false
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prefetch_miss=false
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prefetch_access=false
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prefetcher_size=100
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prefetch_past_page=false
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prefetch_serial_squash=false
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prefetch_latency=10
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prefetch_degree=1
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prefetch_policy=none
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prefetch_cache_check_push=true
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prefetch_use_cpu_id=true
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prefetch_data_accesses_only=false
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hit_latency=1
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[system.cpu.workload]
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type=LiveProcess
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cmd=hello
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executable=tests/test-progs/hello/bin/sparc/linux/hello
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input=cin
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output=cout
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env=
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system=system
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uid=100
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euid=100
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gid=100
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egid=100
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pid=100
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ppid=99
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[system.cpu]
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type=TimingSimpleCPU
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max_insts_any_thread=0
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max_insts_all_threads=0
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max_loads_any_thread=0
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max_loads_all_threads=0
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progress_interval=0
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mem=system.cpu.dcache
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system=system
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cpu_id=0
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workload=system.cpu.workload
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clock=1
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defer_registration=false
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// width not specified
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function_trace=false
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function_trace_start=0
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// simulate_stalls not specified
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[system.cpu.toL2Bus]
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type=Bus
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bus_id=0
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clock=1000
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width=64
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[system.cpu.icache]
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type=BaseCache
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size=131072
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assoc=2
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block_size=64
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latency=1
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mshrs=10
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tgts_per_mshr=5
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write_buffers=8
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prioritizeRequests=false
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protocol=null
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trace_addr=0
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hash_delay=1
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repl=null
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compressed_bus=false
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store_compressed=false
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adaptive_compression=false
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compression_latency=0
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block_size=64
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max_miss_count=0
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addr_range=[0,18446744073709551615]
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split=false
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split_size=0
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lifo=false
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two_queue=false
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prefetch_miss=false
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prefetch_access=false
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prefetcher_size=100
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prefetch_past_page=false
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prefetch_serial_squash=false
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prefetch_latency=10
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prefetch_degree=1
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prefetch_policy=none
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prefetch_cache_check_push=true
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prefetch_use_cpu_id=true
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prefetch_data_accesses_only=false
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hit_latency=1
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[system.cpu.l2cache]
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type=BaseCache
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size=2097152
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assoc=2
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block_size=64
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latency=1
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mshrs=10
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tgts_per_mshr=5
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write_buffers=8
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prioritizeRequests=false
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protocol=null
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trace_addr=0
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hash_delay=1
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repl=null
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compressed_bus=false
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store_compressed=false
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adaptive_compression=false
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compression_latency=0
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block_size=64
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max_miss_count=0
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addr_range=[0,18446744073709551615]
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split=false
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split_size=0
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lifo=false
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two_queue=false
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prefetch_miss=false
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prefetch_access=false
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prefetcher_size=100
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prefetch_past_page=false
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prefetch_serial_squash=false
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prefetch_latency=10
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prefetch_degree=1
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prefetch_policy=none
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prefetch_cache_check_push=true
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prefetch_use_cpu_id=true
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prefetch_data_accesses_only=false
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hit_latency=1
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[trace]
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flags=
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start=0
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cycle=0
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bufsize=0
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file=cout
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dump_on_exit=false
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ignore=
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[stats]
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descriptions=true
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project_name=test
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simulation_name=test
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simulation_sample=0
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text_file=m5stats.txt
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|
text_compat=true
|
||||||
|
mysql_db=
|
||||||
|
mysql_user=
|
||||||
|
mysql_password=
|
||||||
|
mysql_host=
|
||||||
|
events_start=-1
|
||||||
|
dump_reset=false
|
||||||
|
dump_cycle=0
|
||||||
|
dump_period=0
|
||||||
|
ignore_events=
|
||||||
|
|
||||||
|
[random]
|
||||||
|
seed=1
|
||||||
|
|
||||||
|
[exetrace]
|
||||||
|
speculative=true
|
||||||
|
print_cycle=true
|
||||||
|
print_opclass=true
|
||||||
|
print_thread=true
|
||||||
|
print_effaddr=true
|
||||||
|
print_data=true
|
||||||
|
print_iregs=false
|
||||||
|
print_fetchseq=false
|
||||||
|
print_cpseq=false
|
||||||
|
print_reg_delta=false
|
||||||
|
pc_symbol=true
|
||||||
|
intel_format=false
|
||||||
|
trace_system=client
|
||||||
|
|
||||||
|
[debug]
|
||||||
|
break_cycles=
|
||||||
|
|
||||||
|
[statsreset]
|
||||||
|
reset_cycle=0
|
||||||
|
|
214
tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt
Normal file
214
tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt
Normal file
|
@ -0,0 +1,214 @@
|
||||||
|
|
||||||
|
---------- Begin Simulation Statistics ----------
|
||||||
|
host_inst_rate 53689 # Simulator instruction rate (inst/s)
|
||||||
|
host_mem_usage 177104 # Number of bytes of host memory used
|
||||||
|
host_seconds 0.08 # Real time elapsed on the host
|
||||||
|
host_tick_rate 17808084 # Simulator tick rate (ticks/s)
|
||||||
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
|
sim_insts 4483 # Number of instructions simulated
|
||||||
|
sim_seconds 0.000001 # Number of seconds simulated
|
||||||
|
sim_ticks 1497001 # Number of ticks simulated
|
||||||
|
system.cpu.dcache.ReadReq_accesses 464 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.ReadReq_avg_miss_latency 3972.166667 # average ReadReq miss latency
|
||||||
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2972.166667 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.dcache.ReadReq_hits 410 # number of ReadReq hits
|
||||||
|
system.cpu.dcache.ReadReq_miss_latency 214497 # number of ReadReq miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_miss_rate 0.116379 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_latency 160497 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.116379 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.dcache.WriteReq_accesses 501 # number of WriteReq accesses(hits+misses)
|
||||||
|
system.cpu.dcache.WriteReq_avg_miss_latency 3980.840580 # average WriteReq miss latency
|
||||||
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2980.840580 # average WriteReq mshr miss latency
|
||||||
|
system.cpu.dcache.WriteReq_hits 432 # number of WriteReq hits
|
||||||
|
system.cpu.dcache.WriteReq_miss_latency 274678 # number of WriteReq miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_miss_rate 0.137725 # miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_misses 69 # number of WriteReq misses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_latency 205678 # number of WriteReq MSHR miss cycles
|
||||||
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.137725 # mshr miss rate for WriteReq accesses
|
||||||
|
system.cpu.dcache.WriteReq_mshr_misses 69 # number of WriteReq MSHR misses
|
||||||
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.dcache.avg_refs 6.845528 # Average number of references to valid blocks.
|
||||||
|
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.dcache.demand_accesses 965 # number of demand (read+write) accesses
|
||||||
|
system.cpu.dcache.demand_avg_miss_latency 3977.032520 # average overall miss latency
|
||||||
|
system.cpu.dcache.demand_avg_mshr_miss_latency 2977.032520 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.demand_hits 842 # number of demand (read+write) hits
|
||||||
|
system.cpu.dcache.demand_miss_latency 489175 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.dcache.demand_miss_rate 0.127461 # miss rate for demand accesses
|
||||||
|
system.cpu.dcache.demand_misses 123 # number of demand (read+write) misses
|
||||||
|
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.dcache.demand_mshr_miss_latency 366175 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.dcache.demand_mshr_miss_rate 0.127461 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.dcache.demand_mshr_misses 123 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.dcache.overall_accesses 965 # number of overall (read+write) accesses
|
||||||
|
system.cpu.dcache.overall_avg_miss_latency 3977.032520 # average overall miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_miss_latency 2977.032520 # average overall mshr miss latency
|
||||||
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.dcache.overall_hits 842 # number of overall hits
|
||||||
|
system.cpu.dcache.overall_miss_latency 489175 # number of overall miss cycles
|
||||||
|
system.cpu.dcache.overall_miss_rate 0.127461 # miss rate for overall accesses
|
||||||
|
system.cpu.dcache.overall_misses 123 # number of overall misses
|
||||||
|
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.dcache.overall_mshr_miss_latency 366175 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.dcache.overall_mshr_miss_rate 0.127461 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.dcache.overall_mshr_misses 123 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||||
|
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||||
|
system.cpu.dcache.replacements 0 # number of replacements
|
||||||
|
system.cpu.dcache.sampled_refs 123 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.dcache.tagsinuse 71.370810 # Cycle average of tags in use
|
||||||
|
system.cpu.dcache.total_refs 842 # Total number of references to valid blocks.
|
||||||
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.icache.ReadReq_accesses 4484 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.icache.ReadReq_avg_miss_latency 3979.178571 # average ReadReq miss latency
|
||||||
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2979.178571 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.icache.ReadReq_hits 4232 # number of ReadReq hits
|
||||||
|
system.cpu.icache.ReadReq_miss_latency 1002753 # number of ReadReq miss cycles
|
||||||
|
system.cpu.icache.ReadReq_miss_rate 0.056200 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_misses 252 # number of ReadReq misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_latency 750753 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.056200 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.icache.ReadReq_mshr_misses 252 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.icache.avg_refs 16.793651 # Average number of references to valid blocks.
|
||||||
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.icache.demand_accesses 4484 # number of demand (read+write) accesses
|
||||||
|
system.cpu.icache.demand_avg_miss_latency 3979.178571 # average overall miss latency
|
||||||
|
system.cpu.icache.demand_avg_mshr_miss_latency 2979.178571 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.demand_hits 4232 # number of demand (read+write) hits
|
||||||
|
system.cpu.icache.demand_miss_latency 1002753 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.icache.demand_miss_rate 0.056200 # miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_misses 252 # number of demand (read+write) misses
|
||||||
|
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.icache.demand_mshr_miss_latency 750753 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.icache.demand_mshr_miss_rate 0.056200 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.icache.demand_mshr_misses 252 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.icache.overall_accesses 4484 # number of overall (read+write) accesses
|
||||||
|
system.cpu.icache.overall_avg_miss_latency 3979.178571 # average overall miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_miss_latency 2979.178571 # average overall mshr miss latency
|
||||||
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.icache.overall_hits 4232 # number of overall hits
|
||||||
|
system.cpu.icache.overall_miss_latency 1002753 # number of overall miss cycles
|
||||||
|
system.cpu.icache.overall_miss_rate 0.056200 # miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_misses 252 # number of overall misses
|
||||||
|
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.icache.overall_mshr_miss_latency 750753 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.icache.overall_mshr_miss_rate 0.056200 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.icache.overall_mshr_misses 252 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||||
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||||
|
system.cpu.icache.replacements 0 # number of replacements
|
||||||
|
system.cpu.icache.sampled_refs 252 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.icache.tagsinuse 115.914677 # Cycle average of tags in use
|
||||||
|
system.cpu.icache.total_refs 4232 # Total number of references to valid blocks.
|
||||||
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
|
system.cpu.l2cache.ReadReq_accesses 375 # number of ReadReq accesses(hits+misses)
|
||||||
|
system.cpu.l2cache.ReadReq_avg_miss_latency 2986.473118 # average ReadReq miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1985.473118 # average ReadReq mshr miss latency
|
||||||
|
system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
|
||||||
|
system.cpu.l2cache.ReadReq_miss_latency 1110968 # number of ReadReq miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_miss_rate 0.992000 # miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_misses 372 # number of ReadReq misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 738596 # number of ReadReq MSHR miss cycles
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992000 # mshr miss rate for ReadReq accesses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_misses 372 # number of ReadReq MSHR misses
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||||
|
system.cpu.l2cache.avg_refs 0.008065 # Average number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||||
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
|
system.cpu.l2cache.demand_accesses 375 # number of demand (read+write) accesses
|
||||||
|
system.cpu.l2cache.demand_avg_miss_latency 2986.473118 # average overall miss latency
|
||||||
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 1985.473118 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
|
||||||
|
system.cpu.l2cache.demand_miss_latency 1110968 # number of demand (read+write) miss cycles
|
||||||
|
system.cpu.l2cache.demand_miss_rate 0.992000 # miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_misses 372 # number of demand (read+write) misses
|
||||||
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_latency 738596 # number of demand (read+write) MSHR miss cycles
|
||||||
|
system.cpu.l2cache.demand_mshr_miss_rate 0.992000 # mshr miss rate for demand accesses
|
||||||
|
system.cpu.l2cache.demand_mshr_misses 372 # number of demand (read+write) MSHR misses
|
||||||
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
|
system.cpu.l2cache.overall_accesses 375 # number of overall (read+write) accesses
|
||||||
|
system.cpu.l2cache.overall_avg_miss_latency 2986.473118 # average overall miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 1985.473118 # average overall mshr miss latency
|
||||||
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||||
|
system.cpu.l2cache.overall_hits 3 # number of overall hits
|
||||||
|
system.cpu.l2cache.overall_miss_latency 1110968 # number of overall miss cycles
|
||||||
|
system.cpu.l2cache.overall_miss_rate 0.992000 # miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_misses 372 # number of overall misses
|
||||||
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_latency 738596 # number of overall MSHR miss cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_miss_rate 0.992000 # mshr miss rate for overall accesses
|
||||||
|
system.cpu.l2cache.overall_mshr_misses 372 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||||
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||||
|
system.cpu.l2cache.replacements 0 # number of replacements
|
||||||
|
system.cpu.l2cache.sampled_refs 372 # Sample count of references to valid blocks.
|
||||||
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
|
system.cpu.l2cache.tagsinuse 185.896040 # Cycle average of tags in use
|
||||||
|
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
||||||
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||||
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
|
system.cpu.numCycles 1497001 # number of cpu cycles simulated
|
||||||
|
system.cpu.num_insts 4483 # Number of instructions executed
|
||||||
|
system.cpu.num_refs 965 # Number of memory references
|
||||||
|
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
||||||
|
|
||||||
|
---------- End Simulation Statistics ----------
|
|
@ -0,0 +1,3 @@
|
||||||
|
warn: More than two loadable segments in ELF object.
|
||||||
|
warn: Ignoring segment @ 0x0 length 0x0.
|
||||||
|
warn: Entering event queue @ 0. Starting simulation...
|
12
tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout
Normal file
12
tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout
Normal file
|
@ -0,0 +1,12 @@
|
||||||
|
Hello World!M5 Simulator System
|
||||||
|
|
||||||
|
Copyright (c) 2001-2006
|
||||||
|
The Regents of The University of Michigan
|
||||||
|
All Rights Reserved
|
||||||
|
|
||||||
|
|
||||||
|
M5 compiled Oct 23 2006 07:47:36
|
||||||
|
M5 started Mon Oct 23 07:47:41 2006
|
||||||
|
M5 executing on zeep
|
||||||
|
command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing
|
||||||
|
Exiting @ tick 1497001 because target called exit()
|
Loading…
Reference in a new issue