regressions: updates due to changes to o3 cpu, x86 memory map

2013-03-29 14:05:36 -05:00 · 2013-03-29 14:05:36 -05:00 · 26e96b90e1
commit 26e96b90e1
parent ac778b1d02
29 changed files with 3871 additions and 3868 deletions
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
@ -3,8 +3,8 @@ Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/ts
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 26 2013 14:38:52
+gem5 compiled Mar 28 2013 09:43:29
-gem5 started Mar 26 2013 23:18:50
+gem5 started Mar 28 2013 09:43:43
 gem5 executing on ribera.cs.wisc.edu
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
 Global frequency set at 1000000000000 ticks per second
@ -12,4 +12,4 @@ info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 110215000
-Exiting @ tick 1900727015500 because m5_exit instruction encountered
+Exiting @ tick 1900727697500 because m5_exit instruction encountered
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
@ -3,8 +3,8 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 26 2013 15:15:23
+gem5 compiled Mar 28 2013 10:14:03
-gem5 started Mar 27 2013 01:26:55
+gem5 started Mar 28 2013 10:14:28
 gem5 executing on ribera.cs.wisc.edu
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
 Global frequency set at 1000000000000 ticks per second
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
@ -4,11 +4,11 @@ sim_seconds                                  2.533115                       # Nu
 sim_ticks                                2533114761500                       # Number of ticks simulated
 final_tick                               2533114761500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  19921                       # Simulator instruction rate (inst/s)
+host_inst_rate                                  40037                       # Simulator instruction rate (inst/s)
-host_op_rate                                    25633                       # Simulator op (including micro ops) rate (op/s)
+host_op_rate                                    51517                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              836738491                       # Simulator tick rate (ticks/s)
+host_tick_rate                             1681683677                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 439300                       # Number of bytes of host memory used
+host_mem_usage                                 439348                       # Number of bytes of host memory used
-host_seconds                                  3027.37                       # Real time elapsed on the host
+host_seconds                                  1506.30                       # Real time elapsed on the host
 sim_insts                                    60307912                       # Number of instructions simulated
 sim_ops                                      77599507                       # Number of ops (including micro ops) simulated
 system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
@ -570,7 +570,7 @@ system.cpu.int_regfile_reads                550176561                       # nu
 system.cpu.int_regfile_writes                88426578                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                      8298                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                     2914                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                30118912                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                30119271                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                 831902                       # number of misc regfile writes
 system.cpu.icache.replacements                 980182                       # number of replacements
 system.cpu.icache.tagsinuse                511.616610                       # Cycle average of tags in use
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
@ -3,8 +3,8 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 26 2013 15:15:23
+gem5 compiled Mar 28 2013 10:14:03
-gem5 started Mar 27 2013 02:41:12
+gem5 started Mar 28 2013 10:17:38
 gem5 executing on ribera.cs.wisc.edu
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
 Global frequency set at 1000000000000 ticks per second
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@ -4,11 +4,11 @@ sim_seconds                                  2.602779                       # Nu
 sim_ticks                                2602778916500                       # Number of ticks simulated
 final_tick                               2602778916500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  24161                       # Simulator instruction rate (inst/s)
+host_inst_rate                                  48820                       # Simulator instruction rate (inst/s)
-host_op_rate                                    31106                       # Simulator op (including micro ops) rate (op/s)
+host_op_rate                                    62855                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1001764915                       # Simulator tick rate (ticks/s)
+host_tick_rate                             2024215186                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 444424                       # Number of bytes of host memory used
+host_mem_usage                                 443440                       # Number of bytes of host memory used
-host_seconds                                  2598.19                       # Real time elapsed on the host
+host_seconds                                  1285.82                       # Real time elapsed on the host
 sim_insts                                    62774383                       # Number of instructions simulated
 sim_ops                                      80820330                       # Number of ops (including micro ops) simulated
 system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
@ -993,7 +993,7 @@ system.cpu0.int_regfile_reads               174070948                       # nu
 system.cpu0.int_regfile_writes               34592870                       # number of integer regfile writes
 system.cpu0.fp_regfile_reads                     3226                       # number of floating regfile reads
 system.cpu0.fp_regfile_writes                     898                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads               13195358                       # number of misc regfile reads
+system.cpu0.misc_regfile_reads               13196303                       # number of misc regfile reads
 system.cpu0.misc_regfile_writes                457522                       # number of misc regfile writes
 system.cpu0.icache.replacements                399011                       # number of replacements
 system.cpu0.icache.tagsinuse               511.581015                       # Cycle average of tags in use
@ -1568,7 +1568,7 @@ system.cpu1.int_regfile_reads               393458890                       # nu
 system.cpu1.int_regfile_writes               57301820                       # number of integer regfile writes
 system.cpu1.fp_regfile_reads                     4905                       # number of floating regfile reads
 system.cpu1.fp_regfile_writes                    2316                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads               18908919                       # number of misc regfile reads
+system.cpu1.misc_regfile_reads               18909839                       # number of misc regfile reads
 system.cpu1.misc_regfile_writes                419175                       # number of misc regfile writes
 system.cpu1.icache.replacements                613709                       # number of replacements
 system.cpu1.icache.tagsinuse               498.827741                       # Cycle average of tags in use
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
@ -3,8 +3,8 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 26 2013 15:15:23
+gem5 compiled Mar 28 2013 10:14:03
-gem5 started Mar 27 2013 02:43:56
+gem5 started Mar 28 2013 10:15:55
 gem5 executing on ribera.cs.wisc.edu
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
 Global frequency set at 1000000000000 ticks per second
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@ -4,11 +4,11 @@ sim_seconds                                  2.533115                       # Nu
 sim_ticks                                2533114761500                       # Number of ticks simulated
 final_tick                               2533114761500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  24105                       # Simulator instruction rate (inst/s)
+host_inst_rate                                  48903                       # Simulator instruction rate (inst/s)
-host_op_rate                                    31016                       # Simulator op (including micro ops) rate (op/s)
+host_op_rate                                    62925                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1012479744                       # Simulator tick rate (ticks/s)
+host_tick_rate                             2054075271                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 439308                       # Number of bytes of host memory used
+host_mem_usage                                 439344                       # Number of bytes of host memory used
-host_seconds                                  2501.89                       # Real time elapsed on the host
+host_seconds                                  1233.21                       # Real time elapsed on the host
 sim_insts                                    60307912                       # Number of instructions simulated
 sim_ops                                      77599507                       # Number of ops (including micro ops) simulated
 system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
@ -525,7 +525,7 @@ system.cpu.int_regfile_reads                550176555                       # nu
 system.cpu.int_regfile_writes                88426576                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                      8298                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                     2914                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                30118912                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                30119271                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                 831902                       # number of misc regfile writes
 system.cpu.icache.replacements                 980182                       # number of replacements
 system.cpu.icache.tagsinuse                511.616610                       # Cycle average of tags in use
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout
@ -3,8 +3,8 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 26 2013 15:15:23
+gem5 compiled Mar 28 2013 10:14:03
-gem5 started Mar 27 2013 02:07:42
+gem5 started Mar 28 2013 10:14:28
 gem5 executing on ribera.cs.wisc.edu
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
 Global frequency set at 1000000000000 ticks per second
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
@ -4,11 +4,11 @@ sim_seconds                                  2.400708                       # Nu
 sim_ticks                                2400708253000                       # Number of ticks simulated
 final_tick                               2400708253000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  71724                       # Simulator instruction rate (inst/s)
+host_inst_rate                                 141448                       # Simulator instruction rate (inst/s)
-host_op_rate                                    92116                       # Simulator op (including micro ops) rate (op/s)
+host_op_rate                                   181662                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2854182500                       # Simulator tick rate (ticks/s)
+host_tick_rate                             5628731106                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 441348                       # Number of bytes of host memory used
+host_mem_usage                                 441396                       # Number of bytes of host memory used
-host_seconds                                   841.12                       # Real time elapsed on the host
+host_seconds                                   426.51                       # Real time elapsed on the host
 sim_insts                                    60328852                       # Number of instructions simulated
 sim_ops                                      77480507                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::realview.clcd    114819072                       # Number of bytes read from this memory
@ -1520,7 +1520,7 @@ system.cpu2.int_regfile_reads               153783407                       # nu
 system.cpu2.int_regfile_writes               29255277                       # number of integer regfile writes
 system.cpu2.fp_regfile_reads                    22374                       # number of floating regfile reads
 system.cpu2.fp_regfile_writes                   20830                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                9021581                       # number of misc regfile reads
+system.cpu2.misc_regfile_reads                9021591                       # number of misc regfile reads
 system.cpu2.misc_regfile_writes                240632                       # number of misc regfile writes
 system.iocache.replacements                         0                       # number of replacements
 system.iocache.tagsinuse                            0                       # Cycle average of tags in use
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout
@ -3,8 +3,8 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 26 2013 15:15:23
+gem5 compiled Mar 28 2013 10:14:03
-gem5 started Mar 27 2013 02:19:45
+gem5 started Mar 28 2013 10:14:28
 gem5 executing on ribera.cs.wisc.edu
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
 Global frequency set at 1000000000000 ticks per second
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
@ -4,11 +4,11 @@ sim_seconds                                  2.543226                       # Nu
 sim_ticks                                2543226083000                       # Number of ticks simulated
 final_tick                               2543226083000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  24298                       # Simulator instruction rate (inst/s)
+host_inst_rate                                  48764                       # Simulator instruction rate (inst/s)
-host_op_rate                                    31265                       # Simulator op (including micro ops) rate (op/s)
+host_op_rate                                    62745                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1024641665                       # Simulator tick rate (ticks/s)
+host_tick_rate                             2056325427                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 442376                       # Number of bytes of host memory used
+host_mem_usage                                 443444                       # Number of bytes of host memory used
-host_seconds                                  2482.06                       # Real time elapsed on the host
+host_seconds                                  1236.78                       # Real time elapsed on the host
 sim_insts                                    60309820                       # Number of instructions simulated
 sim_ops                                      77602107                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
@ -938,7 +938,7 @@ system.cpu0.int_regfile_reads               282333154                       # nu
 system.cpu0.int_regfile_writes               45811922                       # number of integer regfile writes
 system.cpu0.fp_regfile_reads                    22666                       # number of floating regfile reads
 system.cpu0.fp_regfile_writes                   19880                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads               15681131                       # number of misc regfile reads
+system.cpu0.misc_regfile_reads               15681354                       # number of misc regfile reads
 system.cpu0.misc_regfile_writes                434463                       # number of misc regfile writes
 system.cpu0.icache.replacements                984470                       # number of replacements
 system.cpu0.icache.tagsinuse               511.608417                       # Cycle average of tags in use
@ -1626,7 +1626,7 @@ system.cpu1.int_regfile_reads               267548470                       # nu
 system.cpu1.int_regfile_writes               42457075                       # number of integer regfile writes
 system.cpu1.fp_regfile_reads                    22098                       # number of floating regfile reads
 system.cpu1.fp_regfile_writes                   19630                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads               14600078                       # number of misc regfile reads
+system.cpu1.misc_regfile_reads               14600215                       # number of misc regfile reads
 system.cpu1.misc_regfile_writes                398004                       # number of misc regfile writes
 system.iocache.replacements                         0                       # number of replacements
 system.iocache.tagsinuse                            0                       # Cycle average of tags in use
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
@ -600,17 +600,23 @@ type=ExeTracer
 [system.e820_table]
 type=X86E820Table
-children=entries0 entries1
+children=entries0 entries1 entries2
-entries=system.e820_table.entries0 system.e820_table.entries1
+entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2
 [system.e820_table.entries0]
 type=X86E820Entry
 addr=0
-range_type=2
+range_type=1
-size=1048576
+size=654336
 [system.e820_table.entries1]
 type=X86E820Entry
 addr=654336
 range_type=2
 size=394240
 [system.e820_table.entries2]
 type=X86E820Entry
 addr=1048576
 range_type=1
 size=133169152
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
@ -5,7 +5,6 @@ warn: Sockets disabled, not accepting gdb connections
 warn: Don't know what interrupt to clear for console.
 warn: x86 cpuid: unknown family 0xbacc
 warn: x86 cpuid: unknown family 0xbacc
 warn: x86 cpuid: unknown family 0xbacc
 warn: instruction 'fxsave' unimplemented
 warn: x86 cpuid: unknown family 0x8086
 warn: x86 cpuid: unknown family 0x8086
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
@ -3,12 +3,12 @@ Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 26 2013 15:13:59
+gem5 compiled Mar 28 2013 09:59:18
-gem5 started Mar 27 2013 00:32:51
+gem5 started Mar 28 2013 09:59:39
 gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5132865528000 because m5_exit instruction encountered
+Exiting @ tick 5132969930500 because m5_exit instruction encountered
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
@ -16,7 +16,7 @@ e820_table=system.e820_table
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/panfs/panasas-01.cs.wisc.edu/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
 load_addr_mask=18446744073709551615
 mem_mode=timing
 mem_ranges=0:134217727
@ -195,17 +195,23 @@ type=ExeTracer
 [system.e820_table]
 type=X86E820Table
-children=entries0 entries1
+children=entries0 entries1 entries2
-entries=system.e820_table.entries0 system.e820_table.entries1
+entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2
 [system.e820_table.entries0]
 type=X86E820Entry
 addr=0
-range_type=2
+range_type=1
-size=1048576
+size=654336
 [system.e820_table.entries1]
 type=X86E820Entry
 addr=654336
 range_type=2
 size=394240
 [system.e820_table.entries2]
 type=X86E820Entry
 addr=1048576
 range_type=1
 size=133169152
@ -818,7 +824,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
-image_file=/panfs/panasas-01.cs.wisc.edu/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
 read_only=true
 [system.pc.south_bridge.ide.disks1]
@ -838,7 +844,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
-image_file=/panfs/panasas-01.cs.wisc.edu/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 [system.pc.south_bridge.int_lines0]
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
@ -1,26 +1,26 @@
-Real time: Feb/02/2013 09:14:12
+Real time: Mar/28/2013 10:19:36
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 436
+Elapsed_time_in_seconds: 824
-Elapsed_time_in_minutes: 7.26667
+Elapsed_time_in_minutes: 13.7333
-Elapsed_time_in_hours: 0.121111
+Elapsed_time_in_hours: 0.228889
-Elapsed_time_in_days: 0.0050463
+Elapsed_time_in_days: 0.00953704
-Virtual_time_in_seconds: 433.18
+Virtual_time_in_seconds: 785.96
-Virtual_time_in_minutes: 7.21967
+Virtual_time_in_minutes: 13.0993
-Virtual_time_in_hours:   0.120328
+Virtual_time_in_hours:   0.218322
-Virtual_time_in_days:    0.00501366
+Virtual_time_in_days:    0.00909676
-Ruby_current_time: 10409965061
+Ruby_current_time: 10416271238
 Ruby_start_time: 0
-Ruby_cycles: 10409965061
+Ruby_cycles: 10416271238
-mbytes_resident: 588.68
+mbytes_resident: 597.965
-mbytes_total: 829.668
+mbytes_total: 848.508
-resident_ratio: 0.709551
+resident_ratio: 0.704734
-ruby_cycles_executed: [ 10409965062 10409965062 ]
+ruby_cycles_executed: [ 10416271239 10416271239 ]
 Busy Controller Counts:
 L1Cache-0:0  L1Cache-1:0  
@ -30,18 +30,18 @@ DMA-0:0
 Busy Bank Count:0
-sequencer_requests_outstanding: [binsize: 1 max: 2 count: 154388627 average: 1.00012 | standard deviation: 0.0108509 | 0 154370447 18180 ]
+sequencer_requests_outstanding: [binsize: 1 max: 2 count: 151895075 average: 1.00011 | standard deviation: 0.0104983 | 0 151878333 16742 ]
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
-miss_latency: [binsize: 2 max: 263 count: 154388626 average: 3.45295 | standard deviation: 5.08093 | 0 151691060 0 0 0 0 0 0 0 932074 1700 1471491 1386 91484 1411 25274 359 175 10 52 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3366 5595 7267 9460 50995 170 509 87 93 127 5 22 5 6 11 7 11 5 8 21 3 15 7 8 14 12 467 4221 10035 17511 13265 42618 770 863 2296 301 820 9 29 31 16 29 22 21 60 9 34 12 15 39 13 22 17 19 28 73 118 136 139 258 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 2 max: 270 count: 151895074 average: 3.45632 | standard deviation: 5.15571 | 0 149239942 0 0 0 0 0 0 0 967471 601 1437653 515 54191 578 16215 159 100 5 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3728 6095 8851 10338 50892 181 524 114 95 129 11 19 5 10 11 7 17 11 13 20 10 22 6 8 20 12 460 4446 10447 18595 13927 42308 850 876 2239 314 825 19 13 50 26 40 9 27 54 19 22 11 23 46 13 18 16 21 30 78 155 130 157 221 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 2 max: 216 count: 15287660 average: 5.10329 | standard deviation: 8.51802 | 0 13851030 0 0 0 0 0 0 0 114273 254 1245086 851 32917 901 11066 297 137 7 51 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 906 733 2346 2626 1955 53 89 31 23 28 1 1 1 1 2 2 3 2 5 2 1 2 5 1 0 5 0 1358 2851 4652 6044 5789 287 265 232 122 109 1 14 3 7 5 8 8 4 4 4 6 2 4 7 8 4 4 7 24 17 51 40 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 2 max: 218 count: 14874061 average: 5.10543 | standard deviation: 8.68005 | 0 13485161 0 0 0 0 0 0 0 129669 71 1200389 321 19342 354 4658 120 69 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 946 797 3688 3455 2377 59 103 45 35 24 6 0 1 3 5 3 8 4 3 2 5 4 5 2 7 3 3 1340 2962 4560 6434 5662 323 275 230 120 126 7 4 3 16 9 3 17 8 8 3 7 7 6 3 3 5 5 12 23 21 44 49 12 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 2 max: 263 count: 9717541 average: 5.12153 | standard deviation: 15.1014 | 0 9364158 0 0 0 0 0 0 0 26589 30 173008 277 26750 293 2179 37 9 2 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 752 3237 3695 6369 48930 84 395 41 60 99 4 19 3 1 9 4 7 2 1 19 2 12 0 4 12 4 465 856 2775 8650 6848 36461 339 481 1953 169 701 7 12 27 7 23 5 9 52 3 25 2 11 33 5 12 6 12 17 15 67 61 98 232 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 2 max: 270 count: 9471875 average: 5.1858 | standard deviation: 15.4023 | 0 9121731 0 0 0 0 0 0 0 27134 22 181251 122 14247 125 1633 27 16 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 780 3347 3709 6401 48396 97 398 53 53 99 4 17 4 4 4 3 7 5 7 15 3 18 1 5 10 6 457 1055 3050 9771 7123 36234 361 508 1904 182 686 8 8 45 4 27 3 7 43 7 17 3 13 40 5 12 5 11 15 22 105 69 105 209 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 2 max: 212 count: 128176357 average: 3.11389 | standard deviation: 1.98121 | 0 127382579 0 0 0 0 0 0 0 775132 1367 1483 160 160 47 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1608 1524 785 35 36 16 21 9 3 0 0 2 1 4 0 1 1 1 2 0 0 1 1 3 1 2 2 1994 4324 4157 217 167 139 103 109 1 7 1 3 0 2 1 9 4 4 1 5 4 2 2 1 2 7 3 4 34 34 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 2 max: 213 count: 126380154 average: 3.11846 | standard deviation: 2.02437 | 0 125567964 0 0 0 0 0 0 0 794781 477 434 39 45 17 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1899 1850 989 40 49 13 20 10 1 5 1 2 0 2 1 1 2 1 1 3 0 0 0 1 2 2 0 2035 4358 4208 198 205 161 86 103 7 4 4 1 2 6 4 3 3 3 4 1 1 2 0 5 2 6 5 2 33 28 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_RMW_Read: [binsize: 2 max: 214 count: 522204 average: 6.16903 | standard deviation: 9.47337 | 0 450068 0 0 0 0 0 0 0 10580 41 32976 18 17714 78 9308 10 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 77 84 382 378 52 13 4 6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 9 66 17 117 166 2 10 2 9 2 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_RMW_Read: [binsize: 2 max: 214 count: 490994 average: 6.03795 | standard deviation: 9.42736 | 0 425859 0 0 0 0 0 0 0 10420 25 32755 15 11997 35 8470 5 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83 81 392 393 46 9 3 4 5 1 0 0 0 1 0 0 0 1 2 0 2 0 0 0 1 1 0 8 55 15 120 161 1 4 2 4 9 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_Locked_RMW_Read: [binsize: 2 max: 216 count: 342432 average: 5.6474 | standard deviation: 7.89999 | 0 300793 0 0 0 0 0 0 0 5500 8 18938 80 13943 92 2721 15 19 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 17 59 52 22 4 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 19 35 39 35 3 4 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_Locked_RMW_Read: [binsize: 2 max: 212 count: 338995 average: 5.4473 | standard deviation: 7.76902 | 0 300232 0 0 0 0 0 0 0 5467 6 22824 18 8560 47 1454 7 6 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 20 73 49 24 3 0 2 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 8 22 41 52 46 4 3 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 342432 average:     3 | standard deviation: 0 | 0 0 0 342432 ]
+miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 338995 average:     3 | standard deviation: 0 | 0 0 0 338995 ]
-miss_latency_NULL: [binsize: 2 max: 263 count: 154388626 average: 3.45295 | standard deviation: 5.08093 | 0 151691060 0 0 0 0 0 0 0 932074 1700 1471491 1386 91484 1411 25274 359 175 10 52 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3366 5595 7267 9460 50995 170 509 87 93 127 5 22 5 6 11 7 11 5 8 21 3 15 7 8 14 12 467 4221 10035 17511 13265 42618 770 863 2296 301 820 9 29 31 16 29 22 21 60 9 34 12 15 39 13 22 17 19 28 73 118 136 139 258 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_NULL: [binsize: 2 max: 270 count: 151895074 average: 3.45632 | standard deviation: 5.15571 | 0 149239942 0 0 0 0 0 0 0 967471 601 1437653 515 54191 578 16215 159 100 5 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3728 6095 8851 10338 50892 181 524 114 95 129 11 19 5 10 11 7 17 11 13 20 10 22 6 8 20 12 460 4446 10447 18595 13927 42308 850 876 2239 314 825 19 13 50 26 40 9 27 54 19 22 11 23 46 13 18 16 21 30 78 155 130 157 221 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@ -52,12 +52,12 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
 miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 imcomplete_dir_Times: 0
-miss_latency_LD_NULL: [binsize: 2 max: 216 count: 15287660 average: 5.10329 | standard deviation: 8.51802 | 0 13851030 0 0 0 0 0 0 0 114273 254 1245086 851 32917 901 11066 297 137 7 51 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 906 733 2346 2626 1955 53 89 31 23 28 1 1 1 1 2 2 3 2 5 2 1 2 5 1 0 5 0 1358 2851 4652 6044 5789 287 265 232 122 109 1 14 3 7 5 8 8 4 4 4 6 2 4 7 8 4 4 7 24 17 51 40 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_NULL: [binsize: 2 max: 218 count: 14874061 average: 5.10543 | standard deviation: 8.68005 | 0 13485161 0 0 0 0 0 0 0 129669 71 1200389 321 19342 354 4658 120 69 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 946 797 3688 3455 2377 59 103 45 35 24 6 0 1 3 5 3 8 4 3 2 5 4 5 2 7 3 3 1340 2962 4560 6434 5662 323 275 230 120 126 7 4 3 16 9 3 17 8 8 3 7 7 6 3 3 5 5 12 23 21 44 49 12 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_NULL: [binsize: 2 max: 263 count: 9717541 average: 5.12153 | standard deviation: 15.1014 | 0 9364158 0 0 0 0 0 0 0 26589 30 173008 277 26750 293 2179 37 9 2 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 752 3237 3695 6369 48930 84 395 41 60 99 4 19 3 1 9 4 7 2 1 19 2 12 0 4 12 4 465 856 2775 8650 6848 36461 339 481 1953 169 701 7 12 27 7 23 5 9 52 3 25 2 11 33 5 12 6 12 17 15 67 61 98 232 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_NULL: [binsize: 2 max: 270 count: 9471875 average: 5.1858 | standard deviation: 15.4023 | 0 9121731 0 0 0 0 0 0 0 27134 22 181251 122 14247 125 1633 27 16 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 780 3347 3709 6401 48396 97 398 53 53 99 4 17 4 4 4 3 7 5 7 15 3 18 1 5 10 6 457 1055 3050 9771 7123 36234 361 508 1904 182 686 8 8 45 4 27 3 7 43 7 17 3 13 40 5 12 5 11 15 22 105 69 105 209 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH_NULL: [binsize: 2 max: 212 count: 128176357 average: 3.11389 | standard deviation: 1.98121 | 0 127382579 0 0 0 0 0 0 0 775132 1367 1483 160 160 47 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1608 1524 785 35 36 16 21 9 3 0 0 2 1 4 0 1 1 1 2 0 0 1 1 3 1 2 2 1994 4324 4157 217 167 139 103 109 1 7 1 3 0 2 1 9 4 4 1 5 4 2 2 1 2 7 3 4 34 34 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH_NULL: [binsize: 2 max: 213 count: 126380154 average: 3.11846 | standard deviation: 2.02437 | 0 125567964 0 0 0 0 0 0 0 794781 477 434 39 45 17 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1899 1850 989 40 49 13 20 10 1 5 1 2 0 2 1 1 2 1 1 3 0 0 0 1 2 2 0 2035 4358 4208 198 205 161 86 103 7 4 4 1 2 6 4 3 3 3 4 1 1 2 0 5 2 6 5 2 33 28 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_RMW_Read_NULL: [binsize: 2 max: 214 count: 522204 average: 6.16903 | standard deviation: 9.47337 | 0 450068 0 0 0 0 0 0 0 10580 41 32976 18 17714 78 9308 10 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 77 84 382 378 52 13 4 6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 9 66 17 117 166 2 10 2 9 2 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_RMW_Read_NULL: [binsize: 2 max: 214 count: 490994 average: 6.03795 | standard deviation: 9.42736 | 0 425859 0 0 0 0 0 0 0 10420 25 32755 15 11997 35 8470 5 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83 81 392 393 46 9 3 4 5 1 0 0 0 1 0 0 0 1 2 0 2 0 0 0 1 1 0 8 55 15 120 161 1 4 2 4 9 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_Locked_RMW_Read_NULL: [binsize: 2 max: 216 count: 342432 average: 5.6474 | standard deviation: 7.89999 | 0 300793 0 0 0 0 0 0 0 5500 8 18938 80 13943 92 2721 15 19 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 17 59 52 22 4 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 19 35 39 35 3 4 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_Locked_RMW_Read_NULL: [binsize: 2 max: 212 count: 338995 average: 5.4473 | standard deviation: 7.76902 | 0 300232 0 0 0 0 0 0 0 5467 6 22824 18 8560 47 1454 7 6 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 20 73 49 24 3 0 2 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 8 22 41 52 46 4 3 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 342432 average:     3 | standard deviation: 0 | 0 0 0 342432 ]
+miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 338995 average:     3 | standard deviation: 0 | 0 0 0 338995 ]
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@ -71,10 +71,10 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
 Message Delayed Cycles
 ----------------------
-Total_delay_cycles: [binsize: 1 max: 13 count: 11148256 average: 0.604022 | standard deviation: 1.43415 | 9463853 2800 1710 2621 1672785 2644 328 252 266 847 12 8 32 98 ]
+Total_delay_cycles: [binsize: 1 max: 19 count: 10868463 average: 0.59509 | standard deviation: 1.42425 | 9251200 1053 635 975 1612868 1042 121 110 109 275 4 9 9 51 0 0 1 0 0 1 ]
-  virtual_network_0_delay_cycles: [binsize: 1 max: 13 count: 6239603 average: 1.0483 | standard deviation: 1.76244 | 4605589 1196 497 650 1627478 2413 310 248 251 821 12 8 32 98 ]
+  virtual_network_0_delay_cycles: [binsize: 1 max: 19 count: 6100210 average: 1.0435 | standard deviation: 1.75778 | 4509207 549 222 262 1588385 908 120 110 101 271 4 9 9 51 0 0 1 0 0 1 ]
-  virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4783107 average: 0.0397315 | standard deviation: 0.393864 | 4733754 1343 974 1793 45008 175 18 4 15 23 ]
+  virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4687708 average: 0.0215679 | standard deviation: 0.291665 | 4661845 408 333 614 24389 107 1 0 8 3 ]
-  virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 125546 average: 0.0221114 | standard deviation: 0.270483 | 124510 261 239 178 299 56 0 0 0 3 ]
+  virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 80545 average: 0.0133217 | standard deviation: 0.21003 | 80148 96 80 99 94 27 0 0 0 1 ]
  virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
  virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
  virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@ -86,82 +86,82 @@ Total_delay_cycles: [binsize: 1 max: 13 count: 11148256 average: 0.604022 | stan
 Resource Usage
 --------------
 page_size: 4096
-user_time: 432
+user_time: 784
-system_time: 0
+system_time: 1
-page_reclaims: 142268
+page_reclaims: 148403
-page_faults: 18
+page_faults: 35
 swaps: 0
-block_inputs: 28312
+block_inputs: 20600
-block_outputs: 488
+block_outputs: 736
 Network Stats
 -------------
-total_msg_count_Control: 8609139 68873112
+total_msg_count_Control: 8498316 67986528
-total_msg_count_Request_Control: 374943 2999544
+total_msg_count_Request_Control: 239871 1918968
-total_msg_count_Response_Data: 8904543 641127096
+total_msg_count_Response_Data: 8796423 633342456
-total_msg_count_Response_Control: 11255934 90047472
+total_msg_count_Response_Control: 10879743 87037944
-total_msg_count_Writeback_Data: 4892277 352243944
+total_msg_count_Writeback_Data: 4769004 343368288
-total_msg_count_Writeback_Control: 242529 1940232
+total_msg_count_Writeback_Control: 289518 2316144
-total_msgs: 34279365 total_bytes: 1157231400
+total_msgs: 33472875 total_bytes: 1135970328
 switch_0_inlinks: 2
 switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.0914404
+links_utilized_percent_switch_0: 0.0315382
-  links_utilized_percent_switch_0_link_0: 0.0993566 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_0_link_0: 0.037253 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_0_link_1: 0.0835243 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_0_link_1: 0.0258234 bw: 16000 base_latency: 1
-  outgoing_messages_switch_0_link_0_Request_Control: 66161 529288 [ 66161 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Request_Control: 41862 334896 [ 41862 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Response_Data: 2118925 152562600 [ 0 2118925 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Data: 805815 58018680 [ 0 805815 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Response_Control: 1549490 12395920 [ 0 1549490 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Control: 466550 3732400 [ 0 466550 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Control: 2137842 17102736 [ 2137842 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Control: 817583 6540664 [ 817583 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Response_Data: 60657 4367304 [ 0 60657 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Data: 39381 2835432 [ 0 39381 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Response_Control: 1598105 12784840 [ 0 28048 1570057 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Control: 495523 3964184 [ 0 15983 479540 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Writeback_Data: 1449700 104378400 [ 1449590 110 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Writeback_Data: 408673 29424456 [ 408575 98 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Writeback_Control: 60538 484304 [ 60538 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Writeback_Control: 34072 272576 [ 34072 0 0 0 0 0 0 0 0 0 ] base_latency: 1
 switch_1_inlinks: 2
 switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.0196015
+links_utilized_percent_switch_1: 0.0764968
-  links_utilized_percent_switch_1_link_0: 0.0247433 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_1_link_0: 0.0852244 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_1_link_1: 0.0144596 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_1_link_1: 0.0677692 bw: 16000 base_latency: 1
-  outgoing_messages_switch_1_link_0_Request_Control: 59385 475080 [ 59385 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Request_Control: 38683 309464 [ 38683 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Response_Data: 538648 38782656 [ 0 538648 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Response_Data: 1828030 131618160 [ 0 1828030 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Response_Control: 244326 1954608 [ 0 244326 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Response_Control: 1263466 10107728 [ 0 1263466 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Control: 559724 4477792 [ 559724 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Control: 1837549 14700392 [ 1837549 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Data: 57458 4136976 [ 0 57458 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Data: 32554 2343888 [ 0 32554 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Control: 283798 2270384 [ 0 23090 260708 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Control: 1296124 10368992 [ 0 16536 1279588 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Data: 181059 13036248 [ 180839 220 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Data: 1180995 85031640 [ 1180869 126 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Control: 20305 162440 [ 20305 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Control: 62434 499472 [ 62434 0 0 0 0 0 0 0 0 0 ] base_latency: 1
 switch_2_inlinks: 2
 switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0.114092
+links_utilized_percent_switch_2: 0.112511
-  links_utilized_percent_switch_2_link_0: 0.102531 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_2_link_0: 0.0996306 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_2_link_1: 0.125652 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_2_link_1: 0.125392 bw: 16000 base_latency: 1
-  outgoing_messages_switch_2_link_0_Control: 2697566 21580528 [ 2697566 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Control: 2655132 21241056 [ 2655132 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Response_Data: 216184 15565248 [ 0 216184 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Data: 201773 14527656 [ 0 201773 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Response_Control: 1945969 15567752 [ 0 115204 1830765 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Control: 1880978 15047824 [ 0 121850 1759128 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Writeback_Data: 1630759 117414648 [ 1630429 330 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Data: 1589668 114456096 [ 1589444 224 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Writeback_Control: 80843 646744 [ 80843 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Control: 96506 772048 [ 96506 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Control: 172147 1377176 [ 172147 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Control: 177640 1421120 [ 177640 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Request_Control: 123851 990808 [ 123851 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Request_Control: 78781 630248 [ 78781 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Response_Data: 2677919 192810168 [ 0 2677919 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Data: 2682566 193144752 [ 0 2682566 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Response_Control: 1763458 14107664 [ 0 1763458 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Control: 1722824 13782592 [ 0 1722824 0 0 0 0 0 0 0 0 ] base_latency: 1
 switch_3_inlinks: 2
 switch_3_outlinks: 2
-links_utilized_percent_switch_3: 0.00646039
+links_utilized_percent_switch_3: 0.00665498
-  links_utilized_percent_switch_3_link_0: 0.00496714 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_3_link_0: 0.00509748 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_3_link_1: 0.00795363 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_3_link_1: 0.00821249 bw: 16000 base_latency: 1
-  outgoing_messages_switch_3_link_0_Control: 172147 1377176 [ 172147 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Control: 177640 1421120 [ 177640 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Response_Data: 94424 6798528 [ 0 94424 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Response_Data: 96523 6949656 [ 0 96523 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Response_Control: 12193 97544 [ 0 12193 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Response_Control: 15587 124696 [ 0 15587 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Response_Data: 172147 12394584 [ 0 172147 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Data: 177640 12790080 [ 0 177640 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Response_Control: 106617 852936 [ 0 106617 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Control: 112110 896880 [ 0 112110 0 0 0 0 0 0 0 0 ] base_latency: 1
 switch_4_inlinks: 2
 switch_4_outlinks: 2
@ -172,117 +172,117 @@ links_utilized_percent_switch_4: 0
 switch_5_inlinks: 5
 switch_5_outlinks: 5
-links_utilized_percent_switch_5: 0.0463196
+links_utilized_percent_switch_5: 0.0454411
-  links_utilized_percent_switch_5_link_0: 0.0993566 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_5_link_0: 0.037253 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_5_link_1: 0.0247433 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_5_link_1: 0.0852244 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_5_link_2: 0.102531 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_5_link_2: 0.0996306 bw: 16000 base_latency: 1
-  links_utilized_percent_switch_5_link_3: 0.00496714 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_5_link_3: 0.00509748 bw: 16000 base_latency: 1
  links_utilized_percent_switch_5_link_4: 0 bw: 16000 base_latency: 1
-  outgoing_messages_switch_5_link_0_Request_Control: 66161 529288 [ 66161 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Request_Control: 41862 334896 [ 41862 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Response_Data: 2118925 152562600 [ 0 2118925 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Response_Data: 805815 58018680 [ 0 805815 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Response_Control: 1549490 12395920 [ 0 1549490 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Response_Control: 466550 3732400 [ 0 466550 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Request_Control: 59385 475080 [ 59385 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Request_Control: 38683 309464 [ 38683 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Response_Data: 538648 38782656 [ 0 538648 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Data: 1828030 131618160 [ 0 1828030 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Response_Control: 244326 1954608 [ 0 244326 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Control: 1263466 10107728 [ 0 1263466 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_2_Control: 2697566 21580528 [ 2697566 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_2_Control: 2655132 21241056 [ 2655132 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_2_Response_Data: 216184 15565248 [ 0 216184 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_2_Response_Data: 201773 14527656 [ 0 201773 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_2_Response_Control: 1945969 15567752 [ 0 115204 1830765 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_2_Response_Control: 1880978 15047824 [ 0 121850 1759128 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_2_Writeback_Data: 1630759 117414648 [ 1630429 330 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_2_Writeback_Data: 1589668 114456096 [ 1589444 224 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_2_Writeback_Control: 80843 646744 [ 80843 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_2_Writeback_Control: 96506 772048 [ 96506 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_3_Control: 172147 1377176 [ 172147 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_3_Control: 177640 1421120 [ 177640 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_3_Response_Data: 94424 6798528 [ 0 94424 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_3_Response_Data: 96523 6949656 [ 0 96523 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_3_Response_Control: 12193 97544 [ 0 12193 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_3_Response_Control: 15587 124696 [ 0 15587 0 0 0 0 0 0 0 0 ] base_latency: 1
 Cache Stats: system.ruby.l1_cntrl0.L1IcacheMemory
-  system.ruby.l1_cntrl0.L1IcacheMemory_total_misses: 519313
+  system.ruby.l1_cntrl0.L1IcacheMemory_total_misses: 313126
-  system.ruby.l1_cntrl0.L1IcacheMemory_total_demand_misses: 519313
+  system.ruby.l1_cntrl0.L1IcacheMemory_total_demand_misses: 313126
  system.ruby.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
  system.ruby.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
  system.ruby.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
  system.ruby.l1_cntrl0.L1IcacheMemory_request_type_IFETCH:   100%
-  system.ruby.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor:   519313    100%
+  system.ruby.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor:   313126    100%
 Cache Stats: system.ruby.l1_cntrl0.L1DcacheMemory
-  system.ruby.l1_cntrl0.L1DcacheMemory_total_misses: 1618529
+  system.ruby.l1_cntrl0.L1DcacheMemory_total_misses: 504457
-  system.ruby.l1_cntrl0.L1DcacheMemory_total_demand_misses: 1618529
+  system.ruby.l1_cntrl0.L1DcacheMemory_total_demand_misses: 504457
  system.ruby.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
  system.ruby.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
  system.ruby.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
-  system.ruby.l1_cntrl0.L1DcacheMemory_request_type_LD:   80.1035%
+  system.ruby.l1_cntrl0.L1DcacheMemory_request_type_LD:   54.7331%
-  system.ruby.l1_cntrl0.L1DcacheMemory_request_type_ST:   19.8965%
+  system.ruby.l1_cntrl0.L1DcacheMemory_request_type_ST:   45.2669%
-  system.ruby.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor:   1618529    100%
+  system.ruby.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor:   504457    100%
 --- L1Cache ---
 - Event Counts -
-Load [11524819 3762841 ] 15287660
+Load [6004899 8869162 ] 14874061
-Ifetch [108056158 20120206 ] 128176364
+Ifetch [67402410 58977750 ] 126380160
-Store [7679126 3245483 ] 10924609
+Store [5078812 5562047 ] 10640859
-Inv [28158 23310 ] 51468
+Inv [16081 16662 ] 32743
-L1_Replacement [2094939 513666 ] 2608605
+L1_Replacement [790678 1810849 ] 2601527
-Fwd_GETX [15349 14692 ] 30041
+Fwd_GETX [12181 11488 ] 23669
-Fwd_GETS [22649 21383 ] 44032
+Fwd_GETS [13596 10533 ] 24129
-Fwd_GET_INSTR [5 0 ] 5
+Fwd_GET_INSTR [4 0 ] 4
-Data [1528 1030 ] 2558
+Data [367 1125 ] 1492
-Data_Exclusive [1226643 92927 ] 1319570
+Data_Exclusive [240655 1040298 ] 1280953
-DataS_fromL1 [21383 22654 ] 44037
+DataS_fromL1 [10533 13600 ] 24133
-Data_all_Acks [869371 422037 ] 1291408
+Data_all_Acks [554260 773007 ] 1327267
-Ack [18917 21076 ] 39993
+Ack [11768 9519 ] 21287
-Ack_all [20445 22106 ] 42551
+Ack_all [12135 10644 ] 22779
-WB_Ack [1510128 201144 ] 1711272
+WB_Ack [442647 1243303 ] 1685950
 PF_Load [0 0 ] 0
 PF_Ifetch [0 0 ] 0
 PF_Store [0 0 ] 0
 - Transitions -
-NP  Load [1280962 125221 ] 1406183
+NP  Load [267792 1102795 ] 1370587
-NP  Ifetch [519202 274242 ] 793444
+NP  Ifetch [313000 498627 ] 811627
-NP  Store [295799 115227 ] 411026
+NP  Store [210910 210451 ] 421361
-NP  Inv [6572 2932 ] 9504
+NP  Inv [5429 3933 ] 9362
 NP  L1_Replacement [0 0 ] 0
 NP  PF_Load [0 0 ] 0
 NP  PF_Ifetch [0 0 ] 0
 NP  PF_Store [0 0 ] 0
-I  Load [15536 14911 ] 30447
+I  Load [8313 10000 ] 18313
-I  Ifetch [111 223 ] 334
+I  Ifetch [126 437 ] 563
-I  Store [7315 8824 ] 16139
+I  Store [5674 5720 ] 11394
 I  Inv [0 0 ] 0
-I  L1_Replacement [13898 11112 ] 25010
+I  L1_Replacement [8682 8060 ] 16742
 I  PF_Load [0 0 ] 0
 I  PF_Ifetch [0 0 ] 0
 I  PF_Store [0 0 ] 0
-S  Load [750748 485618 ] 1236366
+S  Load [551889 484566 ] 1036455
-S  Ifetch [107536840 19845739 ] 127382579
+S  Ifetch [67089280 58478684 ] 125567964
-S  Store [18917 21076 ] 39993
+S  Store [11768 9519 ] 21287
-S  Inv [21408 20030 ] 41438
+S  Inv [10451 12551 ] 23002
-S  L1_Replacement [570913 301410 ] 872323
+S  L1_Replacement [339349 559486 ] 898835
 S  PF_Load [0 0 ] 0
 S  PF_Store [0 0 ] 0
-E  Load [3053712 595313 ] 3649025
+E  Load [1058703 2799902 ] 3858605
 E  Ifetch [0 0 ] 0
-E  Store [120709 32416 ] 153125
+E  Store [78784 87850 ] 166634
-E  Inv [68 128 ] 196
+E  Inv [103 52 ] 155
-E  L1_Replacement [1104096 58890 ] 1162986
+E  L1_Replacement [160570 950900 ] 1111470
-E  Fwd_GETX [187 209 ] 396
+E  Fwd_GETX [228 182 ] 410
-E  Fwd_GETS [1490 1115 ] 2605
+E  Fwd_GETS [848 1108 ] 1956
-E  Fwd_GET_INSTR [1 0 ] 1
+E  Fwd_GET_INSTR [0 0 ] 0
 E  PF_Load [0 0 ] 0
 E  PF_Store [0 0 ] 0
-M  Load [6423861 2541778 ] 8965639
+M  Load [4118202 4471899 ] 8590101
 M  Ifetch [0 0 ] 0
-M  Store [7236386 3067940 ] 10304326
+M  Store [4771676 5248507 ] 10020183
-M  Inv [110 220 ] 330
+M  Inv [98 126 ] 224
-M  L1_Replacement [406032 142254 ] 548286
+M  L1_Replacement [282077 292403 ] 574480
-M  Fwd_GETX [15162 14483 ] 29645
+M  Fwd_GETX [11953 11306 ] 23259
-M  Fwd_GETS [21159 20268 ] 41427
+M  Fwd_GETS [12747 9423 ] 22170
 M  Fwd_GET_INSTR [4 0 ] 4
 M  PF_Load [0 0 ] 0
 M  PF_Store [0 0 ] 0
@ -292,9 +292,9 @@ IS  Ifetch [0 0 ] 0
 IS  Store [0 0 ] 0
 IS  Inv [0 0 ] 0
 IS  L1_Replacement [0 0 ] 0
-IS  Data_Exclusive [1226643 92927 ] 1319570
+IS  Data_Exclusive [240655 1040298 ] 1280953
-IS  DataS_fromL1 [21383 22654 ] 44037
+IS  DataS_fromL1 [10533 13600 ] 24133
-IS  Data_all_Acks [567785 299016 ] 866801
+IS  Data_all_Acks [338043 557961 ] 896004
 IS  PF_Load [0 0 ] 0
 IS  PF_Store [0 0 ] 0
@ -303,8 +303,8 @@ IM  Ifetch [0 0 ] 0
 IM  Store [0 0 ] 0
 IM  Inv [0 0 ] 0
 IM  L1_Replacement [0 0 ] 0
-IM  Data [1528 1030 ] 2558
+IM  Data [367 1125 ] 1492
-IM  Data_all_Acks [301586 123021 ] 424607
+IM  Data_all_Acks [216217 215046 ] 431263
 IM  Ack [0 0 ] 0
 IM  PF_Load [0 0 ] 0
 IM  PF_Store [0 0 ] 0
@ -314,8 +314,8 @@ SM  Ifetch [0 0 ] 0
 SM  Store [0 0 ] 0
 SM  Inv [0 0 ] 0
 SM  L1_Replacement [0 0 ] 0
-SM  Ack [18917 21076 ] 39993
+SM  Ack [11768 9519 ] 21287
-SM  Ack_all [20445 22106 ] 42551
+SM  Ack_all [12135 10644 ] 22779
 SM  PF_Load [0 0 ] 0
 SM  PF_Store [0 0 ] 0
@ -331,14 +331,14 @@ IS_I  PF_Load [0 0 ] 0
 IS_I  PF_Store [0 0 ] 0
 M_I  Load [0 0 ] 0
-M_I  Ifetch [5 2 ] 7
+M_I  Ifetch [4 2 ] 6
 M_I  Store [0 0 ] 0
 M_I  Inv [0 0 ] 0
 M_I  L1_Replacement [0 0 ] 0
 M_I  Fwd_GETX [0 0 ] 0
-M_I  Fwd_GETS [0 0 ] 0
+M_I  Fwd_GETS [1 2 ] 3
 M_I  Fwd_GET_INSTR [0 0 ] 0
-M_I  WB_Ack [1510128 201144 ] 1711272
+M_I  WB_Ack [442646 1243301 ] 1685947
 M_I  PF_Load [0 0 ] 0
 M_I  PF_Store [0 0 ] 0
@ -347,7 +347,7 @@ SINK_WB_ACK  Ifetch [0 0 ] 0
 SINK_WB_ACK  Store [0 0 ] 0
 SINK_WB_ACK  Inv [0 0 ] 0
 SINK_WB_ACK  L1_Replacement [0 0 ] 0
-SINK_WB_ACK  WB_Ack [0 0 ] 0
+SINK_WB_ACK  WB_Ack [1 2 ] 3
 SINK_WB_ACK  PF_Load [0 0 ] 0
 SINK_WB_ACK  PF_Store [0 0 ] 0
@ -390,98 +390,98 @@ PF_IS_I  DataS_fromL1 [0 0 ] 0
 PF_IS_I  Data_all_Acks [0 0 ] 0
 Cache Stats: system.ruby.l1_cntrl1.L1IcacheMemory
-  system.ruby.l1_cntrl1.L1IcacheMemory_total_misses: 274465
+  system.ruby.l1_cntrl1.L1IcacheMemory_total_misses: 499064
-  system.ruby.l1_cntrl1.L1IcacheMemory_total_demand_misses: 274465
+  system.ruby.l1_cntrl1.L1IcacheMemory_total_demand_misses: 499064
  system.ruby.l1_cntrl1.L1IcacheMemory_total_prefetches: 0
  system.ruby.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0
  system.ruby.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0
  system.ruby.l1_cntrl1.L1IcacheMemory_request_type_IFETCH:   100%
-  system.ruby.l1_cntrl1.L1IcacheMemory_access_mode_type_Supervisor:   274465    100%
+  system.ruby.l1_cntrl1.L1IcacheMemory_access_mode_type_Supervisor:   499064    100%
 Cache Stats: system.ruby.l1_cntrl1.L1DcacheMemory
-  system.ruby.l1_cntrl1.L1DcacheMemory_total_misses: 285259
+  system.ruby.l1_cntrl1.L1DcacheMemory_total_misses: 1338485
-  system.ruby.l1_cntrl1.L1DcacheMemory_total_demand_misses: 285259
+  system.ruby.l1_cntrl1.L1DcacheMemory_total_demand_misses: 1338485
  system.ruby.l1_cntrl1.L1DcacheMemory_total_prefetches: 0
  system.ruby.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0
  system.ruby.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0
-  system.ruby.l1_cntrl1.L1DcacheMemory_request_type_LD:   49.1245%
+  system.ruby.l1_cntrl1.L1DcacheMemory_request_type_LD:   83.1384%
-  system.ruby.l1_cntrl1.L1DcacheMemory_request_type_ST:   50.8755%
+  system.ruby.l1_cntrl1.L1DcacheMemory_request_type_ST:   16.8616%
-  system.ruby.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor:   285259    100%
+  system.ruby.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor:   1338485    100%
 Cache Stats: system.ruby.l2_cntrl0.L2cacheMemory
-  system.ruby.l2_cntrl0.L2cacheMemory_total_misses: 246225
+  system.ruby.l2_cntrl0.L2cacheMemory_total_misses: 225442
-  system.ruby.l2_cntrl0.L2cacheMemory_total_demand_misses: 246225
+  system.ruby.l2_cntrl0.L2cacheMemory_total_demand_misses: 225442
  system.ruby.l2_cntrl0.L2cacheMemory_total_prefetches: 0
  system.ruby.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
  system.ruby.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
-  system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETS:   30.3877%
+  system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETS:   25.7405%
-  system.ruby.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR:   6.26541%
+  system.ruby.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR:   7.27238%
-  system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETX:   63.3469%
+  system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETX:   66.9871%
-  system.ruby.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor:   246225    100%
+  system.ruby.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor:   225442    100%
 --- L2Cache ---
 - Event Counts -
-L1_GET_INSTR [793778 ] 793778
+L1_GET_INSTR [812190 ] 812190
-L1_GETS [1436873 ] 1436873
+L1_GETS [1389132 ] 1389132
-L1_GETX [427166 ] 427166
+L1_GETX [432758 ] 432758
-L1_UPGRADE [39993 ] 39993
+L1_UPGRADE [21287 ] 21287
-L1_PUTX [1711272 ] 1711272
+L1_PUTX [1685953 ] 1685953
 L1_PUTX_old [0 ] 0
 Fwd_L1_GETX [0 ] 0
 Fwd_L1_GETS [0 ] 0
 Fwd_L1_GET_INSTR [0 ] 0
-L2_Replacement [94211 ] 94211
+L2_Replacement [96407 ] 96407
-L2_Replacement_clean [12406 ] 12406
+L2_Replacement_clean [15703 ] 15703
-Mem_Data [172147 ] 172147
+Mem_Data [177640 ] 177640
-Mem_Ack [106617 ] 106617
+Mem_Ack [112110 ] 112110
-WB_Data [43745 ] 43745
+WB_Data [23855 ] 23855
-WB_Data_clean [622 ] 622
+WB_Data_clean [502 ] 502
-Ack [1695 ] 1695
+Ack [1764 ] 1764
-Ack_all [6892 ] 6892
+Ack_all [7976 ] 7976
-Unblock [44037 ] 44037
+Unblock [24133 ] 24133
 Unblock_Cancel [0 ] 0
-Exclusive_Unblock [1786728 ] 1786728
+Exclusive_Unblock [1734995 ] 1734995
 MEM_Inv [0 ] 0
 - Transitions -
-NP  L1_GET_INSTR [15422 ] 15422
+NP  L1_GET_INSTR [16391 ] 16391
-NP  L1_GETS [30790 ] 30790
+NP  L1_GETS [33901 ] 33901
-NP  L1_GETX [125935 ] 125935
+NP  L1_GETX [127348 ] 127348
 NP  L1_PUTX [0 ] 0
 NP  L1_PUTX_old [0 ] 0
-SS  L1_GET_INSTR [778102 ] 778102
+SS  L1_GET_INSTR [795630 ] 795630
-SS  L1_GETS [73028 ] 73028
+SS  L1_GETS [83818 ] 83818
-SS  L1_GETX [2798 ] 2798
+SS  L1_GETX [1691 ] 1691
-SS  L1_UPGRADE [39993 ] 39993
+SS  L1_UPGRADE [21287 ] 21287
-SS  L1_PUTX [0 ] 0
+SS  L1_PUTX [3 ] 3
 SS  L1_PUTX_old [0 ] 0
-SS  L2_Replacement [248 ] 248
+SS  L2_Replacement [258 ] 258
-SS  L2_Replacement_clean [6448 ] 6448
+SS  L2_Replacement_clean [7563 ] 7563
 SS  MEM_Inv [0 ] 0
-M  L1_GET_INSTR [249 ] 249
+M  L1_GET_INSTR [165 ] 165
-M  L1_GETS [1288780 ] 1288780
+M  L1_GETS [1247052 ] 1247052
-M  L1_GETX [268391 ] 268391
+M  L1_GETX [280047 ] 280047
 M  L1_PUTX [0 ] 0
 M  L1_PUTX_old [0 ] 0
-M  L2_Replacement [93815 ] 93815
+M  L2_Replacement [95992 ] 95992
-M  L2_Replacement_clean [5580 ] 5580
+M  L2_Replacement_clean [7918 ] 7918
 M  MEM_Inv [0 ] 0
-MT  L1_GET_INSTR [5 ] 5
+MT  L1_GET_INSTR [4 ] 4
-MT  L1_GETS [44032 ] 44032
+MT  L1_GETS [24129 ] 24129
-MT  L1_GETX [30041 ] 30041
+MT  L1_GETX [23669 ] 23669
-MT  L1_PUTX [1711272 ] 1711272
+MT  L1_PUTX [1685947 ] 1685947
 MT  L1_PUTX_old [0 ] 0
-MT  L2_Replacement [148 ] 148
+MT  L2_Replacement [157 ] 157
-MT  L2_Replacement_clean [378 ] 378
+MT  L2_Replacement_clean [222 ] 222
 MT  MEM_Inv [0 ] 0
 M_I  L1_GET_INSTR [0 ] 0
@ -490,7 +490,7 @@ M_I  L1_GETX [0 ] 0
 M_I  L1_UPGRADE [0 ] 0
 M_I  L1_PUTX [0 ] 0
 M_I  L1_PUTX_old [0 ] 0
-M_I  Mem_Ack [106617 ] 106617
+M_I  Mem_Ack [112110 ] 112110
 M_I  MEM_Inv [0 ] 0
 MT_I  L1_GET_INSTR [0 ] 0
@ -499,9 +499,9 @@ MT_I  L1_GETX [0 ] 0
 MT_I  L1_UPGRADE [0 ] 0
 MT_I  L1_PUTX [0 ] 0
 MT_I  L1_PUTX_old [0 ] 0
-MT_I  WB_Data [117 ] 117
+MT_I  WB_Data [108 ] 108
 MT_I  WB_Data_clean [0 ] 0
-MT_I  Ack_all [31 ] 31
+MT_I  Ack_all [49 ] 49
 MT_I  MEM_Inv [0 ] 0
 MCT_I  L1_GET_INSTR [0 ] 0
@ -510,9 +510,9 @@ MCT_I  L1_GETX [0 ] 0
 MCT_I  L1_UPGRADE [0 ] 0
 MCT_I  L1_PUTX [0 ] 0
 MCT_I  L1_PUTX_old [0 ] 0
-MCT_I  WB_Data [213 ] 213
+MCT_I  WB_Data [116 ] 116
 MCT_I  WB_Data_clean [0 ] 0
-MCT_I  Ack_all [165 ] 165
+MCT_I  Ack_all [106 ] 106
 I_I  L1_GET_INSTR [0 ] 0
 I_I  L1_GETS [0 ] 0
@ -520,8 +520,8 @@ I_I  L1_GETX [0 ] 0
 I_I  L1_UPGRADE [0 ] 0
 I_I  L1_PUTX [0 ] 0
 I_I  L1_PUTX_old [0 ] 0
-I_I  Ack [1454 ] 1454
+I_I  Ack [1506 ] 1506
-I_I  Ack_all [6448 ] 6448
+I_I  Ack_all [7563 ] 7563
 S_I  L1_GET_INSTR [0 ] 0
 S_I  L1_GETS [0 ] 0
@ -529,8 +529,8 @@ S_I  L1_GETX [0 ] 0
 S_I  L1_UPGRADE [0 ] 0
 S_I  L1_PUTX [0 ] 0
 S_I  L1_PUTX_old [0 ] 0
-S_I  Ack [241 ] 241
+S_I  Ack [258 ] 258
-S_I  Ack_all [248 ] 248
+S_I  Ack_all [258 ] 258
 S_I  MEM_Inv [0 ] 0
 ISS  L1_GET_INSTR [0 ] 0
@ -540,7 +540,7 @@ ISS  L1_PUTX [0 ] 0
 ISS  L1_PUTX_old [0 ] 0
 ISS  L2_Replacement [0 ] 0
 ISS  L2_Replacement_clean [0 ] 0
-ISS  Mem_Data [30790 ] 30790
+ISS  Mem_Data [33901 ] 33901
 ISS  MEM_Inv [0 ] 0
 IS  L1_GET_INSTR [0 ] 0
@ -550,7 +550,7 @@ IS  L1_PUTX [0 ] 0
 IS  L1_PUTX_old [0 ] 0
 IS  L2_Replacement [0 ] 0
 IS  L2_Replacement_clean [0 ] 0
-IS  Mem_Data [15422 ] 15422
+IS  Mem_Data [16391 ] 16391
 IS  MEM_Inv [0 ] 0
 IM  L1_GET_INSTR [0 ] 0
@ -560,31 +560,31 @@ IM  L1_PUTX [0 ] 0
 IM  L1_PUTX_old [0 ] 0
 IM  L2_Replacement [0 ] 0
 IM  L2_Replacement_clean [0 ] 0
-IM  Mem_Data [125935 ] 125935
+IM  Mem_Data [127348 ] 127348
 IM  MEM_Inv [0 ] 0
 SS_MB  L1_GET_INSTR [0 ] 0
-SS_MB  L1_GETS [194 ] 194
+SS_MB  L1_GETS [186 ] 186
-SS_MB  L1_GETX [0 ] 0
+SS_MB  L1_GETX [1 ] 1
 SS_MB  L1_UPGRADE [0 ] 0
 SS_MB  L1_PUTX [0 ] 0
 SS_MB  L1_PUTX_old [0 ] 0
 SS_MB  L2_Replacement [0 ] 0
 SS_MB  L2_Replacement_clean [0 ] 0
 SS_MB  Unblock_Cancel [0 ] 0
-SS_MB  Exclusive_Unblock [42791 ] 42791
+SS_MB  Exclusive_Unblock [22978 ] 22978
 SS_MB  MEM_Inv [0 ] 0
 MT_MB  L1_GET_INSTR [0 ] 0
-MT_MB  L1_GETS [49 ] 49
+MT_MB  L1_GETS [46 ] 46
-MT_MB  L1_GETX [1 ] 1
+MT_MB  L1_GETX [2 ] 2
 MT_MB  L1_UPGRADE [0 ] 0
 MT_MB  L1_PUTX [0 ] 0
 MT_MB  L1_PUTX_old [0 ] 0
 MT_MB  L2_Replacement [0 ] 0
 MT_MB  L2_Replacement_clean [0 ] 0
 MT_MB  Unblock_Cancel [0 ] 0
-MT_MB  Exclusive_Unblock [1743937 ] 1743937
+MT_MB  Exclusive_Unblock [1712017 ] 1712017
 MT_MB  MEM_Inv [0 ] 0
 M_MB  L1_GET_INSTR [0 ] 0
@ -602,13 +602,13 @@ MT_IIB  L1_GET_INSTR [0 ] 0
 MT_IIB  L1_GETS [0 ] 0
 MT_IIB  L1_GETX [0 ] 0
 MT_IIB  L1_UPGRADE [0 ] 0
-MT_IIB  L1_PUTX [0 ] 0
+MT_IIB  L1_PUTX [3 ] 3
 MT_IIB  L1_PUTX_old [0 ] 0
 MT_IIB  L2_Replacement [0 ] 0
 MT_IIB  L2_Replacement_clean [0 ] 0
-MT_IIB  WB_Data [43373 ] 43373
+MT_IIB  WB_Data [23620 ] 23620
-MT_IIB  WB_Data_clean [622 ] 622
+MT_IIB  WB_Data_clean [502 ] 502
-MT_IIB  Unblock [42 ] 42
+MT_IIB  Unblock [11 ] 11
 MT_IIB  MEM_Inv [0 ] 0
 MT_IB  L1_GET_INSTR [0 ] 0
@ -619,7 +619,7 @@ MT_IB  L1_PUTX [0 ] 0
 MT_IB  L1_PUTX_old [0 ] 0
 MT_IB  L2_Replacement [0 ] 0
 MT_IB  L2_Replacement_clean [0 ] 0
-MT_IB  WB_Data [42 ] 42
+MT_IB  WB_Data [11 ] 11
 MT_IB  WB_Data_clean [0 ] 0
 MT_IB  Unblock_Cancel [0 ] 0
 MT_IB  MEM_Inv [0 ] 0
@ -632,41 +632,41 @@ MT_SB  L1_PUTX [0 ] 0
 MT_SB  L1_PUTX_old [0 ] 0
 MT_SB  L2_Replacement [0 ] 0
 MT_SB  L2_Replacement_clean [0 ] 0
-MT_SB  Unblock [43995 ] 43995
+MT_SB  Unblock [24122 ] 24122
 MT_SB  MEM_Inv [0 ] 0
 Memory controller: system.ruby.dir_cntrl0.memBuffer:
-  memory_total_requests: 266571
+  memory_total_requests: 274163
-  memory_reads: 172147
+  memory_reads: 177640
-  memory_writes: 94424
+  memory_writes: 96523
-  memory_refreshes: 536635
+  memory_refreshes: 588410
-  memory_total_request_delays: 1016542
+  memory_total_request_delays: 1038324
-  memory_delays_per_request: 3.8134
+  memory_delays_per_request: 3.78725
-  memory_delays_in_input_queue: 40049
+  memory_delays_in_input_queue: 39505
-  memory_delays_behind_head_of_bank_queue: 7609
+  memory_delays_behind_head_of_bank_queue: 7889
-  memory_delays_stalled_at_head_of_bank_queue: 968884
+  memory_delays_stalled_at_head_of_bank_queue: 990930
-  memory_stalls_for_bank_busy: 959552
+  memory_stalls_for_bank_busy: 981321
  memory_stalls_for_random_busy: 0
  memory_stalls_for_anti_starvation: 0
-  memory_stalls_for_arbitration: 2148
+  memory_stalls_for_arbitration: 2239
-  memory_stalls_for_bus: 7162
+  memory_stalls_for_bus: 7329
  memory_stalls_for_tfaw: 0
-  memory_stalls_for_read_write_turnaround: 15
+  memory_stalls_for_read_write_turnaround: 29
-  memory_stalls_for_read_read_turnaround: 7
+  memory_stalls_for_read_read_turnaround: 12
-  accesses_per_bank: 8989  7974  8010  8055  8487  8273  8235  8188  8380  8237  8148  8446  8268  8048  8068  7184  8265  8304  8191  8114  8382  8281  8178  8162  8416  8296  8511  9107  9086  9056  8973  8259  
+  accesses_per_bank: 9082  9112  8244  8400  9230  8573  8966  8230  8398  8230  8230  8246  8347  8114  8111  7298  8351  8467  8382  8429  8595  8485  8298  8250  8587  8384  8675  9378  9287  9169  10231  8384  
 --- Directory ---
 - Event Counts -
-Fetch [172147 ] 172147
+Fetch [177640 ] 177640
-Data [94424 ] 94424
+Data [96523 ] 96523
-Memory_Data [172147 ] 172147
+Memory_Data [177640 ] 177640
-Memory_Ack [94424 ] 94424
+Memory_Ack [96523 ] 96523
 DMA_READ [0 ] 0
 DMA_WRITE [0 ] 0
-CleanReplacement [12193 ] 12193
+CleanReplacement [15587 ] 15587
 - Transitions -
-I  Fetch [172147 ] 172147
+I  Fetch [177640 ] 177640
 I  DMA_READ [0 ] 0
 I  DMA_WRITE [0 ] 0
@ -682,20 +682,20 @@ ID_W  Memory_Ack [0 ] 0
 ID_W  DMA_READ [0 ] 0
 ID_W  DMA_WRITE [0 ] 0
-M  Data [94424 ] 94424
+M  Data [96523 ] 96523
 M  DMA_READ [0 ] 0
 M  DMA_WRITE [0 ] 0
-M  CleanReplacement [12193 ] 12193
+M  CleanReplacement [15587 ] 15587
 IM  Fetch [0 ] 0
 IM  Data [0 ] 0
-IM  Memory_Data [172147 ] 172147
+IM  Memory_Data [177640 ] 177640
 IM  DMA_READ [0 ] 0
 IM  DMA_WRITE [0 ] 0
 MI  Fetch [0 ] 0
 MI  Data [0 ] 0
-MI  Memory_Ack [94424 ] 94424
+MI  Memory_Ack [96523 ] 96523
 MI  DMA_READ [0 ] 0
 MI  DMA_WRITE [0 ] 0
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr
@ -1,3 +1,4 @@
 warn: add_child('terminal'): child 'terminal' already has parent
 warn: Sockets disabled, not accepting terminal connections
 warn: Reading current count from inactive timer.
 warn: Sockets disabled, not accepting gdb connections
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
@ -3,13 +3,12 @@ Redirecting stderr to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-bo
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 27 2012 15:33:48
+gem5 compiled Mar 28 2013 10:05:24
-gem5 started Oct 27 2012 15:33:58
+gem5 started Mar 28 2013 10:05:51
 gem5 executing on ribera.cs.wisc.edu
 command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5205006494000 because m5_exit instruction encountered
+Exiting @ tick 5208135619000 because m5_exit instruction encountered
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
@ -1,125 +1,125 @@
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.204983                       # Number of seconds simulated
+sim_seconds                                  5.208136                       # Number of seconds simulated
-sim_ticks                                5204982530500                       # Number of ticks simulated
+sim_ticks                                5208135619000                       # Number of ticks simulated
-final_tick                               5204982530500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+final_tick                               5208135619000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  97445                       # Simulator instruction rate (inst/s)
+host_inst_rate                                 129465                       # Simulator instruction rate (inst/s)
-host_op_rate                                   186950                       # Simulator op (including micro ops) rate (op/s)
+host_op_rate                                   248187                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4697195864                       # Simulator tick rate (ticks/s)
+host_tick_rate                             6321029655                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 811856                       # Number of bytes of host memory used
+host_mem_usage                                 868876                       # Number of bytes of host memory used
-host_seconds                                  1108.10                       # Real time elapsed on the host
+host_seconds                                   823.94                       # Real time elapsed on the host
-sim_insts                                   107979048                       # Number of instructions simulated
+sim_insts                                   106670761                       # Number of instructions simulated
-sim_ops                                     207160548                       # Number of ops (including micro ops) simulated
+sim_ops                                     204490715                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide        35152                       # Number of bytes read from this memory
+system.physmem.bytes_read::pc.south_bridge.ide        35248                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker       137616                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker       110464                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker        65352                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        48224                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst        864449144                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst        539219248                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         69078721                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         38302123                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker        87568                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       112752                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker        42392                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        59160                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst        160961656                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst        471821984                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         27339822                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         55029081                       # Number of bytes read from this memory
-system.physmem.bytes_read::total           1122197423                       # Number of bytes read from this memory
+system.physmem.bytes_read::total           1104738284                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst    864449144                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst    539219248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst    160961656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst    471821984                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total      1025410800                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      1011041232                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::pc.south_bridge.ide      2991104                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.itb.walker           16                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data      48342743                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data      30881325                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data      21309908                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data      36960563                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          72643771                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          70833008                       # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide          810                       # Number of read requests responded to by this memory
+system.physmem.num_reads::pc.south_bridge.ide          822                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker        17202                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker        13808                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         8169                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         6028                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst         108056143                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst          67402406                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data          12053062                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data           6418181                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker        10946                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker        14094                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         5299                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         7395                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst          20120207                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst          58977748                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data           4057616                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data           9244544                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             144329454                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             142085026                       # Number of read requests responded to by this memory
 system.physmem.num_writes::pc.south_bridge.ide        46736                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.itb.walker            2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data          7125507                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data          4645692                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data          2934464                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data          5165176                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total             10106709                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              9857606                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide         6754                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide         6768                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker         26439                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker         21210                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker         12556                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          9259                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst           166081085                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst           103534026                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            13271653                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             7354287                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker         16824                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker         21649                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          8145                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker         11359                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst            30924533                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst            90593260                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             5252625                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data            10565985                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               215600613                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               212117803                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst      166081085                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst      103534026                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst       30924533                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst       90593260                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          197005618                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          194127286                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide       574662                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide       574314                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.itb.walker            3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data            9287782                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data            5929439                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data            4094136                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data            7096697                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               13956583                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               13600454                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       581415                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       581082                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker        26439                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker        21210                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker        12559                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         9262                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst          166081085                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst          103534026                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           22559435                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           13283726                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker        16824                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker        21649                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         8145                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker        11359                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst           30924533                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst           90593260                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            9346761                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data           17662682                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              229557196                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              225718257                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           810                       # Total number of read requests seen
+system.physmem.readReqs                           822                       # Total number of read requests seen
 system.physmem.writeReqs                        46736                       # Total number of write requests seen
 system.physmem.cpureqs                          47278                       # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead                        51840                       # Total number of bytes read from memory
+system.physmem.bytesRead                        52608                       # Total number of bytes read from memory
 system.physmem.bytesWritten                   2991104                       # Total number of bytes written to memory
-system.physmem.bytesConsumedRd                  35152                       # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd                  35248                       # bytesRead derated as per pkt->getSize()
 system.physmem.bytesConsumedWr                2991104                       # bytesWritten derated as per pkt->getSize()
 system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
 system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
-system.physmem.perBankRdReqs::0                    16                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0                    32                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1                    16                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1                    48                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2                   298                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2                    64                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3                     0                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3                    32                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4                    16                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4                   326                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5                    32                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5                    16                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6                    32                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6                    48                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7                    32                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7                    48                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8                    48                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8                    32                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9                    96                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9                    32                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10                   32                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10                   48                       # Track reads on a per bank basis
 system.physmem.perBankRdReqs::11                   16                       # Track reads on a per bank basis
 system.physmem.perBankRdReqs::12                    0                       # Track reads on a per bank basis
 system.physmem.perBankRdReqs::13                   32                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14                   96                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14                    0                       # Track reads on a per bank basis
 system.physmem.perBankRdReqs::15                   48                       # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0                  2952                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::0                  2992                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1                  2848                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1                  2928                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2                  3008                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2                  2960                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3                  2928                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3                  2784                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4                  2928                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4                  2944                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5                  2944                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5                  2848                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6                  3056                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6                  2856                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7                  2944                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7                  2912                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8                  2848                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8                  2952                       # Track writes on a per bank basis
 system.physmem.perBankWrReqs::9                  2912                       # Track writes on a per bank basis
 system.physmem.perBankWrReqs::10                 2848                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11                 2704                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11                 2832                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12                 2864                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12                 3024                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13                 2864                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13                 2992                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14                 3048                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14                 2976                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15                 3040                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15                 2976                       # Track writes on a per bank basis
 system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
 system.physmem.numWrRetry                          30                       # Number of times wr buffer was full causing retry
-system.physmem.totGap                     63182142000                       # Total gap between requests
+system.physmem.totGap                     67214585000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::3                     298                       # Categorize read packet sizes
+system.physmem.readPktSize::3                     310                       # Categorize read packet sizes
 system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::6                     512                       # Categorize read packet sizes
@ -130,7 +130,7 @@ system.physmem.writePktSize::3                      0                       # Ca
 system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::6                  46736                       # Categorize write packet sizes
-system.physmem.rdQLenPdf::0                       328                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       340                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                        30                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        30                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        30                       # What read queue length does an incoming req see
@ -162,15 +162,15 @@ system.physmem.rdQLenPdf::28                        2                       # Wh
 system.physmem.rdQLenPdf::29                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        2                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      1965                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                      1967                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      1971                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                      1977                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                      1995                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::3                      1995                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::4                      1995                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      1996                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                      1995                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      1996                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                      1995                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      1999                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                      1996                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      1999                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                      2000                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::9                      2032                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::10                     2032                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::11                     2032                       # What write queue length does an incoming req see
@ -185,23 +185,23 @@ system.physmem.wrQLenPdf::19                     2032                       # Wh
 system.physmem.wrQLenPdf::20                     2032                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::21                     2032                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::22                     2032                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       61                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                       55                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::25                       37                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::26                       37                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::27                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                       33                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                       33                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                       32                       # What write queue length does an incoming req see
-system.physmem.totQLat                       40945522                       # Total cycles spent in queuing delays
+system.physmem.totQLat                       44820022                       # Total cycles spent in queuing delays
-system.physmem.totMemAccLat                  52544272                       # Sum of mem lat for all requests
+system.physmem.totMemAccLat                  56685022                       # Sum of mem lat for all requests
-system.physmem.totBusLat                      4050000                       # Total cycles spent in databus access
+system.physmem.totBusLat                      4110000                       # Total cycles spent in databus access
-system.physmem.totBankLat                     7548750                       # Total cycles spent in bank access
+system.physmem.totBankLat                     7755000                       # Total cycles spent in bank access
-system.physmem.avgQLat                       50550.03                       # Average queueing delay per request
+system.physmem.avgQLat                       54525.57                       # Average queueing delay per request
-system.physmem.avgBankLat                     9319.44                       # Average bank access latency per request
+system.physmem.avgBankLat                     9434.31                       # Average bank access latency per request
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
-system.physmem.avgMemAccLat                  64869.47                       # Average memory access latency
+system.physmem.avgMemAccLat                  68959.88                       # Average memory access latency
 system.physmem.avgRdBW                           0.01                       # Average achieved read bandwidth in MB/s
 system.physmem.avgWrBW                           0.57                       # Average achieved write bandwidth in MB/s
 system.physmem.avgConsumedRdBW                   0.01                       # Average consumed read bandwidth in MB/s
@ -210,11 +210,11 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.00                       # Data bus utilization in percentage
 system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
 system.physmem.avgWrQLen                         0.15                       # Average write queue length over time
-system.physmem.readRowHits                        696                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        707                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     45224                       # Number of row buffer hits during writes
+system.physmem.writeRowHits                     45223                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   85.93                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   86.01                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  96.76                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1328863.46                       # Average gap between requests
+system.physmem.avgGap                      1413318.16                       # Average gap between requests
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        32768                       # Number of bytes transfered via DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_txs           30                       # Number of DMA read transactions (not PRD).
@ -275,52 +275,52 @@ system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_reads            0
 system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_writes            0                       # number of tag array writes
 system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_stalls            0                       # number of stalls caused by tag array
 system.ruby.l2_cntrl0.L2cacheMemory.num_data_array_stalls            0                       # number of stalls caused by data array
-system.cpu0.numCycles                     10407785676                       # number of cpu cycles simulated
+system.cpu0.numCycles                     10415384713                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   92551738                       # Number of instructions committed
+system.cpu0.committedInsts                   58007070                       # Number of instructions committed
-system.cpu0.committedOps                    178518541                       # Number of ops (including micro ops) committed
+system.cpu0.committedOps                    111693294                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            168457745                       # Number of integer alu accesses
+system.cpu0.num_int_alu_accesses            104699305                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu0.num_func_calls                          0                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     16414009                       # number of instructions that are conditional controls
+system.cpu0.num_conditional_control_insts      9926831                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   168457745                       # number of integer instructions
+system.cpu0.num_int_insts                   104699305                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads          415888462                       # number of times the integer registers were read
+system.cpu0.num_int_register_reads          256785271                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         210334505                       # number of times the integer registers were written
+system.cpu0.num_int_register_writes         132412981                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     20039556                       # number of memory refs
+system.cpu0.num_mem_refs                     11918647                       # number of memory refs
-system.cpu0.num_load_insts                   12899829                       # Number of load instructions
+system.cpu0.num_load_insts                    7262283                       # Number of load instructions
-system.cpu0.num_store_insts                   7139727                       # Number of store instructions
+system.cpu0.num_store_insts                   4656364                       # Number of store instructions
-system.cpu0.num_idle_cycles              9669887390.939814                       # Number of idle cycles
+system.cpu0.num_idle_cycles              9902585340.160280                       # Number of idle cycles
-system.cpu0.num_busy_cycles              737898285.060187                       # Number of busy cycles
+system.cpu0.num_busy_cycles              512799372.839719                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.070899                       # Percentage of non-idle cycles
+system.cpu0.not_idle_fraction                0.049235                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.929101                       # Percentage of idle cycles
+system.cpu0.idle_fraction                    0.950765                       # Percentage of idle cycles
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.numCycles                     10409965061                       # number of cpu cycles simulated
+system.cpu1.numCycles                     10416271238                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   15427310                       # Number of instructions committed
+system.cpu1.committedInsts                   48663691                       # Number of instructions committed
-system.cpu1.committedOps                     28642007                       # Number of ops (including micro ops) committed
+system.cpu1.committedOps                     92797421                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             28123684                       # Number of integer alu accesses
+system.cpu1.num_int_alu_accesses             89245391                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu1.num_func_calls                          0                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      1978311                       # number of instructions that are conditional controls
+system.cpu1.num_conditional_control_insts      8303775                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    28123684                       # number of integer instructions
+system.cpu1.num_int_insts                    89245391                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads           73029212                       # number of times the integer registers were read
+system.cpu1.num_int_register_reads          224679883                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          31865924                       # number of times the integer registers were written
+system.cpu1.num_int_register_writes         106822538                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      7025200                       # number of memory refs
+system.cpu1.num_mem_refs                     14447171                       # number of memory refs
-system.cpu1.num_load_insts                    4066766                       # Number of load instructions
+system.cpu1.num_load_insts                    9256256                       # Number of load instructions
-system.cpu1.num_store_insts                   2958434                       # Number of store instructions
+system.cpu1.num_store_insts                   5190915                       # Number of store instructions
-system.cpu1.num_idle_cycles              10280018132.934025                       # Number of idle cycles
+system.cpu1.num_idle_cycles              10072379281.574066                       # Number of idle cycles
-system.cpu1.num_busy_cycles              129946928.065975                       # Number of busy cycles
+system.cpu1.num_busy_cycles              343891956.425934                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.012483                       # Percentage of non-idle cycles
+system.cpu1.not_idle_fraction                0.033015                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.987517                       # Percentage of idle cycles
+system.cpu1.idle_fraction                    0.966985                       # Percentage of idle cycles
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
@ -185,7 +185,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
 [system.cpu.interrupts]
 type=X86LocalApic
-clock=500
+clock=8000
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@ -258,6 +258,7 @@ type=CoherentBus
 block_size=64
 clock=500
 header_cycles=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@ -268,17 +269,23 @@ type=ExeTracer
 [system.e820_table]
 type=X86E820Table
-children=entries0 entries1
+children=entries0 entries1 entries2
-entries=system.e820_table.entries0 system.e820_table.entries1
+entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2
 [system.e820_table.entries0]
 type=X86E820Entry
 addr=0
-range_type=2
+range_type=1
-size=1048576
+size=654336
 [system.e820_table.entries1]
 type=X86E820Entry
 addr=654336
 range_type=2
 size=394240
 [system.e820_table.entries2]
 type=X86E820Entry
 addr=1048576
 range_type=1
 size=133169152
@ -668,6 +675,7 @@ children=badaddr_responder
 block_size=64
 clock=1000
 header_cycles=1
 system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
@ -1127,25 +1135,28 @@ pio=system.iobus.master[9]
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
 addr_mapping=openmap
 banks_per_rank=8
 channels=1
 clock=1000
 conf_table_reported=false
 in_addr_map=true
-lines_per_rowbuffer=64
+lines_per_rowbuffer=32
-mem_sched_policy=fcfs
+mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
-tBURST=4000
+tBURST=5000
-tCL=14000
+tCL=13750
-tRCD=14000
+tRCD=13750
 tREFI=7800000
 tRFC=300000
-tRP=14000
+tRP=13750
-tWTR=1000
+tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
 zero=false
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
@ -1,3 +1,4 @@
 warn: add_child('terminal'): child 'terminal' already has parent
 warn: Sockets disabled, not accepting terminal connections
 warn: Reading current count from inactive timer.
 warn: Sockets disabled, not accepting gdb connections
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
@ -3,13 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-si
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 16:30:44
+gem5 compiled Mar 28 2013 09:59:18
-gem5 started Jan 23 2013 18:32:27
+gem5 started Mar 28 2013 09:59:40
 gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5112040970500 because m5_exit instruction encountered
+Exiting @ tick 5112099860500 because m5_exit instruction encountered
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
@ -1,51 +1,51 @@
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.112041                       # Number of seconds simulated
+sim_seconds                                  5.112100                       # Number of seconds simulated
-sim_ticks                                5112040970500                       # Number of ticks simulated
+sim_ticks                                5112099860500                       # Number of ticks simulated
-final_tick                               5112040970500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+final_tick                               5112099860500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1074050                       # Simulator instruction rate (inst/s)
+host_inst_rate                                1028107                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2199194                       # Simulator op (including micro ops) rate (op/s)
+host_op_rate                                  2105009                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            27479001055                       # Simulator tick rate (ticks/s)
+host_tick_rate                            26291327617                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 583620                       # Number of bytes of host memory used
+host_mem_usage                                 628192                       # Number of bytes of host memory used
-host_seconds                                   186.03                       # Real time elapsed on the host
+host_seconds                                   194.44                       # Real time elapsed on the host
-sim_insts                                   199810242                       # Number of instructions simulated
+sim_insts                                   199905607                       # Number of instructions simulated
-sim_ops                                     409125913                       # Number of ops (including micro ops) simulated
+sim_ops                                     409299132                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide      2464640                       # Number of bytes read from this memory
+system.physmem.bytes_read::pc.south_bridge.ide      2420928                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.dtb.walker          128                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            853824                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            852736                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10600128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10605184                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             13919040                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             13879296                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       853824                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       852736                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          853824                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          852736                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9292608                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks      9264448                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9292608                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9264448                       # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide        38510                       # Number of read requests responded to by this memory
+system.physmem.num_reads::pc.south_bridge.ide        37827                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.dtb.walker            2                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              13341                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              13324                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             165627                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             165706                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                217485                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                216864                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          145197                       # Number of write requests responded to by this memory
+system.physmem.num_writes::writebacks          144757                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               145197                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               144757                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide       482124                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide       473568                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.dtb.walker             25                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             63                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               167022                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               166807                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2073561                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2074526                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2722795                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2714989                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          167022                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          166807                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             167022                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             166807                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1817788                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1812259                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1817788                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1812259                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1817788                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1812259                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       482124                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       473568                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker            25                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            63                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              167022                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              166807                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2073561                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2074526                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4540583                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4527248                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                             0                       # Total number of read requests seen
 system.physmem.writeReqs                            0                       # Total number of write requests seen
 system.physmem.cpureqs                              0                       # Reqs generatd by CPU via cache - shady
@ -189,31 +189,31 @@ system.physmem.writeRowHits                         0                       # Nu
 system.physmem.readRowHitRate                     nan                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
 system.physmem.avgGap                             nan                       # Average gap between requests
-system.iocache.replacements                     47569                       # number of replacements
+system.iocache.replacements                     47568                       # number of replacements
-system.iocache.tagsinuse                     0.042402                       # Cycle average of tags in use
+system.iocache.tagsinuse                     0.042441                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.sampled_refs                     47585                       # Sample count of references to valid blocks.
+system.iocache.sampled_refs                     47584                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              4994776682059                       # Cycle when the warmup percentage was hit.
+system.iocache.warmup_cycle              4994822603059                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide     0.042402                       # Average occupied blocks per requestor
+system.iocache.occ_blocks::pc.south_bridge.ide     0.042441                       # Average occupied blocks per requestor
-system.iocache.occ_percent::pc.south_bridge.ide     0.002650                       # Average percentage of cache occupancy
+system.iocache.occ_percent::pc.south_bridge.ide     0.002653                       # Average percentage of cache occupancy
-system.iocache.occ_percent::total            0.002650                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.002653                       # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide          904                       # number of ReadReq misses
+system.iocache.ReadReq_misses::pc.south_bridge.ide          903                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              904                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              903                       # number of ReadReq misses
 system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide        47624                       # number of demand (read+write) misses
+system.iocache.demand_misses::pc.south_bridge.ide        47623                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47624                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             47623                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide        47624                       # number of overall misses
+system.iocache.overall_misses::pc.south_bridge.ide        47623                       # number of overall misses
-system.iocache.overall_misses::total            47624                       # number of overall misses
+system.iocache.overall_misses::total            47623                       # number of overall misses
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          904                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          903                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            904                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            903                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide        47624                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide        47623                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47624                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           47623                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide        47624                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide        47623                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47624                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          47623                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
@ -245,63 +245,63 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.cpu.numCycles                      10224081964                       # number of cpu cycles simulated
+system.cpu.numCycles                      10224199744                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   199810242                       # Number of instructions committed
+system.cpu.committedInsts                   199905607                       # Number of instructions committed
-system.cpu.committedOps                     409125913                       # Number of ops (including micro ops) committed
+system.cpu.committedOps                     409299132                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             374289904                       # Number of integer alu accesses
+system.cpu.num_int_alu_accesses             374462045                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     39954533                       # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts     39972114                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    374289904                       # number of integer instructions
+system.cpu.num_int_insts                    374462045                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads           915450656                       # number of times the integer registers were read
+system.cpu.num_int_register_reads           915890298                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          480322719                       # number of times the integer registers were written
+system.cpu.num_int_register_writes          480542887                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      35624590                       # number of memory refs
+system.cpu.num_mem_refs                      35654170                       # number of memory refs
-system.cpu.num_load_insts                    27216588                       # Number of load instructions
+system.cpu.num_load_insts                    27234345                       # Number of load instructions
-system.cpu.num_store_insts                    8408002                       # Number of store instructions
+system.cpu.num_store_insts                    8419825                       # Number of store instructions
-system.cpu.num_idle_cycles               9770609609.165962                       # Number of idle cycles
+system.cpu.num_idle_cycles               9770518400.401503                       # Number of idle cycles
-system.cpu.num_busy_cycles               453472354.834038                       # Number of busy cycles
+system.cpu.num_busy_cycles               453681343.598497                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.044353                       # Percentage of non-idle cycles
+system.cpu.not_idle_fraction                 0.044373                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.955647                       # Percentage of idle cycles
+system.cpu.idle_fraction                     0.955627                       # Percentage of idle cycles
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
-system.cpu.icache.replacements                 790732                       # number of replacements
+system.cpu.icache.replacements                 790584                       # number of replacements
-system.cpu.icache.tagsinuse                510.627675                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                510.666660                       # Cycle average of tags in use
-system.cpu.icache.total_refs                243360727                       # Total number of references to valid blocks.
+system.cpu.icache.total_refs                243492014                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                 791244                       # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs                 791096                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                 307.567232                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                 307.790728                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle           148763114500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.warmup_cycle           148824778500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     510.627675                       # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst     510.666660                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.997320                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::cpu.inst      0.997396                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.997320                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.997396                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    243360727                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::cpu.inst    243492014                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       243360727                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       243492014                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     243360727                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::cpu.inst     243492014                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        243360727                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        243492014                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    243360727                       # number of overall hits
+system.cpu.icache.overall_hits::cpu.inst    243492014                       # number of overall hits
-system.cpu.icache.overall_hits::total       243360727                       # number of overall hits
+system.cpu.icache.overall_hits::total       243492014                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       791251                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::cpu.inst       791103                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        791251                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        791103                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       791251                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::cpu.inst       791103                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         791251                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         791103                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       791251                       # number of overall misses
+system.cpu.icache.overall_misses::cpu.inst       791103                       # number of overall misses
-system.cpu.icache.overall_misses::total        791251                       # number of overall misses
+system.cpu.icache.overall_misses::total        791103                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst    244151978                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::cpu.inst    244283117                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    244151978                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    244283117                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    244151978                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::cpu.inst    244283117                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    244151978                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    244283117                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    244151978                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    244283117                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    244151978                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    244283117                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.003241                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.003238                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.003241                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.003238                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.003241                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.003238                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.003241                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.003238                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.003241                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.003238                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.003241                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.003238                       # miss rate for overall accesses
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@ -311,43 +311,43 @@ system.cpu.icache.avg_blocked_cycles::no_targets          nan
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.replacements         3335                       # number of replacements
+system.cpu.itb_walker_cache.replacements         3477                       # number of replacements
-system.cpu.itb_walker_cache.tagsinuse        3.026483                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tagsinuse        3.026333                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.total_refs           8029                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.total_refs           7886                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.sampled_refs         3346                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.sampled_refs         3489                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.avg_refs         2.399582                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.avg_refs         2.260246                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5102019607500                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.warmup_cycle 5102064745500                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     3.026483                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     3.026333                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.189155                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.189146                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.occ_percent::total     0.189155                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.occ_percent::total     0.189146                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         8031                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7887                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total         8031                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total         7887                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         8033                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7889                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total         8033                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total         7889                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         8033                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7889                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total         8033                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total         7889                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4194                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4332                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total         4194                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total         4332                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4194                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4332                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total         4194                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total         4332                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4194                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4332                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total         4194                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total         4332                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12225                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12219                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        12225                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        12219                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12227                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12221                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        12227                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        12221                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12227                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12221                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        12227                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        12221                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.343067                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.354530                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.343067                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.354530                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.343011                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.354472                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.343011                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.354472                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.343011                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.354472                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.343011                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.354472                       # miss rate for overall accesses
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@ -356,42 +356,42 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks          593                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::writebacks          526                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total          593                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total          526                       # number of writebacks
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.replacements         7597                       # number of replacements
+system.cpu.dtb_walker_cache.replacements         7629                       # number of replacements
-system.cpu.dtb_walker_cache.tagsinuse        5.013746                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tagsinuse        5.014191                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs          13015                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.total_refs          12947                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.sampled_refs         7611                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.sampled_refs         7641                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.avg_refs         1.710025                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.avg_refs         1.694412                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5101206385500                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.warmup_cycle 5100425401500                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker     5.013746                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker     5.014191                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.313359                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.313387                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.occ_percent::total     0.313359                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.occ_percent::total     0.313387                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        13017                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        12955                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total        13017                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total        12955                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        13017                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        12955                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total        13017                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total        12955                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        13017                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        12955                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total        13017                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total        12955                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8791                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8819                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total         8791                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total         8819                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8791                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8819                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total         8791                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total         8819                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8791                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8819                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total         8791                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total         8819                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        21808                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        21774                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total        21808                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total        21774                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        21808                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        21774                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total        21808                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total        21774                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21808                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21774                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total        21808                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total        21774                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.403109                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.405024                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.403109                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.405024                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.403109                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.405024                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.403109                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.405024                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.403109                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.405024                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.403109                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.405024                       # miss rate for overall accesses
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@ -400,50 +400,50 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks         2556                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::writebacks         2413                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total         2556                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total         2413                       # number of writebacks
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1621135                       # number of replacements
+system.cpu.dcache.replacements                1621965                       # number of replacements
-system.cpu.dcache.tagsinuse                511.999456                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                511.999425                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 20140431                       # Total number of references to valid blocks.
+system.cpu.dcache.total_refs                 20168700                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1621647                       # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs                1622477                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  12.419738                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  12.430808                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                7549500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.999456                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data     511.999425                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.999999                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.999999                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     12055941                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data     12073043                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        12055941                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        12073043                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8082228                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8093389                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8082228                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8093389                       # number of WriteReq hits
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 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@ -452,106 +452,106 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
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 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                106558                       # number of replacements
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-system.cpu.l2cache.tagsinuse             64822.149220                       # Cycle average of tags in use
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-system.cpu.l2cache.avg_refs                 20.250086                       # Average number of references to valid blocks.
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 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
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+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001781                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016862                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016844                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.102750                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.102746                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.074295                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.074299                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@ -560,8 +560,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        98530                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        98090                       # number of writebacks
-system.cpu.l2cache.writebacks::total            98530                       # number of writebacks
+system.cpu.l2cache.writebacks::total            98090                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 ---------- End Simulation Statistics   ----------
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
@ -181,7 +181,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
 [system.cpu.interrupts]
 type=X86LocalApic
-clock=500
+clock=8000
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@ -254,6 +254,7 @@ type=CoherentBus
 block_size=64
 clock=500
 header_cycles=1
 system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@ -264,17 +265,23 @@ type=ExeTracer
 [system.e820_table]
 type=X86E820Table
-children=entries0 entries1
+children=entries0 entries1 entries2
-entries=system.e820_table.entries0 system.e820_table.entries1
+entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2
 [system.e820_table.entries0]
 type=X86E820Entry
 addr=0
-range_type=2
+range_type=1
-size=1048576
+size=654336
 [system.e820_table.entries1]
 type=X86E820Entry
 addr=654336
 range_type=2
 size=394240
 [system.e820_table.entries2]
 type=X86E820Entry
 addr=1048576
 range_type=1
 size=133169152
@ -664,6 +671,7 @@ children=badaddr_responder
 block_size=64
 clock=1000
 header_cycles=1
 system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
@ -1123,25 +1131,28 @@ pio=system.iobus.master[9]
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
 addr_mapping=openmap
 banks_per_rank=8
 channels=1
 clock=1000
 conf_table_reported=false
 in_addr_map=true
-lines_per_rowbuffer=64
+lines_per_rowbuffer=32
-mem_sched_policy=fcfs
+mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
-tBURST=4000
+tBURST=5000
-tCL=14000
+tCL=13750
-tRCD=14000
+tRCD=13750
 tREFI=7800000
 tRFC=300000
-tRP=14000
+tRP=13750
-tWTR=1000
+tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
 zero=false
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
@ -1,3 +1,4 @@
 warn: add_child('terminal'): child 'terminal' already has parent
 warn: Sockets disabled, not accepting terminal connections
 warn: Reading current count from inactive timer.
 warn: Sockets disabled, not accepting gdb connections
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
@ -3,13 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-si
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 16:30:44
+gem5 compiled Mar 28 2013 09:59:18
-gem5 started Jan 23 2013 18:02:27
+gem5 started Mar 28 2013 09:59:40
 gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5191112864000 because m5_exit instruction encountered
+Exiting @ tick 5191816279000 because m5_exit instruction encountered
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt