Merge with head.

--HG--
extra : convert_revision : 4a34b3f91c4fc90055596245ae3efec45ea33888

src/SConscript

@@ -26,14 +26,17 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Steve Reinhardt
+# Authors: Nathan Binkert
 
+import imp
 import os
 import sys
-import zipfile
 
 from os.path import basename
 from os.path import join as joinpath
+from os.path import exists
+from os.path import isdir
+from os.path import isfile
 
 import SCons
 
@@ -45,47 +48,87 @@ Import('*')
 # Children need to see the environment
 Export('env')
 
-########################################################################
+def sort_list(_list):
-# Code for adding source files
+    """return a sorted copy of '_list'"""
-#
+    if isinstance(_list, list):
-sources = []
+        _list = _list[:]
-def Source(source):
-    if isinstance(source, SCons.Node.FS.File):
-        sources.append(source)
     else:
-        sources.append(File(source))
+        _list = list(_list)
+    _list.sort()
+    return _list
+
+class PySourceFile(object):
+    def __init__(self, package, source):
+        filename = str(source)
+        pyname = basename(filename)
+        assert pyname.endswith('.py')
+        name = pyname[:-3]
+        path = package.split('.')
+        modpath = path
+        if name != '__init__':
+            modpath += [name]
+        modpath = '.'.join(modpath)
+
+        arcpath = package.split('.') + [ pyname + 'c' ]
+        arcname = joinpath(*arcpath)
+
+        self.source = source
+        self.pyname = pyname
+        self.srcpath = source.srcnode().abspath
+        self.package = package
+        self.modpath = modpath
+        self.arcname = arcname
+        self.filename = filename
+        self.compiled = File(filename + 'c')
+
+########################################################################
+# Code for adding source files of various types
+#
+cc_sources = []
+def Source(source):
+    '''Add a C/C++ source file to the build'''
+    if not isinstance(source, SCons.Node.FS.File):
+        source = File(source)
+
+    cc_sources.append(source)
+
+py_sources = []
+def PySource(package, source):
+    '''Add a python source file to the named package'''
+    if not isinstance(source, SCons.Node.FS.File):
+        source = File(source)
+
+    source = PySourceFile(package, source)
+    py_sources.append(source)
+
+sim_objects_fixed = False
+sim_object_modfiles = set()
+def SimObject(source):
+    '''Add a SimObject python file as a python source object and add
+    it to a list of sim object modules'''
+
+    if sim_objects_fixed:
+        raise AttributeError, "Too late to call SimObject now."
+
+    if not isinstance(source, SCons.Node.FS.File):
+        source = File(source)
+
+    PySource('m5.objects', source)
+    modfile = basename(str(source))
+    assert modfile.endswith('.py')
+    modname = modfile[:-3]
+    sim_object_modfiles.add(modname)
+
+swig_sources = []
+def SwigSource(package, source):
+    '''Add a swig file to build'''
+    if not isinstance(source, SCons.Node.FS.File):
+        source = File(source)
+    val = source,package
+    swig_sources.append(val)
 
 # Children should have access
 Export('Source')
-
-########################################################################
-# Code for adding python objects
-#
-py_sources = []
-py_source_packages = {}
-def PySource(package, source):
-    if not isinstance(source, SCons.Node.FS.File):
-        source = File(source)
-    py_source_packages[source] = package
-    py_sources.append(source)
-
-sim_objects = []
-def SimObject(source):
-    if not isinstance(source, SCons.Node.FS.File):
-        source = File(source)
-    PySource('m5.objects', source)
-    modname = basename(str(source))
-    sim_objects.append(modname)
-
-swig_sources = []
-swig_source_packages = {}
-def SwigSource(package, source):
-    if not isinstance(source, SCons.Node.FS.File):
-        source = File(source)
-    swig_source_packages[source] = package
-    swig_sources.append(source)
-
-# Children should have access
 Export('PySource')
 Export('SimObject')
 Export('SwigSource')
@@ -105,6 +148,7 @@ env.Append(CPPPATH=Dir('.'))
 env.Append(CPPDEFINES=[('THE_ISA','%s_ISA' % env['TARGET_ISA'].upper())])
 
 ########################################################################
+#
 # Walk the tree and execute all SConscripts
 #
 scripts = []
@@ -113,7 +157,7 @@ for root, dirs, files in os.walk(srcdir, topdown=True):
     if root == srcdir:
         # we don't want to recurse back into this SConscript
         continue
-    
+
     if 'SConscript' in files:
         # strip off the srcdir part since scons will try to find the
         # script in the build directory
@@ -125,120 +169,148 @@ for opt in env.ExportOptions:
 
 ########################################################################
 #
-# Deal with python/swig, object code.  Collect .py files and
+# Prevent any SimObjects from being added after this point, they
-# generating a zip archive that is appended to the m5 binary.
+# should all have been added in the SConscripts above
+#
+sim_objects_fixed = True
+
+########################################################################
+#
+# Manually turn python/generate.py into a python module and import it
+#
+generate_file = File('python/generate.py')
+generate_module = imp.new_module('generate')
+sys.modules['generate'] = generate_module
+exec file(generate_file.srcnode().abspath, 'r') in generate_module.__dict__
+
+########################################################################
+#
+# build a generate
+#
+from generate import Generate
+optionDict = dict([(opt, env[opt]) for opt in env.ExportOptions])
+generate = Generate(py_sources, sim_object_modfiles, optionDict)
+m5 = generate.m5
+
+########################################################################
+#
+# calculate extra dependencies
+#
+module_depends = ["m5", "m5.SimObject", "m5.params"]
+module_depends = [ File(generate.py_modules[dep]) for dep in module_depends ]
+file_depends = [ generate_file ]
+depends = module_depends + file_depends
+
+########################################################################
+#
+# Commands for the basic automatically generated python files
 #
 
-# Generate Python file that contains a dict specifying the current
+# Generate a file with all of the compile options in it
-# build_env flags.
+env.Command('python/m5/defines.py', Value(optionDict),
-def MakeDefinesPyFile(target, source, env):
+            generate.makeDefinesPyFile)
-    f = file(str(target[0]), 'w')
-    print >>f, "m5_build_env = ", source[0]
-    f.close()
-
-optionDict = dict([(opt, env[opt]) for opt in env.ExportOptions])
-env.Command('python/m5/defines.py', Value(optionDict), MakeDefinesPyFile)
 PySource('m5', 'python/m5/defines.py')
 
-def MakeInfoPyFile(target, source, env):
+# Generate a file that wraps the basic top level files
-    f = file(str(target[0]), 'w')
-    for src in source:
-        data = ''.join(file(src.srcnode().abspath, 'r').xreadlines())
-        print >>f, "%s = %s" % (src, repr(data))
-    f.close()
-
 env.Command('python/m5/info.py',
             [ '#/AUTHORS', '#/LICENSE', '#/README', '#/RELEASE_NOTES' ],
-            MakeInfoPyFile)
+            generate.makeInfoPyFile)
 PySource('m5', 'python/m5/info.py')
 
-def MakeObjectsInitFile(target, source, env):
+# Generate an __init__.py file for the objects package
-    f = file(str(target[0]), 'w')
-    print >>f, 'from m5.SimObject import *'
-    for src_path in source:
-        src_file = basename(src_path.get_contents())
-        assert(src_file.endswith('.py'))
-        src_module = src_file[:-3]
-        print >>f, 'from %s import *' % src_module
-    f.close()
-
 env.Command('python/m5/objects/__init__.py',
-            [ Value(o) for o in sim_objects],
+            [ Value(o) for o in sort_list(sim_object_modfiles) ],
-            MakeObjectsInitFile)
+            generate.makeObjectsInitFile)
 PySource('m5.objects', 'python/m5/objects/__init__.py')
 
-swig_modules = []
+########################################################################
-for source in swig_sources:
+#
-    source.rfile() # Hack to cause the symlink to the .i file to be created
+# Create all of the SimObject param headers and enum headers
-    package = swig_source_packages[source]
+#
-    filename = str(source)
-    module = basename(filename)
 
-    assert(module.endswith('.i'))
+# Generate all of the SimObject param struct header files
-    module = module[:-2]
+params_hh_files = []
-    cc_file = 'swig/%s_wrap.cc' % module
+for name,simobj in generate.sim_objects.iteritems():
-    py_file = 'm5/internal/%s.py' % module
+    extra_deps = [ File(generate.py_modules[simobj.__module__]) ]
+
+    hh_file = File('params/%s.hh' % name)
+    params_hh_files.append(hh_file)
+    env.Command(hh_file, Value(name), generate.createSimObjectParam)
+    env.Depends(hh_file, depends + extra_deps)
+
+# Generate any parameter header files needed
+for name,param in generate.params.iteritems():
+    if isinstance(param, m5.params.VectorParamDesc):
+        ext = 'vptype'
+    else:
+        ext = 'ptype'
+
+    i_file = File('params/%s_%s.i' % (name, ext))
+    env.Command(i_file, Value(name), generate.createSwigParam)
+    env.Depends(i_file, depends)
+
+# Generate all enum header files
+for name,enum in generate.enums.iteritems():
+    extra_deps = [ File(generate.py_modules[enum.__module__]) ]
+
+    cc_file = File('enums/%s.cc' % name)
+    env.Command(cc_file, Value(name), generate.createEnumStrings)
+    env.Depends(cc_file, depends + extra_deps)
+    Source(cc_file)
+
+    hh_file = File('enums/%s.hh' % name)
+    env.Command(hh_file, Value(name), generate.createEnumParam)
+    env.Depends(hh_file, depends + extra_deps)
+
+# Build the big monolithic swigged params module (wraps all SimObject
+# param structs and enum structs)
+params_file = File('params/params.i')
+names = sort_list(generate.sim_objects.keys())
+env.Command(params_file, [ Value(v) for v in names ],
+            generate.buildParams)
+env.Depends(params_file, params_hh_files + depends)
+SwigSource('m5.objects', params_file)
+
+# Build all swig modules
+swig_modules = []
+for source,package in swig_sources:
+    filename = str(source)
+    assert filename.endswith('.i')
+
+    base = '.'.join(filename.split('.')[:-1])
+    module = basename(base)
+    cc_file = base + '_wrap.cc'
+    py_file = base + '.py'
 
     env.Command([cc_file, py_file], source,
                 '$SWIG $SWIGFLAGS -outdir ${TARGETS[1].dir} '
                 '-o ${TARGETS[0]} $SOURCES')
     env.Depends(py_file, source)
     env.Depends(cc_file, source)
-                
+
     swig_modules.append(Value(module))
     Source(cc_file)
     PySource(package, py_file)
 
-def MakeSwigInit(target, source, env):
+# Generate the main swig init file
-    f = file(str(target[0]), 'w')
+env.Command('swig/init.cc', swig_modules, generate.makeSwigInit)
-    print >>f, 'extern "C" {'
+Source('swig/init.cc')
-    for module in source:
-        print >>f, '    void init_%s();' % module.get_contents()
-    print >>f, '}'
-    print >>f, 'void init_swig() {'
-    for module in source:
-        print >>f, '    init_%s();' % module.get_contents()
-    print >>f, '}'
-    f.close()
-env.Command('python/swig/init.cc', swig_modules, MakeSwigInit)
-
-def CompilePyFile(target, source, env):
-    import py_compile
-    py_compile.compile(str(source[0]), str(target[0]))
 
+# Build the zip file
 py_compiled = []
-py_arcname = {}
 py_zip_depends = []
 for source in py_sources:
-    filename = str(source)
+    env.Command(source.compiled, source.source, generate.compilePyFile)
-    package = py_source_packages[source]
+    py_compiled.append(source.compiled)
-    arc_path = package.split('.') + [ basename(filename) + 'c' ]
-    zip_path = [ 'zip' ] + arc_path
-    arcname = joinpath(*arc_path)
-    zipname = joinpath(*zip_path)
-    f = File(zipname)
-
-    env.Command(f, source, CompilePyFile)
-    py_compiled.append(f)
-    py_arcname[f] = arcname
 
     # make the zipfile depend on the archive name so that the archive
     # is rebuilt if the name changes
-    py_zip_depends.append(Value(arcname))
+    py_zip_depends.append(Value(source.arcname))
-
-# Action function to build the zip archive.  Uses the PyZipFile module
-# included in the standard Python library.
-def buildPyZip(target, source, env):
-    zf = zipfile.ZipFile(str(target[0]), 'w')
-    for s in source:
-        arcname = py_arcname[s]
-        zipname = str(s)
-        zf.write(zipname, arcname)
-    zf.close()
 
 # Add the zip file target to the environment.
-env.Command('m5py.zip', py_compiled, buildPyZip)
+m5zip = File('m5py.zip')
-env.Depends('m5py.zip', py_zip_depends)
+env.Command(m5zip, py_compiled, generate.buildPyZip)
+env.Depends(m5zip, py_zip_depends)
 
 ########################################################################
 #
@@ -273,7 +345,7 @@ def makeEnv(label, objsfx, strip = False, **kwargs):
     newEnv.Append(**kwargs)
     exe = 'm5.' + label  # final executable
     bin = exe + '.bin'   # executable w/o appended Python zip archive
-    newEnv.Program(bin, make_objs(sources, newEnv))
+    newEnv.Program(bin, make_objs(cc_sources, newEnv))
     if strip:
         stripped_bin = bin + '.stripped'
         if sys.platform == 'sunos5':
@@ -308,7 +380,7 @@ elif env['ICC']:
     ccflags['prof'] = '-fast -g -pg'
 else:
     print 'Unknown compiler, please fix compiler options'
-    Exit(1)    
+    Exit(1)
 
 makeEnv('debug', '.do',
         CCFLAGS = Split(ccflags['debug']),

src/arch/alpha/AlphaTLB.py

@@ -35,8 +35,14 @@ class AlphaTLB(SimObject):
 
 class AlphaDTB(AlphaTLB):
     type = 'AlphaDTB'
+    cxx_namespace = 'AlphaISA'
+    cxx_class = 'DTB'
+
     size = 64
 
 class AlphaITB(AlphaTLB):
     type = 'AlphaITB'
+    cxx_namespace = 'AlphaISA'
+    cxx_class = 'ITB'
+
     size = 48

src/arch/alpha/freebsd/system.cc

@@ -35,16 +35,15 @@
  *
  */
 
-#include "arch/alpha/system.hh"
 #include "arch/alpha/freebsd/system.hh"
+#include "arch/alpha/system.hh"
+#include "arch/isa_traits.hh"
+#include "arch/vtophys.hh"
 #include "base/loader/symtab.hh"
 #include "cpu/thread_context.hh"
 #include "mem/physical.hh"
 #include "mem/port.hh"
-#include "arch/isa_traits.hh"
-#include "sim/builder.hh"
 #include "sim/byteswap.hh"
-#include "arch/vtophys.hh"
 
 #define TIMER_FREQUENCY 1193180
 
@@ -92,64 +91,8 @@ FreebsdAlphaSystem::SkipCalibrateClocksEvent::process(ThreadContext *tc)
     ((FreebsdAlphaSystem *)tc->getSystemPtr())->doCalibrateClocks(tc);
 }
 
-
+FreebsdAlphaSystem *
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
+FreebsdAlphaSystemParams::create()
-
-    Param<Tick> boot_cpu_frequency;
-    SimObjectParam<PhysicalMemory *> physmem;
-    SimpleEnumParam<System::MemoryMode> mem_mode;
-
-    Param<string> kernel;
-    Param<string> console;
-    Param<string> pal;
-
-    Param<string> boot_osflags;
-    Param<string> readfile;
-    Param<string> symbolfile;
-    Param<unsigned int> init_param;
-
-    Param<uint64_t> system_type;
-    Param<uint64_t> system_rev;
-
-END_DECLARE_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
-
-    INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
-    INIT_PARAM(physmem, "phsyical memory"),
-    INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
-            System::MemoryModeStrings),
-    INIT_PARAM(kernel, "file that contains the kernel code"),
-    INIT_PARAM(console, "file that contains the console code"),
-    INIT_PARAM(pal, "file that contains palcode"),
-    INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
-                    "a"),
-    INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
-    INIT_PARAM_DFLT(symbolfile, "file to read symbols from", ""),
-    INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
-    INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34),
-    INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10)
-
-END_INIT_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
-
-CREATE_SIM_OBJECT(FreebsdAlphaSystem)
 {
-    AlphaSystem::Params *p = new AlphaSystem::Params;
+    return new FreebsdAlphaSystem(this);
-    p->name = getInstanceName();
-    p->boot_cpu_frequency = boot_cpu_frequency;
-    p->physmem = physmem;
-    p->mem_mode = mem_mode;
-    p->kernel_path = kernel;
-    p->console_path = console;
-    p->palcode = pal;
-    p->boot_osflags = boot_osflags;
-    p->init_param = init_param;
-    p->readfile = readfile;
-    p->symbolfile = symbolfile;
-    p->system_type = system_type;
-    p->system_rev = system_rev;
-    return new FreebsdAlphaSystem(p);
 }
-
-REGISTER_SIM_OBJECT("FreebsdAlphaSystem", FreebsdAlphaSystem)
-

src/arch/alpha/freebsd/system.hh

@@ -28,10 +28,13 @@
  * Authors: Ben Nash
  */
 
-#ifndef __KERN_FREEBSD_FREEBSD_SYSTEM_HH__
+#ifndef __ARCH_ALPHA_FREEBSD_SYSTEM_HH__
-#define __KERN_FREEBSD_FREEBSD_SYSTEM_HH__
+#define __ARCH_ALPHA_FREEBSD_SYSTEM_HH__
 
+#include "arch/alpha/system.hh"
 #include "kern/system_events.hh"
+#include "params/FreebsdAlphaSystem.hh"
+#include "sim/system.hh"
 
 class FreebsdAlphaSystem : public AlphaSystem
 {
@@ -49,10 +52,12 @@ class FreebsdAlphaSystem : public AlphaSystem
     SkipCalibrateClocksEvent *skipCalibrateClocks;
 
   public:
+    typedef FreebsdAlphaSystemParams Params;
     FreebsdAlphaSystem(Params *p);
     ~FreebsdAlphaSystem();
+
     void doCalibrateClocks(ThreadContext *tc);
 
 };
 
-#endif // __KERN_FREEBSD_FREEBSD_SYSTEM_HH__
+#endif // __ARCH_ALPHA_FREEBSD_SYSTEM_HH__

src/arch/alpha/linux/system.cc

@@ -54,7 +54,6 @@
 #include "kern/linux/events.hh"
 #include "mem/physical.hh"
 #include "mem/port.hh"
-#include "sim/builder.hh"
 #include "sim/byteswap.hh"
 
 using namespace std;
@@ -192,64 +191,8 @@ LinuxAlphaSystem::PrintThreadInfo::process(ThreadContext *tc)
             ti.curTaskName(), ti.curTaskPID(), ti.curTaskStart());
 }
 
-
+LinuxAlphaSystem *
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
+LinuxAlphaSystemParams::create()
-
-    Param<Tick> boot_cpu_frequency;
-    SimObjectParam<PhysicalMemory *> physmem;
-    SimpleEnumParam<System::MemoryMode> mem_mode;
-
-    Param<string> kernel;
-    Param<string> console;
-    Param<string> pal;
-
-    Param<string> boot_osflags;
-    Param<string> readfile;
-    Param<string> symbolfile;
-    Param<unsigned int> init_param;
-
-    Param<uint64_t> system_type;
-    Param<uint64_t> system_rev;
-
-END_DECLARE_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
-
-    INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
-    INIT_PARAM(physmem, "phsyical memory"),
-    INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
-            System::MemoryModeStrings),
-    INIT_PARAM(kernel, "file that contains the kernel code"),
-    INIT_PARAM(console, "file that contains the console code"),
-    INIT_PARAM(pal, "file that contains palcode"),
-    INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
-                    "a"),
-    INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
-    INIT_PARAM_DFLT(symbolfile, "file to read symbols from", ""),
-    INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
-    INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34),
-    INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10)
-
-END_INIT_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
-
-CREATE_SIM_OBJECT(LinuxAlphaSystem)
 {
-    AlphaSystem::Params *p = new AlphaSystem::Params;
+    return new LinuxAlphaSystem(this);
-    p->name = getInstanceName();
-    p->boot_cpu_frequency = boot_cpu_frequency;
-    p->physmem = physmem;
-    p->mem_mode = mem_mode;
-    p->kernel_path = kernel;
-    p->console_path = console;
-    p->palcode = pal;
-    p->boot_osflags = boot_osflags;
-    p->init_param = init_param;
-    p->readfile = readfile;
-    p->symbolfile = symbolfile;
-    p->system_type = system_type;
-    p->system_rev = system_rev;
-    return new LinuxAlphaSystem(p);
 }
-
-REGISTER_SIM_OBJECT("LinuxAlphaSystem", LinuxAlphaSystem)
-

src/arch/alpha/linux/system.hh

@@ -41,6 +41,7 @@ class IdleStartEvent;
 #include "arch/alpha/idle_event.hh"
 #include "arch/alpha/system.hh"
 #include "kern/linux/events.hh"
+#include "params/LinuxAlphaSystem.hh"
 
 using namespace AlphaISA;
 using namespace Linux;
@@ -129,6 +130,7 @@ class LinuxAlphaSystem : public AlphaSystem
     IdleStartEvent *idleStartEvent;
 
   public:
+    typedef LinuxAlphaSystemParams Params;
     LinuxAlphaSystem(Params *p);
     ~LinuxAlphaSystem();
 

src/arch/alpha/system.cc

@@ -39,8 +39,8 @@
 #include "base/loader/symtab.hh"
 #include "base/trace.hh"
 #include "mem/physical.hh"
+#include "params/AlphaSystem.hh"
 #include "sim/byteswap.hh"
-#include "sim/builder.hh"
 
 
 using namespace LittleEndianGuest;
@@ -56,14 +56,14 @@ AlphaSystem::AlphaSystem(Params *p)
      * Load the pal, and console code into memory
      */
     // Load Console Code
-    console = createObjectFile(params()->console_path);
+    console = createObjectFile(params()->console);
     if (console == NULL)
-        fatal("Could not load console file %s", params()->console_path);
+        fatal("Could not load console file %s", params()->console);
 
     // Load pal file
-    pal = createObjectFile(params()->palcode);
+    pal = createObjectFile(params()->pal);
     if (pal == NULL)
-        fatal("Could not load PALcode file %s", params()->palcode);
+        fatal("Could not load PALcode file %s", params()->pal);
 
 
     // Load program sections into memory
@@ -212,65 +212,8 @@ AlphaSystem::unserialize(Checkpoint *cp, const std::string &section)
     palSymtab->unserialize("pal_symtab", cp, section);
 }
 
-
+AlphaSystem *
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaSystem)
+AlphaSystemParams::create()
-
-    Param<Tick> boot_cpu_frequency;
-    SimObjectParam<PhysicalMemory *> physmem;
-    SimpleEnumParam<System::MemoryMode> mem_mode;
-
-    Param<std::string> kernel;
-    Param<std::string> console;
-    Param<std::string> pal;
-
-    Param<std::string> boot_osflags;
-    Param<std::string> readfile;
-    Param<std::string> symbolfile;
-    Param<unsigned int> init_param;
-
-    Param<uint64_t> system_type;
-    Param<uint64_t> system_rev;
-
-END_DECLARE_SIM_OBJECT_PARAMS(AlphaSystem)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaSystem)
-
-    INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
-    INIT_PARAM(physmem, "phsyical memory"),
-    INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
-            System::MemoryModeStrings),
-    INIT_PARAM(kernel, "file that contains the kernel code"),
-    INIT_PARAM(console, "file that contains the console code"),
-    INIT_PARAM(pal, "file that contains palcode"),
-    INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
-                    "a"),
-    INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
-    INIT_PARAM_DFLT(symbolfile, "file to read symbols from", ""),
-    INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
-    INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34),
-    INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10)
-
-END_INIT_SIM_OBJECT_PARAMS(AlphaSystem)
-
-CREATE_SIM_OBJECT(AlphaSystem)
 {
-    AlphaSystem::Params *p = new AlphaSystem::Params;
+    return new AlphaSystem(this);
-    p->name = getInstanceName();
-    p->boot_cpu_frequency = boot_cpu_frequency;
-    p->physmem = physmem;
-    p->mem_mode = mem_mode;
-    p->kernel_path = kernel;
-    p->console_path = console;
-    p->palcode = pal;
-    p->boot_osflags = boot_osflags;
-    p->init_param = init_param;
-    p->readfile = readfile;
-    p->symbolfile = symbolfile;
-    p->system_type = system_type;
-    p->system_rev = system_rev;
-    return new AlphaSystem(p);
 }
-
-REGISTER_SIM_OBJECT("AlphaSystem", AlphaSystem)
-
-

src/arch/alpha/system.hh

@@ -35,25 +35,18 @@
 #include <string>
 #include <vector>
 
-#include "sim/system.hh"
 #include "base/loader/symtab.hh"
 #include "cpu/pc_event.hh"
 #include "kern/system_events.hh"
+#include "params/AlphaSystem.hh"
 #include "sim/sim_object.hh"
+#include "sim/system.hh"
 
 class AlphaSystem : public System
 {
   public:
-    struct Params : public System::Params
+    typedef AlphaSystemParams Params;
-    {
-        std::string console_path;
-        std::string palcode;
-        uint64_t system_type;
-        uint64_t system_rev;
-    };
-
     AlphaSystem(Params *p);
-
     ~AlphaSystem();
 
 /**

src/arch/alpha/tlb.cc

@@ -41,7 +41,8 @@
 #include "base/trace.hh"
 #include "config/alpha_tlaser.hh"
 #include "cpu/thread_context.hh"
-#include "sim/builder.hh"
+#include "params/AlphaDTB.hh"
+#include "params/AlphaITB.hh"
 
 using namespace std;
 using namespace EV5;
@@ -600,44 +601,14 @@ TLB::index(bool advance)
 
 /* end namespace AlphaISA */ }
 
-DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", TLB)
+AlphaISA::ITB *
-
+AlphaITBParams::create()
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
-
-    Param<int> size;
-
-END_DECLARE_SIM_OBJECT_PARAMS(ITB)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
-
-    INIT_PARAM_DFLT(size, "TLB size", 48)
-
-END_INIT_SIM_OBJECT_PARAMS(ITB)
-
-
-CREATE_SIM_OBJECT(ITB)
 {
-    return new ITB(getInstanceName(), size);
+    return new AlphaISA::ITB(name, size);
 }
 
-REGISTER_SIM_OBJECT("AlphaITB", ITB)
+AlphaISA::DTB *
-
+AlphaDTBParams::create()
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
-
-    Param<int> size;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DTB)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
-
-    INIT_PARAM_DFLT(size, "TLB size", 64)
-
-END_INIT_SIM_OBJECT_PARAMS(DTB)
-
-
-CREATE_SIM_OBJECT(DTB)
 {
-    return new DTB(getInstanceName(), size);
+    return new AlphaISA::DTB(name, size);
 }
-
-REGISTER_SIM_OBJECT("AlphaDTB", DTB)

src/arch/alpha/tru64/system.cc

@@ -40,7 +40,6 @@
 #include "kern/system_events.hh"
 #include "mem/physical.hh"
 #include "mem/port.hh"
-#include "sim/builder.hh"
 
 using namespace std;
 
@@ -91,63 +90,8 @@ Tru64AlphaSystem::~Tru64AlphaSystem()
 #endif
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
+Tru64AlphaSystem *
-
+Tru64AlphaSystemParams::create()
-    Param<Tick> boot_cpu_frequency;
-    SimObjectParam<PhysicalMemory *> physmem;
-    SimpleEnumParam<System::MemoryMode> mem_mode;
-
-    Param<string> kernel;
-    Param<string> console;
-    Param<string> pal;
-
-    Param<string> boot_osflags;
-    Param<string> readfile;
-    Param<string> symbolfile;
-    Param<unsigned int> init_param;
-
-    Param<uint64_t> system_type;
-    Param<uint64_t> system_rev;
-
-END_DECLARE_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
-
-    INIT_PARAM(boot_cpu_frequency, "frequency of the boot cpu"),
-    INIT_PARAM(physmem, "phsyical memory"),
-    INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
-            System::MemoryModeStrings),
-    INIT_PARAM(kernel, "file that contains the kernel code"),
-    INIT_PARAM(console, "file that contains the console code"),
-    INIT_PARAM(pal, "file that contains palcode"),
-    INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
-                    "a"),
-    INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
-    INIT_PARAM_DFLT(symbolfile, "file to read symbols from", ""),
-    INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
-    INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 12),
-    INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 2<<1)
-
-END_INIT_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
-
-CREATE_SIM_OBJECT(Tru64AlphaSystem)
 {
-    AlphaSystem::Params *p = new AlphaSystem::Params;
+    return new Tru64AlphaSystem(this);
-    p->name = getInstanceName();
-    p->boot_cpu_frequency = boot_cpu_frequency;
-    p->physmem = physmem;
-    p->mem_mode = mem_mode;
-    p->kernel_path = kernel;
-    p->console_path = console;
-    p->palcode = pal;
-    p->boot_osflags = boot_osflags;
-    p->init_param = init_param;
-    p->readfile = readfile;
-    p->symbolfile = symbolfile;
-    p->system_type = system_type;
-    p->system_rev = system_rev;
-
-    return new Tru64AlphaSystem(p);
 }
-
-REGISTER_SIM_OBJECT("Tru64AlphaSystem", Tru64AlphaSystem)

src/arch/alpha/tru64/system.hh

@@ -34,6 +34,7 @@
 
 #include "arch/alpha/system.hh"
 #include "arch/isa_traits.hh"
+#include "params/Tru64AlphaSystem.hh"
 #include "sim/system.hh"
 
 class ThreadContext;
@@ -64,6 +65,7 @@ class Tru64AlphaSystem : public AlphaSystem
     DumpMbufEvent *dumpMbufEvent;
 
   public:
+    typedef Tru64AlphaSystemParams Params;
     Tru64AlphaSystem(Params *p);
     ~Tru64AlphaSystem();
 

src/arch/sparc/SparcTLB.py

@@ -35,8 +35,14 @@ class SparcTLB(SimObject):
 
 class SparcDTB(SparcTLB):
     type = 'SparcDTB'
+    cxx_namespace = 'SparcISA'
+    cxx_class = 'DTB'
+
     size = 64
 
 class SparcITB(SparcTLB):
     type = 'SparcITB'
+    cxx_namespace = 'SparcISA'
+    cxx_class = 'ITB'
+
     size = 64

src/arch/sparc/system.cc

@@ -35,8 +35,8 @@
 #include "base/loader/symtab.hh"
 #include "base/trace.hh"
 #include "mem/physical.hh"
+#include "params/SparcSystem.hh"
 #include "sim/byteswap.hh"
-#include "sim/builder.hh"
 
 
 using namespace BigEndianGuest;
@@ -216,104 +216,8 @@ SparcSystem::unserialize(Checkpoint *cp, const std::string &section)
     partitionDescSymtab->unserialize("partition_desc_symtab", cp, section);
 }
 
-
+SparcSystem *
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(SparcSystem)
+SparcSystemParams::create()
-
-    SimObjectParam<PhysicalMemory *> physmem;
-    SimObjectParam<PhysicalMemory *> rom;
-    SimObjectParam<PhysicalMemory *> nvram;
-    SimObjectParam<PhysicalMemory *> hypervisor_desc;
-    SimObjectParam<PhysicalMemory *> partition_desc;
-    SimpleEnumParam<System::MemoryMode> mem_mode;
-
-    Param<Addr> reset_addr;
-    Param<Addr> hypervisor_addr;
-    Param<Addr> openboot_addr;
-    Param<Addr> nvram_addr;
-    Param<Addr> hypervisor_desc_addr;
-    Param<Addr> partition_desc_addr;
-
-    Param<std::string> kernel;
-    Param<std::string> reset_bin;
-    Param<std::string> hypervisor_bin;
-    Param<std::string> openboot_bin;
-    Param<std::string> nvram_bin;
-    Param<std::string> hypervisor_desc_bin;
-    Param<std::string> partition_desc_bin;
-
-    Param<Tick> boot_cpu_frequency;
-    Param<std::string> boot_osflags;
-    Param<std::string> readfile;
-    Param<unsigned int> init_param;
-
-END_DECLARE_SIM_OBJECT_PARAMS(SparcSystem)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(SparcSystem)
-
-    INIT_PARAM(physmem, "phsyical memory"),
-    INIT_PARAM(rom, "ROM for boot code"),
-    INIT_PARAM(nvram, "Non-volatile RAM for the nvram"),
-    INIT_PARAM(hypervisor_desc, "ROM for the hypervisor description"),
-    INIT_PARAM(partition_desc, "ROM for the partition description"),
-    INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
-            System::MemoryModeStrings),
-
-    INIT_PARAM(reset_addr, "Address that reset should be loaded at"),
-    INIT_PARAM(hypervisor_addr, "Address that hypervisor should be loaded at"),
-    INIT_PARAM(openboot_addr, "Address that openboot should be loaded at"),
-    INIT_PARAM(nvram_addr, "Address that nvram should be loaded at"),
-    INIT_PARAM(hypervisor_desc_addr,
-            "Address that hypervisor description should be loaded at"),
-    INIT_PARAM(partition_desc_addr,
-            "Address that partition description should be loaded at"),
-
-    INIT_PARAM(kernel, "file that contains the kernel code"),
-    INIT_PARAM(reset_bin, "file that contains the reset code"),
-    INIT_PARAM(hypervisor_bin, "file that contains the hypervisor code"),
-    INIT_PARAM(openboot_bin, "file that contains the openboot code"),
-    INIT_PARAM(nvram_bin, "file that contains the nvram image"),
-    INIT_PARAM(hypervisor_desc_bin,
-            "file that contains the hypervisor description image"),
-    INIT_PARAM(partition_desc_bin,
-            "file that contains the partition description image"),
-    INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
-    INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
-                    "a"),
-    INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
-    INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0)
-
-END_INIT_SIM_OBJECT_PARAMS(SparcSystem)
-
-CREATE_SIM_OBJECT(SparcSystem)
 {
-    SparcSystem::Params *p = new SparcSystem::Params;
+    return new SparcSystem(this);
-    p->name = getInstanceName();
-    p->boot_cpu_frequency = boot_cpu_frequency;
-    p->physmem = physmem;
-    p->rom = rom;
-    p->nvram = nvram;
-    p->hypervisor_desc = hypervisor_desc;
-    p->partition_desc = partition_desc;
-    p->mem_mode = mem_mode;
-    p->kernel_path = kernel;
-    p->reset_addr = reset_addr;
-    p->hypervisor_addr = hypervisor_addr;
-    p->openboot_addr = openboot_addr;
-    p->nvram_addr = nvram_addr;
-    p->hypervisor_desc_addr = hypervisor_desc_addr;
-    p->partition_desc_addr = partition_desc_addr;
-    p->reset_bin = reset_bin;
-    p->hypervisor_bin = hypervisor_bin;
-    p->openboot_bin = openboot_bin;
-    p->nvram_bin = nvram_bin;
-    p->hypervisor_desc_bin = hypervisor_desc_bin;
-    p->partition_desc_bin = partition_desc_bin;
-    p->boot_osflags = boot_osflags;
-    p->init_param = init_param;
-    p->readfile = readfile;
-    return new SparcSystem(p);
 }
-
-REGISTER_SIM_OBJECT("SparcSystem", SparcSystem)
-
-

src/arch/sparc/system.hh

@@ -37,35 +37,15 @@
 #include "base/loader/symtab.hh"
 #include "cpu/pc_event.hh"
 #include "kern/system_events.hh"
+#include "params/SparcSystem.hh"
 #include "sim/sim_object.hh"
 #include "sim/system.hh"
 
 class SparcSystem : public System
 {
   public:
-    struct Params : public System::Params
+    typedef SparcSystemParams Params;
-    {
-        PhysicalMemory *rom;
-        PhysicalMemory *nvram;
-        PhysicalMemory *hypervisor_desc;
-        PhysicalMemory *partition_desc;
-        Addr reset_addr;
-        Addr hypervisor_addr;
-        Addr openboot_addr;
-        Addr nvram_addr;
-        Addr hypervisor_desc_addr;
-        Addr partition_desc_addr;
-        std::string reset_bin;
-        std::string hypervisor_bin;
-        std::string openboot_bin;
-        std::string nvram_bin;
-        std::string hypervisor_desc_bin;
-        std::string partition_desc_bin;
-        std::string boot_osflags;
-    };
-
     SparcSystem(Params *p);
-
     ~SparcSystem();
 
 /**

src/arch/sparc/tlb.cc

@@ -39,7 +39,8 @@
 #include "cpu/base.hh"
 #include "mem/packet_access.hh"
 #include "mem/request.hh"
-#include "sim/builder.hh"
+#include "params/SparcDTB.hh"
+#include "params/SparcITB.hh"
 #include "sim/system.hh"
 
 /* @todo remove some of the magic constants.  -- ali
@@ -1386,46 +1387,14 @@ TLB::unserialize(Checkpoint *cp, const std::string &section)
 
 /* end namespace SparcISA */ }
 
-using namespace SparcISA;
+SparcISA::ITB *
-
+SparcITBParams::create()
-DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB)
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
-
-    Param<int> size;
-
-END_DECLARE_SIM_OBJECT_PARAMS(ITB)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
-
-    INIT_PARAM_DFLT(size, "TLB size", 48)
-
-END_INIT_SIM_OBJECT_PARAMS(ITB)
-
-
-CREATE_SIM_OBJECT(ITB)
 {
-    return new ITB(getInstanceName(), size);
+    return new SparcISA::ITB(name, size);
 }
 
-REGISTER_SIM_OBJECT("SparcITB", ITB)
+SparcISA::DTB *
-
+SparcDTBParams::create()
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
-
-    Param<int> size;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DTB)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
-
-    INIT_PARAM_DFLT(size, "TLB size", 64)
-
-END_INIT_SIM_OBJECT_PARAMS(DTB)
-
-
-CREATE_SIM_OBJECT(DTB)
 {
-    return new DTB(getInstanceName(), size);
+    return new SparcISA::DTB(name, size);
 }
-
-REGISTER_SIM_OBJECT("SparcDTB", DTB)

src/cpu/SConscript

@@ -72,7 +72,7 @@ temp_cpu_list = env['CPU_MODELS'][:]
 if env['USE_CHECKER']:
     temp_cpu_list.append('CheckerCPU')
 
-# Generate header.  
+# Generate header.
 def gen_cpu_exec_signatures(target, source, env):
     f = open(str(target[0]), 'w')
     print >> f, '''
@@ -111,7 +111,6 @@ Source('base.cc')
 Source('cpuevent.cc')
 Source('exetrace.cc')
 Source('func_unit.cc')
-Source('op_class.cc')
 Source('pc_event.cc')
 Source('quiesce_event.cc')
 Source('static_inst.cc')

src/cpu/base.cc

@@ -42,7 +42,6 @@
 #include "cpu/thread_context.hh"
 #include "cpu/profile.hh"
 #include "sim/sim_exit.hh"
-#include "sim/param.hh"
 #include "sim/process.hh"
 #include "sim/sim_events.hh"
 #include "sim/system.hh"
@@ -455,6 +454,3 @@ BaseCPU::traceFunctionsInternal(Addr pc)
         functionEntryTick = curTick;
     }
 }
-
-
-DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU)

src/cpu/exetrace.cc

@@ -46,7 +46,7 @@
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/static_inst.hh"
-#include "sim/param.hh"
+#include "enums/OpClass.hh"
 #include "sim/system.hh"
 
 #if FULL_SYSTEM
@@ -355,7 +355,7 @@ Trace::InstRecord::dump()
         outs << " : ";
 
         if (IsOn(ExecOpClass)) {
-            outs << opClassStrings[staticInst->opClass()] << " : ";
+            outs << Enums::OpClassStrings[staticInst->opClass()] << " : ";
         }
 
         if (IsOn(ExecResult) && data_status != DataInvalid) {

src/cpu/func_unit.cc

@@ -32,7 +32,8 @@
 
 #include "base/misc.hh"
 #include "cpu/func_unit.hh"
-#include "sim/builder.hh"
+#include "params/OpDesc.hh"
+#include "params/FUDesc.hh"
 
 using namespace std;
 
@@ -116,56 +117,17 @@ FuncUnit::issueLatency(OpClass capability)
 //
 //  The operation-class description object
 //
-
+OpDesc *
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(OpDesc)
+OpDescParams::create()
-
-    SimpleEnumParam<OpClass> opClass;
-    Param<unsigned>    opLat;
-    Param<unsigned>    issueLat;
-
-END_DECLARE_SIM_OBJECT_PARAMS(OpDesc)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(OpDesc)
-
-    INIT_ENUM_PARAM(opClass, "type of operation", opClassStrings),
-    INIT_PARAM(opLat,        "cycles until result is available"),
-    INIT_PARAM(issueLat,     "cycles until another can be issued")
-
-END_INIT_SIM_OBJECT_PARAMS(OpDesc)
-
-
-CREATE_SIM_OBJECT(OpDesc)
 {
-    return new OpDesc(getInstanceName(), opClass, opLat, issueLat);
+    return new OpDesc(name, opClass, opLat, issueLat);
 }
 
-REGISTER_SIM_OBJECT("OpDesc", OpDesc)
-
-
 //
 //  The FuDesc object
 //
-
+FUDesc *
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(FUDesc)
+FUDescParams::create()
-
-    SimObjectVectorParam<OpDesc *> opList;
-    Param<unsigned>                count;
-
-END_DECLARE_SIM_OBJECT_PARAMS(FUDesc)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(FUDesc)
-
-    INIT_PARAM(opList, "list of operation classes for this FU type"),
-    INIT_PARAM(count,  "number of these FU's available")
-
-END_INIT_SIM_OBJECT_PARAMS(FUDesc)
-
-
-CREATE_SIM_OBJECT(FUDesc)
 {
-    return new FUDesc(getInstanceName(), opList, count);
+    return new FUDesc(name, opList, count);
 }
-
-REGISTER_SIM_OBJECT("FUDesc", FUDesc)
-

src/cpu/intr_control.cc

@@ -35,7 +35,7 @@
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/intr_control.hh"
-#include "sim/builder.hh"
+#include "params/IntrControl.hh"
 #include "sim/sim_object.hh"
 
 using namespace std;
@@ -76,21 +76,8 @@ IntrControl::clear(int cpu_id, int int_num, int index)
     temp->clear_interrupt(int_num, index);
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
+IntrControl *
-
+IntrControlParams::create()
-    SimObjectParam<System *> sys;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IntrControl)
-
-    INIT_PARAM(sys, "the system we are part of")
-
-END_INIT_SIM_OBJECT_PARAMS(IntrControl)
-
-CREATE_SIM_OBJECT(IntrControl)
 {
-    return new IntrControl(getInstanceName(), sys);
+    return new IntrControl(name, sys);
 }
-
-REGISTER_SIM_OBJECT("IntrControl", IntrControl)

src/cpu/memtest/memtest.cc

@@ -46,7 +46,7 @@
 #include "mem/packet.hh"
 //#include "mem/physical.hh"
 #include "mem/request.hh"
-#include "sim/builder.hh"
+#include "params/MemTest.hh"
 #include "sim/sim_events.hh"
 #include "sim/stats.hh"
 
@@ -496,53 +496,15 @@ MemTest::doRetry()
     }
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
+MemTest *
-
+MemTestParams::create()
-//    SimObjectParam<BaseCache *> cache;
-//    SimObjectParam<PhysicalMemory *> main_mem;
-//    SimObjectParam<PhysicalMemory *> check_mem;
-    Param<unsigned> memory_size;
-    Param<unsigned> percent_reads;
-    Param<unsigned> percent_functional;
-    Param<unsigned> percent_uncacheable;
-    Param<unsigned> progress_interval;
-    Param<unsigned> percent_source_unaligned;
-    Param<unsigned> percent_dest_unaligned;
-    Param<Addr> trace_addr;
-    Param<Counter> max_loads;
-    Param<bool> atomic;
-
-END_DECLARE_SIM_OBJECT_PARAMS(MemTest)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
-
-//    INIT_PARAM(cache, "L1 cache"),
-//    INIT_PARAM(main_mem, "hierarchical memory"),
-//    INIT_PARAM(check_mem, "check memory"),
-    INIT_PARAM(memory_size, "memory size"),
-    INIT_PARAM(percent_reads, "target read percentage"),
-    INIT_PARAM(percent_functional, "percentage of access that are functional"),
-    INIT_PARAM(percent_uncacheable, "target uncacheable percentage"),
-    INIT_PARAM(progress_interval, "progress report interval (in accesses)"),
-    INIT_PARAM(percent_source_unaligned,
-               "percent of copy source address that are unaligned"),
-    INIT_PARAM(percent_dest_unaligned,
-               "percent of copy dest address that are unaligned"),
-    INIT_PARAM(trace_addr, "address to trace"),
-                              INIT_PARAM(max_loads, "terminate when we have reached this load count"),
-    INIT_PARAM(atomic, "Is the tester testing atomic mode (or timing)")
-
-END_INIT_SIM_OBJECT_PARAMS(MemTest)
-
-
-CREATE_SIM_OBJECT(MemTest)
 {
-    return new MemTest(getInstanceName(), /*cache->getInterface(),*/ /*main_mem,*/
+    return new MemTest(name,
-                       /*check_mem,*/ memory_size, percent_reads, percent_functional,
+#if 0
+                       cache->getInterface(), main_mem, check_mem,
+#endif
+                       memory_size, percent_reads, percent_functional,
                        percent_uncacheable, progress_interval,
                        percent_source_unaligned, percent_dest_unaligned,
                        trace_addr, max_loads, atomic);
 }
-
-REGISTER_SIM_OBJECT("MemTest", MemTest)

src/cpu/o3/alpha/cpu_builder.cc

@@ -30,12 +30,13 @@
 
 #include <string>
 
+#include "config/use_checker.hh"
 #include "cpu/base.hh"
 #include "cpu/o3/alpha/cpu.hh"
 #include "cpu/o3/alpha/impl.hh"
 #include "cpu/o3/alpha/params.hh"
 #include "cpu/o3/fu_pool.hh"
-#include "sim/builder.hh"
+#include "params/DerivO3CPU.hh"
 
 class DerivO3CPU : public AlphaO3CPU<AlphaSimpleImpl>
 {
@@ -45,245 +46,8 @@ class DerivO3CPU : public AlphaO3CPU<AlphaSimpleImpl>
     { }
 };
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
+DerivO3CPU *
-
+DerivO3CPUParams::create()
-    Param<int> clock;
-    Param<int> phase;
-    Param<int> numThreads;
-Param<int> cpu_id;
-Param<int> activity;
-
-#if FULL_SYSTEM
-SimObjectParam<System *> system;
-SimObjectParam<AlphaISA::ITB *> itb;
-SimObjectParam<AlphaISA::DTB *> dtb;
-Param<Tick> profile;
-
-Param<bool> do_quiesce;
-Param<bool> do_checkpoint_insts;
-Param<bool> do_statistics_insts;
-#else
-SimObjectVectorParam<Process *> workload;
-#endif // FULL_SYSTEM
-
-SimObjectParam<BaseCPU *> checker;
-
-Param<Counter> max_insts_any_thread;
-Param<Counter> max_insts_all_threads;
-Param<Counter> max_loads_any_thread;
-Param<Counter> max_loads_all_threads;
-Param<Tick> progress_interval;
-
-Param<unsigned> cachePorts;
-
-Param<unsigned> decodeToFetchDelay;
-Param<unsigned> renameToFetchDelay;
-Param<unsigned> iewToFetchDelay;
-Param<unsigned> commitToFetchDelay;
-Param<unsigned> fetchWidth;
-
-Param<unsigned> renameToDecodeDelay;
-Param<unsigned> iewToDecodeDelay;
-Param<unsigned> commitToDecodeDelay;
-Param<unsigned> fetchToDecodeDelay;
-Param<unsigned> decodeWidth;
-
-Param<unsigned> iewToRenameDelay;
-Param<unsigned> commitToRenameDelay;
-Param<unsigned> decodeToRenameDelay;
-Param<unsigned> renameWidth;
-
-Param<unsigned> commitToIEWDelay;
-Param<unsigned> renameToIEWDelay;
-Param<unsigned> issueToExecuteDelay;
-Param<unsigned> dispatchWidth;
-Param<unsigned> issueWidth;
-Param<unsigned> wbWidth;
-Param<unsigned> wbDepth;
-SimObjectParam<FUPool *> fuPool;
-
-Param<unsigned> iewToCommitDelay;
-Param<unsigned> renameToROBDelay;
-Param<unsigned> commitWidth;
-Param<unsigned> squashWidth;
-Param<Tick> trapLatency;
-
-Param<unsigned> backComSize;
-Param<unsigned> forwardComSize;
-
-Param<std::string> predType;
-Param<unsigned> localPredictorSize;
-Param<unsigned> localCtrBits;
-Param<unsigned> localHistoryTableSize;
-Param<unsigned> localHistoryBits;
-Param<unsigned> globalPredictorSize;
-Param<unsigned> globalCtrBits;
-Param<unsigned> globalHistoryBits;
-Param<unsigned> choicePredictorSize;
-Param<unsigned> choiceCtrBits;
-
-Param<unsigned> BTBEntries;
-Param<unsigned> BTBTagSize;
-
-Param<unsigned> RASSize;
-
-Param<unsigned> LQEntries;
-Param<unsigned> SQEntries;
-Param<unsigned> LFSTSize;
-Param<unsigned> SSITSize;
-
-Param<unsigned> numPhysIntRegs;
-Param<unsigned> numPhysFloatRegs;
-Param<unsigned> numIQEntries;
-Param<unsigned> numROBEntries;
-
-Param<unsigned> smtNumFetchingThreads;
-Param<std::string>   smtFetchPolicy;
-Param<std::string>   smtLSQPolicy;
-Param<unsigned> smtLSQThreshold;
-Param<std::string>   smtIQPolicy;
-Param<unsigned> smtIQThreshold;
-Param<std::string>   smtROBPolicy;
-Param<unsigned> smtROBThreshold;
-Param<std::string>   smtCommitPolicy;
-
-Param<unsigned> instShiftAmt;
-
-Param<bool> defer_registration;
-
-Param<bool> function_trace;
-Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-    INIT_PARAM(clock, "clock speed"),
-    INIT_PARAM_DFLT(phase, "clock phase", 0),
-    INIT_PARAM(numThreads, "number of HW thread contexts"),
-    INIT_PARAM(cpu_id, "processor ID"),
-    INIT_PARAM_DFLT(activity, "Initial activity count", 0),
-
-#if FULL_SYSTEM
-    INIT_PARAM(system, "System object"),
-    INIT_PARAM(itb, "Instruction translation buffer"),
-    INIT_PARAM(dtb, "Data translation buffer"),
-    INIT_PARAM(profile, ""),
-
-    INIT_PARAM(do_quiesce, ""),
-    INIT_PARAM(do_checkpoint_insts, ""),
-    INIT_PARAM(do_statistics_insts, ""),
-#else
-    INIT_PARAM(workload, "Processes to run"),
-#endif // FULL_SYSTEM
-
-    INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
-
-    INIT_PARAM_DFLT(max_insts_any_thread,
-                    "Terminate when any thread reaches this inst count",
-                    0),
-    INIT_PARAM_DFLT(max_insts_all_threads,
-                    "Terminate when all threads have reached"
-                    "this inst count",
-                    0),
-    INIT_PARAM_DFLT(max_loads_any_thread,
-                    "Terminate when any thread reaches this load count",
-                    0),
-    INIT_PARAM_DFLT(max_loads_all_threads,
-                    "Terminate when all threads have reached this load"
-                    "count",
-                    0),
-    INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
-
-    INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
-
-    INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
-    INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
-    INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
-               "delay"),
-    INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
-    INIT_PARAM(fetchWidth, "Fetch width"),
-    INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
-    INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
-               "delay"),
-    INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
-    INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
-    INIT_PARAM(decodeWidth, "Decode width"),
-
-    INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
-               "delay"),
-    INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
-    INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
-    INIT_PARAM(renameWidth, "Rename width"),
-
-    INIT_PARAM(commitToIEWDelay, "Commit to "
-               "Issue/Execute/Writeback delay"),
-    INIT_PARAM(renameToIEWDelay, "Rename to "
-               "Issue/Execute/Writeback delay"),
-    INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
-               "to the IEW stage)"),
-    INIT_PARAM(dispatchWidth, "Dispatch width"),
-    INIT_PARAM(issueWidth, "Issue width"),
-    INIT_PARAM(wbWidth, "Writeback width"),
-    INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"),
-    INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
-
-    INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
-               "delay"),
-    INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
-    INIT_PARAM(commitWidth, "Commit width"),
-    INIT_PARAM(squashWidth, "Squash width"),
-    INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6),
-
-    INIT_PARAM(backComSize, "Time buffer size for backwards communication"),
-    INIT_PARAM(forwardComSize, "Time buffer size for forward communication"),
-
-    INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
-    INIT_PARAM(localPredictorSize, "Size of local predictor"),
-    INIT_PARAM(localCtrBits, "Bits per counter"),
-    INIT_PARAM(localHistoryTableSize, "Size of local history table"),
-    INIT_PARAM(localHistoryBits, "Bits for the local history"),
-    INIT_PARAM(globalPredictorSize, "Size of global predictor"),
-    INIT_PARAM(globalCtrBits, "Bits per counter"),
-    INIT_PARAM(globalHistoryBits, "Bits of history"),
-    INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
-    INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
-
-    INIT_PARAM(BTBEntries, "Number of BTB entries"),
-    INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
-
-    INIT_PARAM(RASSize, "RAS size"),
-
-    INIT_PARAM(LQEntries, "Number of load queue entries"),
-    INIT_PARAM(SQEntries, "Number of store queue entries"),
-    INIT_PARAM(LFSTSize, "Last fetched store table size"),
-    INIT_PARAM(SSITSize, "Store set ID table size"),
-
-    INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
-    INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
-               "registers"),
-    INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
-    INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
-
-    INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
-    INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
-    INIT_PARAM_DFLT(smtLSQPolicy,   "SMT LSQ Sharing Policy",    "Partitioned"),
-    INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
-    INIT_PARAM_DFLT(smtIQPolicy,    "SMT IQ Policy",    "Partitioned"),
-    INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
-    INIT_PARAM_DFLT(smtROBPolicy,   "SMT ROB Sharing Policy", "Partitioned"),
-    INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
-    INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
-
-    INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
-    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-
-    INIT_PARAM(function_trace, "Enable function trace"),
-    INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-CREATE_SIM_OBJECT(DerivO3CPU)
 {
     DerivO3CPU *cpu;
 
@@ -294,8 +58,7 @@ CREATE_SIM_OBJECT(DerivO3CPU)
     // In non-full-system mode, we infer the number of threads from
     // the workload if it's not explicitly specified.
     int actual_num_threads =
-        (numThreads.isValid() && numThreads >= workload.size()) ?
+        (numThreads >= workload.size()) ? numThreads : workload.size();
-         numThreads : workload.size();
 
     if (workload.size() == 0) {
         fatal("Must specify at least one workload!");
@@ -307,7 +70,7 @@ CREATE_SIM_OBJECT(DerivO3CPU)
     params->clock = clock;
     params->phase = phase;
 
-    params->name = getInstanceName();
+    params->name = name;
     params->numberOfThreads = actual_num_threads;
     params->cpu_id = cpu_id;
     params->activity = activity;
@@ -325,7 +88,9 @@ CREATE_SIM_OBJECT(DerivO3CPU)
     params->workload = workload;
 #endif // FULL_SYSTEM
 
+#if USE_CHECKER
     params->checker = checker;
+#endif
 
     params->max_insts_any_thread = max_insts_any_thread;
     params->max_insts_all_threads = max_insts_all_threads;
@@ -429,6 +194,3 @@ CREATE_SIM_OBJECT(DerivO3CPU)
 
     return cpu;
 }
-
-REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU)
-

src/cpu/o3/checker_builder.cc

@@ -34,7 +34,7 @@
 #include "cpu/inst_seq.hh"
 #include "cpu/o3/alpha/dyn_inst.hh"
 #include "cpu/o3/alpha/impl.hh"
-#include "sim/builder.hh"
+#include "params/O3Checker.hh"
 #include "sim/process.hh"
 #include "sim/sim_object.hh"
 
@@ -58,73 +58,11 @@ class O3Checker : public Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> >
 //
 //  CheckerCPU Simulation Object
 //
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
+O3Checker *
-
+O3CheckerParams::create()
-    Param<Counter> max_insts_any_thread;
-    Param<Counter> max_insts_all_threads;
-    Param<Counter> max_loads_any_thread;
-    Param<Counter> max_loads_all_threads;
-    Param<Tick> progress_interval;
-
-#if FULL_SYSTEM
-    SimObjectParam<TheISA::ITB *> itb;
-    SimObjectParam<TheISA::DTB *> dtb;
-    SimObjectParam<System *> system;
-    Param<int> cpu_id;
-    Param<Tick> profile;
-#else
-    SimObjectParam<Process *> workload;
-#endif // FULL_SYSTEM
-    Param<int> clock;
-
-    Param<bool> defer_registration;
-    Param<bool> exitOnError;
-    Param<bool> updateOnError;
-    Param<bool> warnOnlyOnLoadError;
-    Param<bool> function_trace;
-    Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker)
-
-    INIT_PARAM(max_insts_any_thread,
-               "terminate when any thread reaches this inst count"),
-    INIT_PARAM(max_insts_all_threads,
-               "terminate when all threads have reached this inst count"),
-    INIT_PARAM(max_loads_any_thread,
-               "terminate when any thread reaches this load count"),
-    INIT_PARAM(max_loads_all_threads,
-               "terminate when all threads have reached this load count"),
-    INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0),
-
-#if FULL_SYSTEM
-    INIT_PARAM(itb, "Instruction TLB"),
-    INIT_PARAM(dtb, "Data TLB"),
-    INIT_PARAM(system, "system object"),
-    INIT_PARAM(cpu_id, "processor ID"),
-    INIT_PARAM(profile, ""),
-#else
-    INIT_PARAM(workload, "processes to run"),
-#endif // FULL_SYSTEM
-
-    INIT_PARAM(clock, "clock speed"),
-
-    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-    INIT_PARAM(exitOnError, "exit on error"),
-    INIT_PARAM(updateOnError, "Update the checker with the main CPU's state on error"),
-    INIT_PARAM_DFLT(warnOnlyOnLoadError, "warn, but don't exit, if a load "
-                    "result errors", false),
-    INIT_PARAM(function_trace, "Enable function trace"),
-    INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(O3Checker)
-
-
-CREATE_SIM_OBJECT(O3Checker)
 {
     O3Checker::Params *params = new O3Checker::Params();
-    params->name = getInstanceName();
+    params->name = name;
     params->numberOfThreads = 1;
     params->max_insts_any_thread = 0;
     params->max_insts_all_threads = 0;
@@ -161,5 +99,3 @@ CREATE_SIM_OBJECT(O3Checker)
     O3Checker *cpu = new O3Checker(params);
     return cpu;
 }
-
-REGISTER_SIM_OBJECT("O3Checker", O3Checker)

src/cpu/o3/cpu.cc

@@ -32,6 +32,15 @@
 #include "config/full_system.hh"
 #include "config/use_checker.hh"
 
+#include "cpu/activity.hh"
+#include "cpu/simple_thread.hh"
+#include "cpu/thread_context.hh"
+#include "cpu/o3/isa_specific.hh"
+#include "cpu/o3/cpu.hh"
+#include "enums/MemoryMode.hh"
+#include "sim/core.hh"
+#include "sim/stat_control.hh"
+
 #if FULL_SYSTEM
 #include "cpu/quiesce_event.hh"
 #include "sim/system.hh"
@@ -39,15 +48,6 @@
 #include "sim/process.hh"
 #endif
 
-#include "cpu/activity.hh"
-#include "cpu/simple_thread.hh"
-#include "cpu/thread_context.hh"
-#include "cpu/o3/isa_specific.hh"
-#include "cpu/o3/cpu.hh"
-
-#include "sim/core.hh"
-#include "sim/stat_control.hh"
-
 #if USE_CHECKER
 #include "cpu/checker/cpu.hh"
 #endif
@@ -882,7 +882,7 @@ FullO3CPU<Impl>::resume()
         return;
 
 #if FULL_SYSTEM
-    assert(system->getMemoryMode() == System::Timing);
+    assert(system->getMemoryMode() == Enums::timing);
 #endif
 
     if (!tickEvent.scheduled())

src/cpu/o3/fu_pool.cc

@@ -32,7 +32,7 @@
 
 #include "cpu/o3/fu_pool.hh"
 #include "cpu/func_unit.hh"
-#include "sim/builder.hh"
+#include "params/FUPool.hh"
 
 using namespace std;
 
@@ -275,25 +275,8 @@ FUPool::takeOverFrom()
 //
 //  The FuPool object
 //
-
+FUPool *
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(FUPool)
+FUPoolParams::create()
-
-    SimObjectVectorParam<FUDesc *> FUList;
-
-END_DECLARE_SIM_OBJECT_PARAMS(FUPool)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(FUPool)
-
-    INIT_PARAM(FUList, "list of FU's for this pool")
-
-END_INIT_SIM_OBJECT_PARAMS(FUPool)
-
-
-CREATE_SIM_OBJECT(FUPool)
 {
-    return new FUPool(getInstanceName(), FUList);
+    return new FUPool(name, FUList);
 }
-
-REGISTER_SIM_OBJECT("FUPool", FUPool)
-

src/cpu/o3/inst_queue_impl.hh

@@ -32,10 +32,10 @@
 #include <limits>
 #include <vector>
 
-#include "sim/core.hh"
-
 #include "cpu/o3/fu_pool.hh"
 #include "cpu/o3/inst_queue.hh"
+#include "enums/OpClass.hh"
+#include "sim/core.hh"
 
 template <class Impl>
 InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
@@ -259,12 +259,12 @@ InstructionQueue<Impl>::regStats()
     }
 */
     statIssuedInstType
-        .init(numThreads,Num_OpClasses)
+        .init(numThreads,Enums::Num_OpClass)
         .name(name() + ".ISSUE:FU_type")
         .desc("Type of FU issued")
         .flags(total | pdf | dist)
         ;
-    statIssuedInstType.ysubnames(opClassStrings);
+    statIssuedInstType.ysubnames(Enums::OpClassStrings);
 
     //
     //  How long did instructions for a particular FU type wait prior to issue
@@ -297,7 +297,7 @@ InstructionQueue<Impl>::regStats()
         .flags(pdf | dist)
         ;
     for (int i=0; i < Num_OpClasses; ++i) {
-        statFuBusy.subname(i, opClassStrings[i]);
+        statFuBusy.subname(i, Enums::OpClassStrings[i]);
     }
 
     fuBusy

src/cpu/o3/mips/cpu_builder.cc

@@ -31,12 +31,13 @@
 
 #include <string>
 
+#include "config/use_checker.hh"
 #include "cpu/base.hh"
 #include "cpu/o3/mips/cpu.hh"
 #include "cpu/o3/mips/impl.hh"
 #include "cpu/o3/mips/params.hh"
 #include "cpu/o3/fu_pool.hh"
-#include "sim/builder.hh"
+#include "params/DerivO3CPU.hh"
 
 class DerivO3CPU : public MipsO3CPU<MipsSimpleImpl>
 {
@@ -46,229 +47,15 @@ class DerivO3CPU : public MipsO3CPU<MipsSimpleImpl>
     { }
 };
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
+DerivO3CPU *
-
+DerivO3CPUParams::create()
-Param<int> clock;
-Param<int> phase;
-Param<int> numThreads;
-Param<int> cpu_id;
-Param<int> activity;
-
-SimObjectVectorParam<Process *> workload;
-
-SimObjectParam<BaseCPU *> checker;
-
-Param<Counter> max_insts_any_thread;
-Param<Counter> max_insts_all_threads;
-Param<Counter> max_loads_any_thread;
-Param<Counter> max_loads_all_threads;
-
-Param<unsigned> cachePorts;
-
-Param<unsigned> decodeToFetchDelay;
-Param<unsigned> renameToFetchDelay;
-Param<unsigned> iewToFetchDelay;
-Param<unsigned> commitToFetchDelay;
-Param<unsigned> fetchWidth;
-
-Param<unsigned> renameToDecodeDelay;
-Param<unsigned> iewToDecodeDelay;
-Param<unsigned> commitToDecodeDelay;
-Param<unsigned> fetchToDecodeDelay;
-Param<unsigned> decodeWidth;
-
-Param<unsigned> iewToRenameDelay;
-Param<unsigned> commitToRenameDelay;
-Param<unsigned> decodeToRenameDelay;
-Param<unsigned> renameWidth;
-
-Param<unsigned> commitToIEWDelay;
-Param<unsigned> renameToIEWDelay;
-Param<unsigned> issueToExecuteDelay;
-Param<unsigned> dispatchWidth;
-Param<unsigned> issueWidth;
-Param<unsigned> wbWidth;
-Param<unsigned> wbDepth;
-SimObjectParam<FUPool *> fuPool;
-
-Param<unsigned> iewToCommitDelay;
-Param<unsigned> renameToROBDelay;
-Param<unsigned> commitWidth;
-Param<unsigned> squashWidth;
-Param<Tick> trapLatency;
-
-Param<unsigned> backComSize;
-Param<unsigned> forwardComSize;
-
-Param<std::string> predType;
-Param<unsigned> localPredictorSize;
-Param<unsigned> localCtrBits;
-Param<unsigned> localHistoryTableSize;
-Param<unsigned> localHistoryBits;
-Param<unsigned> globalPredictorSize;
-Param<unsigned> globalCtrBits;
-Param<unsigned> globalHistoryBits;
-Param<unsigned> choicePredictorSize;
-Param<unsigned> choiceCtrBits;
-
-Param<unsigned> BTBEntries;
-Param<unsigned> BTBTagSize;
-
-Param<unsigned> RASSize;
-
-Param<unsigned> LQEntries;
-Param<unsigned> SQEntries;
-Param<unsigned> LFSTSize;
-Param<unsigned> SSITSize;
-
-Param<unsigned> numPhysIntRegs;
-Param<unsigned> numPhysFloatRegs;
-Param<unsigned> numIQEntries;
-Param<unsigned> numROBEntries;
-
-Param<unsigned> smtNumFetchingThreads;
-Param<std::string>   smtFetchPolicy;
-Param<std::string>   smtLSQPolicy;
-Param<unsigned> smtLSQThreshold;
-Param<std::string>   smtIQPolicy;
-Param<unsigned> smtIQThreshold;
-Param<std::string>   smtROBPolicy;
-Param<unsigned> smtROBThreshold;
-Param<std::string>   smtCommitPolicy;
-
-Param<unsigned> instShiftAmt;
-
-Param<bool> defer_registration;
-
-Param<bool> function_trace;
-Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-    INIT_PARAM(clock, "clock speed"),
-    INIT_PARAM_DFLT(phase, "clock phase", 0),
-    INIT_PARAM(numThreads, "number of HW thread contexts"),
-    INIT_PARAM(cpu_id, "processor ID"),
-    INIT_PARAM_DFLT(activity, "Initial activity count", 0),
-
-    INIT_PARAM(workload, "Processes to run"),
-
-    INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
-
-    INIT_PARAM_DFLT(max_insts_any_thread,
-                    "Terminate when any thread reaches this inst count",
-                    0),
-    INIT_PARAM_DFLT(max_insts_all_threads,
-                    "Terminate when all threads have reached"
-                    "this inst count",
-                    0),
-    INIT_PARAM_DFLT(max_loads_any_thread,
-                    "Terminate when any thread reaches this load count",
-                    0),
-    INIT_PARAM_DFLT(max_loads_all_threads,
-                    "Terminate when all threads have reached this load"
-                    "count",
-                    0),
-
-    INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
-
-    INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
-    INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
-    INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
-               "delay"),
-    INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
-    INIT_PARAM(fetchWidth, "Fetch width"),
-    INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
-    INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
-               "delay"),
-    INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
-    INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
-    INIT_PARAM(decodeWidth, "Decode width"),
-
-    INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
-               "delay"),
-    INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
-    INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
-    INIT_PARAM(renameWidth, "Rename width"),
-
-    INIT_PARAM(commitToIEWDelay, "Commit to "
-               "Issue/Execute/Writeback delay"),
-    INIT_PARAM(renameToIEWDelay, "Rename to "
-               "Issue/Execute/Writeback delay"),
-    INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
-               "to the IEW stage)"),
-    INIT_PARAM(dispatchWidth, "Dispatch width"),
-    INIT_PARAM(issueWidth, "Issue width"),
-    INIT_PARAM(wbWidth, "Writeback width"),
-    INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"),
-    INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
-
-    INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
-               "delay"),
-    INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
-    INIT_PARAM(commitWidth, "Commit width"),
-    INIT_PARAM(squashWidth, "Squash width"),
-    INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6),
-
-    INIT_PARAM(backComSize, "Time buffer size for backwards communication"),
-    INIT_PARAM(forwardComSize, "Time buffer size for forward communication"),
-
-    INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
-    INIT_PARAM(localPredictorSize, "Size of local predictor"),
-    INIT_PARAM(localCtrBits, "Bits per counter"),
-    INIT_PARAM(localHistoryTableSize, "Size of local history table"),
-    INIT_PARAM(localHistoryBits, "Bits for the local history"),
-    INIT_PARAM(globalPredictorSize, "Size of global predictor"),
-    INIT_PARAM(globalCtrBits, "Bits per counter"),
-    INIT_PARAM(globalHistoryBits, "Bits of history"),
-    INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
-    INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
-
-    INIT_PARAM(BTBEntries, "Number of BTB entries"),
-    INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
-
-    INIT_PARAM(RASSize, "RAS size"),
-
-    INIT_PARAM(LQEntries, "Number of load queue entries"),
-    INIT_PARAM(SQEntries, "Number of store queue entries"),
-    INIT_PARAM(LFSTSize, "Last fetched store table size"),
-    INIT_PARAM(SSITSize, "Store set ID table size"),
-
-    INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
-    INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
-               "registers"),
-    INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
-    INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
-
-    INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
-    INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
-    INIT_PARAM_DFLT(smtLSQPolicy,   "SMT LSQ Sharing Policy",    "Partitioned"),
-    INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
-    INIT_PARAM_DFLT(smtIQPolicy,    "SMT IQ Policy",    "Partitioned"),
-    INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
-    INIT_PARAM_DFLT(smtROBPolicy,   "SMT ROB Sharing Policy", "Partitioned"),
-    INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
-    INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
-
-    INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
-    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-
-    INIT_PARAM(function_trace, "Enable function trace"),
-    INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-CREATE_SIM_OBJECT(DerivO3CPU)
 {
     DerivO3CPU *cpu;
 
     // In non-full-system mode, we infer the number of threads from
     // the workload if it's not explicitly specified.
     int actual_num_threads =
-        (numThreads.isValid() && numThreads >= workload.size()) ?
+        (numThreads >= workload.size()) ? numThreads : workload.size();
-         numThreads : workload.size();
 
     if (workload.size() == 0) {
         fatal("Must specify at least one workload!");
@@ -279,14 +66,16 @@ CREATE_SIM_OBJECT(DerivO3CPU)
     params->clock = clock;
     params->phase = phase;
 
-    params->name = getInstanceName();
+    params->name = name;
     params->numberOfThreads = actual_num_threads;
     params->cpu_id = cpu_id;
     params->activity = activity;
 
     params->workload = workload;
 
+#if USE_CHECKER
     params->checker = checker;
+#endif
 
     params->max_insts_any_thread = max_insts_any_thread;
     params->max_insts_all_threads = max_insts_all_threads;
@@ -389,6 +178,3 @@ CREATE_SIM_OBJECT(DerivO3CPU)
 
     return cpu;
 }
-
-REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU)
-

src/cpu/o3/sparc/cpu_builder.cc

@@ -30,12 +30,14 @@
 
 #include <string>
 
+#include "config/full_system.hh"
+#include "config/use_checker.hh"
 #include "cpu/base.hh"
 #include "cpu/o3/sparc/cpu.hh"
 #include "cpu/o3/sparc/impl.hh"
 #include "cpu/o3/sparc/params.hh"
 #include "cpu/o3/fu_pool.hh"
-#include "sim/builder.hh"
+#include "params/DerivO3CPU.hh"
 
 class DerivO3CPU : public SparcO3CPU<SparcSimpleImpl>
 {
@@ -45,245 +47,8 @@ class DerivO3CPU : public SparcO3CPU<SparcSimpleImpl>
     { }
 };
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
+DerivO3CPU *
-
+DerivO3CPUParams::create()
-    Param<int> clock;
-    Param<int> phase;
-    Param<int> numThreads;
-    Param<int> cpu_id;
-    Param<int> activity;
-
-#if FULL_SYSTEM
-    SimObjectParam<System *> system;
-    SimObjectParam<SparcISA::ITB *> itb;
-    SimObjectParam<SparcISA::DTB *> dtb;
-    Param<Tick> profile;
-
-    Param<bool> do_quiesce;
-    Param<bool> do_checkpoint_insts;
-    Param<bool> do_statistics_insts;
-#else
-    SimObjectVectorParam<Process *> workload;
-#endif // FULL_SYSTEM
-
-    SimObjectParam<BaseCPU *> checker;
-
-    Param<Counter> max_insts_any_thread;
-    Param<Counter> max_insts_all_threads;
-    Param<Counter> max_loads_any_thread;
-    Param<Counter> max_loads_all_threads;
-    Param<Tick> progress_interval;
-
-    Param<unsigned> cachePorts;
-
-    Param<unsigned> decodeToFetchDelay;
-    Param<unsigned> renameToFetchDelay;
-    Param<unsigned> iewToFetchDelay;
-    Param<unsigned> commitToFetchDelay;
-    Param<unsigned> fetchWidth;
-
-    Param<unsigned> renameToDecodeDelay;
-    Param<unsigned> iewToDecodeDelay;
-    Param<unsigned> commitToDecodeDelay;
-    Param<unsigned> fetchToDecodeDelay;
-    Param<unsigned> decodeWidth;
-
-    Param<unsigned> iewToRenameDelay;
-    Param<unsigned> commitToRenameDelay;
-    Param<unsigned> decodeToRenameDelay;
-    Param<unsigned> renameWidth;
-
-    Param<unsigned> commitToIEWDelay;
-    Param<unsigned> renameToIEWDelay;
-    Param<unsigned> issueToExecuteDelay;
-    Param<unsigned> dispatchWidth;
-    Param<unsigned> issueWidth;
-    Param<unsigned> wbWidth;
-    Param<unsigned> wbDepth;
-    SimObjectParam<FUPool *> fuPool;
-
-    Param<unsigned> iewToCommitDelay;
-    Param<unsigned> renameToROBDelay;
-    Param<unsigned> commitWidth;
-    Param<unsigned> squashWidth;
-    Param<Tick> trapLatency;
-
-    Param<unsigned> backComSize;
-    Param<unsigned> forwardComSize;
-
-    Param<std::string> predType;
-    Param<unsigned> localPredictorSize;
-    Param<unsigned> localCtrBits;
-    Param<unsigned> localHistoryTableSize;
-    Param<unsigned> localHistoryBits;
-    Param<unsigned> globalPredictorSize;
-    Param<unsigned> globalCtrBits;
-    Param<unsigned> globalHistoryBits;
-    Param<unsigned> choicePredictorSize;
-    Param<unsigned> choiceCtrBits;
-
-    Param<unsigned> BTBEntries;
-    Param<unsigned> BTBTagSize;
-
-    Param<unsigned> RASSize;
-
-    Param<unsigned> LQEntries;
-    Param<unsigned> SQEntries;
-    Param<unsigned> LFSTSize;
-    Param<unsigned> SSITSize;
-
-    Param<unsigned> numPhysIntRegs;
-    Param<unsigned> numPhysFloatRegs;
-    Param<unsigned> numIQEntries;
-    Param<unsigned> numROBEntries;
-
-    Param<unsigned> smtNumFetchingThreads;
-    Param<std::string>   smtFetchPolicy;
-    Param<std::string>   smtLSQPolicy;
-    Param<unsigned> smtLSQThreshold;
-    Param<std::string>   smtIQPolicy;
-    Param<unsigned> smtIQThreshold;
-    Param<std::string>   smtROBPolicy;
-    Param<unsigned> smtROBThreshold;
-    Param<std::string>   smtCommitPolicy;
-
-    Param<unsigned> instShiftAmt;
-
-    Param<bool> defer_registration;
-
-    Param<bool> function_trace;
-    Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-    INIT_PARAM(clock, "clock speed"),
-    INIT_PARAM_DFLT(phase, "clock phase", 0),
-    INIT_PARAM(numThreads, "number of HW thread contexts"),
-    INIT_PARAM(cpu_id, "processor ID"),
-    INIT_PARAM_DFLT(activity, "Initial activity count", 0),
-
-#if FULL_SYSTEM
-    INIT_PARAM(system, "System object"),
-    INIT_PARAM(itb, "Instruction translation buffer"),
-    INIT_PARAM(dtb, "Data translation buffer"),
-    INIT_PARAM(profile, ""),
-
-    INIT_PARAM(do_quiesce, ""),
-    INIT_PARAM(do_checkpoint_insts, ""),
-    INIT_PARAM(do_statistics_insts, ""),
-#else
-    INIT_PARAM(workload, "Processes to run"),
-#endif // FULL_SYSTEM
-
-    INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
-
-    INIT_PARAM_DFLT(max_insts_any_thread,
-                    "Terminate when any thread reaches this inst count",
-                    0),
-    INIT_PARAM_DFLT(max_insts_all_threads,
-                    "Terminate when all threads have reached"
-                    "this inst count",
-                    0),
-    INIT_PARAM_DFLT(max_loads_any_thread,
-                    "Terminate when any thread reaches this load count",
-                    0),
-    INIT_PARAM_DFLT(max_loads_all_threads,
-                    "Terminate when all threads have reached this load"
-                    "count",
-                    0),
-    INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
-
-    INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
-
-    INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
-    INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
-    INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
-               "delay"),
-    INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
-    INIT_PARAM(fetchWidth, "Fetch width"),
-    INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
-    INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
-               "delay"),
-    INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
-    INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
-    INIT_PARAM(decodeWidth, "Decode width"),
-
-    INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
-               "delay"),
-    INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
-    INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
-    INIT_PARAM(renameWidth, "Rename width"),
-
-    INIT_PARAM(commitToIEWDelay, "Commit to "
-               "Issue/Execute/Writeback delay"),
-    INIT_PARAM(renameToIEWDelay, "Rename to "
-               "Issue/Execute/Writeback delay"),
-    INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
-               "to the IEW stage)"),
-    INIT_PARAM(dispatchWidth, "Dispatch width"),
-    INIT_PARAM(issueWidth, "Issue width"),
-    INIT_PARAM(wbWidth, "Writeback width"),
-    INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"),
-    INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
-
-    INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
-               "delay"),
-    INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
-    INIT_PARAM(commitWidth, "Commit width"),
-    INIT_PARAM(squashWidth, "Squash width"),
-    INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6),
-
-    INIT_PARAM(backComSize, "Time buffer size for backwards communication"),
-    INIT_PARAM(forwardComSize, "Time buffer size for forward communication"),
-
-    INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
-    INIT_PARAM(localPredictorSize, "Size of local predictor"),
-    INIT_PARAM(localCtrBits, "Bits per counter"),
-    INIT_PARAM(localHistoryTableSize, "Size of local history table"),
-    INIT_PARAM(localHistoryBits, "Bits for the local history"),
-    INIT_PARAM(globalPredictorSize, "Size of global predictor"),
-    INIT_PARAM(globalCtrBits, "Bits per counter"),
-    INIT_PARAM(globalHistoryBits, "Bits of history"),
-    INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
-    INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
-
-    INIT_PARAM(BTBEntries, "Number of BTB entries"),
-    INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
-
-    INIT_PARAM(RASSize, "RAS size"),
-
-    INIT_PARAM(LQEntries, "Number of load queue entries"),
-    INIT_PARAM(SQEntries, "Number of store queue entries"),
-    INIT_PARAM(LFSTSize, "Last fetched store table size"),
-    INIT_PARAM(SSITSize, "Store set ID table size"),
-
-    INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
-    INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
-               "registers"),
-    INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
-    INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
-
-    INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
-    INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
-    INIT_PARAM_DFLT(smtLSQPolicy,   "SMT LSQ Sharing Policy",    "Partitioned"),
-    INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
-    INIT_PARAM_DFLT(smtIQPolicy,    "SMT IQ Policy",    "Partitioned"),
-    INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
-    INIT_PARAM_DFLT(smtROBPolicy,   "SMT ROB Sharing Policy", "Partitioned"),
-    INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
-    INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
-
-    INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
-    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-
-    INIT_PARAM(function_trace, "Enable function trace"),
-    INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-CREATE_SIM_OBJECT(DerivO3CPU)
 {
     DerivO3CPU *cpu;
 
@@ -294,8 +59,7 @@ CREATE_SIM_OBJECT(DerivO3CPU)
     // In non-full-system mode, we infer the number of threads from
     // the workload if it's not explicitly specified.
     int actual_num_threads =
-        (numThreads.isValid() && numThreads >= workload.size()) ?
+        (numThreads >= workload.size()) ? numThreads : workload.size();
-         numThreads : workload.size();
 
     if (workload.size() == 0) {
         fatal("Must specify at least one workload!");
@@ -307,7 +71,7 @@ CREATE_SIM_OBJECT(DerivO3CPU)
     params->clock = clock;
     params->phase = phase;
 
-    params->name = getInstanceName();
+    params->name = name;
     params->numberOfThreads = actual_num_threads;
     params->cpu_id = cpu_id;
     params->activity = activity;
@@ -325,7 +89,9 @@ CREATE_SIM_OBJECT(DerivO3CPU)
     params->workload = workload;
 #endif // FULL_SYSTEM
 
+#if USE_CHECKER
     params->checker = checker;
+#endif
 
     params->max_insts_any_thread = max_insts_any_thread;
     params->max_insts_all_threads = max_insts_all_threads;
@@ -429,6 +195,3 @@ CREATE_SIM_OBJECT(DerivO3CPU)
 
     return cpu;
 }
-
-REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU)
-

src/cpu/op_class.hh

@@ -25,43 +25,35 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Steve Reinhardt
+ * Authors: Nathan Binkert
- *          Nathan Binkert
  */
 
 #ifndef __CPU__OP_CLASS_HH__
 #define __CPU__OP_CLASS_HH__
 
-/**
+#include "enums/OpClass.hh"
- * @file
- * Definition of operation classes.
- */
 
-/**
+/*
- * Instruction operation classes.  These classes are used for
+ * Do a bunch of wonky stuff to maintain backward compatability so I
- * assigning instructions to functional units.
+ * don't have to change code in a zillion places.
  */
-enum OpClass {
+using Enums::OpClass;
-    No_OpClass = 0,	///< Instruction does not use a functional unit
+using Enums::No_OpClass;
-    IntAluOp,		///< Integer ALU operaton (add/sub/logical)
+using Enums::Num_OpClass;
-    IntMultOp,		///< Integer multiply
-    IntDivOp,		///< Integer divide
-    FloatAddOp,		///< Floating point add/subtract
-    FloatCmpOp,		///< Floating point comparison
-    FloatCvtOp,		///< Floating point<->integer conversion
-    FloatMultOp,	///< Floating point multiply
-    FloatDivOp,		///< Floating point divide
-    FloatSqrtOp,	///< Floating point square root
-    MemReadOp,		///< Memory read port
-    MemWriteOp,		///< Memory write port
-    IprAccessOp,	///< Internal Processor Register read/write port
-    InstPrefetchOp,	///< Instruction prefetch port (on I-cache)
-    Num_OpClasses	///< Total number of operation classes
-};
 
-/**
+const OpClass IntAluOp = Enums::IntAlu;
- * Array mapping OpClass enum values to strings.  Defined in op_class.cc.
+const OpClass IntMultOp = Enums::IntMult;
- */
+const OpClass IntDivOp = Enums::IntDiv;
-extern const char *opClassStrings[Num_OpClasses];
+const OpClass FloatAddOp = Enums::FloatAdd;
+const OpClass FloatCmpOp = Enums::FloatCmp;
+const OpClass FloatCvtOp = Enums::FloatCvt;
+const OpClass FloatMultOp = Enums::FloatMult;
+const OpClass FloatDivOp = Enums::FloatDiv;
+const OpClass FloatSqrtOp = Enums::FloatSqrt;
+const OpClass MemReadOp = Enums::MemRead;
+const OpClass MemWriteOp = Enums::MemWrite;
+const OpClass IprAccessOp = Enums::IprAccess;
+const OpClass InstPrefetchOp = Enums::InstPrefetch;
+const OpClass Num_OpClasses = Num_OpClass;
 
 #endif // __CPU__OP_CLASS_HH__

src/cpu/ozone/checker_builder.cc

@@ -34,7 +34,7 @@
 #include "cpu/inst_seq.hh"
 #include "cpu/ozone/dyn_inst.hh"
 #include "cpu/ozone/ozone_impl.hh"
-#include "sim/builder.hh"
+#include "params/OzoneChecker.hh"
 #include "sim/process.hh"
 #include "sim/sim_object.hh"
 
@@ -59,73 +59,11 @@ class OzoneChecker :
 //
 //  CheckerCPU Simulation Object
 //
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker)
+OzoneChecker *
-
+OzoneCheckerParams::create()
-    Param<Counter> max_insts_any_thread;
-    Param<Counter> max_insts_all_threads;
-    Param<Counter> max_loads_any_thread;
-    Param<Counter> max_loads_all_threads;
-    Param<Tick> progress_interval;
-
-#if FULL_SYSTEM
-    SimObjectParam<TheISA::ITB *> itb;
-    SimObjectParam<TheISA::DTB *> dtb;
-    SimObjectParam<System *> system;
-    Param<int> cpu_id;
-    Param<Tick> profile;
-#else
-    SimObjectParam<Process *> workload;
-#endif // FULL_SYSTEM
-    Param<int> clock;
-
-    Param<bool> defer_registration;
-    Param<bool> exitOnError;
-    Param<bool> updateOnError;
-    Param<bool> warnOnlyOnLoadError;
-    Param<bool> function_trace;
-    Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(OzoneChecker)
-
-    INIT_PARAM(max_insts_any_thread,
-               "terminate when any thread reaches this inst count"),
-    INIT_PARAM(max_insts_all_threads,
-               "terminate when all threads have reached this inst count"),
-    INIT_PARAM(max_loads_any_thread,
-               "terminate when any thread reaches this load count"),
-    INIT_PARAM(max_loads_all_threads,
-               "terminate when all threads have reached this load count"),
-    INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0),
-
-#if FULL_SYSTEM
-    INIT_PARAM(itb, "Instruction TLB"),
-    INIT_PARAM(dtb, "Data TLB"),
-    INIT_PARAM(system, "system object"),
-    INIT_PARAM(cpu_id, "processor ID"),
-    INIT_PARAM(profile, ""),
-#else
-    INIT_PARAM(workload, "processes to run"),
-#endif // FULL_SYSTEM
-
-    INIT_PARAM(clock, "clock speed"),
-
-    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-    INIT_PARAM(exitOnError, "exit on error"),
-    INIT_PARAM(updateOnError, "Update the checker with the main CPU's state on error"),
-    INIT_PARAM_DFLT(warnOnlyOnLoadError, "warn, but don't exit, if a load "
-                    "result errors", false),
-    INIT_PARAM(function_trace, "Enable function trace"),
-    INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(OzoneChecker)
-
-
-CREATE_SIM_OBJECT(OzoneChecker)
 {
     OzoneChecker::Params *params = new OzoneChecker::Params();
-    params->name = getInstanceName();
+    params->name = name;
     params->numberOfThreads = 1;
     params->max_insts_any_thread = 0;
     params->max_insts_all_threads = 0;
@@ -162,5 +100,3 @@ CREATE_SIM_OBJECT(OzoneChecker)
     OzoneChecker *cpu = new OzoneChecker(params);
     return cpu;
 }
-
-REGISTER_SIM_OBJECT("OzoneChecker", OzoneChecker)

src/cpu/ozone/cpu_builder.cc

@@ -35,7 +35,7 @@
 #include "cpu/ozone/cpu.hh"
 #include "cpu/ozone/ozone_impl.hh"
 #include "cpu/ozone/simple_params.hh"
-#include "sim/builder.hh"
+#include "params/DerivOzoneCPU.hh"
 #include "sim/process.hh"
 #include "sim/sim_object.hh"
 
@@ -52,271 +52,8 @@ class DerivOzoneCPU : public OzoneCPU<OzoneImpl>
 //
 //  OzoneCPU Simulation Object
 //
-
+DerivOzoneCPU *
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
+DerivOzoneCPUParams::create()
-
-    Param<int> clock;
-    Param<int> numThreads;
-
-#if FULL_SYSTEM
-SimObjectParam<System *> system;
-Param<int> cpu_id;
-SimObjectParam<TheISA::ITB *> itb;
-SimObjectParam<TheISA::DTB *> dtb;
-Param<Tick> profile;
-
-Param<bool> do_quiesce;
-Param<bool> do_checkpoint_insts;
-Param<bool> do_statistics_insts;
-#else
-SimObjectVectorParam<Process *> workload;
-//SimObjectParam<PageTable *> page_table;
-#endif // FULL_SYSTEM
-
-SimObjectParam<BaseCPU *> checker;
-
-Param<Counter> max_insts_any_thread;
-Param<Counter> max_insts_all_threads;
-Param<Counter> max_loads_any_thread;
-Param<Counter> max_loads_all_threads;
-Param<Tick> progress_interval;
-
-//SimObjectParam<BaseCache *> icache;
-//SimObjectParam<BaseCache *> dcache;
-
-Param<unsigned> cachePorts;
-Param<unsigned> width;
-Param<unsigned> frontEndLatency;
-Param<unsigned> frontEndWidth;
-Param<unsigned> backEndLatency;
-Param<unsigned> backEndWidth;
-Param<unsigned> backEndSquashLatency;
-Param<unsigned> maxInstBufferSize;
-Param<unsigned> numPhysicalRegs;
-Param<unsigned> maxOutstandingMemOps;
-
-Param<unsigned> decodeToFetchDelay;
-Param<unsigned> renameToFetchDelay;
-Param<unsigned> iewToFetchDelay;
-Param<unsigned> commitToFetchDelay;
-Param<unsigned> fetchWidth;
-
-Param<unsigned> renameToDecodeDelay;
-Param<unsigned> iewToDecodeDelay;
-Param<unsigned> commitToDecodeDelay;
-Param<unsigned> fetchToDecodeDelay;
-Param<unsigned> decodeWidth;
-
-Param<unsigned> iewToRenameDelay;
-Param<unsigned> commitToRenameDelay;
-Param<unsigned> decodeToRenameDelay;
-Param<unsigned> renameWidth;
-
-Param<unsigned> commitToIEWDelay;
-Param<unsigned> renameToIEWDelay;
-Param<unsigned> issueToExecuteDelay;
-Param<unsigned> issueWidth;
-Param<unsigned> executeWidth;
-Param<unsigned> executeIntWidth;
-Param<unsigned> executeFloatWidth;
-Param<unsigned> executeBranchWidth;
-Param<unsigned> executeMemoryWidth;
-
-Param<unsigned> iewToCommitDelay;
-Param<unsigned> renameToROBDelay;
-Param<unsigned> commitWidth;
-Param<unsigned> squashWidth;
-
-Param<std::string> predType;
-Param<unsigned> localPredictorSize;
-Param<unsigned> localCtrBits;
-Param<unsigned> localHistoryTableSize;
-Param<unsigned> localHistoryBits;
-Param<unsigned> globalPredictorSize;
-Param<unsigned> globalCtrBits;
-Param<unsigned> globalHistoryBits;
-Param<unsigned> choicePredictorSize;
-Param<unsigned> choiceCtrBits;
-
-Param<unsigned> BTBEntries;
-Param<unsigned> BTBTagSize;
-
-Param<unsigned> RASSize;
-
-Param<unsigned> LQEntries;
-Param<unsigned> SQEntries;
-Param<bool> lsqLimits;
-Param<unsigned> LFSTSize;
-Param<unsigned> SSITSize;
-
-Param<unsigned> numPhysIntRegs;
-Param<unsigned> numPhysFloatRegs;
-Param<unsigned> numIQEntries;
-Param<unsigned> numROBEntries;
-
-Param<bool> decoupledFrontEnd;
-Param<int> dispatchWidth;
-Param<int> wbWidth;
-
-Param<unsigned> smtNumFetchingThreads;
-Param<std::string>   smtFetchPolicy;
-Param<std::string>   smtLSQPolicy;
-Param<unsigned> smtLSQThreshold;
-Param<std::string>   smtIQPolicy;
-Param<unsigned> smtIQThreshold;
-Param<std::string>   smtROBPolicy;
-Param<unsigned> smtROBThreshold;
-Param<std::string>   smtCommitPolicy;
-
-Param<unsigned> instShiftAmt;
-
-Param<bool> defer_registration;
-
-Param<bool> function_trace;
-Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
-
-    INIT_PARAM(clock, "clock speed"),
-    INIT_PARAM(numThreads, "number of HW thread contexts"),
-
-#if FULL_SYSTEM
-    INIT_PARAM(system, "System object"),
-    INIT_PARAM(cpu_id, "processor ID"),
-    INIT_PARAM(itb, "Instruction translation buffer"),
-    INIT_PARAM(dtb, "Data translation buffer"),
-    INIT_PARAM(profile, ""),
-    INIT_PARAM(do_quiesce, ""),
-    INIT_PARAM(do_checkpoint_insts, ""),
-    INIT_PARAM(do_statistics_insts, ""),
-#else
-    INIT_PARAM(workload, "Processes to run"),
-//    INIT_PARAM(page_table, "Page table"),
-#endif // FULL_SYSTEM
-
-    INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
-
-    INIT_PARAM_DFLT(max_insts_any_thread,
-                    "Terminate when any thread reaches this inst count",
-                    0),
-    INIT_PARAM_DFLT(max_insts_all_threads,
-                    "Terminate when all threads have reached"
-                    "this inst count",
-                    0),
-    INIT_PARAM_DFLT(max_loads_any_thread,
-                    "Terminate when any thread reaches this load count",
-                    0),
-    INIT_PARAM_DFLT(max_loads_all_threads,
-                    "Terminate when all threads have reached this load"
-                    "count",
-                    0),
-    INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
-
-//    INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
-//    INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
-
-    INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
-    INIT_PARAM_DFLT(width, "Width", 1),
-    INIT_PARAM_DFLT(frontEndLatency, "Front end latency", 1),
-    INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
-    INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
-    INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
-    INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
-    INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
-    INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
-    INIT_PARAM_DFLT(maxOutstandingMemOps, "Maximum outstanding memory operations", 4),
-
-    INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
-    INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
-    INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
-               "delay"),
-    INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
-    INIT_PARAM(fetchWidth, "Fetch width"),
-    INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
-    INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
-               "delay"),
-    INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
-    INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
-    INIT_PARAM(decodeWidth, "Decode width"),
-
-    INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
-               "delay"),
-    INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
-    INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
-    INIT_PARAM(renameWidth, "Rename width"),
-
-    INIT_PARAM(commitToIEWDelay, "Commit to "
-               "Issue/Execute/Writeback delay"),
-    INIT_PARAM(renameToIEWDelay, "Rename to "
-               "Issue/Execute/Writeback delay"),
-    INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
-               "to the IEW stage)"),
-    INIT_PARAM(issueWidth, "Issue width"),
-    INIT_PARAM(executeWidth, "Execute width"),
-    INIT_PARAM(executeIntWidth, "Integer execute width"),
-    INIT_PARAM(executeFloatWidth, "Floating point execute width"),
-    INIT_PARAM(executeBranchWidth, "Branch execute width"),
-    INIT_PARAM(executeMemoryWidth, "Memory execute width"),
-
-    INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
-               "delay"),
-    INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
-    INIT_PARAM(commitWidth, "Commit width"),
-    INIT_PARAM(squashWidth, "Squash width"),
-
-    INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
-    INIT_PARAM(localPredictorSize, "Size of local predictor"),
-    INIT_PARAM(localCtrBits, "Bits per counter"),
-    INIT_PARAM(localHistoryTableSize, "Size of local history table"),
-    INIT_PARAM(localHistoryBits, "Bits for the local history"),
-    INIT_PARAM(globalPredictorSize, "Size of global predictor"),
-    INIT_PARAM(globalCtrBits, "Bits per counter"),
-    INIT_PARAM(globalHistoryBits, "Bits of history"),
-    INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
-    INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
-
-    INIT_PARAM(BTBEntries, "Number of BTB entries"),
-    INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
-
-    INIT_PARAM(RASSize, "RAS size"),
-
-    INIT_PARAM(LQEntries, "Number of load queue entries"),
-    INIT_PARAM(SQEntries, "Number of store queue entries"),
-    INIT_PARAM_DFLT(lsqLimits, "LSQ size limits dispatch", true),
-    INIT_PARAM(LFSTSize, "Last fetched store table size"),
-    INIT_PARAM(SSITSize, "Store set ID table size"),
-
-    INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
-    INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
-               "registers"),
-    INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
-    INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
-
-    INIT_PARAM_DFLT(decoupledFrontEnd, "Decoupled front end", true),
-    INIT_PARAM_DFLT(dispatchWidth, "Dispatch width", 0),
-    INIT_PARAM_DFLT(wbWidth, "Writeback width", 0),
-
-    INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
-    INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
-    INIT_PARAM_DFLT(smtLSQPolicy,   "SMT LSQ Sharing Policy",    "Partitioned"),
-    INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
-    INIT_PARAM_DFLT(smtIQPolicy,    "SMT IQ Policy",    "Partitioned"),
-    INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
-    INIT_PARAM_DFLT(smtROBPolicy,   "SMT ROB Sharing Policy", "Partitioned"),
-    INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
-    INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
-
-    INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
-    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-
-    INIT_PARAM(function_trace, "Enable function trace"),
-    INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
-
-CREATE_SIM_OBJECT(DerivOzoneCPU)
 {
     DerivOzoneCPU *cpu;
 
@@ -339,7 +76,7 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
 
     params->clock = clock;
 
-    params->name = getInstanceName();
+    params->name = name;
     params->numberOfThreads = actual_num_threads;
 
 #if FULL_SYSTEM
@@ -464,5 +201,3 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
 
     return cpu;
 }
-
-REGISTER_SIM_OBJECT("DerivOzoneCPU", DerivOzoneCPU)

src/cpu/ozone/simple_cpu_builder.cc

@@ -36,7 +36,7 @@
 #include "cpu/ozone/simple_impl.hh"
 #include "cpu/ozone/simple_params.hh"
 #include "mem/cache/base_cache.hh"
-#include "sim/builder.hh"
+#include "sim/SimpleOzoneCPU.hh"
 #include "sim/process.hh"
 #include "sim/sim_object.hh"
 
@@ -55,258 +55,8 @@ class SimpleOzoneCPU : public OzoneCPU<SimpleImpl>
 //
 //  OzoneCPU Simulation Object
 //
-
+SimpleOzoneCPU *
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
+SimpleOzoneCPUParams::create()
-
-    Param<int> clock;
-    Param<int> numThreads;
-
-#if FULL_SYSTEM
-SimObjectParam<System *> system;
-Param<int> cpu_id;
-SimObjectParam<TheISA::ITB *> itb;
-SimObjectParam<TheISA::DTB *> dtb;
-#else
-SimObjectVectorParam<Process *> workload;
-//SimObjectParam<PageTable *> page_table;
-#endif // FULL_SYSTEM
-
-SimObjectParam<FunctionalMemory *> mem;
-
-SimObjectParam<BaseCPU *> checker;
-
-Param<Counter> max_insts_any_thread;
-Param<Counter> max_insts_all_threads;
-Param<Counter> max_loads_any_thread;
-Param<Counter> max_loads_all_threads;
-
-SimObjectParam<BaseCache *> icache;
-SimObjectParam<BaseCache *> dcache;
-
-Param<unsigned> cachePorts;
-Param<unsigned> width;
-Param<unsigned> frontEndWidth;
-Param<unsigned> backEndWidth;
-Param<unsigned> backEndSquashLatency;
-Param<unsigned> backEndLatency;
-Param<unsigned> maxInstBufferSize;
-Param<unsigned> numPhysicalRegs;
-
-Param<unsigned> decodeToFetchDelay;
-Param<unsigned> renameToFetchDelay;
-Param<unsigned> iewToFetchDelay;
-Param<unsigned> commitToFetchDelay;
-Param<unsigned> fetchWidth;
-
-Param<unsigned> renameToDecodeDelay;
-Param<unsigned> iewToDecodeDelay;
-Param<unsigned> commitToDecodeDelay;
-Param<unsigned> fetchToDecodeDelay;
-Param<unsigned> decodeWidth;
-
-Param<unsigned> iewToRenameDelay;
-Param<unsigned> commitToRenameDelay;
-Param<unsigned> decodeToRenameDelay;
-Param<unsigned> renameWidth;
-
-Param<unsigned> commitToIEWDelay;
-Param<unsigned> renameToIEWDelay;
-Param<unsigned> issueToExecuteDelay;
-Param<unsigned> issueWidth;
-Param<unsigned> executeWidth;
-Param<unsigned> executeIntWidth;
-Param<unsigned> executeFloatWidth;
-Param<unsigned> executeBranchWidth;
-Param<unsigned> executeMemoryWidth;
-
-Param<unsigned> iewToCommitDelay;
-Param<unsigned> renameToROBDelay;
-Param<unsigned> commitWidth;
-Param<unsigned> squashWidth;
-
-Param<std::string> predType;
-Param<unsigned> localPredictorSize;
-Param<unsigned> localCtrBits;
-Param<unsigned> localHistoryTableSize;
-Param<unsigned> localHistoryBits;
-Param<unsigned> globalPredictorSize;
-Param<unsigned> globalCtrBits;
-Param<unsigned> globalHistoryBits;
-Param<unsigned> choicePredictorSize;
-Param<unsigned> choiceCtrBits;
-
-Param<unsigned> BTBEntries;
-Param<unsigned> BTBTagSize;
-
-Param<unsigned> RASSize;
-
-Param<unsigned> LQEntries;
-Param<unsigned> SQEntries;
-Param<unsigned> LFSTSize;
-Param<unsigned> SSITSize;
-
-Param<unsigned> numPhysIntRegs;
-Param<unsigned> numPhysFloatRegs;
-Param<unsigned> numIQEntries;
-Param<unsigned> numROBEntries;
-
-Param<bool> decoupledFrontEnd;
-Param<int> dispatchWidth;
-Param<int> wbWidth;
-
-Param<unsigned> smtNumFetchingThreads;
-Param<std::string>   smtFetchPolicy;
-Param<std::string>   smtLSQPolicy;
-Param<unsigned> smtLSQThreshold;
-Param<std::string>   smtIQPolicy;
-Param<unsigned> smtIQThreshold;
-Param<std::string>   smtROBPolicy;
-Param<unsigned> smtROBThreshold;
-Param<std::string>   smtCommitPolicy;
-
-Param<unsigned> instShiftAmt;
-
-Param<bool> defer_registration;
-
-Param<bool> function_trace;
-Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
-
-    INIT_PARAM(clock, "clock speed"),
-    INIT_PARAM(numThreads, "number of HW thread contexts"),
-
-#if FULL_SYSTEM
-    INIT_PARAM(system, "System object"),
-    INIT_PARAM(cpu_id, "processor ID"),
-    INIT_PARAM(itb, "Instruction translation buffer"),
-    INIT_PARAM(dtb, "Data translation buffer"),
-#else
-    INIT_PARAM(workload, "Processes to run"),
-//    INIT_PARAM(page_table, "Page table"),
-#endif // FULL_SYSTEM
-
-    INIT_PARAM_DFLT(mem, "Memory", NULL),
-
-    INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
-
-    INIT_PARAM_DFLT(max_insts_any_thread,
-                    "Terminate when any thread reaches this inst count",
-                    0),
-    INIT_PARAM_DFLT(max_insts_all_threads,
-                    "Terminate when all threads have reached"
-                    "this inst count",
-                    0),
-    INIT_PARAM_DFLT(max_loads_any_thread,
-                    "Terminate when any thread reaches this load count",
-                    0),
-    INIT_PARAM_DFLT(max_loads_all_threads,
-                    "Terminate when all threads have reached this load"
-                    "count",
-                    0),
-
-    INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
-    INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
-
-    INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
-    INIT_PARAM_DFLT(width, "Width", 1),
-    INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
-    INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
-    INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
-    INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
-    INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
-    INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
-
-    INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
-    INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
-    INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
-               "delay"),
-    INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
-    INIT_PARAM(fetchWidth, "Fetch width"),
-    INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
-    INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
-               "delay"),
-    INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
-    INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
-    INIT_PARAM(decodeWidth, "Decode width"),
-
-    INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
-               "delay"),
-    INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
-    INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
-    INIT_PARAM(renameWidth, "Rename width"),
-
-    INIT_PARAM(commitToIEWDelay, "Commit to "
-               "Issue/Execute/Writeback delay"),
-    INIT_PARAM(renameToIEWDelay, "Rename to "
-               "Issue/Execute/Writeback delay"),
-    INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
-               "to the IEW stage)"),
-    INIT_PARAM(issueWidth, "Issue width"),
-    INIT_PARAM(executeWidth, "Execute width"),
-    INIT_PARAM(executeIntWidth, "Integer execute width"),
-    INIT_PARAM(executeFloatWidth, "Floating point execute width"),
-    INIT_PARAM(executeBranchWidth, "Branch execute width"),
-    INIT_PARAM(executeMemoryWidth, "Memory execute width"),
-
-    INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
-               "delay"),
-    INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
-    INIT_PARAM(commitWidth, "Commit width"),
-    INIT_PARAM(squashWidth, "Squash width"),
-
-    INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
-    INIT_PARAM(localPredictorSize, "Size of local predictor"),
-    INIT_PARAM(localCtrBits, "Bits per counter"),
-    INIT_PARAM(localHistoryTableSize, "Size of local history table"),
-    INIT_PARAM(localHistoryBits, "Bits for the local history"),
-    INIT_PARAM(globalPredictorSize, "Size of global predictor"),
-    INIT_PARAM(globalCtrBits, "Bits per counter"),
-    INIT_PARAM(globalHistoryBits, "Bits of history"),
-    INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
-    INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
-
-    INIT_PARAM(BTBEntries, "Number of BTB entries"),
-    INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
-
-    INIT_PARAM(RASSize, "RAS size"),
-
-    INIT_PARAM(LQEntries, "Number of load queue entries"),
-    INIT_PARAM(SQEntries, "Number of store queue entries"),
-    INIT_PARAM(LFSTSize, "Last fetched store table size"),
-    INIT_PARAM(SSITSize, "Store set ID table size"),
-
-    INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
-    INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
-               "registers"),
-    INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
-    INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
-
-    INIT_PARAM_DFLT(decoupledFrontEnd, "Decoupled front end", true),
-    INIT_PARAM_DFLT(dispatchWidth, "Dispatch width", 0),
-    INIT_PARAM_DFLT(wbWidth, "Writeback width", 0),
-
-    INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
-    INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
-    INIT_PARAM_DFLT(smtLSQPolicy,   "SMT LSQ Sharing Policy",    "Partitioned"),
-    INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
-    INIT_PARAM_DFLT(smtIQPolicy,    "SMT IQ Policy",    "Partitioned"),
-    INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
-    INIT_PARAM_DFLT(smtROBPolicy,   "SMT ROB Sharing Policy", "Partitioned"),
-    INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
-    INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
-
-    INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
-    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-
-    INIT_PARAM(function_trace, "Enable function trace"),
-    INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
-
-CREATE_SIM_OBJECT(SimpleOzoneCPU)
 {
     SimpleOzoneCPU *cpu;
 
@@ -329,7 +79,7 @@ CREATE_SIM_OBJECT(SimpleOzoneCPU)
 
     params->clock = clock;
 
-    params->name = getInstanceName();
+    params->name = name;
     params->numberOfThreads = actual_num_threads;
 
 #if FULL_SYSTEM
@@ -447,6 +197,3 @@ CREATE_SIM_OBJECT(SimpleOzoneCPU)
 
     return cpu;
 }
-
-REGISTER_SIM_OBJECT("SimpleOzoneCPU", SimpleOzoneCPU)
-

src/cpu/simple/atomic.cc

@@ -36,7 +36,7 @@
 #include "cpu/simple/atomic.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/AtomicSimpleCPU.hh"
 #include "sim/system.hh"
 
 using namespace std;
@@ -198,7 +198,7 @@ void
 AtomicSimpleCPU::resume()
 {
     if (_status != SwitchedOut && _status != Idle) {
-        assert(system->getMemoryMode() == System::Atomic);
+        assert(system->getMemoryMode() == Enums::atomic);
 
         changeState(SimObject::Running);
         if (thread->status() == ThreadContext::Active) {
@@ -570,79 +570,11 @@ AtomicSimpleCPU::tick()
 //
 //  AtomicSimpleCPU Simulation Object
 //
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
+AtomicSimpleCPU *
-
+AtomicSimpleCPUParams::create()
-    Param<Counter> max_insts_any_thread;
-    Param<Counter> max_insts_all_threads;
-    Param<Counter> max_loads_any_thread;
-    Param<Counter> max_loads_all_threads;
-    Param<Tick> progress_interval;
-    SimObjectParam<System *> system;
-    Param<int> cpu_id;
-
-#if FULL_SYSTEM
-    SimObjectParam<TheISA::ITB *> itb;
-    SimObjectParam<TheISA::DTB *> dtb;
-    Param<Tick> profile;
-
-    Param<bool> do_quiesce;
-    Param<bool> do_checkpoint_insts;
-    Param<bool> do_statistics_insts;
-#else
-    SimObjectParam<Process *> workload;
-#endif // FULL_SYSTEM
-
-    Param<int> clock;
-    Param<int> phase;
-
-    Param<bool> defer_registration;
-    Param<int> width;
-    Param<bool> function_trace;
-    Param<Tick> function_trace_start;
-    Param<bool> simulate_stalls;
-
-END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
-
-    INIT_PARAM(max_insts_any_thread,
-               "terminate when any thread reaches this inst count"),
-    INIT_PARAM(max_insts_all_threads,
-               "terminate when all threads have reached this inst count"),
-    INIT_PARAM(max_loads_any_thread,
-               "terminate when any thread reaches this load count"),
-    INIT_PARAM(max_loads_all_threads,
-               "terminate when all threads have reached this load count"),
-    INIT_PARAM(progress_interval, "Progress interval"),
-    INIT_PARAM(system, "system object"),
-    INIT_PARAM(cpu_id, "processor ID"),
-
-#if FULL_SYSTEM
-    INIT_PARAM(itb, "Instruction TLB"),
-    INIT_PARAM(dtb, "Data TLB"),
-    INIT_PARAM(profile, ""),
-    INIT_PARAM(do_quiesce, ""),
-    INIT_PARAM(do_checkpoint_insts, ""),
-    INIT_PARAM(do_statistics_insts, ""),
-#else
-    INIT_PARAM(workload, "processes to run"),
-#endif // FULL_SYSTEM
-
-    INIT_PARAM(clock, "clock speed"),
-    INIT_PARAM_DFLT(phase, "clock phase", 0),
-    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-    INIT_PARAM(width, "cpu width"),
-    INIT_PARAM(function_trace, "Enable function trace"),
-    INIT_PARAM(function_trace_start, "Cycle to start function trace"),
-    INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
-
-END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
-
-
-CREATE_SIM_OBJECT(AtomicSimpleCPU)
 {
     AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
-    params->name = getInstanceName();
+    params->name = name;
     params->numberOfThreads = 1;
     params->max_insts_any_thread = max_insts_any_thread;
     params->max_insts_all_threads = max_insts_all_threads;
@@ -667,12 +599,11 @@ CREATE_SIM_OBJECT(AtomicSimpleCPU)
     params->do_checkpoint_insts = do_checkpoint_insts;
     params->do_statistics_insts = do_statistics_insts;
 #else
-    params->process = workload;
+    if (workload.size() != 1)
+        panic("only one workload allowed");
+    params->process = workload[0];
 #endif
 
     AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
     return cpu;
 }
-
-REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
-

src/cpu/simple/base.cc

@@ -47,7 +47,6 @@
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
 #include "mem/packet.hh"
-#include "sim/builder.hh"
 #include "sim/byteswap.hh"
 #include "sim/debug.hh"
 #include "sim/host.hh"

src/cpu/simple/timing.cc

@@ -35,7 +35,7 @@
 #include "cpu/simple/timing.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/TimingSimpleCPU.hh"
 #include "sim/system.hh"
 
 using namespace std;
@@ -158,7 +158,7 @@ void
 TimingSimpleCPU::resume()
 {
     if (_status != SwitchedOut && _status != Idle) {
-        assert(system->getMemoryMode() == System::Timing);
+        assert(system->getMemoryMode() == Enums::timing);
 
         // Delete the old event if it existed.
         if (fetchEvent) {
@@ -701,79 +701,11 @@ TimingSimpleCPU::DcachePort::recvRetry()
 //
 //  TimingSimpleCPU Simulation Object
 //
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
+TimingSimpleCPU *
-
+TimingSimpleCPUParams::create()
-    Param<Counter> max_insts_any_thread;
-    Param<Counter> max_insts_all_threads;
-    Param<Counter> max_loads_any_thread;
-    Param<Counter> max_loads_all_threads;
-    Param<Tick> progress_interval;
-    SimObjectParam<System *> system;
-    Param<int> cpu_id;
-
-#if FULL_SYSTEM
-    SimObjectParam<TheISA::ITB *> itb;
-    SimObjectParam<TheISA::DTB *> dtb;
-    Param<Tick> profile;
-
-    Param<bool> do_quiesce;
-    Param<bool> do_checkpoint_insts;
-    Param<bool> do_statistics_insts;
-#else
-    SimObjectParam<Process *> workload;
-#endif // FULL_SYSTEM
-
-    Param<int> clock;
-    Param<int> phase;
-
-    Param<bool> defer_registration;
-    Param<int> width;
-    Param<bool> function_trace;
-    Param<Tick> function_trace_start;
-    Param<bool> simulate_stalls;
-
-END_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
-
-    INIT_PARAM(max_insts_any_thread,
-               "terminate when any thread reaches this inst count"),
-    INIT_PARAM(max_insts_all_threads,
-               "terminate when all threads have reached this inst count"),
-    INIT_PARAM(max_loads_any_thread,
-               "terminate when any thread reaches this load count"),
-    INIT_PARAM(max_loads_all_threads,
-               "terminate when all threads have reached this load count"),
-    INIT_PARAM(progress_interval, "Progress interval"),
-    INIT_PARAM(system, "system object"),
-    INIT_PARAM(cpu_id, "processor ID"),
-
-#if FULL_SYSTEM
-    INIT_PARAM(itb, "Instruction TLB"),
-    INIT_PARAM(dtb, "Data TLB"),
-    INIT_PARAM(profile, ""),
-    INIT_PARAM(do_quiesce, ""),
-    INIT_PARAM(do_checkpoint_insts, ""),
-    INIT_PARAM(do_statistics_insts, ""),
-#else
-    INIT_PARAM(workload, "processes to run"),
-#endif // FULL_SYSTEM
-
-    INIT_PARAM(clock, "clock speed"),
-    INIT_PARAM_DFLT(phase, "clock phase", 0),
-    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-    INIT_PARAM(width, "cpu width"),
-    INIT_PARAM(function_trace, "Enable function trace"),
-    INIT_PARAM(function_trace_start, "Cycle to start function trace"),
-    INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
-
-END_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
-
-
-CREATE_SIM_OBJECT(TimingSimpleCPU)
 {
     TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();
-    params->name = getInstanceName();
+    params->name = name;
     params->numberOfThreads = 1;
     params->max_insts_any_thread = max_insts_any_thread;
     params->max_insts_all_threads = max_insts_all_threads;
@@ -796,12 +728,11 @@ CREATE_SIM_OBJECT(TimingSimpleCPU)
     params->do_checkpoint_insts = do_checkpoint_insts;
     params->do_statistics_insts = do_statistics_insts;
 #else
-    params->process = workload;
+    if (workload.size() != 1)
+        panic("only one workload allowed");
+    params->process = workload[0];
 #endif
 
     TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
     return cpu;
 }
-
-REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU)
-

src/cpu/trace/opt_cpu.cc

@@ -38,8 +38,7 @@
 
 #include "cpu/trace/opt_cpu.hh"
 #include "cpu/trace/reader/mem_trace_reader.hh"
-
+#include "params/OptCPU.hh"
-#include "sim/builder.hh"
 #include "sim/sim_events.hh"
 
 using namespace std;
@@ -211,31 +210,8 @@ OptCPU::TickEvent::description()
 }
 
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(OptCPU)
+OptCPU *
-
+OptCPUParams::create()
-    SimObjectParam<MemTraceReader *> data_trace;
-    Param<int> size;
-    Param<int> block_size;
-Param<int> assoc;
-
-END_DECLARE_SIM_OBJECT_PARAMS(OptCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(OptCPU)
-
-    INIT_PARAM_DFLT(data_trace, "memory trace", NULL),
-    INIT_PARAM(size, "cache size"),
-    INIT_PARAM(block_size, "block size"),
-    INIT_PARAM(assoc,"associativity")
-
-END_INIT_SIM_OBJECT_PARAMS(OptCPU)
-
-CREATE_SIM_OBJECT(OptCPU)
 {
-    return new OptCPU(getInstanceName(),
+    return new OptCPU(name, data_trace, block_size, size, assoc);
-                      data_trace,
-                      block_size,
-                      size,
-                      assoc);
 }
-
-REGISTER_SIM_OBJECT("OptCPU", OptCPU)

src/cpu/trace/reader/ibm_reader.cc

@@ -34,9 +34,9 @@
  */
 #include <sstream>
 
-#include "cpu/trace/reader/ibm_reader.hh"
-#include "sim/builder.hh"
 #include "base/misc.hh" // for fatal
+#include "cpu/trace/reader/ibm_reader.hh"
+#include "params/IBMReader.hh"
 
 using namespace std;
 
@@ -100,23 +100,8 @@ IBMReader::getNextReq(MemReqPtr &req)
     return 0;
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IBMReader)
+IBMReader *
-
+IBMReaderParams::create()
-    Param<string> filename;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IBMReader)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IBMReader)
-
-    INIT_PARAM(filename, "trace file")
-
-END_INIT_SIM_OBJECT_PARAMS(IBMReader)
-
-
-CREATE_SIM_OBJECT(IBMReader)
 {
-    return new IBMReader(getInstanceName(), filename);
+    return new IBMReader(name, filename);
 }
-
-REGISTER_SIM_OBJECT("IBMReader", IBMReader)

src/cpu/trace/reader/itx_reader.cc

@@ -34,9 +34,9 @@
  */
 #include <sstream>
 
-#include "cpu/trace/reader/itx_reader.hh"
-#include "sim/builder.hh"
 #include "base/misc.hh" // for fatal
+#include "cpu/trace/reader/itx_reader.hh"
+#include "params/ITXReader.hh"
 
 using namespace std;
 
@@ -186,23 +186,8 @@ ITXReader::getNextReq(MemReqPtr &req)
     return 0;
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITXReader)
+ITXReader *
-
+ITXReaderParams::create()
-    Param<string> filename;
-
-END_DECLARE_SIM_OBJECT_PARAMS(ITXReader)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(ITXReader)
-
-    INIT_PARAM(filename, "trace file")
-
-END_INIT_SIM_OBJECT_PARAMS(ITXReader)
-
-
-CREATE_SIM_OBJECT(ITXReader)
 {
-    return new ITXReader(getInstanceName(), filename);
+    return new ITXReader(name, filename);
 }
-
-REGISTER_SIM_OBJECT("ITXReader", ITXReader)

src/cpu/trace/reader/m5_reader.cc

@@ -36,7 +36,7 @@
 #include "cpu/trace/reader/m5_reader.hh"
 #include "mem/trace/m5_format.hh"
 #include "mem/mem_cmd.hh"
-#include "sim/builder.hh"
+#include "params/M5Reader.hh"
 
 using namespace std;
 
@@ -77,23 +77,8 @@ M5Reader::getNextReq(MemReqPtr &req)
     return ref.cycle;
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(M5Reader)
+M5Reader *
-
+M5ReaderParams::create()
-    Param<string> filename;
-
-END_DECLARE_SIM_OBJECT_PARAMS(M5Reader)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(M5Reader)
-
-    INIT_PARAM(filename, "trace file")
-
-END_INIT_SIM_OBJECT_PARAMS(M5Reader)
-
-
-CREATE_SIM_OBJECT(M5Reader)
 {
-    return new M5Reader(getInstanceName(), filename);
+    return new M5Reader(name, filename);
 }
-
-REGISTER_SIM_OBJECT("M5Reader", M5Reader)

src/cpu/trace/trace_cpu.cc

@@ -40,7 +40,7 @@
 #include "cpu/trace/reader/mem_trace_reader.hh"
 #include "mem/base_mem.hh" // For PARAM constructor
 #include "mem/mem_interface.hh"
-#include "sim/builder.hh"
+#include "params/TraceCPU.hh"
 #include "sim/sim_events.hh"
 
 using namespace std;
@@ -151,31 +151,11 @@ TraceCPU::TickEvent::description()
     return "TraceCPU tick event";
 }
 
-
+TraceCPU *
-
+TraceCPUParams::create()
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
-
-    SimObjectParam<BaseMem *> icache;
-    SimObjectParam<BaseMem *> dcache;
-    SimObjectParam<MemTraceReader *> data_trace;
-
-END_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(TraceCPU)
-
-    INIT_PARAM_DFLT(icache, "instruction cache", NULL),
-    INIT_PARAM_DFLT(dcache, "data cache", NULL),
-    INIT_PARAM_DFLT(data_trace, "data trace", NULL)
-
-END_INIT_SIM_OBJECT_PARAMS(TraceCPU)
-
-CREATE_SIM_OBJECT(TraceCPU)
 {
-    return new TraceCPU(getInstanceName(),
+    return new TraceCPU(name,
                         (icache) ? icache->getInterface() : NULL,
                         (dcache) ? dcache->getInterface() : NULL,
                         data_trace);
 }
-
-REGISTER_SIM_OBJECT("TraceCPU", TraceCPU)
-

src/dev/Ethernet.py

@@ -180,6 +180,8 @@ class SinicPciData(PciConfigData):
 
 class Sinic(EtherDevBase):
     type = 'Sinic'
+    cxx_namespace = 'Sinic'
+    cxx_class = 'Device'
 
     rx_max_copy = Param.MemorySize('1514B', "rx max copy")
     tx_max_copy = Param.MemorySize('16kB', "tx max copy")
@@ -197,4 +199,7 @@ class Sinic(EtherDevBase):
 
 class SinicInt(EtherInt):
     type = 'SinicInt'
+    cxx_namespace = 'Sinic'
+    cxx_class = 'Interface'
+
     device = Param.Sinic("Ethernet device of this interface")

src/dev/SConscript

@@ -50,7 +50,7 @@ if env['FULL_SYSTEM']:
     Source('etherint.cc')
     Source('etherlink.cc')
     Source('etherpkt.cc')
-    Source('ethertap.cc')	
+    Source('ethertap.cc')
     Source('i8254xGBe.cc')
     Source('ide_ctrl.cc')
     Source('ide_disk.cc')
@@ -63,6 +63,6 @@ if env['FULL_SYSTEM']:
     Source('platform.cc')
     Source('simconsole.cc')
     Source('simple_disk.cc')
-    #Source('sinic.cc')
+    Source('sinic.cc')
     Source('uart.cc')
     Source('uart8250.cc')

src/dev/alpha/console.cc

@@ -51,15 +51,15 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "mem/physical.hh"
-#include "sim/builder.hh"
+#include "params/AlphaConsole.hh"
 #include "sim/sim_object.hh"
 
 using namespace std;
 using namespace AlphaISA;
 
-AlphaConsole::AlphaConsole(Params *p)
+AlphaConsole::AlphaConsole(const Params *p)
-    : BasicPioDevice(p), disk(p->disk),
+    : BasicPioDevice(p), disk(p->disk), console(p->sim_console),
-      console(params()->cons), system(params()->alpha_sys), cpu(params()->cpu)
+      system(p->system), cpu(p->cpu)
 {
 
     pioSize = sizeof(struct AlphaAccess);
@@ -306,43 +306,8 @@ AlphaConsole::unserialize(Checkpoint *cp, const std::string &section)
     alphaAccess->unserialize(cp, section);
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
+AlphaConsole *
-
+AlphaConsoleParams::create()
-    SimObjectParam<SimConsole *> sim_console;
-    SimObjectParam<SimpleDisk *> disk;
-    Param<Addr> pio_addr;
-    SimObjectParam<AlphaSystem *> system;
-    SimObjectParam<BaseCPU *> cpu;
-    SimObjectParam<Platform *> platform;
-    Param<Tick> pio_latency;
-
-END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
-
-    INIT_PARAM(sim_console, "The Simulator Console"),
-    INIT_PARAM(disk, "Simple Disk"),
-    INIT_PARAM(pio_addr, "Device Address"),
-    INIT_PARAM(system, "system object"),
-    INIT_PARAM(cpu, "Processor"),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000)
-
-END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
-
-CREATE_SIM_OBJECT(AlphaConsole)
 {
-    AlphaConsole::Params *p = new AlphaConsole::Params;
+    return new AlphaConsole(this);
-    p->name = getInstanceName();
-    p->platform = platform;
-    p->pio_addr = pio_addr;
-    p->pio_delay = pio_latency;
-    p->cons = sim_console;
-    p->disk = disk;
-    p->alpha_sys = system;
-    p->system = system;
-    p->cpu = cpu;
-    return new AlphaConsole(p);
 }
-
-REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)

src/dev/alpha/console.hh

@@ -38,6 +38,7 @@
 #include "base/range.hh"
 #include "dev/alpha/access.h"
 #include "dev/io_device.hh"
+#include "params/AlphaConsole.hh"
 #include "sim/host.hh"
 #include "sim/sim_object.hh"
 
@@ -98,20 +99,14 @@ class AlphaConsole : public BasicPioDevice
     BaseCPU *cpu;
 
   public:
-    struct Params : public BasicPioDevice::Params
+    typedef AlphaConsoleParams Params;
+    AlphaConsole(const Params *p);
+
+    const Params *
+    params() const
     {
-        SimConsole *cons;
+        return dynamic_cast<const Params *>(_params);
-        SimpleDisk *disk;
+    }
-        AlphaSystem *alpha_sys;
-        BaseCPU *cpu;
-    };
-  protected:
-    const Params *params() const {return (const Params *)_params; }
-
-  public:
-
-    /** Standard Constructor */
-    AlphaConsole(Params *p);
 
     virtual void startup();
 

src/dev/alpha/tsunami.cc

@@ -42,7 +42,7 @@
 #include "dev/alpha/tsunami_pchip.hh"
 #include "dev/alpha/tsunami_io.hh"
 #include "dev/alpha/tsunami.hh"
-#include "sim/builder.hh"
+#include "params/Tsunami.hh"
 #include "sim/system.hh"
 
 using namespace std;
@@ -114,23 +114,8 @@ Tsunami::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
+Tsunami *
-
+TsunamiParams::create()
-    SimObjectParam<System *> system;
-    SimObjectParam<IntrControl *> intrctrl;
-
-END_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Tsunami)
-
-    INIT_PARAM(system, "system"),
-    INIT_PARAM(intrctrl, "interrupt controller")
-
-END_INIT_SIM_OBJECT_PARAMS(Tsunami)
-
-CREATE_SIM_OBJECT(Tsunami)
 {
-    return new Tsunami(getInstanceName(), system, intrctrl);
+    return new Tsunami(name, system, intrctrl);
 }
-
-REGISTER_SIM_OBJECT("Tsunami", Tsunami)

src/dev/alpha/tsunami_cchip.cc

@@ -47,14 +47,14 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "mem/port.hh"
-#include "sim/builder.hh"
+#include "params/TsunamiCChip.hh"
 #include "sim/system.hh"
 
 using namespace std;
 //Should this be AlphaISA?
 using namespace TheISA;
 
-TsunamiCChip::TsunamiCChip(Params *p)
+TsunamiCChip::TsunamiCChip(const Params *p)
     : BasicPioDevice(p), tsunami(p->tsunami)
 {
     pioSize = 0x10000000;
@@ -522,36 +522,8 @@ TsunamiCChip::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_SCALAR(drir);
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
+TsunamiCChip *
-
+TsunamiCChipParams::create()
-    Param<Addr> pio_addr;
-    Param<Tick> pio_latency;
-    SimObjectParam<Platform *> platform;
-    SimObjectParam<System *> system;
-    SimObjectParam<Tsunami *> tsunami;
-
-END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
-
-    INIT_PARAM(pio_addr, "Device Address"),
-    INIT_PARAM(pio_latency, "Programmed IO latency"),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM(system, "system object"),
-    INIT_PARAM(tsunami, "Tsunami")
-
-END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
-
-CREATE_SIM_OBJECT(TsunamiCChip)
 {
-    TsunamiCChip::Params *p = new TsunamiCChip::Params;
+    return new TsunamiCChip(this);
-    p->name = getInstanceName();
-    p->pio_addr = pio_addr;
-    p->pio_delay = pio_latency;
-    p->platform = platform;
-    p->system = system;
-    p->tsunami = tsunami;
-    return new TsunamiCChip(p);
 }
-
-REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)

src/dev/alpha/tsunami_cchip.hh

@@ -35,10 +35,10 @@
 #ifndef __TSUNAMI_CCHIP_HH__
 #define __TSUNAMI_CCHIP_HH__
 
-#include "dev/alpha/tsunami.hh"
 #include "base/range.hh"
+#include "dev/alpha/tsunami.hh"
 #include "dev/io_device.hh"
-
+#include "params/TsunamiCChip.hh"
 
 /**
  * Tsunami CChip CSR Emulation. This device includes all the interrupt
@@ -79,20 +79,19 @@ class TsunamiCChip : public BasicPioDevice
     uint64_t itint;
 
   public:
-    struct Params : public BasicPioDevice::Params
+    typedef TsunamiCChipParams Params;
-    {
-        Tsunami *tsunami;
-    };
-  protected:
-    const Params *params() const {return (const Params *)_params; }
-
-  public:
     /**
      * Initialize the Tsunami CChip by setting all of the
      * device register to 0.
      * @param p params struct
      */
-    TsunamiCChip(Params *p);
+    TsunamiCChip(const Params *p);
+
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
 
     virtual Tick read(PacketPtr pkt);
 

src/dev/alpha/tsunami_io.cc

@@ -40,6 +40,7 @@
 #include <string>
 #include <vector>
 
+#include "base/time.hh"
 #include "base/trace.hh"
 #include "dev/pitreg.h"
 #include "dev/rtcreg.h"
@@ -50,27 +51,23 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "mem/port.hh"
-#include "sim/builder.hh"
 #include "sim/system.hh"
 
 using namespace std;
 //Should this be AlphaISA?
 using namespace TheISA;
 
-TsunamiIO::RTC::RTC(const string &n, Tsunami* tsunami, const vector<int> &t,
+TsunamiIO::RTC::RTC(const string &n, Tsunami* tsunami,
-                    bool bcd, Tick i)
+                    const TsunamiIO::Params *p)
-    : _name(n), event(tsunami, i), addr(0), year_is_bcd(bcd)
+    : _name(n), event(tsunami, p->frequency), addr(0)
 {
     memset(clock_data, 0, sizeof(clock_data));
     stat_regA = RTCA_32768HZ | RTCA_1024HZ;
     stat_regB = RTCB_PRDC_IE |RTCB_BIN | RTCB_24HR;
 
-    struct tm tm;
+    year = p->time.tm_year;
-    parseTime(t, &tm);
 
-    year = tm.tm_year;
+    if (p->year_is_bcd) {
-
-    if (year_is_bcd) {
         // The datasheet says that the year field can be either BCD or
         // years since 1900.  Linux seems to be happy with years since
         // 1900.
@@ -81,16 +78,16 @@ TsunamiIO::RTC::RTC(const string &n, Tsunami* tsunami, const vector<int> &t,
     }
 
     // Unix is 0-11 for month, data seet says start at 1
-    mon = tm.tm_mon + 1;
+    mon = p->time.tm_mon + 1;
-    mday = tm.tm_mday;
+    mday = p->time.tm_mday;
-    hour = tm.tm_hour;
+    hour = p->time.tm_hour;
-    min = tm.tm_min;
+    min = p->time.tm_min;
-    sec = tm.tm_sec;
+    sec = p->time.tm_sec;
 
     // Datasheet says 1 is sunday
-    wday = tm.tm_wday + 1;
+    wday = p->time.tm_wday + 1;
 
-    DPRINTFN("Real-time clock set to %s", asctime(&tm));
+    DPRINTFN("Real-time clock set to %s", asctime(&p->time));
 }
 
 void
@@ -437,10 +434,9 @@ TsunamiIO::PITimer::Counter::CounterEvent::description()
     return "tsunami 8254 Interval timer";
 }
 
-TsunamiIO::TsunamiIO(Params *p)
+TsunamiIO::TsunamiIO(const Params *p)
     : BasicPioDevice(p), tsunami(p->tsunami), pitimer(p->name + "pitimer"),
-      rtc(p->name + ".rtc", p->tsunami, p->init_time, p->year_is_bcd,
+      rtc(p->name + ".rtc", p->tsunami, p)
-          p->frequency)
 {
     pioSize = 0x100;
 
@@ -658,45 +654,8 @@ TsunamiIO::unserialize(Checkpoint *cp, const string &section)
     rtc.unserialize("rtc", cp, section);
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
+TsunamiIO *
-
+TsunamiIOParams::create()
-    Param<Addr> pio_addr;
-    Param<Tick> pio_latency;
-    Param<Tick> frequency;
-    SimObjectParam<Platform *> platform;
-    SimObjectParam<System *> system;
-    VectorParam<int> time;
-    Param<bool> year_is_bcd;
-    SimObjectParam<Tsunami *> tsunami;
-
-END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
-
-    INIT_PARAM(pio_addr, "Device Address"),
-    INIT_PARAM(pio_latency, "Programmed IO latency"),
-    INIT_PARAM(frequency, "clock interrupt frequency"),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM(system, "system object"),
-    INIT_PARAM(time, "System time to use (0 for actual time"),
-    INIT_PARAM(year_is_bcd, ""),
-    INIT_PARAM(tsunami, "Tsunami")
-
-END_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
-
-CREATE_SIM_OBJECT(TsunamiIO)
 {
-    TsunamiIO::Params *p = new TsunamiIO::Params;
+    return new TsunamiIO(this);
-    p->frequency = frequency;
-    p->name = getInstanceName();
-    p->pio_addr = pio_addr;
-    p->pio_delay = pio_latency;
-    p->platform = platform;
-    p->system = system;
-    p->init_time = time;
-    p->year_is_bcd = year_is_bcd;
-    p->tsunami = tsunami;
-    return new TsunamiIO(p);
 }
-
-REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO)

src/dev/alpha/tsunami_io.hh

@@ -37,9 +37,10 @@
 #ifndef __DEV_TSUNAMI_IO_HH__
 #define __DEV_TSUNAMI_IO_HH__
 
-#include "dev/io_device.hh"
 #include "base/range.hh"
 #include "dev/alpha/tsunami.hh"
+#include "dev/io_device.hh"
+#include "params/TsunamiIO.hh"
 #include "sim/eventq.hh"
 
 /**
@@ -85,9 +86,6 @@ class TsunamiIO : public BasicPioDevice
         /** Current RTC register address/index */
         int addr;
 
-        /** should the year be interpreted as BCD? */
-        bool year_is_bcd;
-
         /** Data for real-time clock function */
         union {
             uint8_t clock_data[10];
@@ -114,7 +112,7 @@ class TsunamiIO : public BasicPioDevice
 
       public:
         RTC(const std::string &name, Tsunami* tsunami,
-            const std::vector<int> &t, bool bcd, Tick i);
+            const TsunamiIOParams *params);
 
         /** RTC address port: write address of RTC RAM data to access */
         void writeAddr(const uint8_t data);
@@ -313,23 +311,19 @@ class TsunamiIO : public BasicPioDevice
      */
     Tick frequency() const;
 
-    struct Params : public BasicPioDevice::Params
-    {
-        Tick frequency;
-        Tsunami *tsunami;
-        std::vector<int> init_time;
-        bool year_is_bcd;
-    };
-
-  protected:
-    const Params *params() const { return (const Params*)_params; }
-
   public:
+    typedef TsunamiIOParams Params;
     /**
      * Initialize all the data for devices supported by Tsunami I/O.
      * @param p pointer to Params struct
      */
-    TsunamiIO(Params *p);
+    TsunamiIO(const Params *p);
+
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
 
     virtual Tick read(PacketPtr pkt);
     virtual Tick write(PacketPtr pkt);

src/dev/alpha/tsunami_pchip.cc

@@ -43,14 +43,13 @@
 #include "dev/alpha/tsunami.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
 #include "sim/system.hh"
 
 using namespace std;
 //Should this be AlphaISA?
 using namespace TheISA;
 
-TsunamiPChip::TsunamiPChip(Params *p)
+TsunamiPChip::TsunamiPChip(const Params *p)
 : BasicPioDevice(p)
 {
     pioSize = 0x1000;
@@ -334,36 +333,8 @@ TsunamiPChip::unserialize(Checkpoint *cp, const std::string &section)
 }
 
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
+TsunamiPChip *
-
+TsunamiPChipParams::create()
-    Param<Addr> pio_addr;
-    Param<Tick> pio_latency;
-    SimObjectParam<Platform *> platform;
-    SimObjectParam<System *> system;
-    SimObjectParam<Tsunami *> tsunami;
-
-END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
-
-    INIT_PARAM(pio_addr, "Device Address"),
-    INIT_PARAM(pio_latency, "Programmed IO latency"),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM(system, "system object"),
-    INIT_PARAM(tsunami, "Tsunami")
-
-END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
-
-CREATE_SIM_OBJECT(TsunamiPChip)
 {
-    TsunamiPChip::Params *p = new TsunamiPChip::Params;
+    return new TsunamiPChip(this);
-    p->name = getInstanceName();
-    p->pio_addr = pio_addr;
-    p->pio_delay = pio_latency;
-    p->platform = platform;
-    p->system = system;
-    p->tsunami = tsunami;
-    return new TsunamiPChip(p);
 }
-
-REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)

src/dev/alpha/tsunami_pchip.hh

@@ -35,9 +35,10 @@
 #ifndef __TSUNAMI_PCHIP_HH__
 #define __TSUNAMI_PCHIP_HH__
 
-#include "dev/alpha/tsunami.hh"
 #include "base/range.hh"
+#include "dev/alpha/tsunami.hh"
 #include "dev/io_device.hh"
+#include "params/TsunamiPChip.hh"
 
 /**
  * A very simple implementation of the Tsunami PCI interface chips.
@@ -61,19 +62,18 @@ class TsunamiPChip : public BasicPioDevice
     uint64_t tba[4];
 
   public:
-    struct Params : public BasicPioDevice::Params
+    typedef TsunamiPChipParams Params;
-    {
-        Tsunami *tsunami;
-    };
-  protected:
-    const Params *params() const { return (const Params*)_params; }
-
-  public:
     /**
      * Register the PChip with the mmu and init all wsba, wsm, and tba to 0
      * @param p pointer to the parameters struct
      */
-    TsunamiPChip(Params *p);
+    TsunamiPChip(const Params *p);
+
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
 
     /**
      * Translate a PCI bus address to a memory address for DMA.

src/dev/baddev.cc

@@ -40,14 +40,14 @@
 #include "dev/baddev.hh"
 #include "dev/platform.hh"
 #include "mem/port.hh"
-#include "sim/builder.hh"
+#include "params/BadDevice.hh"
 #include "sim/system.hh"
 
 using namespace std;
 using namespace TheISA;
 
 BadDevice::BadDevice(Params *p)
-    : BasicPioDevice(p), devname(p->device_name)
+    : BasicPioDevice(p), devname(p->devicename)
 {
     pioSize = 0x10;
 }
@@ -66,36 +66,8 @@ BadDevice::write(PacketPtr pkt)
     M5_DUMMY_RETURN
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
+BadDevice *
-
+BadDeviceParams::create()
-    Param<string> devicename;
-    Param<Addr> pio_addr;
-    SimObjectParam<System *> system;
-    SimObjectParam<Platform *> platform;
-    Param<Tick> pio_latency;
-
-END_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(BadDevice)
-
-    INIT_PARAM(devicename, "Name of device to error on"),
-    INIT_PARAM(pio_addr, "Device Address"),
-    INIT_PARAM(system, "system object"),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000)
-
-END_INIT_SIM_OBJECT_PARAMS(BadDevice)
-
-CREATE_SIM_OBJECT(BadDevice)
 {
-    BadDevice::Params *p = new BadDevice::Params;
+    return new BadDevice(this);
-    p->name =getInstanceName();
-    p->platform = platform;
-    p->pio_addr = pio_addr;
-    p->pio_delay = pio_latency;
-    p->system = system;
-    p->device_name = devicename;
-    return new BadDevice(p);
 }
-
-REGISTER_SIM_OBJECT("BadDevice", BadDevice)

src/dev/baddev.hh

@@ -38,7 +38,7 @@
 
 #include "base/range.hh"
 #include "dev/io_device.hh"
-
+#include "params/BadDevice.hh"
 
 /**
  * BadDevice
@@ -52,12 +52,14 @@ class BadDevice : public BasicPioDevice
     std::string devname;
 
   public:
-    struct Params : public BasicPioDevice::Params
+    typedef BadDeviceParams Params;
-    {
+
-        std::string device_name;
-    };
   protected:
-    const Params *params() const { return (const Params *)_params; }
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
 
   public:
      /**

src/dev/disk_image.cc

@@ -45,7 +45,8 @@
 #include "base/misc.hh"
 #include "base/trace.hh"
 #include "dev/disk_image.hh"
-#include "sim/builder.hh"
+#include "params/CowDiskImage.hh"
+#include "params/RawDiskImage.hh"
 #include "sim/sim_exit.hh"
 #include "sim/byteswap.hh"
 
@@ -143,30 +144,12 @@ RawDiskImage::write(const uint8_t *data, off_t offset)
     return stream.tellp() - pos;
 }
 
-DEFINE_SIM_OBJECT_CLASS_NAME("DiskImage", DiskImage)
+RawDiskImage *
-
+RawDiskImageParams::create()
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(RawDiskImage)
-
-    Param<string> image_file;
-    Param<bool> read_only;
-
-END_DECLARE_SIM_OBJECT_PARAMS(RawDiskImage)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(RawDiskImage)
-
-    INIT_PARAM(image_file, "disk image file"),
-    INIT_PARAM_DFLT(read_only, "read only image", false)
-
-END_INIT_SIM_OBJECT_PARAMS(RawDiskImage)
-
-
-CREATE_SIM_OBJECT(RawDiskImage)
 {
-    return new RawDiskImage(getInstanceName(), image_file, read_only);
+    return new RawDiskImage(name, image_file, read_only);
 }
 
-REGISTER_SIM_OBJECT("RawDiskImage", RawDiskImage)
-
 ////////////////////////////////////////////////////////////////////////
 //
 // Copy on Write Disk image
@@ -440,33 +423,12 @@ CowDiskImage::unserialize(Checkpoint *cp, const string &section)
     open(cowFilename);
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(CowDiskImage)
+CowDiskImage *
-
+CowDiskImageParams::create()
-    SimObjectParam<DiskImage *> child;
-    Param<string> image_file;
-    Param<int> table_size;
-    Param<bool> read_only;
-
-END_DECLARE_SIM_OBJECT_PARAMS(CowDiskImage)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(CowDiskImage)
-
-    INIT_PARAM(child, "child image"),
-    INIT_PARAM_DFLT(image_file, "disk image file", ""),
-    INIT_PARAM_DFLT(table_size, "initial table size", 65536),
-    INIT_PARAM_DFLT(read_only, "don't write back to the copy-on-write file",
-                    true)
-
-END_INIT_SIM_OBJECT_PARAMS(CowDiskImage)
-
-
-CREATE_SIM_OBJECT(CowDiskImage)
 {
     if (((string)image_file).empty())
-        return new CowDiskImage(getInstanceName(), child, table_size);
+        return new CowDiskImage(name, child, table_size);
     else
-        return new CowDiskImage(getInstanceName(), child, table_size,
+        return new CowDiskImage(name, child, table_size,
                                 image_file, read_only);
 }
-
-REGISTER_SIM_OBJECT("CowDiskImage", CowDiskImage)

src/dev/etherbus.cc

@@ -42,7 +42,7 @@
 #include "dev/etherdump.hh"
 #include "dev/etherint.hh"
 #include "dev/etherpkt.hh"
-#include "sim/builder.hh"
+#include "params/EtherBus.hh"
 #include "sim/core.hh"
 
 using namespace std;
@@ -103,25 +103,8 @@ EtherBus::send(EtherInt *sndr, EthPacketPtr &pkt)
     return true;
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherBus)
+EtherBus *
-
+EtherBusParams::create()
-    Param<bool> loopback;
-    Param<double> speed;
-    SimObjectParam<EtherDump *> packet_dump;
-
-END_DECLARE_SIM_OBJECT_PARAMS(EtherBus)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(EtherBus)
-
-    INIT_PARAM(loopback, "send the packet back to the sending interface"),
-    INIT_PARAM(speed, "bus speed in ticks per byte"),
-    INIT_PARAM(packet_dump, "object to dump network packets to")
-
-END_INIT_SIM_OBJECT_PARAMS(EtherBus)
-
-CREATE_SIM_OBJECT(EtherBus)
 {
-    return new EtherBus(getInstanceName(), speed, loopback, packet_dump);
+    return new EtherBus(name, speed, loopback, dump);
 }
-
-REGISTER_SIM_OBJECT("EtherBus", EtherBus)

src/dev/etherdump.cc

@@ -40,7 +40,7 @@
 #include "base/misc.hh"
 #include "base/output.hh"
 #include "dev/etherdump.hh"
-#include "sim/builder.hh"
+#include "params/EtherDump.hh"
 #include "sim/core.hh"
 
 using std::string;
@@ -116,23 +116,8 @@ EtherDump::dumpPacket(EthPacketPtr &packet)
     stream.flush();
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherDump)
+EtherDump *
-
+EtherDumpParams::create()
-    Param<string> file;
-    Param<int> maxlen;
-
-END_DECLARE_SIM_OBJECT_PARAMS(EtherDump)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(EtherDump)
-
-    INIT_PARAM(file, "file to dump packets to"),
-    INIT_PARAM(maxlen, "max portion of packet data to dump")
-
-END_INIT_SIM_OBJECT_PARAMS(EtherDump)
-
-CREATE_SIM_OBJECT(EtherDump)
 {
-    return new EtherDump(getInstanceName(), simout.resolve(file), maxlen);
+    return new EtherDump(name, simout.resolve(file), maxlen);
 }
-
-REGISTER_SIM_OBJECT("EtherDump", EtherDump)

src/dev/etherint.cc

@@ -30,7 +30,6 @@
 
 #include "dev/etherint.hh"
 #include "base/misc.hh"
-#include "sim/param.hh"
 #include "sim/sim_object.hh"
 
 void
@@ -42,6 +41,3 @@ EtherInt::setPeer(EtherInt *p)
 
     peer = p;
 }
-
-DEFINE_SIM_OBJECT_CLASS_NAME("EtherInt", EtherInt)
-

src/dev/etherlink.cc

@@ -44,7 +44,7 @@
 #include "dev/etherint.hh"
 #include "dev/etherlink.hh"
 #include "dev/etherpkt.hh"
-#include "sim/builder.hh"
+#include "params/EtherLink.hh"
 #include "sim/serialize.hh"
 #include "sim/system.hh"
 #include "sim/core.hh"
@@ -272,32 +272,8 @@ LinkDelayEvent::createForUnserialize(Checkpoint *cp, const string &section)
 
 REGISTER_SERIALIZEABLE("LinkDelayEvent", LinkDelayEvent)
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherLink)
+EtherLink *
-
+EtherLinkParams::create()
-    SimObjectParam<EtherInt *> int1;
-    SimObjectParam<EtherInt *> int2;
-    Param<double> speed;
-    Param<Tick> delay;
-    Param<Tick> delay_var;
-    SimObjectParam<EtherDump *> dump;
-
-END_DECLARE_SIM_OBJECT_PARAMS(EtherLink)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(EtherLink)
-
-    INIT_PARAM(int1, "interface 1"),
-    INIT_PARAM(int2, "interface 2"),
-    INIT_PARAM(speed, "link speed in bits per second"),
-    INIT_PARAM(delay, "transmit delay of packets in us"),
-    INIT_PARAM(delay_var, "Difference in amount of time to traverse wire"),
-    INIT_PARAM(dump, "object to dump network packets to")
-
-END_INIT_SIM_OBJECT_PARAMS(EtherLink)
-
-CREATE_SIM_OBJECT(EtherLink)
 {
-    return new EtherLink(getInstanceName(), int1, int2, speed, delay, delay_var,
+    return new EtherLink(name, int1, int2, speed, delay, delay_var, dump);
-                         dump);
 }
-
-REGISTER_SIM_OBJECT("EtherLink", EtherLink)

src/dev/ethertap.cc

@@ -50,7 +50,7 @@
 #include "dev/etherint.hh"
 #include "dev/etherpkt.hh"
 #include "dev/ethertap.hh"
-#include "sim/builder.hh"
+#include "params/EtherTap.hh"
 
 using namespace std;
 
@@ -313,28 +313,10 @@ EtherTap::unserialize(Checkpoint *cp, const std::string &section)
 
 //=====================================================================
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherTap)
+EtherTap *
-
+EtherTapParams::create()
-    SimObjectParam<EtherInt *> peer;
-    SimObjectParam<EtherDump *> dump;
-    Param<unsigned> port;
-    Param<unsigned> bufsz;
-
-END_DECLARE_SIM_OBJECT_PARAMS(EtherTap)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(EtherTap)
-
-    INIT_PARAM_DFLT(peer, "peer interface", NULL),
-    INIT_PARAM_DFLT(dump, "object to dump network packets to", NULL),
-    INIT_PARAM_DFLT(port, "tap port", 3500),
-    INIT_PARAM_DFLT(bufsz, "tap buffer size", 10000)
-
-END_INIT_SIM_OBJECT_PARAMS(EtherTap)
-
-
-CREATE_SIM_OBJECT(EtherTap)
 {
-    EtherTap *tap = new EtherTap(getInstanceName(), dump, port, bufsz);
+    EtherTap *tap = new EtherTap(name, dump, port, bufsz);
 
     if (peer) {
         tap->setPeer(peer);
@@ -343,5 +325,3 @@ CREATE_SIM_OBJECT(EtherTap)
 
     return tap;
 }
-
-REGISTER_SIM_OBJECT("EtherTap", EtherTap)

src/dev/i8254xGBe.cc

@@ -40,17 +40,18 @@
  * @todo really there are multiple dma engines.. we should implement them.
  */
 
+#include <algorithm>
+
 #include "base/inet.hh"
 #include "base/trace.hh"
 #include "dev/i8254xGBe.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/IGbE.hh"
+#include "params/IGbEInt.hh"
 #include "sim/stats.hh"
 #include "sim/system.hh"
 
-#include <algorithm>
-
 using namespace iGbReg;
 using namespace Net;
 
@@ -1446,24 +1447,10 @@ IGbE::unserialize(Checkpoint *cp, const std::string &section)
     rxDescCache.unserialize(cp, csprintf("%s.RxDescCache", section));
 }
 
-
+IGbEInt *
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbEInt)
+IGbEIntParams::create()
-
-    SimObjectParam<EtherInt *> peer;
-    SimObjectParam<IGbE *> device;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IGbEInt)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IGbEInt)
-
-    INIT_PARAM_DFLT(peer, "peer interface", NULL),
-    INIT_PARAM(device, "Ethernet device of this interface")
-
-END_INIT_SIM_OBJECT_PARAMS(IGbEInt)
-
-CREATE_SIM_OBJECT(IGbEInt)
 {
-    IGbEInt *dev_int = new IGbEInt(getInstanceName(), device);
+    IGbEInt *dev_int = new IGbEInt(name, device);
 
     EtherInt *p = (EtherInt *)peer;
     if (p) {
@@ -1474,80 +1461,8 @@ CREATE_SIM_OBJECT(IGbEInt)
     return dev_int;
 }
 
-REGISTER_SIM_OBJECT("IGbEInt", IGbEInt)
+IGbE *
-
+IGbEParams::create()
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbE)
-
-    SimObjectParam<System *> system;
-    SimObjectParam<Platform *> platform;
-    Param<Tick> min_backoff_delay;
-    Param<Tick> max_backoff_delay;
-    SimObjectParam<PciConfigData *> configdata;
-    Param<uint32_t> pci_bus;
-    Param<uint32_t> pci_dev;
-    Param<uint32_t> pci_func;
-    Param<Tick> pio_latency;
-    Param<Tick> config_latency;
-    Param<std::string> hardware_address;
-    Param<bool> use_flow_control;
-    Param<int> rx_fifo_size;
-    Param<int> tx_fifo_size;
-    Param<int> rx_desc_cache_size;
-    Param<int> tx_desc_cache_size;
-    Param<Tick> clock;
-
-
-END_DECLARE_SIM_OBJECT_PARAMS(IGbE)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IGbE)
-
-    INIT_PARAM(system, "System pointer"),
-    INIT_PARAM(platform, "Platform pointer"),
-    INIT_PARAM(min_backoff_delay, "Minimum delay after receving a nack packed"),
-    INIT_PARAM(max_backoff_delay, "Maximum delay after receving a nack packed"),
-    INIT_PARAM(configdata, "PCI Config data"),
-    INIT_PARAM(pci_bus, "PCI bus ID"),
-    INIT_PARAM(pci_dev, "PCI device number"),
-    INIT_PARAM(pci_func, "PCI function code"),
-    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
-    INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
-    INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
-    INIT_PARAM(use_flow_control,"Should the device use xon/off packets"),
-    INIT_PARAM(rx_fifo_size,"Size of the RX FIFO"),
-    INIT_PARAM(tx_fifo_size,"Size of the TX FIFO"),
-    INIT_PARAM(rx_desc_cache_size,"Size of the RX descriptor cache"),
-    INIT_PARAM(tx_desc_cache_size,"Size of the TX descriptor cache"),
-    INIT_PARAM(clock,"Clock rate for the device to tick at")
-
-END_INIT_SIM_OBJECT_PARAMS(IGbE)
-
-
-CREATE_SIM_OBJECT(IGbE)
 {
-    IGbE::Params *params = new IGbE::Params;
+    return new IGbE(this);
-
-    params->name = getInstanceName();
-    params->platform = platform;
-    params->system = system;
-    params->min_backoff_delay = min_backoff_delay;
-    params->max_backoff_delay = max_backoff_delay;
-    params->configData = configdata;
-    params->busNum = pci_bus;
-    params->deviceNum = pci_dev;
-    params->functionNum = pci_func;
-    params->pio_delay = pio_latency;
-    params->config_delay = config_latency;
-    params->hardware_address = hardware_address;
-    params->use_flow_control = use_flow_control;
-    params->rx_fifo_size = rx_fifo_size;
-    params->tx_fifo_size = tx_fifo_size;
-    params->rx_desc_cache_size = rx_desc_cache_size;
-    params->tx_desc_cache_size = tx_desc_cache_size;
-    params->clock = clock;
-
-
-    return new IGbE(params);
 }
-
-REGISTER_SIM_OBJECT("IGbE", IGbE)

src/dev/i8254xGBe.hh

@@ -45,6 +45,7 @@
 #include "dev/i8254xGBe_defs.hh"
 #include "dev/pcidev.hh"
 #include "dev/pktfifo.hh"
+#include "params/IGbE.hh"
 #include "sim/eventq.hh"
 
 class IGbEInt;
@@ -585,19 +586,14 @@ class IGbE : public PciDev
     TxDescCache txDescCache;
 
   public:
-    struct Params : public PciDev::Params
+    typedef IGbEParams Params;
+    const Params *
+    params() const
     {
-        Net::EthAddr hardware_address;
+        return dynamic_cast<const Params *>(_params);
-        bool use_flow_control;
+    }
-        int rx_fifo_size;
-        int tx_fifo_size;
-        int rx_desc_cache_size;
-        int tx_desc_cache_size;
-        Tick clock;
-    };
-
     IGbE(Params *params);
-    ~IGbE() {;}
+    ~IGbE() {}
 
     Tick clock;
     inline Tick cycles(int numCycles) const { return numCycles * clock; }
@@ -612,9 +608,6 @@ class IGbE : public PciDev
 
     void setEthInt(IGbEInt *i) { assert(!etherInt); etherInt = i; }
 
-
-    const Params *params() const {return (const Params *)_params; }
-
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
     virtual unsigned int drain(Event *de);

src/dev/ide_ctrl.cc

@@ -44,7 +44,7 @@
 #include "dev/platform.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/IdeController.hh"
 #include "sim/sim_object.hh"
 #include "sim/byteswap.hh"
 
@@ -745,58 +745,8 @@ IdeController::unserialize(Checkpoint *cp, const std::string &section)
                       sizeof(cmd_in_progress) / sizeof(cmd_in_progress[0]));
 }
 
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
+IdeController *
-
+IdeControllerParams::create()
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController)
-
-    SimObjectParam<System *> system;
-    SimObjectParam<Platform *> platform;
-    Param<Tick> min_backoff_delay;
-    Param<Tick> max_backoff_delay;
-    SimObjectParam<PciConfigData *> configdata;
-    Param<uint32_t> pci_bus;
-    Param<uint32_t> pci_dev;
-    Param<uint32_t> pci_func;
-    Param<Tick> pio_latency;
-    Param<Tick> config_latency;
-    SimObjectVectorParam<IdeDisk *> disks;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController)
-
-    INIT_PARAM(system, "System pointer"),
-    INIT_PARAM(platform, "Platform pointer"),
-    INIT_PARAM(min_backoff_delay, "Minimum delay after receving a nack packed"),
-    INIT_PARAM(max_backoff_delay, "Maximum delay after receving a nack packed"),
-    INIT_PARAM(configdata, "PCI Config data"),
-    INIT_PARAM(pci_bus, "PCI bus ID"),
-    INIT_PARAM(pci_dev, "PCI device number"),
-    INIT_PARAM(pci_func, "PCI function code"),
-    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
-    INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
-    INIT_PARAM(disks, "IDE disks attached to this controller")
-
-END_INIT_SIM_OBJECT_PARAMS(IdeController)
-
-CREATE_SIM_OBJECT(IdeController)
 {
-    IdeController::Params *params = new IdeController::Params;
+    return new IdeController(this);
-    params->name = getInstanceName();
-    params->platform = platform;
-    params->system = system;
-    params->min_backoff_delay = min_backoff_delay;
-    params->max_backoff_delay = max_backoff_delay;
-    params->configData = configdata;
-    params->busNum = pci_bus;
-    params->deviceNum = pci_dev;
-    params->functionNum = pci_func;
-    params->pio_delay = pio_latency;
-    params->config_delay = config_latency;
-    params->disks = disks;
-    return new IdeController(params);
 }
-
-REGISTER_SIM_OBJECT("IdeController", IdeController)
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS

src/dev/ide_ctrl.hh

@@ -40,6 +40,7 @@
 #include "dev/pcidev.hh"
 #include "dev/pcireg.h"
 #include "dev/io_device.hh"
+#include "params/IdeController.hh"
 
 #define BMIC0    0x0  // Bus master IDE command register
 #define BMIS0    0x2  // Bus master IDE status register
@@ -193,14 +194,8 @@ class IdeController : public PciDev
     bool isDiskSelected(IdeDisk *diskPtr);
 
   public:
-    struct Params : public PciDev::Params
+    typedef IdeControllerParams Params;
-    {
-        /** Array of disk objects */
-        std::vector<IdeDisk *> disks;
-    };
     const Params *params() const { return (const Params *)_params; }
-
-  public:
     IdeController(Params *p);
     ~IdeController();
 

src/dev/ide_disk.cc

@@ -38,18 +38,16 @@
 #include <deque>
 #include <string>
 
+#include "arch/isa_traits.hh"
 #include "base/chunk_generator.hh"
 #include "base/cprintf.hh" // csprintf
 #include "base/trace.hh"
 #include "dev/disk_image.hh"
-#include "dev/ide_disk.hh"
 #include "dev/ide_ctrl.hh"
-#include "dev/alpha/tsunami.hh"
+#include "dev/ide_disk.hh"
-#include "dev/alpha/tsunami_pchip.hh"
+#include "params/IdeDisk.hh"
-#include "sim/builder.hh"
-#include "sim/sim_object.hh"
 #include "sim/core.hh"
-#include "arch/isa_traits.hh"
+#include "sim/sim_object.hh"
 
 using namespace std;
 using namespace TheISA;
@@ -1116,32 +1114,8 @@ IdeDisk::unserialize(Checkpoint *cp, const string &section)
     UNSERIALIZE_ARRAY(dataBuffer, MAX_DMA_SIZE);
 }
 
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
+IdeDisk *
-
+IdeDiskParams::create()
-enum DriveID { master, slave };
-static const char *DriveID_strings[] = { "master", "slave" };
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeDisk)
-
-    SimObjectParam<DiskImage *> image;
-    SimpleEnumParam<DriveID> driveID;
-    Param<int> delay;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IdeDisk)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IdeDisk)
-
-    INIT_PARAM(image, "Disk image"),
-    INIT_ENUM_PARAM(driveID, "Drive ID (0=master 1=slave)", DriveID_strings),
-    INIT_PARAM_DFLT(delay, "Fixed disk delay in microseconds", 1)
-
-END_INIT_SIM_OBJECT_PARAMS(IdeDisk)
-
-
-CREATE_SIM_OBJECT(IdeDisk)
 {
-    return new IdeDisk(getInstanceName(), image, driveID, delay);
+    return new IdeDisk(name, image, driveID, delay);
 }
-
-REGISTER_SIM_OBJECT("IdeDisk", IdeDisk)
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS

src/dev/io_device.cc

@@ -32,7 +32,6 @@
 #include "base/chunk_generator.hh"
 #include "base/trace.hh"
 #include "dev/io_device.hh"
-#include "sim/builder.hh"
 #include "sim/system.hh"
 
 
@@ -55,6 +54,10 @@ PioPort::getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
 }
 
 
+PioDevice::PioDevice(const Params *p)
+    : MemObject(p), platform(p->platform), sys(p->system), pioPort(NULL)
+{}
+
 PioDevice::~PioDevice()
 {
     if (pioPort)
@@ -82,6 +85,11 @@ PioDevice::drain(Event *de)
     return count;
 }
 
+BasicPioDevice::BasicPioDevice(const Params *p)
+    : PioDevice(p), pioAddr(p->pio_addr), pioSize(0),
+      pioDelay(p->pio_latency)
+{}
+
 void
 BasicPioDevice::addressRanges(AddrRangeList &range_list)
 {
@@ -149,7 +157,7 @@ DmaPort::recvTiming(PacketPtr pkt)
     return true;
 }
 
-DmaDevice::DmaDevice(Params *p)
+DmaDevice::DmaDevice(const Params *p)
     : PioDevice(p), dmaPort(NULL), minBackoffDelay(p->min_backoff_delay),
       maxBackoffDelay(p->max_backoff_delay)
 { }
@@ -262,8 +270,8 @@ DmaPort::sendDma()
     assert(transmitList.size());
     PacketPtr pkt = transmitList.front();
 
-    System::MemoryMode state = sys->getMemoryMode();
+    Enums::MemoryMode state = sys->getMemoryMode();
-    if (state == System::Timing) {
+    if (state == Enums::timing) {
         if (backoffEvent.scheduled() || inRetry) {
             DPRINTF(DMA, "Can't send immediately, waiting for retry or backoff timer\n");
             return;
@@ -290,7 +298,7 @@ DmaPort::sendDma()
                     backoffTime+curTick);
             backoffEvent.schedule(backoffTime+curTick);
         }
-    } else if (state == System::Atomic) {
+    } else if (state == Enums::atomic) {
         transmitList.pop_front();
 
         Tick lat;
@@ -330,5 +338,3 @@ DmaDevice::~DmaDevice()
     if (dmaPort)
         delete dmaPort;
 }
-
-

src/dev/io_device.hh

@@ -35,6 +35,9 @@
 #include "mem/mem_object.hh"
 #include "mem/packet.hh"
 #include "mem/tport.hh"
+#include "params/BasicPioDevice.hh"
+#include "params/DmaDevice.hh"
+#include "params/PioDevice.hh"
 #include "sim/sim_object.hh"
 
 class Event;
@@ -186,29 +189,16 @@ class PioDevice : public MemObject
     virtual Tick write(PacketPtr pkt) = 0;
 
   public:
-    /** Params struct which is extended through each device based on
+    typedef PioDeviceParams Params;
-     * the parameters it needs. Since we are re-writing everything, we
+    PioDevice(const Params *p);
-     * might as well start from the bottom this time. */
-    struct Params
-    {
-        std::string name;
-        Platform *platform;
-        System *system;
-    };
-
-  protected:
-    Params *_params;
-
-  public:
-    const Params *params() const { return _params; }
-
-    PioDevice(Params *p)
-              : MemObject(p->name),  platform(p->platform), sys(p->system),
-              pioPort(NULL), _params(p)
-              {}
-
     virtual ~PioDevice();
 
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+
     virtual void init();
 
     virtual unsigned int drain(Event *de);
@@ -229,13 +219,6 @@ class PioDevice : public MemObject
 
 class BasicPioDevice : public PioDevice
 {
-  public:
-    struct Params :  public PioDevice::Params
-    {
-        Addr pio_addr;
-        Tick pio_delay;
-    };
-
   protected:
     /** Address that the device listens to. */
     Addr pioAddr;
@@ -247,10 +230,14 @@ class BasicPioDevice : public PioDevice
     Tick pioDelay;
 
   public:
-    BasicPioDevice(Params *p)
+    typedef BasicPioDeviceParams Params;
-        : PioDevice(p), pioAddr(p->pio_addr), pioSize(0),
+    BasicPioDevice(const Params *p);
-          pioDelay(p->pio_delay)
+
-    {}
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
 
     /** return the address ranges that this device responds to.
      * @param range_list range list to populate with ranges
@@ -261,22 +248,22 @@ class BasicPioDevice : public PioDevice
 
 class DmaDevice : public PioDevice
 {
-  public:
-    struct Params :  public PioDevice::Params
-    {
-        Tick min_backoff_delay;
-        Tick max_backoff_delay;
-    };
-
    protected:
     DmaPort *dmaPort;
     Tick minBackoffDelay;
     Tick maxBackoffDelay;
 
   public:
-    DmaDevice(Params *p);
+    typedef DmaDeviceParams Params;
+    DmaDevice(const Params *p);
     virtual ~DmaDevice();
 
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+
     void dmaWrite(Addr addr, int size, Event *event, uint8_t *data)
     {
         dmaPort->dmaAction(MemCmd::WriteInvalidateReq,

src/dev/isa_fake.cc

@@ -36,7 +36,6 @@
 #include "dev/isa_fake.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
 #include "sim/system.hh"
 
 using namespace std;
@@ -44,13 +43,13 @@ using namespace std;
 IsaFake::IsaFake(Params *p)
     : BasicPioDevice(p)
 {
-    if (!params()->retBadAddr)
+    if (!p->ret_bad_addr)
         pioSize = p->pio_size;
 
-    retData8 = params()->retData8;
+    retData8 = p->ret_data8;
-    retData16 = params()->retData16;
+    retData16 = p->ret_data16;
-    retData32 = params()->retData32;
+    retData32 = p->ret_data32;
-    retData64 = params()->retData64;
+    retData64 = p->ret_data64;
 }
 
 Tick
@@ -58,10 +57,10 @@ IsaFake::read(PacketPtr pkt)
 {
     assert(pkt->result == Packet::Unknown);
 
-    if (params()->warnAccess != "")
+    if (params()->warn_access != "")
         warn("Device %s accessed by read to address %#x size=%d\n",
                 name(), pkt->getAddr(), pkt->getSize());
-    if (params()->retBadAddr) {
+    if (params()->ret_bad_addr) {
         DPRINTF(Tsunami, "read to bad address va=%#x size=%d\n",
                 pkt->getAddr(), pkt->getSize());
         pkt->result = Packet::BadAddress;
@@ -93,7 +92,7 @@ IsaFake::read(PacketPtr pkt)
 Tick
 IsaFake::write(PacketPtr pkt)
 {
-    if (params()->warnAccess != "") {
+    if (params()->warn_access != "") {
         uint64_t data;
         switch (pkt->getSize()) {
           case sizeof(uint64_t):
@@ -114,7 +113,7 @@ IsaFake::write(PacketPtr pkt)
         warn("Device %s accessed by write to address %#x size=%d data=%#x\n",
                 name(), pkt->getAddr(), pkt->getSize(), data);
     }
-    if (params()->retBadAddr) {
+    if (params()->ret_bad_addr) {
         DPRINTF(Tsunami, "write to bad address va=%#x size=%d \n",
                 pkt->getAddr(), pkt->getSize());
         pkt->result = Packet::BadAddress;
@@ -122,7 +121,7 @@ IsaFake::write(PacketPtr pkt)
         DPRINTF(Tsunami, "write - va=%#x size=%d \n",
                 pkt->getAddr(), pkt->getSize());
 
-        if (params()->updateData) {
+        if (params()->update_data) {
             switch (pkt->getSize()) {
               case sizeof(uint64_t):
                 retData64 = pkt->get<uint64_t>();
@@ -145,57 +144,8 @@ IsaFake::write(PacketPtr pkt)
     return pioDelay;
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
+IsaFake *
-
+IsaFakeParams::create()
-    Param<Addr> pio_addr;
-    Param<Tick> pio_latency;
-    Param<Addr> pio_size;
-    Param<bool> ret_bad_addr;
-    Param<bool> update_data;
-    Param<std::string> warn_access;
-    Param<uint8_t> ret_data8;
-    Param<uint16_t> ret_data16;
-    Param<uint32_t> ret_data32;
-    Param<uint64_t> ret_data64;
-    SimObjectParam<Platform *> platform;
-    SimObjectParam<System *> system;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IsaFake)
-
-    INIT_PARAM(pio_addr, "Device Address"),
-    INIT_PARAM(pio_latency, "Programmed IO latency"),
-    INIT_PARAM(pio_size, "Size of address range"),
-    INIT_PARAM(ret_bad_addr, "Return pkt status BadAddr"),
-    INIT_PARAM(update_data, "Update returned data"),
-    INIT_PARAM(warn_access, "Warn if this device is touched"),
-    INIT_PARAM(ret_data8, "Data to return if not bad addr"),
-    INIT_PARAM(ret_data16, "Data to return if not bad addr"),
-    INIT_PARAM(ret_data32, "Data to return if not bad addr"),
-    INIT_PARAM(ret_data64, "Data to return if not bad addr"),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM(system, "system object")
-
-END_INIT_SIM_OBJECT_PARAMS(IsaFake)
-
-CREATE_SIM_OBJECT(IsaFake)
 {
-    IsaFake::Params *p = new IsaFake::Params;
+    return new IsaFake(this);
-    p->name = getInstanceName();
-    p->pio_addr = pio_addr;
-    p->pio_delay = pio_latency;
-    p->pio_size = pio_size;
-    p->retBadAddr = ret_bad_addr;
-    p->updateData = update_data;
-    p->warnAccess = warn_access;
-    p->retData8= ret_data8;
-    p->retData16 = ret_data16;
-    p->retData32 = ret_data32;
-    p->retData64 = ret_data64;
-    p->platform = platform;
-    p->system = system;
-    return new IsaFake(p);
 }
-
-REGISTER_SIM_OBJECT("IsaFake", IsaFake)

src/dev/isa_fake.hh

@@ -35,13 +35,14 @@
 #ifndef __ISA_FAKE_HH__
 #define __ISA_FAKE_HH__
 
+#include <string>
+
 #include "base/range.hh"
 #include "dev/io_device.hh"
 #include "dev/alpha/tsunami.hh"
+#include "params/IsaFake.hh"
 #include "mem/packet.hh"
 
-#include <string>
-
 /**
  * IsaFake is a device that returns, BadAddr, 1 or 0 on all reads and
  *  rites. It is meant to be placed at an address range
@@ -51,27 +52,19 @@
  */
 class IsaFake : public BasicPioDevice
 {
-  public:
-    struct Params : public BasicPioDevice::Params
-    {
-        Addr pio_size;
-        bool retBadAddr;
-        bool updateData;
-        uint8_t retData8;
-        uint16_t retData16;
-        uint32_t retData32;
-        uint64_t retData64;
-        std::string warnAccess;
-    };
   protected:
-    const Params *params() const { return (const Params*)_params; }
     uint8_t retData8;
     uint16_t retData16;
     uint32_t retData32;
     uint64_t retData64;
 
-
   public:
+    typedef IsaFakeParams Params;
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
     /**
       * The constructor for Tsunmami Fake just registers itself with the MMU.
       * @param p params structure

src/dev/ns_gige.cc

@@ -43,7 +43,8 @@
 #include "dev/pciconfigall.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/NSGigE.hh"
+#include "params/NSGigEInt.hh"
 #include "sim/debug.hh"
 #include "sim/host.hh"
 #include "sim/stats.hh"
@@ -118,7 +119,7 @@ NSGigE::NSGigE(Params *p)
 
 
     regsReset();
-    memcpy(&rom.perfectMatch, p->eaddr.bytes(), ETH_ADDR_LEN);
+    memcpy(&rom.perfectMatch, p->hardware_address.bytes(), ETH_ADDR_LEN);
 
     memset(&rxDesc32, 0, sizeof(rxDesc32));
     memset(&txDesc32, 0, sizeof(txDesc32));
@@ -2773,23 +2774,10 @@ NSGigE::unserialize(Checkpoint *cp, const std::string &section)
     }
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigEInt)
+NSGigEInt *
-
+NSGigEIntParams::create()
-    SimObjectParam<EtherInt *> peer;
-    SimObjectParam<NSGigE *> device;
-
-END_DECLARE_SIM_OBJECT_PARAMS(NSGigEInt)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigEInt)
-
-    INIT_PARAM_DFLT(peer, "peer interface", NULL),
-    INIT_PARAM(device, "Ethernet device of this interface")
-
-END_INIT_SIM_OBJECT_PARAMS(NSGigEInt)
-
-CREATE_SIM_OBJECT(NSGigEInt)
 {
-    NSGigEInt *dev_int = new NSGigEInt(getInstanceName(), device);
+    NSGigEInt *dev_int = new NSGigEInt(name, device);
 
     EtherInt *p = (EtherInt *)peer;
     if (p) {
@@ -2800,121 +2788,8 @@ CREATE_SIM_OBJECT(NSGigEInt)
     return dev_int;
 }
 
-REGISTER_SIM_OBJECT("NSGigEInt", NSGigEInt)
+NSGigE *
-
+NSGigEParams::create()
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
-
-    SimObjectParam<System *> system;
-    SimObjectParam<Platform *> platform;
-    Param<Tick> min_backoff_delay;
-    Param<Tick> max_backoff_delay;
-    SimObjectParam<PciConfigData *> configdata;
-    Param<uint32_t> pci_bus;
-    Param<uint32_t> pci_dev;
-    Param<uint32_t> pci_func;
-    Param<Tick> pio_latency;
-    Param<Tick> config_latency;
-
-    Param<Tick> clock;
-    Param<bool> dma_desc_free;
-    Param<bool> dma_data_free;
-    Param<Tick> dma_read_delay;
-    Param<Tick> dma_write_delay;
-    Param<Tick> dma_read_factor;
-    Param<Tick> dma_write_factor;
-    Param<bool> dma_no_allocate;
-    Param<Tick> intr_delay;
-
-    Param<Tick> rx_delay;
-    Param<Tick> tx_delay;
-    Param<uint32_t> rx_fifo_size;
-    Param<uint32_t> tx_fifo_size;
-
-    Param<bool> rx_filter;
-    Param<string> hardware_address;
-    Param<bool> rx_thread;
-    Param<bool> tx_thread;
-    Param<bool> rss;
-
-END_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
-
-    INIT_PARAM(system, "System pointer"),
-    INIT_PARAM(platform, "Platform pointer"),
-    INIT_PARAM(min_backoff_delay, "Minimum delay after receving a nack packed"),
-    INIT_PARAM(max_backoff_delay, "Maximum delay after receving a nack packed"),
-    INIT_PARAM(configdata, "PCI Config data"),
-    INIT_PARAM(pci_bus, "PCI bus ID"),
-    INIT_PARAM(pci_dev, "PCI device number"),
-    INIT_PARAM(pci_func, "PCI function code"),
-    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
-    INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
-    INIT_PARAM(clock, "State machine cycle time"),
-
-    INIT_PARAM(dma_desc_free, "DMA of Descriptors is free"),
-    INIT_PARAM(dma_data_free, "DMA of Data is free"),
-    INIT_PARAM(dma_read_delay, "fixed delay for dma reads"),
-    INIT_PARAM(dma_write_delay, "fixed delay for dma writes"),
-    INIT_PARAM(dma_read_factor, "multiplier for dma reads"),
-    INIT_PARAM(dma_write_factor, "multiplier for dma writes"),
-    INIT_PARAM(dma_no_allocate, "Should DMA reads allocate cache lines"),
-    INIT_PARAM(intr_delay, "Interrupt Delay in microseconds"),
-
-    INIT_PARAM(rx_delay, "Receive Delay"),
-    INIT_PARAM(tx_delay, "Transmit Delay"),
-    INIT_PARAM(rx_fifo_size, "max size in bytes of rxFifo"),
-    INIT_PARAM(tx_fifo_size, "max size in bytes of txFifo"),
-
-    INIT_PARAM(rx_filter, "Enable Receive Filter"),
-    INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
-    INIT_PARAM(rx_thread, ""),
-    INIT_PARAM(tx_thread, ""),
-    INIT_PARAM(rss, "")
-
-END_INIT_SIM_OBJECT_PARAMS(NSGigE)
-
-
-CREATE_SIM_OBJECT(NSGigE)
 {
-    NSGigE::Params *params = new NSGigE::Params;
+    return new NSGigE(this);
-
-    params->name = getInstanceName();
-    params->platform = platform;
-    params->system = system;
-    params->min_backoff_delay = min_backoff_delay;
-    params->max_backoff_delay = max_backoff_delay;
-    params->configData = configdata;
-    params->busNum = pci_bus;
-    params->deviceNum = pci_dev;
-    params->functionNum = pci_func;
-    params->pio_delay = pio_latency;
-    params->config_delay = config_latency;
-
-    params->clock = clock;
-    params->dma_desc_free = dma_desc_free;
-    params->dma_data_free = dma_data_free;
-    params->dma_read_delay = dma_read_delay;
-    params->dma_write_delay = dma_write_delay;
-    params->dma_read_factor = dma_read_factor;
-    params->dma_write_factor = dma_write_factor;
-    params->dma_no_allocate = dma_no_allocate;
-    params->pio_delay = pio_latency;
-    params->intr_delay = intr_delay;
-
-    params->rx_delay = rx_delay;
-    params->tx_delay = tx_delay;
-    params->rx_fifo_size = rx_fifo_size;
-    params->tx_fifo_size = tx_fifo_size;
-
-    params->rx_filter = rx_filter;
-    params->eaddr = hardware_address;
-    params->rx_thread = rx_thread;
-    params->tx_thread = tx_thread;
-    params->rss = rss;
-
-    return new NSGigE(params);
 }
-
-REGISTER_SIM_OBJECT("NSGigE", NSGigE)

src/dev/ns_gige.hh

@@ -45,6 +45,7 @@
 #include "dev/ns_gige_reg.h"
 #include "dev/pcidev.hh"
 #include "dev/pktfifo.hh"
+#include "params/NSGigE.hh"
 #include "sim/eventq.hh"
 
 // Hash filtering constants
@@ -349,31 +350,10 @@ class NSGigE : public PciDev
     NSGigEInt *interface;
 
   public:
-    struct Params : public PciDev::Params
+    typedef NSGigEParams Params;
-    {
+    const Params *params() const { return (const Params *)_params; }
-        Tick clock;
-        Tick intr_delay;
-        Tick tx_delay;
-        Tick rx_delay;
-        bool dma_desc_free;
-        bool dma_data_free;
-        Tick dma_read_delay;
-        Tick dma_write_delay;
-        Tick dma_read_factor;
-        Tick dma_write_factor;
-        bool rx_filter;
-        Net::EthAddr eaddr;
-        uint32_t tx_fifo_size;
-        uint32_t rx_fifo_size;
-        bool rx_thread;
-        bool tx_thread;
-        bool rss;
-        bool dma_no_allocate;
-    };
-
     NSGigE(Params *params);
     ~NSGigE();
-    const Params *params() const { return (const Params *)_params; }
 
     virtual Tick writeConfig(PacketPtr pkt);
 

src/dev/pciconfigall.cc

@@ -39,7 +39,7 @@
 #include "dev/platform.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/PciConfigAll.hh"
 #include "sim/system.hh"
 
 using namespace std;
@@ -97,27 +97,8 @@ PciConfigAll::addressRanges(AddrRangeList &range_list)
 
 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
+PciConfigAll *
-
+PciConfigAllParams::create()
-    Param<Tick> pio_latency;
-    Param<int> bus;
-    Param<Addr> size;
-    SimObjectParam<Platform *> platform;
-    SimObjectParam<System *> system;
-
-END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
-
-    INIT_PARAM(pio_latency, "Programmed IO latency"),
-    INIT_PARAM(bus, "Bus that this object handles config space for"),
-    INIT_PARAM(size, "The size of config space"),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM(system, "system object")
-
-END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
-
-CREATE_SIM_OBJECT(PciConfigAll)
 {
     PciConfigAll::Params *p = new PciConfigAll::Params;
     p->pio_delay = pio_latency;
@@ -129,6 +110,4 @@ CREATE_SIM_OBJECT(PciConfigAll)
     return new PciConfigAll(p);
 }
 
-REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll)
-
 #endif // DOXYGEN_SHOULD_SKIP_THIS

src/dev/pcidev.cc

@@ -48,9 +48,8 @@
 #include "dev/alpha/tsunamireg.h"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/PciConfigData.hh"
 #include "sim/byteswap.hh"
-#include "sim/param.hh"
 #include "sim/core.hh"
 
 using namespace std;
@@ -84,8 +83,8 @@ PciDev::PciConfigPort::getDeviceAddressRanges(AddrRangeList &resp,
 
 
 PciDev::PciDev(Params *p)
-    : DmaDevice(p), plat(p->platform), configData(p->configData),
+    : DmaDevice(p), plat(p->platform), configData(p->configdata),
-      pioDelay(p->pio_delay), configDelay(p->config_delay),
+      pioDelay(p->pio_latency), configDelay(p->config_latency),
       configPort(NULL)
 {
     // copy the config data from the PciConfigData object
@@ -97,7 +96,7 @@ PciDev::PciDev(Params *p)
 
     memset(BARAddrs, 0, sizeof(BARAddrs));
 
-    plat->registerPciDevice(0, p->deviceNum, p->functionNum,
+    plat->registerPciDevice(0, p->pci_dev, p->pci_func,
             letoh(configData->config.interruptLine));
 }
 
@@ -136,21 +135,21 @@ PciDev::readConfig(PacketPtr pkt)
         pkt->set<uint8_t>(config.data[offset]);
         DPRINTF(PCIDEV,
             "readConfig:  dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
-            params()->deviceNum, params()->functionNum, offset,
+            params()->pci_dev, params()->pci_func, offset,
             (uint32_t)pkt->get<uint8_t>());
         break;
       case sizeof(uint16_t):
         pkt->set<uint16_t>(*(uint16_t*)&config.data[offset]);
         DPRINTF(PCIDEV,
             "readConfig:  dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
-            params()->deviceNum, params()->functionNum, offset,
+            params()->pci_dev, params()->pci_func, offset,
             (uint32_t)pkt->get<uint16_t>());
         break;
       case sizeof(uint32_t):
         pkt->set<uint32_t>(*(uint32_t*)&config.data[offset]);
         DPRINTF(PCIDEV,
             "readConfig:  dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
-            params()->deviceNum, params()->functionNum, offset,
+            params()->pci_dev, params()->pci_func, offset,
             (uint32_t)pkt->get<uint32_t>());
         break;
       default:
@@ -200,7 +199,7 @@ PciDev::writeConfig(PacketPtr pkt)
         }
         DPRINTF(PCIDEV,
             "writeConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
-            params()->deviceNum, params()->functionNum, offset,
+            params()->pci_dev, params()->pci_func, offset,
             (uint32_t)pkt->get<uint8_t>());
         break;
       case sizeof(uint16_t):
@@ -217,7 +216,7 @@ PciDev::writeConfig(PacketPtr pkt)
         }
         DPRINTF(PCIDEV,
             "writeConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
-            params()->deviceNum, params()->functionNum, offset,
+            params()->pci_dev, params()->pci_func, offset,
             (uint32_t)pkt->get<uint16_t>());
         break;
       case sizeof(uint32_t):
@@ -277,7 +276,7 @@ PciDev::writeConfig(PacketPtr pkt)
         }
         DPRINTF(PCIDEV,
             "writeConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
-            params()->deviceNum, params()->functionNum, offset,
+            params()->pci_dev, params()->pci_func, offset,
             (uint32_t)pkt->get<uint32_t>());
         break;
       default:
@@ -307,113 +306,38 @@ PciDev::unserialize(Checkpoint *cp, const std::string &section)
 
 }
 
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
+PciConfigData *
-
+PciConfigDataParams::create()
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
-
-    Param<uint16_t> VendorID;
-    Param<uint16_t> DeviceID;
-    Param<uint16_t> Command;
-    Param<uint16_t> Status;
-    Param<uint8_t> Revision;
-    Param<uint8_t> ProgIF;
-    Param<uint8_t> SubClassCode;
-    Param<uint8_t> ClassCode;
-    Param<uint8_t> CacheLineSize;
-    Param<uint8_t> LatencyTimer;
-    Param<uint8_t> HeaderType;
-    Param<uint8_t> BIST;
-    Param<uint32_t> BAR0;
-    Param<uint32_t> BAR1;
-    Param<uint32_t> BAR2;
-    Param<uint32_t> BAR3;
-    Param<uint32_t> BAR4;
-    Param<uint32_t> BAR5;
-    Param<uint32_t> CardbusCIS;
-    Param<uint16_t> SubsystemVendorID;
-    Param<uint16_t> SubsystemID;
-    Param<uint32_t> ExpansionROM;
-    Param<uint8_t> InterruptLine;
-    Param<uint8_t> InterruptPin;
-    Param<uint8_t> MinimumGrant;
-    Param<uint8_t> MaximumLatency;
-    Param<uint32_t> BAR0Size;
-    Param<uint32_t> BAR1Size;
-    Param<uint32_t> BAR2Size;
-    Param<uint32_t> BAR3Size;
-    Param<uint32_t> BAR4Size;
-    Param<uint32_t> BAR5Size;
-
-END_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigData)
-
-    INIT_PARAM(VendorID, "Vendor ID"),
-    INIT_PARAM(DeviceID, "Device ID"),
-    INIT_PARAM_DFLT(Command, "Command Register", 0x00),
-    INIT_PARAM_DFLT(Status, "Status Register", 0x00),
-    INIT_PARAM_DFLT(Revision, "Device Revision", 0x00),
-    INIT_PARAM_DFLT(ProgIF, "Programming Interface", 0x00),
-    INIT_PARAM(SubClassCode, "Sub-Class Code"),
-    INIT_PARAM(ClassCode, "Class Code"),
-    INIT_PARAM_DFLT(CacheLineSize, "System Cacheline Size", 0x00),
-    INIT_PARAM_DFLT(LatencyTimer, "PCI Latency Timer", 0x00),
-    INIT_PARAM_DFLT(HeaderType, "PCI Header Type", 0x00),
-    INIT_PARAM_DFLT(BIST, "Built In Self Test", 0x00),
-    INIT_PARAM_DFLT(BAR0, "Base Address Register 0", 0x00),
-    INIT_PARAM_DFLT(BAR1, "Base Address Register 1", 0x00),
-    INIT_PARAM_DFLT(BAR2, "Base Address Register 2", 0x00),
-    INIT_PARAM_DFLT(BAR3, "Base Address Register 3", 0x00),
-    INIT_PARAM_DFLT(BAR4, "Base Address Register 4", 0x00),
-    INIT_PARAM_DFLT(BAR5, "Base Address Register 5", 0x00),
-    INIT_PARAM_DFLT(CardbusCIS, "Cardbus Card Information Structure", 0x00),
-    INIT_PARAM_DFLT(SubsystemVendorID, "Subsystem Vendor ID", 0x00),
-    INIT_PARAM_DFLT(SubsystemID, "Subsystem ID", 0x00),
-    INIT_PARAM_DFLT(ExpansionROM, "Expansion ROM Base Address Register", 0x00),
-    INIT_PARAM(InterruptLine, "Interrupt Line Register"),
-    INIT_PARAM(InterruptPin, "Interrupt Pin Register"),
-    INIT_PARAM_DFLT(MinimumGrant, "Minimum Grant", 0x00),
-    INIT_PARAM_DFLT(MaximumLatency, "Maximum Latency", 0x00),
-    INIT_PARAM_DFLT(BAR0Size, "Base Address Register 0 Size", 0x00),
-    INIT_PARAM_DFLT(BAR1Size, "Base Address Register 1 Size", 0x00),
-    INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00),
-    INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00),
-    INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00),
-    INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00)
-
-END_INIT_SIM_OBJECT_PARAMS(PciConfigData)
-
-CREATE_SIM_OBJECT(PciConfigData)
 {
-    PciConfigData *data = new PciConfigData(getInstanceName());
+    PciConfigData *data = new PciConfigData(name);
 
-    data->config.vendor = htole(VendorID.returnValue());
+    data->config.vendor = htole(VendorID);
-    data->config.device = htole(DeviceID.returnValue());
+    data->config.device = htole(DeviceID);
-    data->config.command = htole(Command.returnValue());
+    data->config.command = htole(Command);
-    data->config.status = htole(Status.returnValue());
+    data->config.status = htole(Status);
-    data->config.revision = htole(Revision.returnValue());
+    data->config.revision = htole(Revision);
-    data->config.progIF = htole(ProgIF.returnValue());
+    data->config.progIF = htole(ProgIF);
-    data->config.subClassCode = htole(SubClassCode.returnValue());
+    data->config.subClassCode = htole(SubClassCode);
-    data->config.classCode = htole(ClassCode.returnValue());
+    data->config.classCode = htole(ClassCode);
-    data->config.cacheLineSize = htole(CacheLineSize.returnValue());
+    data->config.cacheLineSize = htole(CacheLineSize);
-    data->config.latencyTimer = htole(LatencyTimer.returnValue());
+    data->config.latencyTimer = htole(LatencyTimer);
-    data->config.headerType = htole(HeaderType.returnValue());
+    data->config.headerType = htole(HeaderType);
-    data->config.bist = htole(BIST.returnValue());
+    data->config.bist = htole(BIST);
 
-    data->config.baseAddr[0] = htole(BAR0.returnValue());
+    data->config.baseAddr[0] = htole(BAR0);
-    data->config.baseAddr[1] = htole(BAR1.returnValue());
+    data->config.baseAddr[1] = htole(BAR1);
-    data->config.baseAddr[2] = htole(BAR2.returnValue());
+    data->config.baseAddr[2] = htole(BAR2);
-    data->config.baseAddr[3] = htole(BAR3.returnValue());
+    data->config.baseAddr[3] = htole(BAR3);
-    data->config.baseAddr[4] = htole(BAR4.returnValue());
+    data->config.baseAddr[4] = htole(BAR4);
-    data->config.baseAddr[5] = htole(BAR5.returnValue());
+    data->config.baseAddr[5] = htole(BAR5);
-    data->config.cardbusCIS = htole(CardbusCIS.returnValue());
+    data->config.cardbusCIS = htole(CardbusCIS);
-    data->config.subsystemVendorID = htole(SubsystemVendorID.returnValue());
+    data->config.subsystemVendorID = htole(SubsystemVendorID);
-    data->config.subsystemID = htole(SubsystemID.returnValue());
+    data->config.subsystemID = htole(SubsystemID);
-    data->config.expansionROM = htole(ExpansionROM.returnValue());
+    data->config.expansionROM = htole(ExpansionROM);
-    data->config.interruptLine = htole(InterruptLine.returnValue());
+    data->config.interruptLine = htole(InterruptLine);
-    data->config.interruptPin = htole(InterruptPin.returnValue());
+    data->config.interruptPin = htole(InterruptPin);
-    data->config.minimumGrant = htole(MinimumGrant.returnValue());
+    data->config.minimumGrant = htole(MinimumGrant);
-    data->config.maximumLatency = htole(MaximumLatency.returnValue());
+    data->config.maximumLatency = htole(MaximumLatency);
 
     data->BARSize[0] = BAR0Size;
     data->BARSize[1] = BAR1Size;
@@ -426,13 +350,9 @@ CREATE_SIM_OBJECT(PciConfigData)
         uint32_t barsize = data->BARSize[i];
         if (barsize != 0 && !isPowerOf2(barsize)) {
             fatal("%s: BAR %d size %d is not a power of 2\n",
-                  getInstanceName(), i, data->BARSize[i]);
+                  name, i, data->BARSize[i]);
         }
     }
 
     return data;
 }
-
-REGISTER_SIM_OBJECT("PciConfigData", PciConfigData)
-
-#endif // DOXYGEN_SHOULD_SKIP_THIS

src/dev/pcidev.hh

@@ -42,6 +42,7 @@
 #include "dev/io_device.hh"
 #include "dev/pcireg.h"
 #include "dev/platform.hh"
+#include "params/PciDevice.hh"
 #include "sim/byteswap.hh"
 
 #define BAR_IO_MASK 0x3
@@ -105,32 +106,12 @@ class PciDev : public DmaDevice
     };
 
   public:
-    struct Params : public DmaDevice::Params
+    typedef PciDeviceParams Params;
+    const Params *
+    params() const
     {
-        /**
+        return dynamic_cast<const Params *>(_params);
-         * A pointer to the object that contains the first 64 bytes of
+    }
-         * config space
-         */
-        PciConfigData *configData;
-
-        /** The bus number we are on */
-        uint32_t busNum;
-
-        /** The device number we have */
-        uint32_t deviceNum;
-
-        /** The function number */
-        uint32_t functionNum;
-
-        /** The latency for pio accesses. */
-        Tick pio_delay;
-
-        /** The latency for a config access. */
-        Tick config_delay;
-    };
-
-  public:
-    const Params *params() const { return (const Params *)_params; }
 
   protected:
     /** The current config space. Unlike the PciConfigData this is
@@ -266,8 +247,8 @@ class PciDev : public DmaDevice
         if (if_name == "config") {
             if (configPort != NULL)
                 panic("pciconfig port already connected to.");
-            configPort = new PciConfigPort(this, params()->busNum,
+            configPort = new PciConfigPort(this, params()->pci_bus,
-                    params()->deviceNum, params()->functionNum,
+                    params()->pci_dev, params()->pci_func,
                     params()->platform);
             return configPort;
         }

src/dev/platform.cc

@@ -31,7 +31,6 @@
 
 #include "base/misc.hh"
 #include "dev/platform.hh"
-#include "sim/builder.hh"
 #include "sim/sim_exit.hh"
 
 using namespace std;
@@ -79,7 +78,3 @@ Platform::registerPciDevice(uint8_t bus, uint8_t dev, uint8_t func, uint8_t intr
 
     intLines.set(intr);
 }
-
-
-DEFINE_SIM_OBJECT_CLASS_NAME("Platform", Platform)
-

src/dev/simconsole.cc

@@ -52,7 +52,7 @@
 #include "dev/platform.hh"
 #include "dev/simconsole.hh"
 #include "dev/uart.hh"
-#include "sim/builder.hh"
+#include "params/SimConsole.hh"
 
 using namespace std;
 
@@ -325,38 +325,17 @@ SimConsole::out(char c)
 
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimConsole)
+SimConsole *
-
+SimConsoleParams::create()
-    SimObjectParam<IntrControl *> intr_control;
-    Param<string> output;
-    Param<int> port;
-    Param<bool> append_name;
-    Param<int> number;
-
-END_DECLARE_SIM_OBJECT_PARAMS(SimConsole)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(SimConsole)
-
-    INIT_PARAM(intr_control, "interrupt controller"),
-    INIT_PARAM(output, "file to dump output to"),
-    INIT_PARAM(port, ""),
-    INIT_PARAM_DFLT(append_name, "append name() to filename", true),
-    INIT_PARAM_DFLT(number, "console number", 0)
-
-END_INIT_SIM_OBJECT_PARAMS(SimConsole)
-
-CREATE_SIM_OBJECT(SimConsole)
 {
     string filename = output;
     ostream *stream = NULL;
 
     if (!filename.empty()) {
         if (append_name)
-            filename += "." + getInstanceName();
+            filename += "." + name;
         stream = simout.find(filename);
     }
 
-    return new SimConsole(getInstanceName(), stream, number, port);
+    return new SimConsole(name, stream, number, port);
 }
-
-REGISTER_SIM_OBJECT("SimConsole", SimConsole)

src/dev/simple_disk.cc

@@ -45,7 +45,7 @@
 #include "dev/disk_image.hh"
 #include "dev/simple_disk.hh"
 #include "mem/port.hh"
-#include "sim/builder.hh"
+#include "params/SimpleDisk.hh"
 #include "sim/system.hh"
 
 using namespace std;
@@ -91,23 +91,8 @@ SimpleDisk::write(Addr addr, baddr_t block, int count)
 #endif
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleDisk)
+SimpleDisk *
-
+SimpleDiskParams::create()
-    SimObjectParam<System *> system;
-    SimObjectParam<DiskImage *> disk;
-
-END_DECLARE_SIM_OBJECT_PARAMS(SimpleDisk)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleDisk)
-
-    INIT_PARAM(system, "System pointer"),
-    INIT_PARAM(disk, "Disk Image")
-
-END_INIT_SIM_OBJECT_PARAMS(SimpleDisk)
-
-CREATE_SIM_OBJECT(SimpleDisk)
 {
-    return new SimpleDisk(getInstanceName(), system, disk);
+    return new SimpleDisk(name, system, disk);
 }
-
-REGISTER_SIM_OBJECT("SimpleDisk", SimpleDisk)

src/dev/sinic.cc

@@ -32,6 +32,7 @@
 #include <limits>
 #include <string>
 
+#include "arch/vtophys.hh"
 #include "base/inet.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/intr_control.hh"
@@ -39,12 +40,10 @@
 #include "dev/sinic.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
 #include "sim/debug.hh"
 #include "sim/eventq.hh"
 #include "sim/host.hh"
 #include "sim/stats.hh"
-#include "arch/vtophys.hh"
 
 using namespace Net;
 using namespace TheISA;
@@ -754,7 +753,7 @@ Device::reset()
     regs.TxFifoSize = params()->tx_fifo_size;
     regs.RxFifoMark = params()->rx_fifo_threshold;
     regs.TxFifoMark = params()->tx_fifo_threshold;
-    regs.HwAddr = params()->eaddr;
+    regs.HwAddr = params()->hardware_address;
 
     rxList.clear();
     rxBusy.clear();
@@ -1596,172 +1595,23 @@ Device::unserialize(Checkpoint *cp, const std::string &section)
 
 /* namespace Sinic */ }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS_WNS(Sinic, SinicInterface)
+Sinic::Interface *
-
+SinicIntParams::create()
-    SimObjectParam<EtherInt *> peer;
-    SimObjectParam<Sinic::Device *> device;
-END_DECLARE_SIM_OBJECT_PARAMS_WNS(Sinic, SinicInterface)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS_WNS(Sinic, SinicInterface)
-
-    INIT_PARAM_DFLT(peer, "peer interface", NULL),
-    INIT_PARAM(device, "Ethernet device of this interface")
-
-END_INIT_SIM_OBJECT_PARAMS_WNS(Sinic, SinicInterface)
-
-CREATE_SIM_OBJECT_WNS(Sinic, SinicInterface)
 {
-    Sinic::Interface *dev_int = new Sinic::Interface(getInstanceName(), device);
+    using namespace Sinic;
 
-    EtherInt *p = (EtherInt *)peer;
+    Interface *dev_int = new Interface(name, device);
-    if (p) {
+
-        dev_int->setPeer(p);
+    if (peer) {
-        p->setPeer(dev_int);
+        dev_int->setPeer(peer);
+        peer->setPeer(dev_int);
     }
 
     return dev_int;
 }
 
-REGISTER_SIM_OBJECT_WNS(Sinic, "SinicInt", SinicInterface)
+Sinic::Device *
-
+SinicParams::create()
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS_WNS(Sinic, SinicDevice)
-
-
-    SimObjectParam<System *> system;
-    SimObjectParam<Platform *> platform;
-    Param<Tick> min_backoff_delay;
-    Param<Tick> max_backoff_delay;
-    SimObjectParam<PciConfigData *> configdata;
-    Param<uint32_t> pci_bus;
-    Param<uint32_t> pci_dev;
-    Param<uint32_t> pci_func;
-    Param<Tick> pio_latency;
-    Param<Tick> config_latency;
-    Param<Tick> intr_delay;
-
-    Param<Tick> clock;
-    Param<Tick> dma_read_delay;
-    Param<Tick> dma_read_factor;
-    Param<Tick> dma_write_delay;
-    Param<Tick> dma_write_factor;
-
-    Param<Tick> rx_delay;
-    Param<Tick> tx_delay;
-    Param<uint32_t> rx_max_copy;
-    Param<uint32_t> tx_max_copy;
-    Param<uint32_t> rx_max_intr;
-    Param<uint32_t> rx_fifo_size;
-    Param<uint32_t> tx_fifo_size;
-    Param<uint32_t> rx_fifo_threshold;
-    Param<uint32_t> rx_fifo_low_mark;
-    Param<uint32_t> tx_fifo_high_mark;
-    Param<uint32_t> tx_fifo_threshold;
-
-    Param<bool> rx_filter;
-    Param<std::string> hardware_address;
-    Param<bool> rx_thread;
-    Param<bool> tx_thread;
-    Param<bool> rss;
-    Param<uint32_t> virtual_count;
-    Param<bool> zero_copy;
-    Param<bool> delay_copy;
-    Param<bool> virtual_addr;
-
-END_DECLARE_SIM_OBJECT_PARAMS_WNS(Sinic, SinicDevice)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS_WNS(Sinic, SinicDevice)
-
-
-    INIT_PARAM(system, "System pointer"),
-    INIT_PARAM(platform, "Platform pointer"),
-    INIT_PARAM(min_backoff_delay, "Minimum delay after receving a nack packed"),
-    INIT_PARAM(max_backoff_delay, "Maximum delay after receving a nack packed"),
-    INIT_PARAM(configdata, "PCI Config data"),
-    INIT_PARAM(pci_bus, "PCI bus ID"),
-    INIT_PARAM(pci_dev, "PCI device number"),
-    INIT_PARAM(pci_func, "PCI function code"),
-    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
-    INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
-    INIT_PARAM(intr_delay, "Interrupt Delay"),
-    INIT_PARAM(clock, "State machine cycle time"),
-
-    INIT_PARAM(dma_read_delay, "fixed delay for dma reads"),
-    INIT_PARAM(dma_read_factor, "multiplier for dma reads"),
-    INIT_PARAM(dma_write_delay, "fixed delay for dma writes"),
-    INIT_PARAM(dma_write_factor, "multiplier for dma writes"),
-
-    INIT_PARAM(rx_delay, "Receive Delay"),
-    INIT_PARAM(tx_delay, "Transmit Delay"),
-    INIT_PARAM(rx_max_copy, "rx max copy"),
-    INIT_PARAM(tx_max_copy, "rx max copy"),
-    INIT_PARAM(rx_max_intr, "rx max intr"),
-    INIT_PARAM(rx_fifo_size, "max size in bytes of rxFifo"),
-    INIT_PARAM(tx_fifo_size, "max size in bytes of txFifo"),
-    INIT_PARAM(rx_fifo_threshold, "max size in bytes of rxFifo"),
-    INIT_PARAM(rx_fifo_low_mark, "max size in bytes of rxFifo"),
-    INIT_PARAM(tx_fifo_high_mark, "max size in bytes of txFifo"),
-    INIT_PARAM(tx_fifo_threshold, "max size in bytes of txFifo"),
-
-    INIT_PARAM(rx_filter, "Enable Receive Filter"),
-    INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
-    INIT_PARAM(rx_thread, ""),
-    INIT_PARAM(tx_thread, ""),
-    INIT_PARAM(rss, ""),
-    INIT_PARAM(virtual_count, ""),
-    INIT_PARAM(zero_copy, ""),
-    INIT_PARAM(delay_copy, ""),
-    INIT_PARAM(virtual_addr, "")
-
-END_INIT_SIM_OBJECT_PARAMS_WNS(Sinic, SinicDevice)
-
-
-CREATE_SIM_OBJECT_WNS(Sinic, SinicDevice)
 {
-    Sinic::Sinic::Device::Params *params = new Device::Params;
+    return new Sinic::Device(this);
-    params->name = getInstanceName();
-    params->platform = platform;
-    params->system = system;
-    params->min_backoff_delay = min_backoff_delay;
-    params->max_backoff_delay = max_backoff_delay;
-    params->configData = configdata;
-    params->busNum = pci_bus;
-    params->deviceNum = pci_dev;
-    params->functionNum = pci_func;
-    params->pio_delay = pio_latency;
-    params->config_delay = config_latency;
-    params->intr_delay = intr_delay;
-    params->clock = clock;
-
-    params->dma_read_delay = dma_read_delay;
-    params->dma_read_factor = dma_read_factor;
-    params->dma_write_delay = dma_write_delay;
-    params->dma_write_factor = dma_write_factor;
-
-    params->tx_delay = tx_delay;
-    params->rx_delay = rx_delay;
-    params->rx_max_copy = rx_max_copy;
-    params->tx_max_copy = tx_max_copy;
-    params->rx_max_intr = rx_max_intr;
-    params->rx_fifo_size = rx_fifo_size;
-    params->tx_fifo_size = tx_fifo_size;
-    params->rx_fifo_threshold = rx_fifo_threshold;
-    params->rx_fifo_low_mark = rx_fifo_low_mark;
-    params->tx_fifo_high_mark = tx_fifo_high_mark;
-    params->tx_fifo_threshold = tx_fifo_threshold;
-
-    params->rx_filter = rx_filter;
-    params->eaddr = hardware_address;
-    params->rx_thread = rx_thread;
-    params->tx_thread = tx_thread;
-    params->rss = rss;
-    params->virtual_count = virtual_count;
-    params->zero_copy = zero_copy;
-    params->delay_copy = delay_copy;
-    params->virtual_addr = virtual_addr;
-
-    return new Sinic::Device(params);
 }
-
-REGISTER_SIM_OBJECT_WNS(Sinic, "Sinic", SinicDevice)
-

src/dev/sinic.hh

@@ -39,6 +39,8 @@
 #include "dev/pcidev.hh"
 #include "dev/pktfifo.hh"
 #include "dev/sinicreg.hh"
+#include "params/Sinic.hh"
+#include "params/SinicInt.hh"
 #include "sim/eventq.hh"
 
 namespace Sinic {
@@ -80,12 +82,8 @@ class Base : public PciDev
  * Construction/Destruction/Parameters
  */
   public:
-    struct Params : public PciDev::Params
+    typedef SinicParams Params;
-    {
+    const Params *params() const { return (const Params *)_params; }
-        Tick clock;
-        Tick intr_delay;
-    };
-
     Base(Params *p);
 };
 
@@ -313,43 +311,8 @@ class Device : public Base
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
-/**
- * Construction/Destruction/Parameters
- */
   public:
-    struct Params : public Base::Params
+    Device(Params *p);
-    {
-        Tick tx_delay;
-        Tick rx_delay;
-        bool rx_filter;
-        Net::EthAddr eaddr;
-        uint32_t rx_max_copy;
-        uint32_t tx_max_copy;
-        uint32_t rx_max_intr;
-        uint32_t rx_fifo_size;
-        uint32_t tx_fifo_size;
-        uint32_t rx_fifo_threshold;
-        uint32_t rx_fifo_low_mark;
-        uint32_t tx_fifo_high_mark;
-        uint32_t tx_fifo_threshold;
-        Tick dma_read_delay;
-        Tick dma_read_factor;
-        Tick dma_write_delay;
-        Tick dma_write_factor;
-        bool rx_thread;
-        bool tx_thread;
-        bool rss;
-        uint32_t virtual_count;
-        bool zero_copy;
-        bool delay_copy;
-        bool virtual_addr;
-    };
-
-  protected:
-    const Params *params() const { return (const Params *)_params; }
-
-  public:
-    Device(Params *params);
     ~Device();
 };
 

src/dev/sparc/dtod.cc

@@ -37,26 +37,25 @@
 #include <string>
 #include <vector>
 
+#include "base/time.hh"
 #include "base/trace.hh"
 #include "dev/sparc/dtod.hh"
 #include "dev/platform.hh"
 #include "mem/packet_access.hh"
 #include "mem/port.hh"
-#include "sim/builder.hh"
 #include "sim/system.hh"
 
 using namespace std;
 using namespace TheISA;
 
-DumbTOD::DumbTOD(Params *p)
+DumbTOD::DumbTOD(const Params *p)
     : BasicPioDevice(p)
 {
-    struct tm tm;
+    struct tm tm = p->time;
     char *tz;
 
     pioSize = 0x08;
 
-    parseTime(p->init_time, &tm);
     tz = getenv("TZ");
     setenv("TZ", "", 1);
     tzset();
@@ -104,37 +103,8 @@ DumbTOD::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_SCALAR(todTime);
 }
 
-
+DumbTOD *
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DumbTOD)
+DumbTODParams::create()
-
-    Param<Addr> pio_addr;
-    Param<Tick> pio_latency;
-    SimObjectParam<Platform *> platform;
-    SimObjectParam<System *> system;
-    VectorParam<int> time;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DumbTOD)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DumbTOD)
-
-    INIT_PARAM(pio_addr, "Device Address"),
-    INIT_PARAM(pio_latency, "Programmed IO latency"),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM(system, "system object"),
-    INIT_PARAM(time, "")
-
-END_INIT_SIM_OBJECT_PARAMS(DumbTOD)
-
-CREATE_SIM_OBJECT(DumbTOD)
 {
-    DumbTOD::Params *p = new DumbTOD::Params;
+    return new DumbTOD(this);
-    p->name =getInstanceName();
-    p->pio_addr = pio_addr;
-    p->pio_delay = pio_latency;
-    p->platform = platform;
-    p->system = system;
-    p->init_time = time;
-    return new DumbTOD(p);
 }
-
-REGISTER_SIM_OBJECT("DumbTOD", DumbTOD)

src/dev/sparc/dtod.hh

@@ -40,7 +40,7 @@
 
 #include "base/range.hh"
 #include "dev/io_device.hh"
-
+#include "params/DumbTOD.hh"
 
 /**
  * DumbTOD simply returns some idea of time when read.  Until we finish with
@@ -52,15 +52,14 @@ class DumbTOD : public BasicPioDevice
     uint64_t todTime;
 
   public:
-    struct Params : public BasicPioDevice::Params
+    typedef DumbTODParams Params;
-    {
+    DumbTOD(const Params *p);
-        std::vector<int> init_time;
-    };
-  protected:
-    const Params *params() const { return (const Params *)_params; }
 
-  public:
+    const Params *
-    DumbTOD(Params *p);
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
 
     virtual Tick read(PacketPtr pkt);
     virtual Tick write(PacketPtr pkt);

src/dev/sparc/iob.cc

@@ -45,11 +45,10 @@
 #include "dev/platform.hh"
 #include "mem/port.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
 #include "sim/faults.hh"
 #include "sim/system.hh"
 
-Iob::Iob(Params *p)
+Iob::Iob(const Params *p)
     : PioDevice(p), ic(p->platform->intrctrl)
 {
     iobManAddr = ULL(0x9800000000);
@@ -372,31 +371,8 @@ Iob::unserialize(Checkpoint *cp, const std::string &section)
     };
 }
 
-
+Iob *
-
+IobParams::create()
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Iob)
-    Param<Tick> pio_latency;
-    SimObjectParam<Platform *> platform;
-    SimObjectParam<System *> system;
-END_DECLARE_SIM_OBJECT_PARAMS(Iob)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Iob)
-
-    INIT_PARAM(pio_latency, "Programmed IO latency"),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM(system, "system object")
-
-END_INIT_SIM_OBJECT_PARAMS(Iob)
-
-CREATE_SIM_OBJECT(Iob)
 {
-    Iob::Params *p = new Iob::Params;
+    return new Iob(this);
-    p->name = getInstanceName();
-    p->pio_delay = pio_latency;
-    p->platform = platform;
-    p->system = system;
-    return new Iob(p);
 }
-
-REGISTER_SIM_OBJECT("Iob", Iob)

src/dev/sparc/iob.hh

@@ -39,6 +39,7 @@
 #include "base/range.hh"
 #include "dev/io_device.hh"
 #include "dev/disk_image.hh"
+#include "params/Iob.hh"
 
 class IntrControl;
 
@@ -123,24 +124,22 @@ class Iob : public PioDevice
     void readIob(PacketPtr pkt);
     void readJBus(PacketPtr pkt);
 
-
   public:
-    struct Params : public PioDevice::Params
+    typedef IobParams Params;
+    Iob(const Params *p);
+
+    const Params *
+    params() const
     {
-        Tick pio_delay;
+        return dynamic_cast<const Params *>(_params);
-    };
+    }
-  protected:
-    const Params *params() const { return (const Params*)_params; }
-
-  public:
-    Iob(Params *p);
 
     virtual Tick read(PacketPtr pkt);
     virtual Tick write(PacketPtr pkt);
     void generateIpi(Type type, int cpu_id, int vector);
     void receiveDeviceInterrupt(DeviceId devid);
-    bool receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1);
+    bool receiveJBusInterrupt(int cpu_id, int source, uint64_t d0,
-
+                              uint64_t d1);
 
     void addressRanges(AddrRangeList &range_list);
 

src/dev/sparc/mm_disk.cc

@@ -40,11 +40,10 @@
 #include "dev/platform.hh"
 #include "mem/port.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
 #include "sim/byteswap.hh"
 #include "sim/system.hh"
 
-MmDisk::MmDisk(Params *p)
+MmDisk::MmDisk(const Params *p)
     : BasicPioDevice(p), image(p->image), curSector((off_t)-1), dirty(false)
 {
     std::memset(&diskData, 0, SectorSize);
@@ -173,39 +172,8 @@ MmDisk::serialize(std::ostream &os)
     }
 }
 
-
+MmDisk *
-
+MmDiskParams::create()
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(MmDisk)
-    Param<Addr> pio_addr;
-    Param<Tick> pio_latency;
-    Param<Addr> pio_size;
-    SimObjectParam<Platform *> platform;
-    SimObjectParam<System *> system;
-    SimObjectParam<DiskImage *> image;
-END_DECLARE_SIM_OBJECT_PARAMS(MmDisk)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(MmDisk)
-
-    INIT_PARAM(pio_addr, "Device Address"),
-    INIT_PARAM(pio_latency, "Programmed IO latency"),
-    INIT_PARAM(pio_size, "Size of address range"),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM(system, "system object"),
-    INIT_PARAM(image, "disk image")
-
-END_INIT_SIM_OBJECT_PARAMS(MmDisk)
-
-CREATE_SIM_OBJECT(MmDisk)
 {
-    MmDisk::Params *p = new MmDisk::Params;
+    return new MmDisk(this);
-    p->name = getInstanceName();
-    p->pio_addr = pio_addr;
-    p->pio_delay = pio_latency;
-    p->platform = platform;
-    p->system = system;
-    p->image = image;
-    return new MmDisk(p);
 }
-
-REGISTER_SIM_OBJECT("MmDisk", MmDisk)

src/dev/sparc/mm_disk.hh

@@ -39,6 +39,7 @@
 #include "base/range.hh"
 #include "dev/io_device.hh"
 #include "dev/disk_image.hh"
+#include "params/MmDisk.hh"
 
 class MmDisk : public BasicPioDevice
 {
@@ -49,15 +50,14 @@ class MmDisk : public BasicPioDevice
     uint8_t diskData[SectorSize];
 
   public:
-    struct Params : public BasicPioDevice::Params
+    typedef MmDiskParams Params;
-    {
+    MmDisk(const Params *p);
-        DiskImage *image;
-    };
-  protected:
-    const Params *params() const { return (const Params*)_params; }
 
-  public:
+    const Params *
-    MmDisk(Params *p);
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
 
     virtual Tick read(PacketPtr pkt);
     virtual Tick write(PacketPtr pkt);

src/dev/sparc/t1000.cc

@@ -39,7 +39,7 @@
 #include "cpu/intr_control.hh"
 #include "dev/simconsole.hh"
 #include "dev/sparc/t1000.hh"
-#include "sim/builder.hh"
+#include "params/T1000.hh"
 #include "sim/system.hh"
 
 using namespace std;
@@ -101,23 +101,8 @@ T1000::calcConfigAddr(int bus, int dev, int func)
     M5_DUMMY_RETURN
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(T1000)
+T1000 *
-
+T1000Params::create()
-    SimObjectParam<System *> system;
-    SimObjectParam<IntrControl *> intrctrl;
-
-END_DECLARE_SIM_OBJECT_PARAMS(T1000)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(T1000)
-
-    INIT_PARAM(system, "system"),
-    INIT_PARAM(intrctrl, "interrupt controller")
-
-END_INIT_SIM_OBJECT_PARAMS(T1000)
-
-CREATE_SIM_OBJECT(T1000)
 {
-    return new T1000(getInstanceName(), system, intrctrl);
+    return new T1000(name, system, intrctrl);
 }
-
-REGISTER_SIM_OBJECT("T1000", T1000)

src/dev/uart.cc

@@ -35,19 +35,14 @@
 #include "dev/simconsole.hh"
 #include "dev/uart.hh"
 #include "dev/platform.hh"
-#include "sim/builder.hh"
 
 using namespace std;
 
-Uart::Uart(Params *p)
+Uart::Uart(const Params *p)
-    : BasicPioDevice(p), platform(p->platform), cons(p->cons)
+    : BasicPioDevice(p), platform(p->platform), cons(p->sim_console)
 {
-
     status = 0;
 
     // set back pointers
     cons->uart = this;
 }
-
-DEFINE_SIM_OBJECT_CLASS_NAME("Uart", Uart)
-

src/dev/uart.hh

@@ -37,6 +37,7 @@
 
 #include "base/range.hh"
 #include "dev/io_device.hh"
+#include "params/Uart.hh"
 
 class SimConsole;
 class Platform;
@@ -44,7 +45,6 @@ class Platform;
 const int RX_INT = 0x1;
 const int TX_INT = 0x2;
 
-
 class Uart : public BasicPioDevice
 {
 
@@ -54,28 +54,25 @@ class Uart : public BasicPioDevice
     SimConsole *cons;
 
   public:
-    struct Params : public BasicPioDevice::Params
+    typedef UartParams Params;
-    {
+    Uart(const Params *p);
-        SimConsole *cons;
-    };
 
-    Uart(Params *p);
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
 
     /**
      * Inform the uart that there is data available.
      */
     virtual void dataAvailable() = 0;
 
-
     /**
      * Return if we have an interrupt pending
      * @return interrupt status
      */
     bool intStatus() { return status ? true : false; }
-
-  protected:
-    const Params *params() const {return (const Params *)_params; }
-
 };
 
 #endif // __UART_HH__

src/dev/uart8250.cc

@@ -43,7 +43,6 @@
 #include "dev/platform.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
 
 using namespace std;
 using namespace TheISA;
@@ -100,12 +99,11 @@ Uart8250::IntrEvent::scheduleIntr()
 }
 
 
-Uart8250::Uart8250(Params *p)
+Uart8250::Uart8250(const Params *p)
     : Uart(p), IER(0), DLAB(0), LCR(0), MCR(0), lastTxInt(0),
       txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
 {
     pioSize = 8;
-
 }
 
 Tick
@@ -338,37 +336,8 @@ Uart8250::unserialize(Checkpoint *cp, const std::string &section)
         txIntrEvent.schedule(txintrwhen);
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
+Uart8250 *
-
+Uart8250Params::create()
-    Param<Addr> pio_addr;
-    Param<Tick> pio_latency;
-    SimObjectParam<Platform *> platform;
-    SimObjectParam<SimConsole *> sim_console;
-    SimObjectParam<System *> system;
-
-END_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Uart8250)
-
-    INIT_PARAM(pio_addr, "Device Address"),
-    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM(sim_console, "The Simulator Console"),
-    INIT_PARAM(system, "system object")
-
-END_INIT_SIM_OBJECT_PARAMS(Uart8250)
-
-CREATE_SIM_OBJECT(Uart8250)
 {
-    Uart8250::Params *p = new Uart8250::Params;
+    return new Uart8250(this);
-    p->name = getInstanceName();
-    p->pio_addr = pio_addr;
-    p->pio_delay = pio_latency;
-    p->platform = platform;
-    p->cons = sim_console;
-    p->system = system;
-    return new Uart8250(p);
 }
-
-REGISTER_SIM_OBJECT("Uart8250", Uart8250)
-

src/dev/uart8250.hh

@@ -38,7 +38,7 @@
 #include "base/range.hh"
 #include "dev/io_device.hh"
 #include "dev/uart.hh"
-
+#include "params/Uart8250.hh"
 
 /* UART8250 Interrupt ID Register
  *  bit 0    Interrupt Pending 0 = true, 1 = false
@@ -70,8 +70,6 @@ class Platform;
 
 class Uart8250 : public Uart
 {
-
-
   protected:
     uint8_t IER, DLAB, LCR, MCR;
     Tick lastTxInt;
@@ -92,13 +90,18 @@ class Uart8250 : public Uart
     IntrEvent rxIntrEvent;
 
   public:
-    Uart8250(Params *p);
+    typedef Uart8250Params Params;
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+    Uart8250(const Params *p);
 
     virtual Tick read(PacketPtr pkt);
     virtual Tick write(PacketPtr pkt);
     virtual void addressRanges(AddrRangeList &range_list);
 
-
     /**
      * Inform the uart that there is data available.
      */

src/mem/MemObject.py

@@ -26,7 +26,6 @@
 #
 # Authors: Ron Dreslinski
 
-from m5.SimObject import SimObject
 from m5.SimObject import SimObject
 
 class MemObject(SimObject):

src/mem/bridge.cc

@@ -39,7 +39,7 @@
 
 #include "base/trace.hh"
 #include "mem/bridge.hh"
-#include "sim/builder.hh"
+#include "params/Bridge.hh"
 
 Bridge::BridgePort::BridgePort(const std::string &_name,
                                Bridge *_bridge, BridgePort *_otherPort,
@@ -367,50 +367,8 @@ Bridge::BridgePort::getDeviceAddressRanges(AddrRangeList &resp,
     otherPort->getPeerAddressRanges(resp, snoop);
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bridge)
+Bridge *
-
+BridgeParams::create()
-   Param<int> req_size_a;
-   Param<int> req_size_b;
-   Param<int> resp_size_a;
-   Param<int> resp_size_b;
-   Param<Tick> delay;
-   Param<Tick> nack_delay;
-   Param<bool> write_ack;
-   Param<bool> fix_partial_write_a;
-   Param<bool> fix_partial_write_b;
-
-END_DECLARE_SIM_OBJECT_PARAMS(Bridge)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Bridge)
-
-    INIT_PARAM(req_size_a, "The size of the queue for requests coming into side a"),
-    INIT_PARAM(req_size_b, "The size of the queue for requests coming into side b"),
-    INIT_PARAM(resp_size_a, "The size of the queue for responses coming into side a"),
-    INIT_PARAM(resp_size_b, "The size of the queue for responses coming into side b"),
-    INIT_PARAM(delay, "The miminum delay to cross this bridge"),
-    INIT_PARAM(nack_delay, "The minimum delay to nack a packet"),
-    INIT_PARAM(write_ack, "Acknowledge any writes that are received."),
-    INIT_PARAM(fix_partial_write_a, "Fixup any partial block writes that are received"),
-    INIT_PARAM(fix_partial_write_b, "Fixup any partial block writes that are received")
-
-END_INIT_SIM_OBJECT_PARAMS(Bridge)
-
-CREATE_SIM_OBJECT(Bridge)
 {
-    Bridge::Params *p = new Bridge::Params;
+    return new Bridge(this);
-    p->name = getInstanceName();
-    p->req_size_a = req_size_a;
-    p->req_size_b = req_size_b;
-    p->resp_size_a = resp_size_a;
-    p->resp_size_b = resp_size_b;
-    p->delay = delay;
-    p->nack_delay = nack_delay;
-    p->write_ack = write_ack;
-    p->fix_partial_write_a = fix_partial_write_a;
-    p->fix_partial_write_b = fix_partial_write_b;
-    return new Bridge(p);
 }
-
-REGISTER_SIM_OBJECT("Bridge", Bridge)
-
-

src/mem/bridge.hh

@@ -45,6 +45,7 @@
 #include "mem/mem_object.hh"
 #include "mem/packet.hh"
 #include "mem/port.hh"
+#include "params/Bridge.hh"
 #include "sim/eventq.hh"
 
 class Bridge : public MemObject
@@ -191,19 +192,7 @@ class Bridge : public MemObject
     bool ackWrites;
 
   public:
-    struct Params
+    typedef BridgeParams Params;
-    {
-        std::string name;
-        int req_size_a;
-        int req_size_b;
-        int resp_size_a;
-        int resp_size_b;
-        Tick delay;
-        Tick nack_delay;
-        bool write_ack;
-        bool fix_partial_write_a;
-        bool fix_partial_write_b;
-    };
 
   protected:
     Params *_params;

src/mem/bus.cc

@@ -39,7 +39,7 @@
 #include "base/misc.hh"
 #include "base/trace.hh"
 #include "mem/bus.hh"
-#include "sim/builder.hh"
+#include "params/Bus.hh"
 
 Port *
 Bus::getPort(const std::string &if_name, int idx)
@@ -612,28 +612,8 @@ Bus::startup()
         tickNextIdle = (curTick / clock) * clock + clock;
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus)
+Bus *
-
+BusParams::create()
-    Param<int> bus_id;
-    Param<int> clock;
-    Param<int> width;
-    Param<bool> responder_set;
-    Param<int> block_size;
-
-END_DECLARE_SIM_OBJECT_PARAMS(Bus)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Bus)
-    INIT_PARAM(bus_id, "a globally unique bus id"),
-    INIT_PARAM(clock, "bus clock speed"),
-    INIT_PARAM(width, "width of the bus (bits)"),
-    INIT_PARAM(responder_set, "Is a default responder set by the user"),
-    INIT_PARAM(block_size, "Default blocksize if no device has one")
-END_INIT_SIM_OBJECT_PARAMS(Bus)
-
-CREATE_SIM_OBJECT(Bus)
 {
-    return new Bus(getInstanceName(), bus_id, clock, width, responder_set,
+    return new Bus(name, bus_id, clock, width, responder_set, block_size);
-            block_size);
 }
-
-REGISTER_SIM_OBJECT("Bus", Bus)

src/mem/cache/cache_builder.cc

@@ -36,14 +36,14 @@
 #include <vector>
 
 // Must be included first to determine which caches we want
+#include "enums/Prefetch.hh"
 #include "mem/config/cache.hh"
 #include "mem/config/prefetch.hh"
-
 #include "mem/cache/base_cache.hh"
 #include "mem/cache/cache.hh"
 #include "mem/bus.hh"
 #include "mem/cache/coherence/coherence_protocol.hh"
-#include "sim/builder.hh"
+#include "params/BaseCache.hh"
 
 // Tag Templates
 #if defined(USE_CACHE_LRU)
@@ -93,123 +93,23 @@
 using namespace std;
 using namespace TheISA;
 
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
-
-    Param<int> size;
-    Param<int> assoc;
-    Param<int> block_size;
-    Param<int> latency;
-    Param<int> mshrs;
-    Param<int> tgts_per_mshr;
-    Param<int> write_buffers;
-    Param<bool> prioritizeRequests;
-    SimObjectParam<CoherenceProtocol *> protocol;
-    Param<Addr> trace_addr;
-    Param<int> hash_delay;
-#if defined(USE_CACHE_IIC)
-    SimObjectParam<Repl *> repl;
-#endif
-    Param<bool> compressed_bus;
-    Param<bool> store_compressed;
-    Param<bool> adaptive_compression;
-    Param<int> compression_latency;
-    Param<int> subblock_size;
-    Param<Counter> max_miss_count;
-    VectorParam<Range<Addr> > addr_range;
-//    SimObjectParam<MemTraceWriter *> mem_trace;
-    Param<bool> split;
-    Param<int> split_size;
-    Param<bool> lifo;
-    Param<bool> two_queue;
-    Param<bool> prefetch_miss;
-    Param<bool> prefetch_access;
-    Param<int> prefetcher_size;
-    Param<bool> prefetch_past_page;
-    Param<bool> prefetch_serial_squash;
-    Param<Tick> prefetch_latency;
-    Param<int> prefetch_degree;
-    Param<string> prefetch_policy;
-    Param<bool> prefetch_cache_check_push;
-    Param<bool> prefetch_use_cpu_id;
-    Param<bool> prefetch_data_accesses_only;
-
-END_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache)
-
-    INIT_PARAM(size, "capacity in bytes"),
-    INIT_PARAM(assoc, "associativity"),
-    INIT_PARAM(block_size, "block size in bytes"),
-    INIT_PARAM(latency, "hit latency in CPU cycles"),
-    INIT_PARAM(mshrs, "number of MSHRs (max outstanding requests)"),
-    INIT_PARAM(tgts_per_mshr, "max number of accesses per MSHR"),
-    INIT_PARAM_DFLT(write_buffers, "number of write buffers", 8),
-    INIT_PARAM_DFLT(prioritizeRequests, "always service demand misses first",
-                    false),
-    INIT_PARAM_DFLT(protocol, "coherence protocol to use in the cache", NULL),
-    INIT_PARAM_DFLT(trace_addr, "address to trace", 0),
-
-    INIT_PARAM_DFLT(hash_delay, "time in cycles of hash access",1),
-#if defined(USE_CACHE_IIC)
-    INIT_PARAM_DFLT(repl, "replacement policy",NULL),
-#endif
-    INIT_PARAM_DFLT(compressed_bus,
-                    "This cache connects to a compressed memory",
-                    false),
-    INIT_PARAM_DFLT(store_compressed, "Store compressed data in the cache",
-                    false),
-    INIT_PARAM_DFLT(adaptive_compression, "Use an adaptive compression scheme",
-                    false),
-    INIT_PARAM_DFLT(compression_latency,
-                    "Latency in cycles of compression algorithm",
-                    0),
-    INIT_PARAM_DFLT(subblock_size,
-                    "Size of subblock in IIC used for compression",
-                    0),
-    INIT_PARAM_DFLT(max_miss_count,
-                    "The number of misses to handle before calling exit",
-                    0),
-    INIT_PARAM_DFLT(addr_range, "The address range in bytes",
-                    vector<Range<Addr> >(1,RangeIn((Addr)0, MaxAddr))),
-//    INIT_PARAM_DFLT(mem_trace, "Memory trace to write accesses to", NULL),
-    INIT_PARAM_DFLT(split, "Whether this is a partitioned cache", false),
-    INIT_PARAM_DFLT(split_size, "the number of \"ways\" belonging to the LRU partition", 0),
-    INIT_PARAM_DFLT(lifo, "whether you are using a LIFO repl. policy", false),
-    INIT_PARAM_DFLT(two_queue, "whether the lifo should have two queue replacement", false),
-    INIT_PARAM_DFLT(prefetch_miss, "wheter you are using the hardware prefetcher from Miss stream", false),
-    INIT_PARAM_DFLT(prefetch_access, "wheter you are using the hardware prefetcher from Access stream", false),
-    INIT_PARAM_DFLT(prefetcher_size, "Number of entries in the harware prefetch queue", 100),
-    INIT_PARAM_DFLT(prefetch_past_page, "Allow prefetches to cross virtual page boundaries", false),
-    INIT_PARAM_DFLT(prefetch_serial_squash, "Squash prefetches with a later time on a subsequent miss", false),
-    INIT_PARAM_DFLT(prefetch_latency, "Latency of the prefetcher", 10),
-    INIT_PARAM_DFLT(prefetch_degree, "Degree of the prefetch depth", 1),
-    INIT_PARAM_DFLT(prefetch_policy, "Type of prefetcher to use", "none"),
-    INIT_PARAM_DFLT(prefetch_cache_check_push, "Check if in cash on push or pop of prefetch queue", true),
-    INIT_PARAM_DFLT(prefetch_use_cpu_id, "Use the CPU ID to seperate calculations of prefetches", true),
-    INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false)
-END_INIT_SIM_OBJECT_PARAMS(BaseCache)
-
-
 #define BUILD_CACHE(TAGS, tags, c)                                      \
     do {                                                                \
-        BasePrefetcher *pf;                                           \
+        BasePrefetcher *pf;                                             \
-        if (pf_policy == "tagged") {                                    \
+        if (prefetch_policy == Enums::tagged) {                         \
             BUILD_TAGGED_PREFETCHER(TAGS);                              \
         }                                                               \
-        else if (pf_policy == "stride") {                               \
+        else if (prefetch_policy == Enums::stride) {                    \
             BUILD_STRIDED_PREFETCHER(TAGS);                             \
         }                                                               \
-        else if (pf_policy == "ghb") {                                  \
+        else if (prefetch_policy == Enums::ghb) {                       \
             BUILD_GHB_PREFETCHER(TAGS);                                 \
         }                                                               \
         else {                                                          \
             BUILD_NULL_PREFETCHER(TAGS);                                \
         }                                                               \
         Cache<TAGS, c>::Params params(tags, mq, coh, base_params,       \
-                                      pf, prefetch_access, latency, \
+                                      pf, prefetch_access, latency,     \
                                       true,                             \
                                       store_compressed,                 \
                                       adaptive_compression,             \
@@ -217,7 +117,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
                                       compAlg, compression_latency,     \
                                       prefetch_miss);                   \
         Cache<TAGS, c> *retval =                                        \
-            new Cache<TAGS, c>(getInstanceName(), params);              \
+            new Cache<TAGS, c>(name, params);                           \
         return retval;                                                  \
     } while (0)
 
@@ -365,11 +265,10 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
 #define BUILD_NULL_PREFETCHER(t) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
 #endif
 
-CREATE_SIM_OBJECT(BaseCache)
+BaseCache *
+BaseCacheParams::create()
 {
-    string name = getInstanceName();
     int numSets = size / (assoc * block_size);
-    string pf_policy = prefetch_policy;
     if (subblock_size == 0) {
         subblock_size = block_size;
     }
@@ -379,24 +278,21 @@ CREATE_SIM_OBJECT(BaseCache)
                                   block_size, max_miss_count);
 
     //Warnings about prefetcher policy
-    if (pf_policy == "none" && (prefetch_miss || prefetch_access)) {
+    if (prefetch_policy == Enums::none) {
-        panic("With no prefetcher, you shouldn't prefetch from"
+        if (prefetch_miss || prefetch_access)
-              " either miss or access stream\n");
+            panic("With no prefetcher, you shouldn't prefetch from"
+                  " either miss or access stream\n");
     }
-    if ((pf_policy == "tagged" || pf_policy == "stride" ||
+
-         pf_policy == "ghb") && !(prefetch_miss || prefetch_access)) {
+    if (prefetch_policy == Enums::tagged || prefetch_policy == Enums::stride ||
-        warn("With this prefetcher you should chose a prefetch"
+        prefetch_policy == Enums::ghb) {
-             " stream (miss or access)\nNo Prefetching will occur\n");
+
-    }
+        if (!prefetch_miss && !prefetch_access)
-    if ((pf_policy == "tagged" || pf_policy == "stride" ||
+            warn("With this prefetcher you should chose a prefetch"
-         pf_policy == "ghb") && prefetch_miss && prefetch_access) {
+                 " stream (miss or access)\nNo Prefetching will occur\n");
-        panic("Can't do prefetches from both miss and access"
+
-              " stream\n");
+        if (prefetch_miss && prefetch_access)
-    }
+            panic("Can't do prefetches from both miss and access stream");
-    if (pf_policy != "tagged" && pf_policy != "stride" &&
-        pf_policy != "ghb"    && pf_policy != "none") {
-        panic("Unrecognized form of a prefetcher: %s, try using"
-              "['none','stride','tagged','ghb']\n", pf_policy);
     }
 
 #if defined(USE_CACHE_IIC)
@@ -424,8 +320,3 @@ CREATE_SIM_OBJECT(BaseCache)
     }
     return NULL;
 }
-
-REGISTER_SIM_OBJECT("BaseCache", BaseCache)
-
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS

src/mem/cache/coherence/coherence_protocol.cc

@@ -41,7 +41,7 @@
 #include "mem/cache/miss/mshr.hh"
 #include "mem/cache/cache.hh"
 #include "mem/cache/coherence/coherence_protocol.hh"
-#include "sim/builder.hh"
+#include "params/CoherenceProtocol.hh"
 
 using namespace std;
 
@@ -258,18 +258,12 @@ CoherenceProtocol::assertShared(BaseCache *cache, PacketPtr &pkt,
 }
 
 CoherenceProtocol::CoherenceProtocol(const string &name,
-                                     const string &protocol,
+                                     Enums::Coherence protocol,
                                      const bool doUpgrades)
     : SimObject(name)
 {
-    // Python should catch this, but in case it doesn't...
+    bool hasOwned = (protocol == Enums::mosi || protocol == Enums::moesi);
-    if (!(protocol == "msi"  || protocol == "mesi" ||
+    bool hasExclusive = (protocol == Enums::mesi || protocol == Enums::moesi);
-          protocol == "mosi" || protocol == "moesi")) {
-        fatal("CoherenceProtocol: unrecognized protocol %s\n",  protocol);
-    }
-
-    bool hasOwned = (protocol == "mosi" || protocol == "moesi");
-    bool hasExclusive = (protocol == "mesi" || protocol == "moesi");
 
     if (hasOwned && !doUpgrades) {
         fatal("CoherenceProtocol: ownership protocols require upgrade "
@@ -466,30 +460,8 @@ CoherenceProtocol::invalidTransition(BaseCache *cache, PacketPtr &pkt,
     return false;
 }
 
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
+CoherenceProtocol *
-
+CoherenceProtocolParams::create()
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(CoherenceProtocol)
-
-    Param<string> protocol;
-    Param<bool> do_upgrades;
-
-END_DECLARE_SIM_OBJECT_PARAMS(CoherenceProtocol)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(CoherenceProtocol)
-
-    INIT_PARAM(protocol, "name of coherence protocol"),
-    INIT_PARAM_DFLT(do_upgrades, "use upgrade transactions?", true)
-
-END_INIT_SIM_OBJECT_PARAMS(CoherenceProtocol)
-
-
-CREATE_SIM_OBJECT(CoherenceProtocol)
 {
-    return new CoherenceProtocol(getInstanceName(), protocol,
+    return new CoherenceProtocol(name, protocol, do_upgrades);
-                                 do_upgrades);
 }
-
-REGISTER_SIM_OBJECT("CoherenceProtocol", CoherenceProtocol)
-
-#endif // DOXYGEN_SHOULD_SKIP_THIS

src/mem/cache/coherence/coherence_protocol.hh

@@ -39,10 +39,11 @@
 
 #include <string>
 
-#include "sim/sim_object.hh"
-#include "mem/packet.hh"
-#include "mem/cache/cache_blk.hh"
 #include "base/statistics.hh"
+#include "enums/Coherence.hh"
+#include "mem/cache/cache_blk.hh"
+#include "mem/packet.hh"
+#include "sim/sim_object.hh"
 
 class BaseCache;
 class MSHR;
@@ -60,7 +61,7 @@ class CoherenceProtocol : public SimObject
      * @param protocol The string representation of the protocol to use.
      * @param doUpgrades True if bus upgrades should be used.
      */
-    CoherenceProtocol(const std::string &name, const std::string &protocol,
+    CoherenceProtocol(const std::string &name, Enums::Coherence protocol,
                       const bool doUpgrades);
 
     /**

src/mem/cache/tags/SConscript

@@ -40,4 +40,3 @@ Source('split_lru.cc')
 
 SimObject('Repl.py')
 Source('repl/gen.cc')
-Source('repl/repl.cc')

src/mem/cache/tags/repl/gen.cc

@@ -39,7 +39,7 @@
 #include "base/misc.hh"
 #include "mem/cache/tags/iic.hh"
 #include "mem/cache/tags/repl/gen.hh"
-#include "sim/builder.hh"
+#include "params/GenRepl.hh"
 #include "sim/host.hh"
 
 using namespace std;
@@ -247,31 +247,8 @@ GenRepl::findTagPtr(unsigned long index)
     return false;
 }
 
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
+GenRepl *
-
+GenReplParams::create()
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(GenRepl)
-
-    Param<int> num_pools;
-    Param<int> fresh_res;
-    Param<int> pool_res;
-
-END_DECLARE_SIM_OBJECT_PARAMS(GenRepl)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(GenRepl)
-
-    INIT_PARAM(num_pools, "capacity in bytes"),
-    INIT_PARAM(fresh_res, "associativity"),
-    INIT_PARAM(pool_res, "block size in bytes")
-
-END_INIT_SIM_OBJECT_PARAMS(GenRepl)
-
-
-CREATE_SIM_OBJECT(GenRepl)
 {
-    return new GenRepl(getInstanceName(), num_pools, fresh_res, pool_res);
+    return new GenRepl(name, num_pools, fresh_res, pool_res);
 }
-
-REGISTER_SIM_OBJECT("GenRepl", GenRepl)
-
-#endif // DOXYGEN_SHOULD_SKIP_THIS

src/mem/dram.cc

@@ -99,11 +99,10 @@ Kluwer Academic, pages 291-310, March, 2000.
  * Definition of a DRAM like main memory.
  */
 
+#include <cstdlib>
+#include <string>
 
 #include "mem/dram.hh"
-#include "sim/builder.hh"
-#include <stdlib.h>
-#include <string>
 
 extern int maxThreadsPerCPU;
 
@@ -174,7 +173,7 @@ extern int maxThreadsPerCPU;
 
 
 
-DRAMMemory::DRAMMemory(Params *p)
+DRAMMemory::DRAMMemory(const Params *p)
     : PhysicalMemory(p), cpu_ratio(p->cpu_ratio), bus_width(p->bus_width),
       mem_type(p->mem_type), mem_actpolicy(p->mem_actpolicy),
       memctrladdr_type(p->memctrladdr_type), act_lat(p->act_lat),
@@ -197,7 +196,7 @@ DRAMMemory::DRAMMemory(Params *p)
       memctrlpipe_enable(false), time_last_access(0)
 {
     warn("This DRAM module has not been tested with the new memory system at all!");
-        bank_size = (params()->addrRange.size() + 1) / num_banks;
+        bank_size = (p->range.size() + 1) / num_banks;
         num_rows = bank_size / SD_ROW_SIZE; /* 0x1000 size of row 4Kbtye */
         active_row = new int[num_banks];
         last_bank = num_banks+1;
@@ -2666,81 +2665,8 @@ else
 return precharge;
 }
 
-
+DRAMMemory *
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
+DRAMMemoryParams::create()
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DRAMMemory)
-
-    Param<std::string> file;
-    Param<Range<Addr> > range;
-    Param<Tick> latency;
-    /* additional params for dram protocol*/
-    Param<int> cpu_ratio;
-    Param<std::string> mem_type;
-    Param<std::string> mem_actpolicy;
-    Param<std::string> memctrladdr_type;
-    Param<int> bus_width;
-    Param<int> act_lat;
-    Param<int> cas_lat;
-    Param<int> war_lat;
-    Param<int> pre_lat;
-    Param<int> dpl_lat;
-    Param<int> trc_lat;
-    Param<int> num_banks;
-    Param<int> num_cpus;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DRAMMemory)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DRAMMemory)
-
-    INIT_PARAM_DFLT(file, "memory mapped file", ""),
-    INIT_PARAM(range, "Device Address Range"),
-    INIT_PARAM(latency, "Memory access latency"),
-
-    /* additional params for dram protocol*/
-    INIT_PARAM_DFLT(cpu_ratio,"ratio between CPU speed and memory bus speed",5),
-    INIT_PARAM_DFLT(mem_type,"type of DRAM","SDRAM"),
-    INIT_PARAM_DFLT(mem_actpolicy,"open / closed page policy","open"),
-    INIT_PARAM_DFLT(memctrladdr_type,"interleaved or direct mapping","interleaved"),
-    INIT_PARAM_DFLT(bus_width,"memory access bus width",16),
-    INIT_PARAM_DFLT(act_lat,"RAS to CAS delay",2),
-    INIT_PARAM_DFLT(cas_lat,"CAS delay",1),
-    INIT_PARAM_DFLT(war_lat,"write after read delay",2),
-    INIT_PARAM_DFLT(pre_lat,"precharge delay",2),
-    INIT_PARAM_DFLT(dpl_lat,"data in to precharge delay",2),
-    INIT_PARAM_DFLT(trc_lat,"row cycle delay",6),
-    INIT_PARAM_DFLT(num_banks,"Number of Banks",4),
-    INIT_PARAM_DFLT(num_cpus,"Number of CPUs connected to DRAM",4)
-
-END_INIT_SIM_OBJECT_PARAMS(DRAMMemory)
-
-CREATE_SIM_OBJECT(DRAMMemory)
 {
-    DRAMMemory::Params *p = new DRAMMemory::Params;
+    return new DRAMMemory(this);
-    p->name = getInstanceName();
-    p->addrRange = range;
-    p->latency = latency;
-
-    /* additional params for dram */
-    p->cpu_ratio = cpu_ratio;
-    p->bus_width = bus_width;
-    p->mem_type = mem_type;
-    p->mem_actpolicy = mem_actpolicy;
-    p->memctrladdr_type = memctrladdr_type;
-    p->act_lat = act_lat;
-    p->cas_lat = cas_lat;
-    p->war_lat = war_lat;
-    p->pre_lat = pre_lat;
-    p->dpl_lat = dpl_lat;
-    p->trc_lat = trc_lat;
-    p->num_banks = num_banks;
-    p->num_cpus = num_cpus;
-
-    return new DRAMMemory(p);
 }
-
-REGISTER_SIM_OBJECT("DRAMMemory", DRAMMemory)
-
-#endif // DOXYGEN_SHOULD_SKIP_THIS
-
-

src/mem/dram.hh

@@ -38,6 +38,7 @@
 
 #include "base/statistics.hh"
 #include "mem/physical.hh"
+#include "params/DRAMMemory.hh"
 
 class DRAMMemory : public PhysicalMemory
 {
@@ -144,28 +145,16 @@ class DRAMMemory : public PhysicalMemory
     int prechargeBanksAround(int bank);
 
   public:
-    struct Params : public PhysicalMemory::Params
+    typedef DRAMMemoryParams Params;
+    DRAMMemory(const Params *p);
+
+    const Params *
+    params() const
     {
-        /* additional params for dram protocol*/
+        return dynamic_cast<const Params *>(_params);
-        int cpu_ratio;
+    }
-        int bus_width;
 
-        std::string mem_type; /* DRDRAM, SDRAM */
-        std::string mem_actpolicy; /* closed, open */
-        std::string memctrladdr_type; /* interleaved, anythingelse */
-
-        int act_lat;
-        int cas_lat;
-        int war_lat;
-        int pre_lat;
-        int dpl_lat;
-        int trc_lat;
-        int num_banks;
-        int num_cpus;
-
-    };
     virtual void regStats();
-    DRAMMemory(Params *p);
 };
 
 #endif// __MEM_DRAM_HH__