Add in files from merge-bare-iron, get them compiling in FS and SE mode

--HG--
extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251

build_opts/MIPS_FS

@@ -0,0 +1,2 @@
+TARGET_ISA = 'mips'
+FULL_SYSTEM = 1

configs/common/FSConfig.py

@@ -52,7 +52,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
     self.iobus = Bus(bus_id=0)
     self.membus = Bus(bus_id=1)
     self.bridge = Bridge(delay='50ns', nack_delay='4ns')
-    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
+    self.physmem = PhysicalMemory(range = AddrRange('64MB'))
     self.bridge.side_a = self.iobus.port
     self.bridge.side_b = self.membus.port
     self.physmem.port = self.membus.port
@@ -118,6 +118,43 @@ def makeSparcSystem(mem_mode, mdesc = None):
 
     return self
 
+def makeLinuxMipsSystem(mem_mode, mdesc = None):
+    class BaseMalta(Malta):
+        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
+        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
+                            pci_func=0, pci_dev=0, pci_bus=0)
+
+    self = LinuxMipsSystem()
+    if not mdesc:
+        # generic system
+        mdesc = SysConfig()
+    self.readfile = mdesc.script()
+    self.iobus = Bus(bus_id=0)
+    self.membus = Bus(bus_id=1)
+    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
+    self.physmem = PhysicalMemory(range = AddrRange('1GB'))
+    self.bridge.side_a = self.iobus.port
+    self.bridge.side_b = self.membus.port
+    self.physmem.port = self.membus.port
+    self.disk0 = CowIdeDisk(driveID='master')
+    self.disk2 = CowIdeDisk(driveID='master')
+    self.disk0.childImage(mdesc.disk())
+    self.disk2.childImage(disk('linux-bigswap2.img'))
+    self.malta = BaseMalta()
+    self.malta.attachIO(self.iobus)
+    self.malta.ide.pio = self.iobus.port
+    self.malta.ethernet.pio = self.iobus.port
+    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
+                                               read_only = True))
+    self.intrctrl = IntrControl()
+    self.mem_mode = mem_mode
+    self.sim_console = SimConsole()
+    self.kernel = binary('mips/vmlinux')
+    self.console = binary('mips/console')
+    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
+
+    return self
+
 def makeX86System(mem_mode, mdesc = None):
     self = X86System()
     if not mdesc:

configs/example/fs.py

@@ -97,6 +97,8 @@ else:
 
 if m5.build_env['TARGET_ISA'] == "alpha":
     test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
+elif m5.build_env['TARGET_ISA'] == "mips":
+    test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
 elif m5.build_env['TARGET_ISA'] == "sparc":
     test_sys = makeSparcSystem(test_mem_mode, bm[0])
 elif m5.build_env['TARGET_ISA'] == "x86":
@@ -140,9 +142,81 @@ for i in xrange(np):
     if options.fastmem:
         test_sys.cpu[i].physmem_port = test_sys.physmem.port
 
+if m5.build_env['TARGET_ISA'] == 'mips':
+        #CP0 Configuration
+        TestCPUClass.CP0_PRId_CompanyOptions = 0
+        TestCPUClass.CP0_PRId_CompanyID = 1
+        TestCPUClass.CP0_PRId_ProcessorID = 147
+        TestCPUClass.CP0_PRId_Revision = 0
+
+        #CP0 Interrupt Control
+        TestCPUClass.CP0_IntCtl_IPTI = 7
+        TestCPUClass.CP0_IntCtl_IPPCI = 7
+
+        # Config Register
+        #TestCPUClass.CP0_Config_K23 = 0 # Since TLB
+        #TestCPUClass.CP0_Config_KU = 0 # Since TLB
+        TestCPUClass.CP0_Config_BE = 0 # Little Endian
+        TestCPUClass.CP0_Config_AR = 1 # Architecture Revision 2
+        TestCPUClass.CP0_Config_AT = 0 # MIPS32
+        TestCPUClass.CP0_Config_MT = 1 # TLB MMU
+        #TestCPUClass.CP0_Config_K0 = 2 # Uncached
+
+        #Config 1 Register
+        TestCPUClass.CP0_Config1_M = 1 # Config2 Implemented
+        TestCPUClass.CP0_Config1_MMU = 63 # TLB Size
+        # ***VERY IMPORTANT***
+        # Remember to modify CP0_Config1 according to cache specs
+        # Examine file ../common/Cache.py
+        TestCPUClass.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
+        TestCPUClass.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
+        TestCPUClass.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
+        TestCPUClass.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
+        TestCPUClass.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
+        TestCPUClass.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
+        TestCPUClass.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
+        TestCPUClass.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
+        TestCPUClass.CP0_Config1_PC = 1 # Performance Counters Implemented
+        TestCPUClass.CP0_Config1_WR = 0 # Watch Registers Implemented
+        TestCPUClass.CP0_Config1_CA = 0 # Mips16e NOT implemented
+        TestCPUClass.CP0_Config1_EP = 0 # EJTag Not Implemented
+        TestCPUClass.CP0_Config1_FP = 0 # FPU Implemented
+
+        #Config 2 Register
+        TestCPUClass.CP0_Config2_M = 1 # Config3 Implemented
+        TestCPUClass.CP0_Config2_TU = 0 # Tertiary Cache Control
+        TestCPUClass.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
+        TestCPUClass.CP0_Config2_TL = 0 # Tertiary Cache Line Size
+        TestCPUClass.CP0_Config2_TA = 0 # Tertiary Cache Associativity
+        TestCPUClass.CP0_Config2_SU = 0 # Secondary Cache Control
+        TestCPUClass.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
+        TestCPUClass.CP0_Config2_SL = 0 # Secondary Cache Line Size
+        TestCPUClass.CP0_Config2_SA = 0 # Secondary Cache Associativity
+
+
+        #Config 3 Register
+        TestCPUClass.CP0_Config3_M = 0 # Config4 Not Implemented
+        TestCPUClass.CP0_Config3_DSPP = 1 # DSP ASE Present
+        TestCPUClass.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
+        TestCPUClass.CP0_Config3_VEIC = 0 # EIC Supported
+        TestCPUClass.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
+        TestCPUClass.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
+        TestCPUClass.CP0_Config3_MT = 0 # MT Not present
+        TestCPUClass.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
+        TestCPUClass.CP0_Config3_TL = 0 # TraceLogic Not implemented
+
+        #SRS Ctl - HSS
+        TestCPUClass.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
+
+
+        #TestCPUClass.tlb = TLB()
+        #TestCPUClass.UnifiedTLB = 1
+
 if len(bm) == 2:
     if m5.build_env['TARGET_ISA'] == 'alpha':
         drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
+    elif m5.build_env['TARGET_ISA'] == 'mips':
+        drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
     elif m5.build_env['TARGET_ISA'] == 'sparc':
         drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
     elif m5.build.env['TARGET_ISA'] == 'x86':

src/arch/alpha/regfile.hh

@@ -177,6 +177,9 @@ namespace AlphaISA
             intRegFile.setReg(intReg, val);
         }
 
+        void setShadowSet(int css)
+        { }
+
         void serialize(std::ostream &os);
         void unserialize(Checkpoint *cp, const std::string &section);
 

src/arch/isa_parser.py

@@ -1414,6 +1414,43 @@ class ControlRegOperand(Operand):
               self.base_name
         return wb
 
+class IControlRegOperand(Operand):
+    def isReg(self):
+        return 1
+
+    def isIControlReg(self):
+        return 1
+
+    def makeConstructor(self):
+        c = ''
+        if self.is_src:
+            c += '\n\t_srcRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \
+                 (self.src_reg_idx, self.reg_spec)
+        if self.is_dest:
+            c += '\n\t_destRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \
+                 (self.dest_reg_idx, self.reg_spec)
+        return c
+
+    def makeRead(self):
+        bit_select = 0
+        if (self.ctype == 'float' or self.ctype == 'double'):
+            error(0, 'Attempt to read control register as FP')
+        base = 'xc->readMiscReg(%s)' % self.reg_spec
+        if self.size == self.dflt_size:
+            return '%s = %s;\n' % (self.base_name, base)
+        else:
+            return '%s = bits(%s, %d, 0);\n' % \
+                   (self.base_name, base, self.size-1)
+
+    def makeWrite(self):
+        if (self.ctype == 'float' or self.ctype == 'double'):
+            error(0, 'Attempt to write control register as FP')
+        wb = 'xc->setMiscReg(%s, %s);\n' % \
+             (self.reg_spec, self.base_name)
+        wb += 'if (traceData) { traceData->setData(%s); }' % \
+              self.base_name
+        return wb
+
 class ControlBitfieldOperand(ControlRegOperand):
     def makeRead(self):
         bit_select = 0

src/arch/mips/BISystem.py

@@ -0,0 +1,47 @@
+# -*- mode:python -*-
+
+# Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
+#
+# This software is part of the M5 simulator.
+#
+# THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
+# DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+# TO THESE TERMS AND CONDITIONS.
+#
+# Permission is granted to use, copy, create derivative works and
+# distribute this software and such derivative works for any purpose,
+# so long as (1) the copyright notice above, this grant of permission,
+# and the disclaimer below appear in all copies and derivative works
+# made, (2) the copyright notice above is augmented as appropriate to
+# reflect the addition of any new copyrightable work in a derivative
+# work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+# the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+# advertising or publicity pertaining to the use or distribution of
+# this software without specific, written prior authorization.
+#
+# THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
+# DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+# OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+# NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+# IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+# INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+# ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+# THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+# IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+# STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+# POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+#
+# Authors: Jaidev Patwardhan
+#
+
+from m5 import build_env
+from System import *
+
+if build_env['FULL_SYSTEM']:
+    class BareIronMipsSystem(MipsSystem):
+        type = 'BareIronMipsSystem'
+        system_type = 34
+        system_rev = 1 << 10
+        hex_file_name = Param.String('test.hex',"hex file that contains [address,data] pairs")
+

src/arch/mips/MipsCPU.py

@@ -0,0 +1,91 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2007 MIPS Technologies, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jaidev Patwardhan
+#          Korey Sewell
+
+from m5.SimObject import SimObject
+from m5.params import *
+from BaseCPU import BaseCPU
+
+class BaseMipsCPU(BaseCPU)
+    if build_env['TARGET_ISA'] == 'mips':
+        CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description")
+        CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description")
+        CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description")
+        CP0_EBase_CPUNum = Param.Unsigned(0,"No Description")
+        CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register")
+        CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register")
+        CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company")
+        CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register")
+        CP0_Config_BE = Param.Unsigned(0,"Big Endian?")
+        CP0_Config_AT = Param.Unsigned(0,"No Description")
+        CP0_Config_AR = Param.Unsigned(0,"No Description")
+        CP0_Config_MT = Param.Unsigned(0,"No Description")
+        CP0_Config_VI = Param.Unsigned(0,"No Description")
+        CP0_Config1_M = Param.Unsigned(0,"Config2 Implemented?")
+        CP0_Config1_MMU = Param.Unsigned(0,"MMU Type")
+        CP0_Config1_IS = Param.Unsigned(0,"No Description")
+        CP0_Config1_IL = Param.Unsigned(0,"No Description")
+        CP0_Config1_IA = Param.Unsigned(0,"No Description")
+        CP0_Config1_DS = Param.Unsigned(0,"No Description")
+        CP0_Config1_DL = Param.Unsigned(0,"No Description")
+        CP0_Config1_DA = Param.Unsigned(0,"No Description")
+        CP0_Config1_C2 = Param.Bool(False,"No Description")
+        CP0_Config1_MD = Param.Bool(False,"No Description")
+        CP0_Config1_PC = Param.Bool(False,"No Description")
+        CP0_Config1_WR = Param.Bool(False,"No Description")
+        CP0_Config1_CA = Param.Bool(False,"No Description")
+        CP0_Config1_EP = Param.Bool(False,"No Description")
+        CP0_Config1_FP = Param.Bool(False,"FPU Implemented?")
+        CP0_Config2_M = Param.Bool(False,"Config3 Implemented?")
+        CP0_Config2_TU = Param.Unsigned(0,"No Description")
+        CP0_Config2_TS = Param.Unsigned(0,"No Description")
+        CP0_Config2_TL = Param.Unsigned(0,"No Description")
+        CP0_Config2_TA = Param.Unsigned(0,"No Description")
+        CP0_Config2_SU = Param.Unsigned(0,"No Description")
+        CP0_Config2_SS = Param.Unsigned(0,"No Description")
+        CP0_Config2_SL = Param.Unsigned(0,"No Description")
+        CP0_Config2_SA = Param.Unsigned(0,"No Description")
+        CP0_Config3_M = Param.Bool(False,"Config4 Implemented?")
+        CP0_Config3_DSPP = Param.Bool(False,"DSP Extensions Present?")
+        CP0_Config3_LPA = Param.Bool(False,"No Description")
+        CP0_Config3_VEIC = Param.Bool(False,"No Description")
+        CP0_Config3_VInt = Param.Bool(False,"No Description")
+        CP0_Config3_SP = Param.Bool(False,"No Description")
+        CP0_Config3_MT = Param.Bool(False,"Multithreading Extensions Present?")
+        CP0_Config3_SM = Param.Bool(False,"No Description")
+        CP0_Config3_TL = Param.Bool(False,"No Description")
+        CP0_WatchHi_M = Param.Bool(False,"No Description")
+        CP0_PerfCtr_M = Param.Bool(False,"No Description")
+        CP0_PerfCtr_W = Param.Bool(False,"No Description")
+        CP0_PRId = Param.Unsigned(0,"CP0 Status Register")
+        CP0_Config = Param.Unsigned(0,"CP0 Config Register")
+        CP0_Config1 = Param.Unsigned(0,"CP0 Config1 Register")
+        CP0_Config2 = Param.Unsigned(0,"CP0 Config2 Register")
+        CP0_Config3 = Param.Unsigned(0,"CP0 Config3 Register")

src/arch/mips/MipsSystem.py

@@ -0,0 +1,57 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2007 MIPS Technologies, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jaidev Patwardhan
+
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
+from m5 import build_env
+from System import System
+
+class MipsSystem(System):
+    type = 'MipsSystem'
+    console = Param.String("file that contains the console code")
+    bare_iron = Param.Bool(False, "Using Bare Iron Mode?")
+    hex_file_name = Param.String("test.hex","hex file that contains [address,data] pairs")
+    system_type = Param.UInt64("Type of system we are emulating")
+    system_rev = Param.UInt64("Revision of system we are emulating")
+
+if build_env['FULL_SYSTEM']:
+    class LinuxMipsSystem(MipsSystem):
+        type = 'LinuxMipsSystem'
+        system_type = 34
+        system_rev = 1 << 10
+
+    class BareIronMipsSystem(MipsSystem):
+        type = 'BareIronMipsSystem'
+        bare_iron = True
+        system_type = 34
+        system_rev = 1 << 10
+        hex_file_name = Param.String('test.hex',"hex file that contains [address,data] pairs")
+

src/arch/mips/MipsTLB.py

@@ -1,20 +1,57 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2007 MIPS Technologies, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jaidev Patwardhan
+
 from m5.SimObject import SimObject
 from m5.params import *
+
 class MipsTLB(SimObject):
-    type = 'MipsTLB'
     abstract = True
-    #size = Param.Int("TLB size")
+    type = 'MipsTLB'
+    cxx_namespace = 'MipsISA'
+    cxx_class = 'TLB'
+    size = Param.Int("TLB size")
 
 class MipsDTB(MipsTLB):
-    type = 'MipsDTB'
+    type = 'DTB'
     cxx_namespace = 'MipsISA'
     cxx_class = 'DTB'
-
+    size = 64
-    #size = 64
 
 class MipsITB(MipsTLB):
-    type = 'MipsITB'
+    type = 'ITB'
     cxx_namespace = 'MipsISA'
     cxx_class = 'ITB'
+    size = 64
 
-    #size = 64
+class MipsUTB(MipsTLB):
+    type = 'UTB'
+    cxx_namespace = 'MipsISA'
+    cxx_class = 'UTB'
+    size = 64

src/arch/mips/SConscript

@@ -1,6 +1,6 @@
 # -*- mode:python -*-
 
-# Copyright (c) 2004-2005 The Regents of The University of Michigan
+# Copyright (c) 2007 MIPS Technologies, Inc.
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -33,24 +33,31 @@
 Import('*')
 
 if env['TARGET_ISA'] == 'mips':
-    Source('dsp.cc')
     Source('faults.cc')
     Source('regfile/int_regfile.cc')
+    Source('regfile/float_regfile.cc')
     Source('regfile/misc_regfile.cc')
     Source('regfile/regfile.cc')
     Source('tlb.cc')
+    Source('pagetable.cc')
     Source('utility.cc')
+    Source('dsp.cc')
 
     SimObject('MipsTLB.py')
-
     TraceFlag('MipsPRA')
 
     if env['FULL_SYSTEM']:
-        #Insert Full-System Files Here
+	SimObject('MipsSystem.py')
-        pass
+        Source('idle_event.cc')
+        Source('mips_core_specific.cc')
+        Source('vtophys.cc')
+        Source('system.cc')
+        Source('stacktrace.cc')
+        Source('linux/system.cc')
+	Source('interrupts.cc')
+        Source('bare_iron/system.cc')
     else:
         Source('process.cc')
-
         Source('linux/linux.cc')
         Source('linux/process.cc')
 

src/arch/mips/SConsopts

@@ -1,6 +1,4 @@
-# -*- mode:python -*-
+# Copyright (c) 2007 MIPS Technologies, Inc.
-
-# Copyright (c) 2006 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -26,7 +24,7 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Nathan Binkert
+# Authors: Jaidev Patwardhan
 
 Import('*')
 

src/arch/mips/bare_iron/system.cc

@@ -0,0 +1,65 @@
+/*
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ *
+ * This software is part of the M5 simulator.
+ *
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+ * TO THESE TERMS AND CONDITIONS.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Jaidev Patwardhan
+ *
+ */
+
+#include "arch/vtophys.hh"
+#include "arch/mips/bare_iron/system.hh"
+#include "arch/mips/system.hh"
+#include "cpu/thread_context.hh"
+#include "cpu/base.hh"
+#include "dev/platform.hh"
+#include "mem/physical.hh"
+#include "mem/port.hh"
+#include "params/BareIronMipsSystem.hh"
+#include "sim/byteswap.hh"
+
+using namespace std;
+using namespace MipsISA;
+
+
+BareIronMipsSystem::BareIronMipsSystem(Params *p)
+    : MipsSystem(p)
+{ }
+
+BareIronMipsSystem::~BareIronMipsSystem()
+{ }
+
+BareIronMipsSystem *
+BareIronMipsSystemParams::create()
+{
+    return new BareIronMipsSystem(this);
+}
+

src/arch/mips/bare_iron/system.hh

@@ -0,0 +1,71 @@
+/*
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ *
+ * This software is part of the M5 simulator.
+ *
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+ * TO THESE TERMS AND CONDITIONS.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Jaidev Patwardhan
+ *
+ */
+
+#ifndef __ARCH_MIPS_BARE_IRON_SYSTEM_HH__
+#define __ARCH_MIPS_BARE_IRON_SYSTEM_HH__
+
+class ThreadContext;
+
+class BreakPCEvent;
+class IdleStartEvent;
+
+#include "arch/mips/system.hh"
+#include "params/BareIronMipsSystem.hh"
+
+using namespace MipsISA;
+
+/**
+ * This class contains linux specific system code (Loading, Events).
+ * It points to objects that are the system binaries to load and patches them
+ * appropriately to work in simulator.
+ */
+class BareIronMipsSystem : public MipsSystem
+{
+  private:
+
+
+  public:
+    static const int CommandLineSize = 256;
+
+  private:
+
+  public:
+    BareIronMipsSystem(Params *p);
+    ~BareIronMipsSystem();
+};
+
+#endif // __ARCH_MIPS_BARE_IRON_SYSTEM_HH__

src/arch/mips/constants.hh

@@ -32,7 +32,6 @@
 #define __ARCH_MIPS_CONSTANTS_HH__
 
 #include "arch/mips/types.hh"
-//#include "config/full_system.hh"
 
 namespace MipsISA
 {

src/arch/mips/dsp.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -30,7 +30,6 @@
 
 #include "arch/mips/isa_traits.hh"
 #include "arch/mips/dsp.hh"
-#include "arch/mips/constants.hh"
 #include "config/full_system.hh"
 #include "cpu/static_inst.hh"
 #include "sim/serialize.hh"

src/arch/mips/dsp.hh

@@ -1,31 +1,38 @@
 /*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
+ * This software is part of the M5 simulator.
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * TO THESE TERMS AND CONDITIONS.
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * Permission is granted to use, copy, create derivative works and
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * distribute this software and such derivative works for any purpose,
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * so long as (1) the copyright notice above, this grant of permission,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * and the disclaimer below appear in all copies and derivative works
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * made, (2) the copyright notice above is augmented as appropriate to
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * reflect the addition of any new copyrightable work in a derivative
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
  *
  * Authors: Brett Miller
+ *
  */
 
 #ifndef __ARCH_MIPS_DSP_HH__

src/arch/mips/dt_constants.hh

@@ -1,38 +1,44 @@
 /*
- * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
+ * This software is part of the M5 simulator.
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * TO THESE TERMS AND CONDITIONS.
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * Permission is granted to use, copy, create derivative works and
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * distribute this software and such derivative works for any purpose,
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * so long as (1) the copyright notice above, this grant of permission,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * and the disclaimer below appear in all copies and derivative works
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * made, (2) the copyright notice above is augmented as appropriate to
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * reflect the addition of any new copyrightable work in a derivative
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
  *
  * Authors: Jaidev Patwardhan
+ *
  */
 
 #ifndef __ARCH_MIPS_DT_CONSTANTS_HH__
 #define __ARCH_MIPS_DT_CONSTANTS_HH__
 
 #include "arch/mips/types.hh"
-//#include "config/full_system.hh"
 
 namespace MipsISA
 {

src/arch/mips/faults.cc

@@ -1,39 +1,46 @@
 /*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
+ * This software is part of the M5 simulator.
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * TO THESE TERMS AND CONDITIONS.
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Gabe Black
+ * Permission is granted to use, copy, create derivative works and
- *          Korey Sewell
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Gabe M. Black
+ *          Korey L. Sewell
+ *          Jaidev Patwardhan
  */
 
 #include "arch/mips/faults.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/base.hh"
 #include "base/trace.hh"
-
+#include "arch/mips/pra_constants.hh"
 #if !FULL_SYSTEM
 #include "sim/process.hh"
 #include "mem/page_table.hh"
@@ -51,15 +58,32 @@ FaultVect AlignmentFault::_vect = 0x0301;
 FaultStat AlignmentFault::_count;
 
 FaultName ResetFault::_name = "reset";
-FaultVect ResetFault::_vect = 0x0001;
+#if  FULL_SYSTEM
+FaultVect ResetFault::_vect = 0xBFC00000;
+#else
+FaultVect ResetFault::_vect = 0x001;
+#endif
 FaultStat ResetFault::_count;
 
+FaultName AddressErrorFault::_name = "Address Error";
+FaultVect AddressErrorFault::_vect = 0x0180;
+FaultStat AddressErrorFault::_count;
+
+FaultName StoreAddressErrorFault::_name = "Store Address Error";
+FaultVect StoreAddressErrorFault::_vect = 0x0180;
+FaultStat StoreAddressErrorFault::_count;
+
+
+FaultName SystemCallFault::_name = "Syscall";
+FaultVect SystemCallFault::_vect = 0x0180;
+FaultStat SystemCallFault::_count;
+
 FaultName CoprocessorUnusableFault::_name = "Coprocessor Unusable";
-FaultVect CoprocessorUnusableFault::_vect = 0xF001;
+FaultVect CoprocessorUnusableFault::_vect = 0x180;
 FaultStat CoprocessorUnusableFault::_count;
 
 FaultName ReservedInstructionFault::_name = "Reserved Instruction";
-FaultVect ReservedInstructionFault::_vect = 0x0F01;
+FaultVect ReservedInstructionFault::_vect = 0x0180;
 FaultStat ReservedInstructionFault::_count;
 
 FaultName ThreadFault::_name = "thread";
@@ -67,8 +91,8 @@ FaultVect ThreadFault::_vect = 0x00F1;
 FaultStat ThreadFault::_count;
 
 
-FaultName ArithmeticFault::_name = "arith";
+FaultName ArithmeticFault::_name = "Arithmetic Overflow Exception";
-FaultVect ArithmeticFault::_vect = 0x0501;
+FaultVect ArithmeticFault::_vect = 0x180;
 FaultStat ArithmeticFault::_count;
 
 FaultName UnimplementedOpcodeFault::_name = "opdec";
@@ -76,9 +100,38 @@ FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
 FaultStat UnimplementedOpcodeFault::_count;
 
 FaultName InterruptFault::_name = "interrupt";
-FaultVect InterruptFault::_vect = 0x0101;
+FaultVect InterruptFault::_vect = 0x0180;
 FaultStat InterruptFault::_count;
 
+FaultName TrapFault::_name = "Trap";
+FaultVect TrapFault::_vect = 0x0180;
+FaultStat TrapFault::_count;
+
+FaultName BreakpointFault::_name = "Breakpoint";
+FaultVect BreakpointFault::_vect = 0x0180;
+FaultStat BreakpointFault::_count;
+
+
+FaultName ItbInvalidFault::_name = "Invalid TLB Entry Exception (I-Fetch/LW)";
+FaultVect ItbInvalidFault::_vect = 0x0180;
+FaultStat ItbInvalidFault::_count;
+
+FaultName ItbPageFault::_name = "itbmiss";
+FaultVect ItbPageFault::_vect = 0x0181;
+FaultStat ItbPageFault::_count;
+
+FaultName ItbMissFault::_name = "itbmiss";
+FaultVect ItbMissFault::_vect = 0x0181;
+FaultStat ItbMissFault::_count;
+
+FaultName ItbAcvFault::_name = "iaccvio";
+FaultVect ItbAcvFault::_vect = 0x0081;
+FaultStat ItbAcvFault::_count;
+
+FaultName ItbRefillFault::_name = "TLB Refill Exception (I-Fetch/LW)";
+FaultVect ItbRefillFault::_vect = 0x0180;
+FaultStat ItbRefillFault::_count;
+
 FaultName NDtbMissFault::_name = "dtb_miss_single";
 FaultVect NDtbMissFault::_vect = 0x0201;
 FaultStat NDtbMissFault::_count;
@@ -95,54 +148,369 @@ FaultName DtbAcvFault::_name = "dfault";
 FaultVect DtbAcvFault::_vect = 0x0381;
 FaultStat DtbAcvFault::_count;
 
-FaultName ItbMissFault::_name = "itbmiss";
+FaultName DtbInvalidFault::_name = "Invalid TLB Entry Exception (Store)";
-FaultVect ItbMissFault::_vect = 0x0181;
+FaultVect DtbInvalidFault::_vect = 0x0180;
-FaultStat ItbMissFault::_count;
+FaultStat DtbInvalidFault::_count;
 
-FaultName ItbPageFault::_name = "itbmiss";
+FaultName DtbRefillFault::_name = "TLB Refill Exception (Store)";
-FaultVect ItbPageFault::_vect = 0x0181;
+FaultVect DtbRefillFault::_vect = 0x0180;
-FaultStat ItbPageFault::_count;
+FaultStat DtbRefillFault::_count;
 
-FaultName ItbAcvFault::_name = "iaccvio";
+FaultName TLBModifiedFault::_name = "TLB Modified Exception";
-FaultVect ItbAcvFault::_vect = 0x0081;
+FaultVect TLBModifiedFault::_vect = 0x0180;
-FaultStat ItbAcvFault::_count;
+FaultStat TLBModifiedFault::_count;
 
-FaultName FloatEnableFault::_name = "fen";
+FaultName FloatEnableFault::_name = "float_enable_fault";
 FaultVect FloatEnableFault::_vect = 0x0581;
 FaultStat FloatEnableFault::_count;
 
-FaultName IntegerOverflowFault::_name = "intover";
+FaultName IntegerOverflowFault::_name = "Integer Overflow Fault";
 FaultVect IntegerOverflowFault::_vect = 0x0501;
 FaultStat IntegerOverflowFault::_count;
 
-FaultName DspStateDisabledFault::_name = "intover";
+FaultName DspStateDisabledFault::_name = "DSP Disabled Fault";
 FaultVect DspStateDisabledFault::_vect = 0x001a;
 FaultStat DspStateDisabledFault::_count;
 
-void ResetFault::invoke(ThreadContext *tc)
+#if FULL_SYSTEM
+void MipsFault::setHandlerPC(Addr HandlerBase, ThreadContext *tc)
 {
-    warn("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name());
+  tc->setPC(HandlerBase);
-    //tc->getCpuPtr()->reset();
+  tc->setNextPC(HandlerBase+sizeof(MachInst));
+  tc->setNextNPC(HandlerBase+2*sizeof(MachInst));
 }
 
-void CoprocessorUnusableFault::invoke(ThreadContext *tc)
+void MipsFault::setExceptionState(ThreadContext *tc,uint8_t ExcCode)
 {
-    panic("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name());
+  // modify SRS Ctl - Save CSS, put ESS into CSS
+  MiscReg stat = tc->readMiscReg(MipsISA::Status);
+  if(bits(stat,Status_EXL) != 1 && bits(stat,Status_BEV) != 1)
+    {
+      // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
+      MiscReg srs = tc->readMiscReg(MipsISA::SRSCtl);
+      uint8_t CSS,ESS;
+      CSS = bits(srs,SRSCtl_CSS_HI,SRSCtl_CSS_LO);
+      ESS = bits(srs,SRSCtl_ESS_HI,SRSCtl_ESS_LO);
+      // Move CSS to PSS
+      replaceBits(srs,SRSCtl_PSS_HI,SRSCtl_PSS_LO,CSS);
+      // Move ESS to CSS
+      replaceBits(srs,SRSCtl_CSS_HI,SRSCtl_CSS_LO,ESS);
+      tc->setMiscRegNoEffect(MipsISA::SRSCtl,srs);
+      tc->setShadowSet(ESS);
+    }
+
+  // set EXL bit (don't care if it is already set!)
+  replaceBits(stat,Status_EXL_HI,Status_EXL_LO,1);
+  tc->setMiscRegNoEffect(MipsISA::Status,stat);
+
+  // write EPC
+  //  warn("Set EPC to %x\n",tc->readPC());
+  // CHECK ME  or FIXME or FIX ME or POSSIBLE HACK
+  // Check to see if the exception occurred in the branch delay slot
+  DPRINTF(MipsPRA,"PC: %x, NextPC: %x, NNPC: %x\n",tc->readPC(),tc->readNextPC(),tc->readNextNPC());
+  int C_BD=0;
+  if(tc->readPC() + sizeof(MachInst) != tc->readNextPC()){
+    tc->setMiscRegNoEffect(MipsISA::EPC,tc->readPC()-sizeof(MachInst));
+    // In the branch delay slot? set CAUSE_31
+    C_BD = 1;
+  } else {
+    tc->setMiscRegNoEffect(MipsISA::EPC,tc->readPC());
+    // In the branch delay slot? reset CAUSE_31
+    C_BD = 0;
+  }
+
+  // Set Cause_EXCCODE field
+  MiscReg cause = tc->readMiscReg(MipsISA::Cause);
+  replaceBits(cause,Cause_EXCCODE_HI,Cause_EXCCODE_LO,ExcCode);
+  replaceBits(cause,Cause_BD_HI,Cause_BD_LO,C_BD);
+  replaceBits(cause,Cause_CE_HI,Cause_CE_LO,0);
+  tc->setMiscRegNoEffect(MipsISA::Cause,cause);
+
+}
+
+void ArithmeticFault::invoke(ThreadContext *tc)
+{
+  DPRINTF(MipsPRA,"%s encountered.\n", name());
+  setExceptionState(tc,0xC);
+
+  // Set new PC
+  Addr HandlerBase;
+  MiscReg stat = tc->readMiscReg(MipsISA::Status);
+  // Here, the handler is dependent on BEV, which is not modified by setExceptionState()
+  if(bits(stat,Status_BEV)==0){ // See MIPS ARM Vol 3, Revision 2, Page 38
+    HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase);
+  }else{
+    HandlerBase = 0xBFC00200;
+  }
+  setHandlerPC(HandlerBase,tc);
+  //      warn("Exception Handler At: %x \n",HandlerBase);
+}
+
+void StoreAddressErrorFault::invoke(ThreadContext *tc)
+{
+  DPRINTF(MipsPRA,"%s encountered.\n", name());
+  setExceptionState(tc,0x5);
+  tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr);
+
+  // Set new PC
+  Addr HandlerBase;
+  HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
+  setHandlerPC(HandlerBase,tc);
+  //      warn("Exception Handler At: %x \n",HandlerBase);
+  //      warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC));
+
+}
+
+void TrapFault::invoke(ThreadContext *tc)
+{
+  DPRINTF(MipsPRA,"%s encountered.\n", name());
+  //  warn("%s encountered.\n", name());
+  setExceptionState(tc,0xD);
+
+  // Set new PC
+  Addr HandlerBase;
+  HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
+  setHandlerPC(HandlerBase,tc);
+  //      warn("Exception Handler At: %x \n",HandlerBase);
+  //      warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC));
+}
+
+void BreakpointFault::invoke(ThreadContext *tc)
+{
+      setExceptionState(tc,0x9);
+
+      // Set new PC
+      Addr HandlerBase;
+      HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
+      setHandlerPC(HandlerBase,tc);
+      //      warn("Exception Handler At: %x \n",HandlerBase);
+      //      warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC));
+
+}
+
+void DtbInvalidFault::invoke(ThreadContext *tc)
+{
+  DPRINTF(MipsPRA,"%s encountered.\n", name());
+  //    warn("%s encountered.\n", name());
+  tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr);
+  MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
+  replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
+  replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
+  replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
+  tc->setMiscRegNoEffect(MipsISA::EntryHi,eh);
+  MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
+  replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
+  tc->setMiscRegNoEffect(MipsISA::Context,ctxt);
+  setExceptionState(tc,0x3);
+
+
+  // Set new PC
+  Addr HandlerBase;
+  HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
+  setHandlerPC(HandlerBase,tc);
+  //      warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC));
+}
+
+void AddressErrorFault::invoke(ThreadContext *tc)
+{
+  DPRINTF(MipsPRA,"%s encountered.\n", name());
+      setExceptionState(tc,0x4);
+      tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr);
+
+      // Set new PC
+      Addr HandlerBase;
+      HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
+      setHandlerPC(HandlerBase,tc);
+}
+
+void ItbInvalidFault::invoke(ThreadContext *tc)
+{
+  DPRINTF(MipsPRA,"%s encountered.\n", name());
+      setExceptionState(tc,0x2);
+      tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr);
+      MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
+      replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
+      replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
+      replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
+      tc->setMiscRegNoEffect(MipsISA::EntryHi,eh);
+      MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
+      replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
+      tc->setMiscRegNoEffect(MipsISA::Context,ctxt);
+
+
+      // Set new PC
+      Addr HandlerBase;
+      HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
+      setHandlerPC(HandlerBase,tc);
+      DPRINTF(MipsPRA,"Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC));
+}
+
+void ItbRefillFault::invoke(ThreadContext *tc)
+{
+  DPRINTF(MipsPRA,"%s encountered (%x).\n", name(),BadVAddr);
+  Addr HandlerBase;
+  tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr);
+  MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
+  replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
+  replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
+  replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
+  tc->setMiscRegNoEffect(MipsISA::EntryHi,eh);
+  MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
+  replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
+  tc->setMiscRegNoEffect(MipsISA::Context,ctxt);
+
+  MiscReg stat = tc->readMiscReg(MipsISA::Status);
+  // Since handler depends on EXL bit, must check EXL bit before setting it!!
+  if(bits(stat,Status_EXL)==1){ // See MIPS ARM Vol 3, Revision 2, Page 38
+    HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
+  }else{
+    HandlerBase = tc->readMiscReg(MipsISA::EBase); // Offset 0x000
+  }
+
+  setExceptionState(tc,0x2);
+  setHandlerPC(HandlerBase,tc);
+}
+
+void DtbRefillFault::invoke(ThreadContext *tc)
+{
+  // Set new PC
+  DPRINTF(MipsPRA,"%s encountered.\n", name());
+  Addr HandlerBase;
+  tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr);
+  MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
+  replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
+  replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
+  replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
+  tc->setMiscRegNoEffect(MipsISA::EntryHi,eh);
+  MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
+  replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
+  tc->setMiscRegNoEffect(MipsISA::Context,ctxt);
+
+  MiscReg stat = tc->readMiscReg(MipsISA::Status);
+  // Since handler depends on EXL bit, must check EXL bit before setting it!!
+  if(bits(stat,Status_EXL)==1){ // See MIPS ARM Vol 3, Revision 2, Page 38
+    HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
+  }else{
+    HandlerBase = tc->readMiscReg(MipsISA::EBase); // Offset 0x000
+  }
+
+
+  setExceptionState(tc,0x3);
+
+  setHandlerPC(HandlerBase,tc);
+}
+
+void TLBModifiedFault::invoke(ThreadContext *tc)
+{
+  DPRINTF(MipsPRA,"%s encountered.\n", name());
+  tc->setMiscRegNoEffect(MipsISA::BadVAddr,BadVAddr);
+  MiscReg eh = tc->readMiscReg(MipsISA::EntryHi);
+  replaceBits(eh,EntryHi_ASID_HI,EntryHi_ASID_LO,EntryHi_Asid);
+  replaceBits(eh,EntryHi_VPN2_HI,EntryHi_VPN2_LO,EntryHi_VPN2);
+  replaceBits(eh,EntryHi_VPN2X_HI,EntryHi_VPN2X_LO,EntryHi_VPN2X);
+  tc->setMiscRegNoEffect(MipsISA::EntryHi,eh);
+  MiscReg ctxt = tc->readMiscReg(MipsISA::Context);
+  replaceBits(ctxt,Context_BadVPN2_HI,Context_BadVPN2_LO,Context_BadVPN2);
+  tc->setMiscRegNoEffect(MipsISA::Context,ctxt);
+
+    // Set new PC
+      Addr HandlerBase;
+      HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
+      setExceptionState(tc,0x1);
+      setHandlerPC(HandlerBase,tc);
+      //      warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC));
+
+}
+
+void SystemCallFault::invoke(ThreadContext *tc)
+{
+  DPRINTF(MipsPRA,"%s encountered.\n", name());
+      setExceptionState(tc,0x8);
+
+      // Set new PC
+      Addr HandlerBase;
+      HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
+      setHandlerPC(HandlerBase,tc);
+      //      warn("Exception Handler At: %x \n",HandlerBase);
+      //      warn("Exception Handler At: %x , EPC set to %x\n",HandlerBase,tc->readMiscReg(MipsISA::EPC));
+
+}
+
+void InterruptFault::invoke(ThreadContext *tc)
+{
+#if  FULL_SYSTEM
+  DPRINTF(MipsPRA,"%s encountered.\n", name());
+  //RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil
+  setExceptionState(tc,0x0A);
+  Addr HandlerBase;
+
+
+  uint8_t IV = bits(tc->readMiscRegNoEffect(MipsISA::Cause),Cause_IV);
+  if (IV)// Offset 200 for release 2
+      HandlerBase= 0x20 + vect() + tc->readMiscRegNoEffect(MipsISA::EBase);
+  else//Ofset at 180 for release 1
+      HandlerBase= vect() + tc->readMiscRegNoEffect(MipsISA::EBase);
+
+  setHandlerPC(HandlerBase,tc);
+#endif
+}
+
+#endif // FULL_SYSTEM
+
+void ResetFault::invoke(ThreadContext *tc)
+{
+  DPRINTF(MipsPRA,"%s encountered.\n", name());
+  /* All reset activity must be invoked from here */
+  tc->setPC(vect());
+  tc->setNextPC(vect()+sizeof(MachInst));
+  tc->setNextNPC(vect()+sizeof(MachInst)+sizeof(MachInst));
+  DPRINTF(MipsPRA,"(%x)  -  ResetFault::invoke : PC set to %x",(unsigned)tc,(unsigned)tc->readPC());
 }
 
 void ReservedInstructionFault::invoke(ThreadContext *tc)
 {
-    panic("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name());
+#if  FULL_SYSTEM
+  DPRINTF(MipsPRA,"%s encountered.\n", name());
+  //RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil
+  setExceptionState(tc,0x0A);
+  Addr HandlerBase;
+  HandlerBase= vect() + tc->readMiscRegNoEffect(MipsISA::EBase); // Offset 0x180 - General Exception Vector
+  setHandlerPC(HandlerBase,tc);
+#else
+    panic("%s encountered.\n", name());
+#endif
 }
 
 void ThreadFault::invoke(ThreadContext *tc)
 {
-    panic("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name());
+  DPRINTF(MipsPRA,"%s encountered.\n", name());
+  panic("%s encountered.\n", name());
 }
 
 void DspStateDisabledFault::invoke(ThreadContext *tc)
 {
-    panic("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name());
+  DPRINTF(MipsPRA,"%s encountered.\n", name());
+  panic("%s encountered.\n", name());
+}
+
+void CoprocessorUnusableFault::invoke(ThreadContext *tc)
+{
+#if FULL_SYSTEM
+  DPRINTF(MipsPRA,"%s encountered.\n", name());
+  setExceptionState(tc,0xb);
+  /* The ID of the coprocessor causing the exception is stored in CoprocessorUnusableFault::coProcID */
+  MiscReg cause = tc->readMiscReg(MipsISA::Cause);
+  replaceBits(cause,Cause_CE_HI,Cause_CE_LO,coProcID);
+  tc->setMiscRegNoEffect(MipsISA::Cause,cause);
+
+  Addr HandlerBase;
+  HandlerBase= vect() + tc->readMiscReg(MipsISA::EBase); // Offset 0x180 - General Exception Vector
+  setHandlerPC(HandlerBase,tc);
+
+  //      warn("Status: %x, Cause: %x\n",tc->readMiscReg(MipsISA::Status),tc->readMiscReg(MipsISA::Cause));
+#else
+    panic("%s encountered.\n", name());
+#endif
 }
 
 } // namespace MipsISA

src/arch/mips/faults.hh

@@ -1,32 +1,39 @@
 /*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
+ * This software is part of the M5 simulator.
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * TO THESE TERMS AND CONDITIONS.
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Gabe Black
+ * Permission is granted to use, copy, create derivative works and
- *          Korey Sewell
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Gabe M. Black
+ *          Korey L. Sewell
+ *          Jaidev Patwardhan
  */
 
 #ifndef __MIPS_FAULTS_HH__
@@ -38,7 +45,6 @@
 
 namespace MipsISA
 {
-
 typedef const Addr FaultVect;
 
 class MipsFault : public FaultBase
@@ -47,8 +53,15 @@ class MipsFault : public FaultBase
     virtual bool skipFaultingInstruction() {return false;}
     virtual bool setRestartAddress() {return true;}
   public:
+    Addr BadVAddr;
+    Addr EntryHi_Asid;
+    Addr EntryHi_VPN2;
+    Addr EntryHi_VPN2X;
+    Addr Context_BadVPN2;
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+  void invoke(ThreadContext * tc) {};
+  void setExceptionState(ThreadContext *,uint8_t);
+  void setHandlerPC(Addr,ThreadContext *);
 #endif
     virtual FaultVect vect() = 0;
     virtual FaultStat & countStat() = 0;
@@ -64,7 +77,20 @@ class MachineCheckFault : public MipsFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    bool isMachineCheckFault() const {return true;}
+    bool isMachineCheckFault() {return true;}
+};
+
+class NonMaskableInterrupt : public MipsFault
+{
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    FaultName name() const {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+    bool isNonMaskableInterrupt() {return true;}
 };
 
 class AlignmentFault : public MipsFault
@@ -77,9 +103,39 @@ class AlignmentFault : public MipsFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    bool isAlignmentFault() const {return true;}
+    bool isAlignmentFault() {return true;}
 };
 
+class AddressErrorFault : public MipsFault
+{
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    FaultName name() const {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+#if FULL_SYSTEM
+    void invoke(ThreadContext * tc);
+#endif
+
+};
+class StoreAddressErrorFault : public MipsFault
+{
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    FaultName name() const {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+#if FULL_SYSTEM
+    void invoke(ThreadContext * tc);
+#endif
+
+};
 class UnimplementedOpcodeFault : public MipsFault
 {
   private:
@@ -92,12 +148,160 @@ class UnimplementedOpcodeFault : public MipsFault
     FaultStat & countStat() {return _count;}
 };
 
+
+class TLBRefillIFetchFault : public MipsFault
+{
+  private:
+    Addr vaddr;
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    FaultName name() const {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+    void invoke(ThreadContext * tc);
+};
+class TLBInvalidIFetchFault : public MipsFault
+{
+  private:
+    Addr vaddr;
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    FaultName name() const {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+    void invoke(ThreadContext * tc);
+};
+
+class NDtbMissFault : public MipsFault
+{
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    FaultName name() const {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+};
+
+class PDtbMissFault : public MipsFault
+{
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    FaultName name() const {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+};
+
+class DtbPageFault : public MipsFault
+{
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    FaultName name() const {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+};
+
+class DtbAcvFault : public MipsFault
+{
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    FaultName name() const {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+};
+
+class CacheErrorFault : public MipsFault
+{
+  private:
+    Addr vaddr;
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    FaultName name() const {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+    void invoke(ThreadContext * tc);
+};
+
+
+
+
 static inline Fault genMachineCheckFault()
 {
     return new MachineCheckFault;
 }
 
+static inline Fault genAlignmentFault()
+{
+    return new AlignmentFault;
+}
+
 class ResetFault : public MipsFault
+{
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    FaultName name() const {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+    void invoke(ThreadContext * tc);
+
+};
+class SystemCallFault : public MipsFault
+{
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    FaultName name() const {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+    void invoke(ThreadContext * tc);
+};
+
+class SoftResetFault : public MipsFault
+{
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    FaultName name() const {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+    void invoke(ThreadContext * tc);
+};
+class DebugSingleStep : public MipsFault
+{
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    FaultName name() const {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+    void invoke(ThreadContext * tc);
+};
+class DebugInterrupt : public MipsFault
 {
   private:
     static FaultName _name;
@@ -116,11 +320,13 @@ class CoprocessorUnusableFault : public MipsFault
     static FaultName _name;
     static FaultVect _vect;
     static FaultStat _count;
+    int coProcID;
   public:
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
     void invoke(ThreadContext * tc);
+    CoprocessorUnusableFault(int _procid){ coProcID = _procid;}
 };
 
 class ReservedInstructionFault : public MipsFault
@@ -179,9 +385,15 @@ class InterruptFault : public MipsFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
+
+#if FULL_SYSTEM
+    void invoke(ThreadContext * tc);
+#endif
+
+    //void invoke(ThreadContext * tc);
 };
 
-class NDtbMissFault : public MipsFault
+class TrapFault : public MipsFault
 {
   private:
     static FaultName _name;
@@ -191,9 +403,12 @@ class NDtbMissFault : public MipsFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
+#if FULL_SYSTEM
+    void invoke(ThreadContext * tc);
+#endif
 };
 
-class PDtbMissFault : public MipsFault
+class BreakpointFault : public MipsFault
 {
   private:
     static FaultName _name;
@@ -203,9 +418,12 @@ class PDtbMissFault : public MipsFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
+#if FULL_SYSTEM
+    void invoke(ThreadContext * tc);
+#endif
 };
 
-class DtbPageFault : public MipsFault
+class ItbRefillFault : public MipsFault
 {
   private:
     static FaultName _name;
@@ -215,9 +433,88 @@ class DtbPageFault : public MipsFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
+#if FULL_SYSTEM
+    void invoke(ThreadContext * tc);
+#endif
+};
+class DtbRefillFault : public MipsFault
+{
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    FaultName name() const {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+#if FULL_SYSTEM
+    void invoke(ThreadContext * tc);
+#endif
 };
 
-class DtbAcvFault : public MipsFault
+class ItbPageFault : public MipsFault
+{
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    FaultName name() const {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+#if FULL_SYSTEM
+    void invoke(ThreadContext * tc);
+#endif
+};
+
+class ItbInvalidFault : public MipsFault
+{
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    FaultName name() const {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+#if FULL_SYSTEM
+    void invoke(ThreadContext * tc);
+#endif
+
+};
+class TLBModifiedFault : public MipsFault
+{
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    FaultName name() const {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+#if FULL_SYSTEM
+    void invoke(ThreadContext * tc);
+#endif
+
+};
+
+class DtbInvalidFault : public MipsFault
+{
+  private:
+    static FaultName _name;
+    static FaultVect _vect;
+    static FaultStat _count;
+  public:
+    FaultName name() const {return _name;}
+    FaultVect vect() {return _vect;}
+    FaultStat & countStat() {return _count;}
+#if FULL_SYSTEM
+    void invoke(ThreadContext * tc);
+#endif
+
+};
+
+class FloatEnableFault : public MipsFault
 {
   private:
     static FaultName _name;
@@ -241,18 +538,6 @@ class ItbMissFault : public MipsFault
     FaultStat & countStat() {return _count;}
 };
 
-class ItbPageFault : public MipsFault
-{
-  private:
-    static FaultName _name;
-    static FaultVect _vect;
-    static FaultStat _count;
-  public:
-    FaultName name() const {return _name;}
-    FaultVect vect() {return _vect;}
-    FaultStat & countStat() {return _count;}
-};
-
 class ItbAcvFault : public MipsFault
 {
   private:
@@ -265,18 +550,6 @@ class ItbAcvFault : public MipsFault
     FaultStat & countStat() {return _count;}
 };
 
-class FloatEnableFault : public MipsFault
-{
-  private:
-    static FaultName _name;
-    static FaultVect _vect;
-    static FaultStat _count;
-  public:
-    FaultName name() const {return _name;}
-    FaultVect vect() {return _vect;}
-    FaultStat & countStat() {return _count;}
-};
-
 class IntegerOverflowFault : public MipsFault
 {
   private:
@@ -304,4 +577,4 @@ class DspStateDisabledFault : public MipsFault
 
 } // MipsISA namespace
 
-#endif // __FAULTS_HH__
+#endif // __MIPS_FAULTS_HH__

src/arch/mips/idle_event.cc

@@ -0,0 +1,54 @@
+/*
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ *
+ * This software is part of the M5 simulator.
+ *
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+ * TO THESE TERMS AND CONDITIONS.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Lisa R. Hsu
+ *          Nathan L. Binkert
+ *          Korey L. Sewell
+ */
+
+#include "arch/mips/idle_event.hh"
+#include "arch/mips/kernel_stats.hh"
+#include "cpu/thread_context.hh"
+
+using namespace TheISA;
+
+void
+IdleStartEvent::process(ThreadContext *tc)
+{
+    fatal("Idle Start Event Not Defined for MIPS ISA ");
+
+    //    if (tc->getKernelStats())
+    //      tc->getKernelStats()->setIdleProcess(
+    //      tc->readMiscRegNoEffect(MipsISA::IPR_PALtemp23), tc);
+    //remove();
+}

src/arch/mips/idle_event.hh

@@ -0,0 +1,53 @@
+/*
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ *
+ * This software is part of the M5 simulator.
+ *
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+ * TO THESE TERMS AND CONDITIONS.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Nathan L. Binkert
+ *          Lisa R. Hsu
+ *          Ali G. Saidi
+ */
+
+#ifndef __KERN_MIPS_IDLE_EVENT_HH__
+#define __KERN_MIPS_IDLE_EVENT_HH__
+
+#include "cpu/pc_event.hh"
+
+class IdleStartEvent : public PCEvent
+{
+  public:
+    IdleStartEvent(PCEventQueue *q, const std::string &desc, Addr addr)
+        : PCEvent(q, desc, addr)
+    {}
+    virtual void process(ThreadContext *tc);
+};
+
+#endif // __KERN_ALPHA_IDLE_EVENT_HH__

src/arch/mips/interrupts.cc

@@ -0,0 +1,289 @@
+/*
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ *
+ * This software is part of the M5 simulator.
+ *
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+ * TO THESE TERMS AND CONDITIONS.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Richard Strong
+ */
+
+
+#include "arch/mips/pra_constants.hh"
+#include "arch/mips/isa_traits.hh"
+#include "cpu/thread_context.hh"
+#include "arch/mips/interrupts.hh"
+
+namespace MipsISA
+{
+static inline uint8_t getCauseIP_(ThreadContext *tc) {
+    MiscReg cause = tc->readMiscRegNoEffect(MipsISA::Cause);
+    uint8_t IP_ = bits(cause,Cause_IP7, Cause_IP0);
+    return IP_;
+}
+
+static inline void setCauseIP_(ThreadContext *tc, uint8_t val) {
+    MiscReg cause = tc->readMiscRegNoEffect(MipsISA::Cause);
+    replaceBits(cause,Cause_IP7,Cause_IP0,val);
+    tc->setMiscRegNoEffect(MipsISA::Cause,cause);
+}
+
+/*
+  void Interrupts::post(int int_num, int index)
+  {
+  DPRINTF(Interrupt, "Interrupt %d posted\n", int_num);
+
+  //index should not be used
+  assert(index == 0);
+
+  if (int_num < 0 || int_num >= NumInterruptLevels)
+  panic("int_num out of bounds\n");
+  intstatus |= 1 << int_num;
+  }
+
+  void Interrupts::clear(int int_num, int index)
+  {
+  DPRINTF(Interrupt, "Interrupt %d cleared\n", int_num);
+
+  //index should not be used
+  assert(index == 0);
+
+  if (int_num < 0 || int_num >= NumInterruptLevels)
+  panic("int_num out of bounds\n");
+
+  intstatus &= ~(1 << int_num);
+  }
+
+  void Interrupts::clear_all()
+  {
+  DPRINTF(Interrupt, "Interrupts all cleared\n");
+  intstatus = 0;
+  }
+
+
+
+  Fault Interrupts::getInterrupt(ThreadContext * tc)
+  {
+  DPRINTF(Interrupt, "Interrupts getInterrupt\n");
+  // If a timer interrupt has occured, check to see if a
+  // mtc0 to Compare register caused this interrupt to
+  // be cleared. If this is the case, clear intstatus
+  // bit for timer interrupt
+  if (oncputimerintr){
+  DPRINTF(Interrupt, "Interrupts oncputimerintr==true\n");
+  MiscReg cause = tc->readMiscRegNoEffect(MipsISA::Cause);
+  uint8_t IP_ = bits(cause,Cause_IP7, Cause_IP0);
+  MiscReg intctl = tc->readMiscRegNoEffect(MipsISA::IntCtl);
+  uint8_t IPTI = bits(intctl, IntCtl_IPTI_HI, IntCtl_IPTI_LO);
+  //mtc0 to compare must have cleared bit in IP
+  if ( ((1 << IPTI) & IP_) == 0){
+  clear(IPTI, 0);
+  oncputimerintr=false;
+  }
+  }
+  //if there is a on cpu timer interrupt (i.e. Compare == Count)
+  //update intstatus before proceeding to interrupt
+  if (onCpuTimerInterrupt(tc)){
+  DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc)==true\n");
+  //determine timer interrupt IP #
+  MiscReg intctl = tc->readMiscRegNoEffect(MipsISA::IntCtl);
+  uint8_t IPTI = bits(intctl, IntCtl_IPTI_HI, IntCtl_IPTI_LO);
+  //set intstatus to correspond
+  post(IPTI, 0);
+  oncputimerintr=true;
+  }
+
+  //Check if there are any outstanding interrupts
+  MiscReg status = tc->readMiscRegNoEffect(MipsISA::Status);
+  if (bits(status, Status_IE_LO) == 1 && //interrupts must be enabled
+  bits(status, Status_ERL) == 0 &&  //error level must be 0 or interrupts inhibited
+  bits(status, Status_EXL) == 0 ) //exception level must be 0 or interrupts inhibited
+  {
+  // Software interrupts & hardware interrupts are handled in software.
+  // So if any interrupt that isn't masked is detected, jump to interrupt
+  // handler
+  uint8_t IM, IP; //IM=interrupt mask, IP=interrupt pending
+  IM = bits(status,Status_IM7,Status_IM0);
+  IP = intstatus;
+  //IM and IP are already correctly aligned
+  if (IM & IP){
+  DPRINTF(Flow, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
+  IM, IP);
+  return new InterruptFault;
+  }
+  }
+
+  return NoFault;
+
+  }
+
+  void Interrupts::updateIntrInfo(ThreadContext *tc) const
+  {
+  //Merge Interrupts.intstatus with mips MipISA::Status
+  MiscReg cause = tc->readMiscRegNoEffect(MipsISA::Cause);
+  replaceBits(cause,Cause_IP7,Cause_IP0,intstatus);
+  tc->setMiscRegNoEffect(MipsISA::Cause,cause);
+  }
+
+  bool Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const
+  {
+  MiscReg compare = tc->readMiscRegNoEffect(MipsISA::Compare);
+  MiscReg count = tc->readMiscRegNoEffect(MipsISA::Count);
+  if (compare == count)
+  return true;
+  return false;
+  }
+
+
+  uint64_t Interrupts::get_vec(int int_num)
+  {
+  panic("MipsISA::Interrupts::get_vec() is not implemented. \n");
+  M5_DUMMY_RETURN
+  }
+*/
+void Interrupts::post(int int_num, ThreadContext* tc)
+{
+    DPRINTF(Interrupt, "Interrupt %d posted\n", int_num);
+    if (int_num < 0 || int_num >= NumInterruptLevels)
+        panic("int_num out of bounds\n");
+
+    uint8_t intstatus= getCauseIP_(tc);
+    intstatus |= 1 << int_num;
+    setCauseIP_(tc, intstatus);
+}
+
+void Interrupts::post(int int_num, int index)
+{
+    fatal("Must use Thread COntext when posting MIPS Interrupts in M5");
+}
+
+void Interrupts::clear(int int_num, ThreadContext* tc)
+{
+    DPRINTF(Interrupt, "Interrupt %d cleared\n", int_num);
+    if (int_num < 0 || int_num >= NumInterruptLevels)
+        panic("int_num out of bounds\n");
+
+    uint8_t intstatus = getCauseIP_(tc);
+    intstatus &= ~(1 << int_num);
+    setCauseIP_(tc, intstatus);
+}
+
+void Interrupts::clear(int int_num, int index)
+{
+    fatal("Must use Thread COntext when clearing MIPS Interrupts in M5");
+}
+
+void Interrupts::clear_all(ThreadContext *tc)
+{
+    DPRINTF(Interrupt, "Interrupts all cleared\n");
+    uint8_t intstatus = 0;
+    setCauseIP_(tc, intstatus);
+}
+
+void Interrupts::clear_all()
+{
+    fatal("Must use Thread COntext when clearing MIPS Interrupts in M5");
+}
+
+
+
+Fault Interrupts::getInterrupt(ThreadContext * tc)
+{
+    DPRINTF(Interrupt, "Interrupts getInterrupt\n");
+
+
+
+    //Check if there are any outstanding interrupts
+    MiscReg status = tc->readMiscRegNoEffect(MipsISA::Status);
+    if (bits(status, Status_IE_LO) == 1 && //interrupts must be enabled
+        bits(status, Status_ERL_HI,Status_ERL_LO) == 0 &&  //error level must be 0 or interrupts inhibited
+        bits(status, Status_EXL_HI,Status_EXL_LO) == 0 ) //exception level must be 0 or interrupts inhibited
+    {
+        // Software interrupts & hardware interrupts are handled in software.
+        // So if any interrupt that isn't masked is detected, jump to interrupt
+        // handler
+        uint8_t IM, IP; //IM=interrupt mask, IP=interrupt pending
+        IM = bits(status,Status_IM7,Status_IM0);
+        IP = getCauseIP_(tc);
+        //IM and IP are already correctly aligned
+        if (IM & IP){
+            DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
+                    IM, IP);
+            return new InterruptFault;
+        }
+    }
+
+    return NoFault;
+
+}
+bool Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const
+{
+    MiscReg compare = tc->readMiscRegNoEffect(MipsISA::Compare);
+    MiscReg count = tc->readMiscRegNoEffect(MipsISA::Count);
+    if (compare == count && count != 0)
+        return true;
+    return false;
+}
+void Interrupts::updateIntrInfo(ThreadContext *tc) const
+{
+    //Nothing needs to be done.
+    ;
+}
+
+uint64_t Interrupts::get_vec(int int_num)
+{
+    panic("MipsISA::Interrupts::get_vec() is not implemented. \n");
+    M5_DUMMY_RETURN
+        }
+
+bool Interrupts::interruptsPending(ThreadContext *tc) const
+{
+    //if there is a on cpu timer interrupt (i.e. Compare == Count)
+    //update CauseIP before proceeding to interrupt
+    if (onCpuTimerInterrupt(tc)){
+        DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc)==true\n");
+        //determine timer interrupt IP #
+        MiscReg intctl = tc->readMiscRegNoEffect(MipsISA::IntCtl);
+        uint8_t IPTI = bits(intctl, IntCtl_IPTI_HI, IntCtl_IPTI_LO);
+        //set intstatus to correspond
+        //post(IPTI, tc);
+        uint8_t intstatus= getCauseIP_(tc);
+        intstatus |= 1 << IPTI;
+        setCauseIP_(tc, intstatus);
+    }
+
+    return (getCauseIP_(tc) != 0);
+
+}
+
+
+
+
+
+}

src/arch/mips/interrupts.hh

@@ -0,0 +1,202 @@
+/*
+ * Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ *
+ * This software is part of the M5 simulator.
+ *
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+ * TO THESE TERMS AND CONDITIONS.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Richard Strong
+ */
+
+#ifndef __ARCH_MIPS_INTERRUPT_HH__
+#define __ARCH_MIPS_INTERRUPT_HH__
+
+
+#include "arch/mips/faults.hh"
+#include "base/compiler.hh"
+
+
+
+namespace MipsISA
+{
+class Interrupts
+{
+    /*
+      protected:
+      uint8_t intstatus;
+      bool oncputimerintr;
+      public:
+      Interrupts()
+      {
+      intstatus = 0;
+      newInfoSet = false;
+      oncputimerintr = false;
+
+      }
+      //  post(int int_num, int index) is responsible
+      //  for posting an interrupt. It sets a bit
+      //  in intstatus corresponding to Cause IP*. The
+      //  MIPS register Cause is updated by updateIntrInfo
+      //  which is called by check_interrupts
+      //
+      void post(int int_num, int index);
+      // clear(int int_num, int index) is responsible
+      //  for clearing an interrupt. It clear a bit
+      //  in intstatus corresponding to Cause IP*. The
+      //  MIPS register Cause is updated by updateIntrInfo
+      //  which is called by check_interrupts
+      //
+      void clear(int int_num, int index);
+      //  clear_all() is responsible
+      //  for clearing all interrupts. It clears all bits
+      //  in intstatus corresponding to Cause IP*. The
+      //  MIPS register Cause is updated by updateIntrInfo
+      //  which is called by check_interrupts
+      //
+      void clear_all();
+
+      // getInterrupt(ThreadContext * tc) checks if an interrupt
+      //  should be returned. It ands the interrupt mask and
+      //  and interrupt pending bits to see if one exists. It
+      //  also makes sure interrupts are enabled (IE) and
+      //  that ERL and ERX are not set
+      //
+      Fault getInterrupt(ThreadContext * tc);
+
+      // updateIntrInfo(ThreadContext *tc) const syncs the
+      //  MIPS cause register with the instatus variable. instatus
+      //  is essentially a copy of the MIPS cause[IP7:IP0]
+      //
+      void updateIntrInfo(ThreadContext *tc) const;
+      void updateIntrInfoCpuTimerIntr(ThreadContext *tc) const;
+      bool onCpuTimerInterrupt(ThreadContext *tc) const;
+
+      uint64_t get_vec(int int_num);
+
+      bool check_interrupts(ThreadContext * tc) const{
+      //return (intstatus != 0) && !(tc->readPC() & 0x3);
+      if (oncputimerintr == false){
+      updateIntrInfo(tc);
+      return ((intstatus != 0) || onCpuTimerInterrupt(tc));
+      }
+      else
+      return true;
+
+      }
+    */
+
+
+  protected:
+    //uint8_t intstatus;
+    //bool oncputimerintr;
+  public:
+    Interrupts()
+    {
+        //intstatus = 0;
+        newInfoSet = false;
+        //oncputimerintr = false;
+
+    }
+    //  post(int int_num, int index) is responsible
+    //  for posting an interrupt. It sets a bit
+    //  in intstatus corresponding to Cause IP*. The
+    //  MIPS register Cause is updated by updateIntrInfo
+    //  which is called by check_interrupts
+    //
+    void post(int int_num, ThreadContext* tc);
+    void post(int int_num, int index);
+
+    // clear(int int_num, int index) is responsible
+    //  for clearing an interrupt. It clear a bit
+    //  in intstatus corresponding to Cause IP*. The
+    //  MIPS register Cause is updated by updateIntrInfo
+    //  which is called by check_interrupts
+    //
+    void clear(int int_num, ThreadContext* tc);
+    void clear(int int_num, int index);
+
+    //  clear_all() is responsible
+    //  for clearing all interrupts. It clears all bits
+    //  in intstatus corresponding to Cause IP*. The
+    //  MIPS register Cause is updated by updateIntrInfo
+    //  which is called by check_interrupts
+    //
+    void clear_all(ThreadContext* tc);
+    void clear_all();
+
+    // getInterrupt(ThreadContext * tc) checks if an interrupt
+    //  should be returned. It ands the interrupt mask and
+    //  and interrupt pending bits to see if one exists. It
+    //  also makes sure interrupts are enabled (IE) and
+    //  that ERL and ERX are not set
+    //
+    Fault getInterrupt(ThreadContext * tc);
+
+    // updateIntrInfo(ThreadContext *tc) const syncs the
+    //  MIPS cause register with the instatus variable. instatus
+    //  is essentially a copy of the MIPS cause[IP7:IP0]
+    //
+    void updateIntrInfo(ThreadContext *tc) const;
+    bool interruptsPending(ThreadContext *tc) const;
+    bool onCpuTimerInterrupt(ThreadContext *tc) const;
+
+    uint64_t get_vec(int int_num);
+
+    bool check_interrupts(ThreadContext * tc) const{
+        return interruptsPending(tc);
+    }
+
+
+    void serialize(std::ostream &os)
+    {
+        fatal("Serialization of Interrupts Unimplemented for MIPS");
+        //SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
+        //SERIALIZE_SCALAR(intstatus);
+    }
+
+    void unserialize(Checkpoint *cp, const std::string &section)
+    {
+        fatal("Unserialization of Interrupts Unimplemented for MIPS");
+        //UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
+        //UNSERIALIZE_SCALAR(intstatus);
+    }
+
+
+
+  private:
+    bool newInfoSet;
+    int newIpl;
+    int newSummary;
+
+};
+
+}
+
+#endif
+

src/arch/mips/isa/base.isa

@@ -1,32 +1,38 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-// All rights reserved.
+
-//
+//  This software is part of the M5 simulator.
-// Redistribution and use in source and binary forms, with or without
+
-// modification, are permitted provided that the following conditions are
+//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-// met: redistributions of source code must retain the above copyright
+//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-// notice, this list of conditions and the following disclaimer;
+//  TO THESE TERMS AND CONDITIONS.
-// redistributions in binary form must reproduce the above copyright
+
-// notice, this list of conditions and the following disclaimer in the
+//  Permission is granted to use, copy, create derivative works and
-// documentation and/or other materials provided with the distribution;
+//  distribute this software and such derivative works for any purpose,
-// neither the name of the copyright holders nor the names of its
+//  so long as (1) the copyright notice above, this grant of permission,
-// contributors may be used to endorse or promote products derived from
+//  and the disclaimer below appear in all copies and derivative works
-// this software without specific prior written permission.
+//  made, (2) the copyright notice above is augmented as appropriate to
-//
+//  reflect the addition of any new copyrightable work in a derivative
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  advertising or publicity pertaining to the use or distribution of
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  this software without specific, written prior authorization.
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//
+//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-// Authors: Korey Sewell
+//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
 
 ////////////////////////////////////////////////////////////////////
 //
@@ -82,7 +88,7 @@ output decoder {{
         // Need to find standard way to not print
         // this info. Maybe add bool variable to
         // class?
-        if (strcmp(mnemonic, "syscall") != 0) {
+        if (mnemonic != "syscall") {
             if(_numDestRegs > 0){
                 printReg(ss, _destRegIdx[0]);
             }
@@ -100,7 +106,7 @@ output decoder {{
 
         // Should we define a separate inst. class
         // just for two insts?
-        if (strcmp(mnemonic, "sll") == 0 || strcmp(mnemonic, "sra") == 0) {
+        if(mnemonic == "sll" || mnemonic == "sra"){
             ccprintf(ss,", %d",SA);
         }
 

src/arch/mips/isa/bitfields.isa

@@ -1,34 +1,41 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-// All rights reserved.
+
-//
+//  This software is part of the M5 simulator.
-// Redistribution and use in source and binary forms, with or without
+
-// modification, are permitted provided that the following conditions are
+//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-// met: redistributions of source code must retain the above copyright
+//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-// notice, this list of conditions and the following disclaimer;
+//  TO THESE TERMS AND CONDITIONS.
-// redistributions in binary form must reproduce the above copyright
+
-// notice, this list of conditions and the following disclaimer in the
+//  Permission is granted to use, copy, create derivative works and
-// documentation and/or other materials provided with the distribution;
+//  distribute this software and such derivative works for any purpose,
-// neither the name of the copyright holders nor the names of its
+//  so long as (1) the copyright notice above, this grant of permission,
-// contributors may be used to endorse or promote products derived from
+//  and the disclaimer below appear in all copies and derivative works
-// this software without specific prior written permission.
+//  made, (2) the copyright notice above is augmented as appropriate to
-//
+//  reflect the addition of any new copyrightable work in a derivative
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  advertising or publicity pertaining to the use or distribution of
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  this software without specific, written prior authorization.
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//
+//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-// Authors: Korey Sewell
+//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
+//         Jaidev Patwardhan
+
 
-//@TODO: Make sure the naming convention is consistent here.
 ////////////////////////////////////////////////////////////////////
 //
 // Bitfield definitions.
@@ -119,3 +126,6 @@ def bitfield BP        <12:11>;
 def bitfield POS   <10: 6>;
 def bitfield MT_U     <5:5>;
 def bitfield MT_H     <4:4>;
+
+//Cache Ops
+def bitfield CACHE_OP <20:16>;

src/arch/mips/isa/decoder.isa

@@ -1,33 +1,40 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
-// All rights reserved.
+
-//
+//  This software is part of the M5 simulator.
-// Redistribution and use in source and binary forms, with or without
+
-// modification, are permitted provided that the following conditions are
+//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-// met: redistributions of source code must retain the above copyright
+//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-// notice, this list of conditions and the following disclaimer;
+//  TO THESE TERMS AND CONDITIONS.
-// redistributions in binary form must reproduce the above copyright
+
-// notice, this list of conditions and the following disclaimer in the
+//  Permission is granted to use, copy, create derivative works and
-// documentation and/or other materials provided with the distribution;
+//  distribute this software and such derivative works for any purpose,
-// neither the name of the copyright holders nor the names of its
+//  so long as (1) the copyright notice above, this grant of permission,
-// contributors may be used to endorse or promote products derived from
+//  and the disclaimer below appear in all copies and derivative works
-// this software without specific prior written permission.
+//  made, (2) the copyright notice above is augmented as appropriate to
-//
+//  reflect the addition of any new copyrightable work in a derivative
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  advertising or publicity pertaining to the use or distribution of
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  this software without specific, written prior authorization.
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//
+//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-// Authors: Korey Sewell
+//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
 //         Brett Miller
+//         Jaidev Patwardhan
 
 ////////////////////////////////////////////////////////////////////
 //
@@ -57,8 +64,8 @@ decode OPCODE_HI default Unknown::unknown() {
                     0x0: decode RS  {
                         0x0: decode RT_RD {
                             0x0: decode SA default Nop::nop() {
-                                0x1: WarnUnimpl::ssnop();
+                                 0x1: ssnop({{;}});
-                                0x3: WarnUnimpl::ehb();
+                                 0x3: ehb({{;}});
                             }
                             default: sll({{ Rd = Rt.uw << SA; }});
                         }
@@ -119,8 +126,8 @@ decode OPCODE_HI default Unknown::unknown() {
                 //used to distinguish JR from JR.HB and JALR from JALR.HB"
                 format Jump {
                     0x0: decode HINT {
-                        0x1: jr_hb({{ NNPC = Rs & ~1; }}, IsReturn, ClearHazards);
+                        0x1: jr_hb({{ if(Config1_CA == 0){NNPC = Rs;}else{panic("MIPS16e not supported\n");}; }}, IsReturn, ClearHazards);
-                        default: jr({{ NNPC = Rs & ~1; }}, IsReturn);
+                        default: jr({{ if(Config1_CA == 0){NNPC = Rs;}else{panic("MIPS16e not supported\n");};}}, IsReturn);
                     }
 
                     0x1: decode HINT {
@@ -133,28 +140,31 @@ decode OPCODE_HI default Unknown::unknown() {
                 format BasicOp {
                     0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
                     0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
+#if FULL_SYSTEM
+                  0x4: syscall({{
+                                   fault = new SystemCallFault();
+                                 }});
+#else
                     0x4: syscall({{ xc->syscall(R2); }},
-                                 IsSerializeAfter, IsNonSpeculative,
+                                 IsSerializing, IsNonSpeculative);
-                                 IsSyscall);
+#endif
                     0x7: sync({{ ; }}, IsMemBarrier);
+                    0x5: break({{fault = new BreakpointFault();}});
                 }
 
-                format FailUnimpl {
-                    0x5: break();
-                }
             }
 
             0x2: decode FUNCTION_LO {
-                0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }});
+                0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}, IntMultOp, IsIprAccess);
                 0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }});
-                0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }});
+                0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }}, IntMultOp, IsIprAccess);
                 0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }});
             }
 
             0x3: decode FUNCTION_LO {
                 format HiLoRdSelValOp {
-                    0x0: mult({{ val = Rs.sd * Rt.sd; }});
+                    0x0: mult({{ val = Rs.sd * Rt.sd; }}, IntMultOp);
-                    0x1: multu({{ val = Rs.ud * Rt.ud; }});
+                    0x1: multu({{ val = Rs.ud * Rt.ud; }}, IntMultOp);
                 }
 
                 format HiLoOp {
@@ -162,21 +172,55 @@ decode OPCODE_HI default Unknown::unknown() {
                         HI0 = Rs.sd % Rt.sd;
                         LO0 = Rs.sd / Rt.sd;
                     }
-                    }});
+                    }}, IntDivOp);
+
                     0x3: divu({{ if (Rt.ud != 0) {
                         HI0 = Rs.ud % Rt.ud;
                         LO0 = Rs.ud / Rt.ud;
                     }
-                    }});
+                    }}, IntDivOp);
                 }
             }
 
             0x4: decode HINT {
                 0x0: decode FUNCTION_LO {
                     format IntOp {
-                        0x0: add({{  Rd.sw = Rs.sw + Rt.sw; /*Trap on Overflow*/}});
+                      0x0: add({{  /* More complicated since an ADD can cause an arithmetic overflow exception */
+                                     int64_t Src1 = Rs.sw;
+                                     int64_t Src2 = Rt.sw;
+                                     int64_t temp_result;
+#if  FULL_SYSTEM
+                                     if(((Src1 >> 31) & 1) == 1)
+                                       Src1 |= 0x100000000LL;
+#endif
+                                     temp_result = Src1 + Src2;
+#if  FULL_SYSTEM
+                                     if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){
+#endif
+                                       Rd.sw = temp_result;
+#if  FULL_SYSTEM
+                                     } else{
+                                       fault = new ArithmeticFault();
+                                     }
+#endif
+
+                                   }});
                         0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
-                        0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;  /*Trap on Overflow*/}});
+                        0x2: sub({{
+                                     /* More complicated since an SUB can cause an arithmetic overflow exception */
+                                     int64_t Src1 = Rs.sw;
+                                     int64_t Src2 = Rt.sw;
+                                     int64_t temp_result = Src1 - Src2;
+#if  FULL_SYSTEM
+                                     if(((temp_result >> 31) & 1) == ((temp_result>>32) & 1)){
+#endif
+                                       Rd.sw = temp_result;
+#if  FULL_SYSTEM
+                                     } else{
+                                       fault = new ArithmeticFault();
+                                     }
+#endif
+                                   }});
                         0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}});
                         0x4: and({{ Rd = Rs & Rt;}});
                         0x5: or({{ Rd = Rs | Rt;}});
@@ -200,7 +244,7 @@ decode OPCODE_HI default Unknown::unknown() {
                     0x0: tge({{  cond = (Rs.sw >= Rt.sw); }});
                     0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }});
                     0x2: tlt({{ cond = (Rs.sw < Rt.sw); }});
-                    0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }});
+                    0x3: tltu({{ cond = (Rs.uw < Rt.uw); }});
                     0x4: teq({{ cond = (Rs.sw == Rt.sw); }});
                     0x6: tne({{ cond = (Rs.sw != Rt.sw); }});
                 }
@@ -218,13 +262,13 @@ decode OPCODE_HI default Unknown::unknown() {
             }
 
             0x1: decode REGIMM_LO {
-                format Trap {
+                format TrapImm {
-                    0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }});
+                    0x0: tgei( {{ cond = (Rs.sw >= (int16_t)INTIMM); }});
-                    0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }});
+                    0x1: tgeiu({{ cond = (Rs.uw >= (uint32_t)((int32_t)((int16_t)INTIMM))); }});
-                    0x2: tlti( {{ cond = (Rs.sw < INTIMM); }});
+                    0x2: tlti( {{ cond = (Rs.sw < (int16_t)INTIMM); }});
-                    0x3: tltiu({{ cond = (Rs.uw < INTIMM); }});
+                    0x3: tltiu({{ cond = (Rs.uw < (uint32_t)((int32_t)((int16_t)INTIMM))); }});
-                    0x4: teqi( {{ cond = (Rs.sw == INTIMM);}});
+                    0x4: teqi( {{ cond = (Rs.sw == (int16_t)INTIMM);}});
-                    0x6: tnei( {{ cond = (Rs.sw != INTIMM);}});
+                    0x6: tnei( {{ cond = (Rs.sw != (int16_t)INTIMM);}});
                 }
             }
 
@@ -268,7 +312,25 @@ decode OPCODE_HI default Unknown::unknown() {
 
     0x1: decode OPCODE_LO {
         format IntImmOp {
-            0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}});
+            0x0: addi({{
+                          int64_t Src1 = Rs.sw;
+                          int64_t Src2 = imm;
+                          int64_t temp_result;
+#if  FULL_SYSTEM
+                          if(((Src1 >> 31) & 1) == 1)
+                            Src1 |= 0x100000000LL;
+#endif
+                          temp_result = Src1 + Src2;
+#if  FULL_SYSTEM
+                          if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){
+#endif
+                            Rt.sw = temp_result;
+#if  FULL_SYSTEM
+                          } else{
+                            fault = new ArithmeticFault();
+                          }
+#endif
+                        }});
             0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
             0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});
 
@@ -295,11 +357,31 @@ decode OPCODE_HI default Unknown::unknown() {
         0x0: decode RS_MSB {
             0x0: decode RS {
                  format CP0Control {
-                    0x0: mfc0({{  Rt = CP0_RD_SEL; }});
+                  0x0: mfc0({{  Rt = CP0_RD_SEL;
-                    0x4: mtc0({{  CP0_RD_SEL = Rt; }});
+                                /* Hack for PageMask */
+                                if(RD == 5) // PageMask
+                                  if(Config3_SP == 0 || PageGrain_ESP == 0)
+                                    Rt &= 0xFFFFE7FF;
+                              }});
+                  0x4: mtc0({{  CP0_RD_SEL = Rt;
+
+                                if(RD == 11) // Compare{
+                                  if(Cause_TI == 1){
+                                    Cause_TI = 0;
+                                    MiscReg cause = xc->readMiscRegNoEffect(MipsISA::Cause);
+                                    int Offset = 10; // corresponding to Cause_IP0
+                                    Offset += ((IntCtl_IPTI) - 2);
+                                    replaceBits(cause,Offset,Offset,0);
+                                    xc->setMiscRegNoEffect(MipsISA::Cause,cause);
                                   }
 
-
+                              }});
+                 }
+                 format CP0Unimpl {
+                   0x1: dmfc0();
+                   0x5: dmtc0();
+                   default: unknown();
+                 }
                 format MT_MFTR { // Decode MIPS MT MFTR instruction into sub-instructions
                     0x8: decode MT_U {
                         0x0: mftc0({{ data = xc->readRegOtherThread((RT << 3 | SEL) +
@@ -321,6 +403,7 @@ decode OPCODE_HI default Unknown::unknown() {
                                 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPHi3); }});
                                 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPACX3); }});
                                 0x16: mftdsp({{ data = xc->readRegOtherThread(MipsISA::DSPControl); }});
+                               default: CP0Unimpl::unknown();
                             }
                             0x2: decode MT_H {
                                 0x0: mftc1({{ data = xc->readRegOtherThread(RT +
@@ -357,6 +440,7 @@ decode OPCODE_HI default Unknown::unknown() {
                                                  fatal("FP Control Value (%d) Not Valid");
                                           }
                                         }});
+                           default: CP0Unimpl::unknown();
                         }
                   }
                 }
@@ -404,6 +488,8 @@ decode OPCODE_HI default Unknown::unknown() {
                                 0x14: mttacx_dsp3({{ xc->setRegOtherThread(MipsISA::DSPACX3, Rt);
                                                   }});
                                 0x16: mttdsp({{ xc->setRegOtherThread(MipsISA::DSPControl, Rt); }});
+                               default: CP0Unimpl::unknown();
+
                             }
                             0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD +
                                                                                 FP_Base_DepTag);
@@ -446,6 +532,7 @@ decode OPCODE_HI default Unknown::unknown() {
                                           }
                                           xc->setRegOtherThread(FCSR, data);
                                        }});
+                               default: CP0Unimpl::unknown();
                         }
                     }
                 }
@@ -466,8 +553,11 @@ decode OPCODE_HI default Unknown::unknown() {
                                                      MVPControl = insertBits(MVPControl, MVPC_EVP, 1);
                                                  }
                                               }});
+                                   default:CP0Unimpl::unknown();
                                 }
+                               default:CP0Unimpl::unknown();
                             }
+                        default:CP0Unimpl::unknown();
                       }
 
                         0x1: decode POS {
@@ -479,9 +569,11 @@ decode OPCODE_HI default Unknown::unknown() {
                                     0x1: emt({{ Rt = VPEControl;
                                                 VPEControl = insertBits(VPEControl, VPEC_TE, 1);
                                          }});
-
+                                   default:CP0Unimpl::unknown();
                                 }
+                               default:CP0Unimpl::unknown();
                             }
+                            default:CP0Unimpl::unknown();
                         }
                     }
                     0xC: decode POS {
@@ -508,15 +600,16 @@ decode OPCODE_HI default Unknown::unknown() {
                                 fault = new ReservedInstructionFault();
                               }
                           }});
+                        default:CP0Unimpl::unknown();
                       }
                     }
+                default: CP0Unimpl::unknown();
                 }
-
                 format CP0Control {
                     0xA: rdpgpr({{
                       if(Config_AR >= 1)
                         { // Rev 2 of the architecture
-                          Rd = xc->tcBase()->readIntReg(Rt + NumIntRegs * SRSCtl_PSS);
+                          Rd = xc->tcBase()->readIntReg(RT + NumIntRegs * SRSCtl_PSS);
                         }
                       else
                         {
@@ -526,7 +619,8 @@ decode OPCODE_HI default Unknown::unknown() {
                     0xE: wrpgpr({{
                       if(Config_AR >= 1)
                         { // Rev 2 of the architecture
-                          xc->tcBase()->setIntReg(Rd + NumIntRegs * SRSCtl_PSS,Rt);
+                          xc->tcBase()->setIntReg(RD + NumIntRegs * SRSCtl_PSS,Rt);
+                          //			  warn("Writing %d to %d, PSS: %d, SRS: %x\n",Rt,RD + NumIntRegs * SRSCtl_PSS, SRSCtl_PSS,SRSCtl);
                         }
                       else
                         {
@@ -534,7 +628,6 @@ decode OPCODE_HI default Unknown::unknown() {
                         }
 
                          }});
-
                 }
 
                }
@@ -543,39 +636,202 @@ decode OPCODE_HI default Unknown::unknown() {
             0x1: decode FUNCTION {
               format CP0Control {
                 0x18: eret({{
+                               DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC);
+                               // Ugly hack to get the value of Status_EXL
+                               if(Status_EXL == 1){
+                                 DPRINTF(MipsPRA,"ERET EXL Hack\n");
+                               }
                   if(Status_ERL == 1){
                     Status_ERL = 0;
                     NPC = ErrorEPC;
+                    NNPC = ErrorEPC + sizeof(MachInst); // Need to adjust NNPC, otherwise things break
                   }
-                  else{
+                  else {
                     NPC = EPC;
+                    NNPC = EPC + sizeof(MachInst); // Need to adjust NNPC, otherwise things break
                     Status_EXL = 0;
-                    if(Config_AR >= 1 && SRSCtl_HSS > 0 && Status_BEV == 0){
+                    if(Config_AR >=1 && SRSCtl_HSS > 0 && Status_BEV == 0){
                       SRSCtl_CSS = SRSCtl_PSS;
+                      xc->setShadowSet(SRSCtl_PSS);
                     }
                   }
-                  //		  LLFlag = 0;
+                  LLFlag = 0;
-                  // ClearHazards(); ?
+                 }},IsReturn,IsSerializing,IsERET);
-                }});
 
                 0x1F: deret({{
-                    //if(Debug_DM == 1){
+                  // if(EJTagImplemented()) {
-                    //Debug_DM = 1;
+                  if(Debug_DM == 1){
-                    //Debug_IEXI = 0;
+                    Debug_DM = 1;
-                    //NPC = DEPC;
+                    Debug_IEXI = 0;
+                    NPC = DEPC;
+                  }
+                  else
+                    {
+                      // Undefined;
+                    }
+                  //} // EJTag Implemented
+                  //else {
+                  // Reserved Instruction Exception
                   //}
-                    panic("deret not implemented");
+                 }},IsReturn,IsSerializing,IsERET);
+              }
+              format CP0TLB {
+                0x01: tlbr({{
+                    MipsISA::PTE *PTEntry = xc->tcBase()->getITBPtr()->getEntry(Index & 0x7FFFFFFF);
+                    if(PTEntry == NULL)
+                      {
+                        fatal("Invalid PTE Entry received on a TLBR instruction\n");
+                      }
+                    /* Setup PageMask */
+                    PageMask = (PTEntry->Mask << 11); // If 1KB pages are not enabled, a read of PageMask must return 0b00 in bits 12, 11
+                    /* Setup EntryHi */
+                    EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid));
+                    /* Setup Entry Lo0 */
+                    EntryLo0 = ((PTEntry->PFN0 << 6) | (PTEntry->C0 << 3) | (PTEntry->D0 << 2) | (PTEntry->V0 << 1) | PTEntry->G);
+                    /* Setup Entry Lo1 */
+                    EntryLo1 = ((PTEntry->PFN1 << 6) | (PTEntry->C1 << 3) | (PTEntry->D1 << 2) | (PTEntry->V1 << 1) | PTEntry->G);
+                }}); // Need to hook up to TLB
+
+                0x02: tlbwi({{
+                                //Create PTE
+                                MipsISA::PTE NewEntry;
+                                //Write PTE
+                                NewEntry.Mask = (Addr)(PageMask >> 11);
+                                NewEntry.VPN = (Addr)(EntryHi >> 11);
+                                /*  PageGrain _ ESP                    Config3 _ SP */
+                                if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) {
+                                  NewEntry.Mask |= 0x3; // If 1KB pages are *NOT* enabled, lowest bits of the mask are 0b11 for TLB writes
+                                  NewEntry.VPN &= 0xFFFFFFFC; // Reset bits 0 and 1 if 1KB pages are not enabled
+                                }
+                                NewEntry.asid = (uint8_t)(EntryHi & 0xFF);
+
+                                NewEntry.PFN0 = (Addr)(EntryLo0 >> 6);
+                                NewEntry.PFN1 = (Addr)(EntryLo1 >> 6);
+                                NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
+                                NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
+                                NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
+                                NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
+                                NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
+                                NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);
+                                NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
+                                /* Now, compute the AddrShiftAmount and OffsetMask - TLB optimizations */
+                                /* Addr Shift Amount for 1KB or larger pages */
+                                //	    warn("PTE->Mask: %x\n",pte->Mask);
+                                if((NewEntry.Mask & 0xFFFF) == 3){
+                                  NewEntry.AddrShiftAmount = 12;
+                                } else if((NewEntry.Mask & 0xFFFF) == 0x0000){
+                                  NewEntry.AddrShiftAmount = 10;
+                                } else if((NewEntry.Mask & 0xFFFC) == 0x000C){
+                                  NewEntry.AddrShiftAmount = 14;
+                                } else if((NewEntry.Mask & 0xFFF0) == 0x0030){
+                                  NewEntry.AddrShiftAmount = 16;
+                                } else if((NewEntry.Mask & 0xFFC0) == 0x00C0){
+                                  NewEntry.AddrShiftAmount = 18;
+                                } else if((NewEntry.Mask & 0xFF00) == 0x0300){
+                                  NewEntry.AddrShiftAmount = 20;
+                                } else if((NewEntry.Mask & 0xFC00) == 0x0C00){
+                                  NewEntry.AddrShiftAmount = 22;
+                                } else if((NewEntry.Mask & 0xF000) == 0x3000){
+                                  NewEntry.AddrShiftAmount = 24;
+                                } else if((NewEntry.Mask & 0xC000) == 0xC000){
+                                  NewEntry.AddrShiftAmount = 26;
+                                } else if((NewEntry.Mask & 0x30000) == 0x30000){
+                                  NewEntry.AddrShiftAmount = 28;
+                                } else {
+                                  fatal("Invalid Mask Pattern Detected!\n");
+                                }
+                                NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1);
+
+                                MipsISA::TLB *Ptr=xc->tcBase()->getITBPtr();
+                                MiscReg c3=xc->readMiscReg(MipsISA::Config3);
+                                MiscReg pg=xc->readMiscReg(MipsISA::PageGrain);
+                                int SP=0;
+                                if(bits(c3,Config3_SP)==1 && bits(pg,PageGrain_ESP)==1){
+                                  SP=1;
+                                }
+                                Ptr->insertAt(NewEntry,Index & 0x7FFFFFFF,SP);
+              }});
+                0x06: tlbwr({{
+                                //Create PTE
+                                MipsISA::PTE NewEntry;
+                                //Write PTE
+                                NewEntry.Mask = (Addr)(PageMask >> 11);
+                                NewEntry.VPN = (Addr)(EntryHi >> 11);
+                                /*  PageGrain _ ESP                    Config3 _ SP */
+                                if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) {
+                                  NewEntry.Mask |= 0x3; // If 1KB pages are *NOT* enabled, lowest bits of the mask are 0b11 for TLB writes
+                                  NewEntry.VPN &= 0xFFFFFFFC; // Reset bits 0 and 1 if 1KB pages are not enabled
+                                }
+                                NewEntry.asid = (uint8_t)(EntryHi & 0xFF);
+
+                                NewEntry.PFN0 = (Addr)(EntryLo0 >> 6);
+                                NewEntry.PFN1 = (Addr)(EntryLo1 >> 6);
+                                NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
+                                NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
+                                NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
+                                NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
+                                NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
+                                NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);
+                                NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
+                                /* Now, compute the AddrShiftAmount and OffsetMask - TLB optimizations */
+                                /* Addr Shift Amount for 1KB or larger pages */
+                                //	    warn("PTE->Mask: %x\n",pte->Mask);
+                                if((NewEntry.Mask & 0xFFFF) == 3){
+                                  NewEntry.AddrShiftAmount = 12;
+                                } else if((NewEntry.Mask & 0xFFFF) == 0x0000){
+                                  NewEntry.AddrShiftAmount = 10;
+                                } else if((NewEntry.Mask & 0xFFFC) == 0x000C){
+                                  NewEntry.AddrShiftAmount = 14;
+                                } else if((NewEntry.Mask & 0xFFF0) == 0x0030){
+                                  NewEntry.AddrShiftAmount = 16;
+                                } else if((NewEntry.Mask & 0xFFC0) == 0x00C0){
+                                  NewEntry.AddrShiftAmount = 18;
+                                } else if((NewEntry.Mask & 0xFF00) == 0x0300){
+                                  NewEntry.AddrShiftAmount = 20;
+                                } else if((NewEntry.Mask & 0xFC00) == 0x0C00){
+                                  NewEntry.AddrShiftAmount = 22;
+                                } else if((NewEntry.Mask & 0xF000) == 0x3000){
+                                  NewEntry.AddrShiftAmount = 24;
+                                } else if((NewEntry.Mask & 0xC000) == 0xC000){
+                                  NewEntry.AddrShiftAmount = 26;
+                                } else if((NewEntry.Mask & 0x30000) == 0x30000){
+                                  NewEntry.AddrShiftAmount = 28;
+                                } else {
+                                  fatal("Invalid Mask Pattern Detected!\n");
+                                }
+                                NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1);
+
+                                MipsISA::TLB *Ptr=xc->tcBase()->getITBPtr();
+                                MiscReg c3=xc->readMiscReg(MipsISA::Config3);
+                                MiscReg pg=xc->readMiscReg(MipsISA::PageGrain);
+                                int SP=0;
+                                if(bits(c3,Config3_SP)==1 && bits(pg,PageGrain_ESP)==1){
+                                  SP=1;
+                                }
+                                Ptr->insertAt(NewEntry,Random,SP);
+                }});
+
+                0x08: tlbp({{
+                               int TLB_Index;
+                               Addr VPN;
+                               if(PageGrain_ESP == 1 && Config3_SP ==1){
+                                 VPN = EntryHi >> 11;
+                               } else {
+                                 VPN = ((EntryHi >> 11) & 0xFFFFFFFC); // Mask off lower 2 bits
+                               }
+                               TLB_Index = xc->tcBase()->getITBPtr()->probeEntry(VPN,EntryHi_ASID);
+                               if(TLB_Index != -1){  // Check TLB for entry matching EntryHi
+                                 Index=TLB_Index;
+                                 //			    warn("\ntlbp: Match Found!\n");
+                               } else {// else, set Index = 1<<31
+                                 Index = (1<<31);
+                               }
                         }});
               }
-
+              format CP0Unimpl {
-              format FailUnimpl {
-                  0x01: tlbr(); // Need to hook up to TLB
-                  0x02: tlbwi(); // Need to hook up to TLB
-                    0x06: tlbwr();// Need to hook up to TLB
-                    0x08: tlbp();// Need to hook up to TLB
-
                 0x20: wait();
               }
+               default: CP0Unimpl::unknown();
 
             }
         }
@@ -607,8 +863,9 @@ decode OPCODE_HI default Unknown::unknown() {
                                 Rt = FCSR;
                                 break;
                               default:
-                                panic("FP Control Value (%d) Not Valid");
+                                warn("FP Control Value (%d) Not Valid");
                             }
+                            //			    warn("FCSR: %x, FS: %d, FIR: %x, Rt: %x\n",FCSR, FS, FIR, Rt);
                         }});
 
                         0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}});
@@ -658,9 +915,16 @@ decode OPCODE_HI default Unknown::unknown() {
                         }});
 
                     }
+                    format CP1Unimpl {
+                      0x1: dmfc1();
+                      0x5: dmtc1();
+                    }
                    }
 
-                0x1: decode ND {
+                0x1:
+                   decode RS_LO {
+                     0x0:
+                     decode ND {
                        format Branch {
                          0x0: decode TF {
                            0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
@@ -676,6 +940,12 @@ decode OPCODE_HI default Unknown::unknown() {
                          }
                        }
                      }
+                   format CP1Unimpl {
+                     0x1: bc1any2();
+                     0x2: bc1any4();
+                     default: unknown();
+                   }
+                   }
             }
 
             0x1: decode RS_HI {
@@ -735,7 +1005,11 @@ decode OPCODE_HI default Unknown::unknown() {
                                 0x5: recip_s({{ Fd = 1 / Fs; }});
                                 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}});
                             }
+                            format CP1Unimpl {
+                              default: unknown();
                             }
+                        }
+                        0x3: CP1Unimpl::unknown();
 
                         0x4: decode FUNCTION_LO {
                             format FloatConvertOp {
@@ -748,7 +1022,11 @@ decode OPCODE_HI default Unknown::unknown() {
                                     Fd.ud = (uint64_t) Fs.uw << 32 |
                                             (uint64_t) Ft.uw;
                                 }});
+                            format CP1Unimpl {
+                              default: unknown();
                             }
+                        }
+                        0x5: CP1Unimpl::unknown();
 
                         0x6: decode FUNCTION_LO {
                             format FloatCompareOp {
@@ -851,14 +1129,18 @@ decode OPCODE_HI default Unknown::unknown() {
                                 0x5: recip_d({{ Fd.df = 1 / Fs.df }});
                                 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df) }});
                             }
+                            format CP1Unimpl {
+                              default: unknown();
                             }
 
+                        }
                         0x4: decode FUNCTION_LO {
                             format FloatConvertOp {
                                 0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle);
                                 0x4: cvt_w_d({{ val = Fs.df; }}, ToWord);
                                 0x5: cvt_l_d({{ val = Fs.df; }}, ToLong);
                             }
+                           default: CP1Unimpl::unknown();
                         }
 
                         0x6: decode FUNCTION_LO {
@@ -902,15 +1184,20 @@ decode OPCODE_HI default Unknown::unknown() {
                                              UnorderedTrue, QnanException);
                             }
                         }
+                       default: CP1Unimpl::unknown();
                     }
+                    0x2: CP1Unimpl::unknown();
+                    0x3: CP1Unimpl::unknown();
+                    0x7: CP1Unimpl::unknown();
 
                     //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
                     0x4: decode FUNCTION {
                         format FloatConvertOp {
                             0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle);
                             0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble);
-                            0x26: FailUnimpl::cvt_ps_w();
+                            0x26: CP1Unimpl::cvt_ps_w();
                         }
+                       default: CP1Unimpl::unknown();
                     }
 
                     //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1
@@ -920,8 +1207,9 @@ decode OPCODE_HI default Unknown::unknown() {
                         format FloatConvertOp {
                             0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle);
                             0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble);
-                            0x26: FailUnimpl::cvt_ps_l();
+                            0x26: CP1Unimpl::cvt_ps_l();
                         }
+                       default: CP1Unimpl::unknown();
                     }
 
                     //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1
@@ -954,9 +1242,10 @@ decode OPCODE_HI default Unknown::unknown() {
                                     Fd1.sf = -(Fs1.sf);
                                     Fd2.sf = -(Fs2.sf);
                                 }});
+                            default: CP1Unimpl::unknown();
                             }
                         }
-
+                        0x1: CP1Unimpl::unknown();
                         0x2: decode FUNCTION_LO {
                             0x1: decode MOVCF {
                                 format Float64Op {
@@ -989,11 +1278,13 @@ decode OPCODE_HI default Unknown::unknown() {
                                         Fs2 : Fd2;
                                 }});
                             }
+                           default: CP1Unimpl::unknown();
 
                         }
-
+                        0x3: CP1Unimpl::unknown();
                         0x4: decode FUNCTION_LO {
                             0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }});
+                            default: CP1Unimpl::unknown();
                         }
 
                         0x5: decode FUNCTION_LO {
@@ -1013,6 +1304,7 @@ decode OPCODE_HI default Unknown::unknown() {
                                                     Ft2.uw;
                                          }});
                             }
+                            default: CP1Unimpl::unknown();
                         }
 
                         0x6: decode FUNCTION_LO {
@@ -1071,12 +1363,13 @@ decode OPCODE_HI default Unknown::unknown() {
                         }
                     }
                 }
+               default: CP1Unimpl::unknown();
             }
         }
 
         //Table A-19 MIPS32 COP2 Encoding of rs Field
         0x2: decode RS_MSB {
-            format FailUnimpl {
+            format CP2Unimpl {
                 0x0: decode RS_HI {
                     0x0: decode RS_LO {
                         0x0: mfc2();
@@ -1085,20 +1378,28 @@ decode OPCODE_HI default Unknown::unknown() {
                         0x4: mtc2();
                         0x6: ctc2();
                         0x7: mftc2();
+                       default: unknown();
                     }
 
                     0x1: decode ND {
                         0x0: decode TF {
                             0x0: bc2f();
                             0x1: bc2t();
+                           default: unknown();
                         }
 
                         0x1: decode TF {
                             0x0: bc2fl();
                             0x1: bc2tl();
+                           default: unknown();
                         }
+                       default: unknown();
+
                        }
+              default: unknown();
+
               }
+            default: unknown();
             }
         }
 
@@ -1197,13 +1498,13 @@ decode OPCODE_HI default Unknown::unknown() {
             0x0: decode FUNCTION_LO {
                 0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd;
                                    Rd.sw = temp1<31:0>;
-                                }});
+                                }}, IntMultOp);
 
                 format HiLoRdSelValOp {
-                    0x0: madd({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.sd * Rt.sd); }});
+                  0x0: madd({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.sd * Rt.sd); }}, IntMultOp);
-                    0x1: maddu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.ud * Rt.ud); }});
+                    0x1: maddu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.ud * Rt.ud); }}, IntMultOp);
-                    0x4: msub({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.sd * Rt.sd); }});
+                    0x4: msub({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.sd * Rt.sd); }}, IntMultOp);
-                    0x5: msubu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.ud * Rt.ud); }});
+                    0x5: msubu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.ud * Rt.ud); }}, IntMultOp);
                 }
             }
 
@@ -1286,9 +1587,9 @@ decode OPCODE_HI default Unknown::unknown() {
                             0x5: subu_s_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB,
                                                               SATURATE, UNSIGNED, &dspctl ); }});
                             0x6: muleu_s_ph_qbl({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw,
-                                                                     MODE_L, &dspctl ); }});
+                                                                     MODE_L, &dspctl ); }}, IntMultOp);
                             0x7: muleu_s_ph_qbr({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw,
-                                                                     MODE_R, &dspctl ); }});
+                                                                     MODE_R, &dspctl ); }}, IntMultOp);
                         }
                     }
                     0x1: decode OP_LO {
@@ -1335,13 +1636,13 @@ decode OPCODE_HI default Unknown::unknown() {
                     0x3: decode OP_LO {
                         format DspIntOp {
                             0x4: muleq_s_w_phl({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw,
-                                                                    MODE_L, &dspctl ); }});
+                                                                    MODE_L, &dspctl ); }}, IntMultOp);
                             0x5: muleq_s_w_phr({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw,
-                                                                    MODE_R, &dspctl ); }});
+                                                                    MODE_R, &dspctl ); }}, IntMultOp);
                             0x6: mulq_s_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH,
-                                                               SATURATE, NOROUND, &dspctl ); }});
+                                                               SATURATE, NOROUND, &dspctl ); }}, IntMultOp);
                             0x7: mulq_rs_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH,
-                                                                SATURATE, ROUND, &dspctl ); }});
+                                                                SATURATE, ROUND, &dspctl ); }}, IntMultOp);
                         }
                     }
                 }
@@ -1559,9 +1860,10 @@ decode OPCODE_HI default Unknown::unknown() {
                             0x3: subqh_r_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH,
                                                                 ROUND, SIGNED ); }});
                             0x4: mul_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH,
-                                                           NOSATURATE, &dspctl ); }});
+                                                           NOSATURATE, &dspctl ); }}, IntMultOp);
                             0x6: mul_s_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH,
-                                                             SATURATE, &dspctl ); }});
+                                                             SATURATE, &dspctl ); }}, IntMultOp);
+
                         }
                     }
                     0x2: decode OP_LO {
@@ -1575,9 +1877,9 @@ decode OPCODE_HI default Unknown::unknown() {
                             0x3: subqh_r_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W,
                                                                ROUND, SIGNED ); }});
                             0x6: mulq_s_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W,
-                                                              SATURATE, NOROUND, &dspctl ); }});
+                                                              SATURATE, NOROUND, &dspctl ); }}, IntMultOp);
                             0x7: mulq_rs_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W,
-                                                               SATURATE, ROUND, &dspctl ); }});
+                                                               SATURATE, ROUND, &dspctl ); }}, IntMultOp);
                         }
                     }
                 }
@@ -1603,61 +1905,61 @@ decode OPCODE_HI default Unknown::unknown() {
                     0x0: decode OP_LO {
                         format DspHiLoOp {
                             0x0: dpa_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
-                                                             SIMD_FMT_PH, SIGNED, MODE_L ); }});
+                                                             SIMD_FMT_PH, SIGNED, MODE_L ); }}, IntMultOp);
                             0x1: dps_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
-                                                             SIMD_FMT_PH, SIGNED, MODE_L ); }});
+                                                             SIMD_FMT_PH, SIGNED, MODE_L ); }}, IntMultOp);
                             0x2: mulsa_w_ph({{ dspac = dspMulsa( dspac, Rs.sw, Rt.sw,
-                                                                 ACDST, SIMD_FMT_PH ); }});
+                                                                 ACDST, SIMD_FMT_PH ); }}, IntMultOp);
                             0x3: dpau_h_qbl({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
-                                                               SIMD_FMT_QB, UNSIGNED, MODE_L ); }});
+                                                               SIMD_FMT_QB, UNSIGNED, MODE_L ); }}, IntMultOp);
                             0x4: dpaq_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
-                                                                 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }});
+                                                                 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}, IntMultOp);
                             0x5: dpsq_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
-                                                                 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }});
+                                                                 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}, IntMultOp);
                             0x6: mulsaq_s_w_ph({{ dspac = dspMulsaq( dspac, Rs.sw, Rt.sw,
-                                                                     ACDST, SIMD_FMT_PH, &dspctl ); }});
+                                                                     ACDST, SIMD_FMT_PH, &dspctl ); }}, IntMultOp);
                             0x7: dpau_h_qbr({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
-                                                               SIMD_FMT_QB, UNSIGNED, MODE_R ); }});
+                                                               SIMD_FMT_QB, UNSIGNED, MODE_R ); }}, IntMultOp);
                         }
                     }
                     0x1: decode OP_LO {
                         format DspHiLoOp {
                             0x0: dpax_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
-                                                              SIMD_FMT_PH, SIGNED, MODE_X ); }});
+                                                              SIMD_FMT_PH, SIGNED, MODE_X ); }}, IntMultOp);
                             0x1: dpsx_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
-                                                              SIMD_FMT_PH, SIGNED, MODE_X ); }});
+                                                              SIMD_FMT_PH, SIGNED, MODE_X ); }}, IntMultOp);
                             0x3: dpsu_h_qbl({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
-                                                               SIMD_FMT_QB, UNSIGNED, MODE_L ); }});
+                                                               SIMD_FMT_QB, UNSIGNED, MODE_L ); }}, IntMultOp);
                             0x4: dpaq_sa_l_w({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W,
-                                                                 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }});
+                                                                 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}, IntMultOp);
                             0x5: dpsq_sa_l_w({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W,
-                                                                 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }});
+                                                                 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}, IntMultOp);
                             0x7: dpsu_h_qbr({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
-                                                               SIMD_FMT_QB, UNSIGNED, MODE_R ); }});
+                                                               SIMD_FMT_QB, UNSIGNED, MODE_R ); }}, IntMultOp);
                         }
                     }
                     0x2: decode OP_LO {
                         format DspHiLoOp {
                             0x0: maq_sa_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
-                                                                 MODE_L, SATURATE, &dspctl ); }});
+                                                                 MODE_L, SATURATE, &dspctl ); }}, IntMultOp);
                             0x2: maq_sa_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
-                                                                 MODE_R, SATURATE, &dspctl ); }});
+                                                                 MODE_R, SATURATE, &dspctl ); }}, IntMultOp);
                             0x4: maq_s_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
-                                                                 MODE_L, NOSATURATE, &dspctl ); }});
+                                                                 MODE_L, NOSATURATE, &dspctl ); }}, IntMultOp);
                             0x6: maq_s_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
-                                                                 MODE_R, NOSATURATE, &dspctl ); }});
+                                                                 MODE_R, NOSATURATE, &dspctl ); }}, IntMultOp);
                         }
                     }
                     0x3: decode OP_LO {
                         format DspHiLoOp {
                             0x0: dpaqx_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
-                                                                  SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }});
+                                                                  SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}, IntMultOp);
                             0x1: dpsqx_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
-                                                                  SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }});
+                                                                  SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}, IntMultOp);
                             0x2: dpaqx_sa_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
-                                                                   SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }});
+                                                                   SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}, IntMultOp);
                             0x3: dpsqx_sa_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
-                                                                   SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }});
+                                                                   SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}, IntMultOp);
                         }
                     }
                 }
@@ -1677,9 +1979,7 @@ decode OPCODE_HI default Unknown::unknown() {
                     }
                 }
 
-                0x7: FailUnimpl::rdhwr();
             }
-
             0x7: decode FUNCTION_LO {
 
                 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field (DSP ASE MANUAL)
@@ -1735,17 +2035,22 @@ decode OPCODE_HI default Unknown::unknown() {
                         }
                     }
                 }
+                0x3: decode OP_HI {
+                    0x2: decode OP_LO {
+                        0x3: FailUnimpl::rdhwr();
+                    }
+                }
             }
         }
     }
 
     0x4: decode OPCODE_LO {
         format LoadMemory {
-            0x0: lb({{ Rt.sw = Mem.sb; }});
+          0x0: lb({{ Rt.sw = Mem.sb; }}, mem_flags = NO_ALIGN_FAULT);
-            0x1: lh({{ Rt.sw = Mem.sh; }});
+          0x1: lh({{ Rt.sw = Mem.sh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT);
             0x3: lw({{ Rt.sw = Mem.sw; }});
-            0x4: lbu({{ Rt.uw = Mem.ub; }});
+            0x4: lbu({{ Rt.uw = Mem.ub;}}, mem_flags = NO_ALIGN_FAULT);
-            0x5: lhu({{ Rt.uw = Mem.uh; }});
+            0x5: lhu({{ Rt.uw = Mem.uh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT);
         }
 
         format LoadUnalignedMemory {
@@ -1762,8 +2067,8 @@ decode OPCODE_HI default Unknown::unknown() {
 
     0x5: decode OPCODE_LO {
         format StoreMemory {
-            0x0: sb({{ Mem.ub = Rt<7:0>; }});
+            0x0: sb({{ Mem.ub = Rt<7:0>; }}, mem_flags = NO_ALIGN_FAULT);
-            0x1: sh({{ Mem.uh = Rt<15:0>; }});
+            0x1: sh({{ Mem.uh = Rt<15:0>; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT);
             0x3: sw({{ Mem.uw = Rt<31:0>; }});
         }
 
@@ -1778,8 +2083,12 @@ decode OPCODE_HI default Unknown::unknown() {
                                    mem_word & (mask(reg_shift));
                      }});
         }
-
+        format CP0Control {
-        0x7: FailUnimpl::cache();
+            0x7: cache({{
+                           Addr CacheEA = Rs.uw + OFFSET;
+                           fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA);
+                         }});
+        }
     }
 
     0x6: decode OPCODE_LO {
@@ -1788,7 +2097,8 @@ decode OPCODE_HI default Unknown::unknown() {
             0x1: lwc1({{ Ft.uw = Mem.uw; }});
             0x5: ldc1({{ Ft.ud = Mem.ud; }});
         }
-
+        0x2: CP2Unimpl::lwc2();
+        0x6: CP2Unimpl::ldc2();
         0x3: Prefetch::pref();
     }
 
@@ -1800,9 +2110,13 @@ decode OPCODE_HI default Unknown::unknown() {
                            }}, mem_flags=LOCKED, inst_flags = IsStoreConditional);
 
         format StoreMemory {
-            0x1: swc1({{ Mem.uw = Ft.uw; }});
+          0x1: swc1({{ Mem.uw = Ft.uw;}});
-            0x5: sdc1({{ Mem.ud = Ft.ud; }});
+          0x5: sdc1({{ Mem.ud = Ft.ud;}});
         }
+
+        0x2: CP2Unimpl::swc2();
+        0x6: CP2Unimpl::sdc2();
+
     }
 }
 

src/arch/mips/isa/formats/basic.isa

@@ -1,33 +1,39 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-// All rights reserved.
+
-//
+//  This software is part of the M5 simulator.
-// Redistribution and use in source and binary forms, with or without
+
-// modification, are permitted provided that the following conditions are
+//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-// met: redistributions of source code must retain the above copyright
+//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-// notice, this list of conditions and the following disclaimer;
+//  TO THESE TERMS AND CONDITIONS.
-// redistributions in binary form must reproduce the above copyright
+
-// notice, this list of conditions and the following disclaimer in the
+//  Permission is granted to use, copy, create derivative works and
-// documentation and/or other materials provided with the distribution;
+//  distribute this software and such derivative works for any purpose,
-// neither the name of the copyright holders nor the names of its
+//  so long as (1) the copyright notice above, this grant of permission,
-// contributors may be used to endorse or promote products derived from
+//  and the disclaimer below appear in all copies and derivative works
-// this software without specific prior written permission.
+//  made, (2) the copyright notice above is augmented as appropriate to
-//
+//  reflect the addition of any new copyrightable work in a derivative
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  advertising or publicity pertaining to the use or distribution of
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  this software without specific, written prior authorization.
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//
+//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-// Authors: Steve Reinhardt
+//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
-//          Korey Sewell
+//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Steven K. Reinhardt
+//         Korey L. Sewell
 
 // Declarations for execute() methods.
 def template BasicExecDeclare {{
@@ -66,12 +72,13 @@ def template BasicExecute {{
                 %(fp_enable_check)s;
                 %(op_decl)s;
                 %(op_rd)s;
-                %(code)s;
-
                 if(fault == NoFault)
                 {
+                  %(code)s;
+                  if(fault == NoFault){
                     %(op_wb)s;
                   }
+                }
                 return fault;
         }
 }};

src/arch/mips/isa/formats/branch.isa

@@ -1,32 +1,38 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-// All rights reserved.
+
-//
+//  This software is part of the M5 simulator.
-// Redistribution and use in source and binary forms, with or without
+
-// modification, are permitted provided that the following conditions are
+//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-// met: redistributions of source code must retain the above copyright
+//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-// notice, this list of conditions and the following disclaimer;
+//  TO THESE TERMS AND CONDITIONS.
-// redistributions in binary form must reproduce the above copyright
+
-// notice, this list of conditions and the following disclaimer in the
+//  Permission is granted to use, copy, create derivative works and
-// documentation and/or other materials provided with the distribution;
+//  distribute this software and such derivative works for any purpose,
-// neither the name of the copyright holders nor the names of its
+//  so long as (1) the copyright notice above, this grant of permission,
-// contributors may be used to endorse or promote products derived from
+//  and the disclaimer below appear in all copies and derivative works
-// this software without specific prior written permission.
+//  made, (2) the copyright notice above is augmented as appropriate to
-//
+//  reflect the addition of any new copyrightable work in a derivative
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  advertising or publicity pertaining to the use or distribution of
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  this software without specific, written prior authorization.
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//
+//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-// Authors: Korey Sewell
+//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
 
 ////////////////////////////////////////////////////////////////////
 //
@@ -133,9 +139,8 @@ output decoder {{
     Addr
     Jump::branchTarget(ThreadContext *tc) const
     {
-        Addr NPC = tc->readPC() + 4;
+      Addr NPC = tc->readNextPC();
-        uint64_t Rb = tc->readIntReg(_srcRegIdx[0]);
+      return (NPC & 0xF0000000) | (disp);
-        return (Rb & ~3) | (NPC & 1);
     }
 
     const std::string &
@@ -196,7 +201,7 @@ output decoder {{
 
         ccprintf(ss, "%-10s ", mnemonic);
 
-        if (strcmp(mnemonic, "jal") == 0) {
+        if ( mnemonic == "jal" ) {
             Addr npc = pc + 4;
             ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp);
         } else if (_numSrcRegs == 0) {

src/arch/mips/isa/formats/control.isa

@@ -1,32 +1,39 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
-// All rights reserved.
+
-//
+//  This software is part of the M5 simulator.
-// Redistribution and use in source and binary forms, with or without
+
-// modification, are permitted provided that the following conditions are
+//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-// met: redistributions of source code must retain the above copyright
+//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-// notice, this list of conditions and the following disclaimer;
+//  TO THESE TERMS AND CONDITIONS.
-// redistributions in binary form must reproduce the above copyright
+
-// notice, this list of conditions and the following disclaimer in the
+//  Permission is granted to use, copy, create derivative works and
-// documentation and/or other materials provided with the distribution;
+//  distribute this software and such derivative works for any purpose,
-// neither the name of the copyright holders nor the names of its
+//  so long as (1) the copyright notice above, this grant of permission,
-// contributors may be used to endorse or promote products derived from
+//  and the disclaimer below appear in all copies and derivative works
-// this software without specific prior written permission.
+//  made, (2) the copyright notice above is augmented as appropriate to
-//
+//  reflect the addition of any new copyrightable work in a derivative
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  advertising or publicity pertaining to the use or distribution of
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  this software without specific, written prior authorization.
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//
+//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-// Authors: Korey Sewell
+//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
+//         Jaidev Patwardhan
 
 ////////////////////////////////////////////////////////////////////
 //
@@ -48,6 +55,19 @@ output header {{
 
                 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
         };
+        class CP0TLB : public MipsStaticInst
+        {
+                protected:
+
+                /// Constructor
+                CP0TLB(const char *mnem, MachInst _machInst, OpClass __opClass) :
+                           MipsStaticInst(mnem, _machInst, __opClass)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        };
+
 
         class CP1Control : public MipsStaticInst
         {
@@ -65,7 +85,7 @@ output header {{
 }};
 
 // Basic instruction class execute method template.
-def template ControlExecute {{
+def template CP0Execute {{
         Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
         {
                 Fault fault = NoFault;
@@ -75,7 +95,7 @@ def template ControlExecute {{
                 if (isCoprocessorEnabled(xc, 0)) {
                     %(code)s;
                 } else {
-                    fault = new CoprocessorUnusableFault();
+                    fault = new CoprocessorUnusableFault(0);
                 }
 
                 if(fault == NoFault)
@@ -86,6 +106,57 @@ def template ControlExecute {{
         }
 }};
 
+def template CP1Execute {{
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+        {
+                Fault fault = NoFault;
+                %(op_decl)s;
+                %(op_rd)s;
+
+                if (isCoprocessorEnabled(xc, 1)) {
+                    %(code)s;
+                } else {
+                    fault = new CoprocessorUnusableFault(1);
+                }
+
+                if(fault == NoFault)
+                {
+                    %(op_wb)s;
+                }
+                return fault;
+        }
+}};
+// Basic instruction class execute method template.
+def template ControlTLBExecute {{
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+        {
+                Fault fault = NoFault;
+                %(op_decl)s;
+                %(op_rd)s;
+
+#if FULL_SYSTEM
+                if (isCoprocessor0Enabled(xc)) {
+                  if(isMMUTLB(xc)){
+                      %(code)s;
+                  } else {
+                    fault = new ReservedInstructionFault();
+                  }
+                } else {
+                  fault = new CoprocessorUnusableFault(0);
+                }
+#else // Syscall Emulation Mode - No TLB Instructions
+                fault = new ReservedInstructionFault();
+#endif
+
+                if(fault == NoFault)
+                {
+                    %(op_wb)s;
+                }
+                return fault;
+
+        }
+}};
+
 //Outputs to decoder.cc
 output decoder {{
         std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
@@ -94,7 +165,12 @@ output decoder {{
             ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
             return ss.str();
         }
-
+        std::string CP0TLB::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+            std::stringstream ss;
+            ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
+            return ss.str();
+        }
         std::string CP1Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
         {
             std::stringstream ss;
@@ -107,29 +183,65 @@ output decoder {{
 output exec {{
         bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
         {
+          MiscReg Stat = xc->readMiscReg(MipsISA::Status);
           switch(cop_num)
             {
             case 0:
+              {
 #if FULL_SYSTEM
-              if((xc->readMiscReg(MipsISA::Status) & 0x10000006) == 0 && (xc->readMiscReg(MipsISA::Debug) & 0x40000000 ) == 0) {
+              MiscReg Dbg = xc->readMiscReg(MipsISA::Debug);
+              if((Stat & 0x10000006) == 0  // EXL, ERL or CU0 set, CP0 accessible
+                 && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
+                 && (Stat & 0x00000018) != 0) {  // KSU = 0, kernel mode is base mode
                 // Unable to use Status_CU0, etc directly, using bitfields & masks
                   return false;
               }
 #else
               //printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n");
 #endif
+              }
               break;
             case 1:
+              if((Stat & 0x20000000) == 0) // CU1 is reset
+                return false;
               break;
             case 2:
+              if((Stat & 0x40000000) == 0) // CU2 is reset
+                return false;
               break;
             case 3:
+              if((Stat & 0x80000000) == 0) // CU3 is reset
+                return false;
               break;
             default: panic("Invalid Coprocessor Number Specified");
               break;
             }
             return true;
         }
+        bool inline isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
+        {
+#if FULL_SYSTEM
+          MiscReg Stat = xc->readMiscRegNoEffect(MipsISA::Status);
+          MiscReg Dbg = xc->readMiscRegNoEffect(MipsISA::Debug);
+          if((Stat & 0x10000006) == 0  // EXL, ERL or CU0 set, CP0 accessible
+                 && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
+                 && (Stat & 0x00000018) != 0) {  // KSU = 0, kernel mode is base mode
+                // Unable to use Status_CU0, etc directly, using bitfields & masks
+                  return false;
+              }
+#else
+              //printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n");
+#endif
+            return true;
+        }
+        bool isMMUTLB(%(CPU_exec_context)s *xc)
+        {
+#if FULL_SYSTEM
+          if((xc->readMiscRegNoEffect(MipsISA::Config) & 0x00000380)==0x80)
+            return true;
+#endif
+          return false;
+        }
 }};
 
 def format CP0Control(code, *flags) {{
@@ -138,16 +250,23 @@ def format CP0Control(code, *flags) {{
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
     decode_block = BasicDecode.subst(iop)
-    exec_output = ControlExecute.subst(iop)
+    exec_output = CP0Execute.subst(iop)
+}};
+def format CP0TLB(code, *flags) {{
+    flags += ('IsNonSpeculative', )
+    iop = InstObjParams(name, Name, 'CP0Control', code, flags)
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = ControlTLBExecute.subst(iop)
 }};
-
 def format CP1Control(code, *flags) {{
     flags += ('IsNonSpeculative', )
     iop = InstObjParams(name, Name, 'CP1Control', code, flags)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
     decode_block = BasicDecode.subst(iop)
-    exec_output = ControlExecute.subst(iop)
+    exec_output = CP1Execute.subst(iop)
 }};
 
 

src/arch/mips/isa/formats/dsp.isa

@@ -1,32 +1,39 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
-// All rights reserved.
+
-//
+//  This software is part of the M5 simulator.
-// Redistribution and use in source and binary forms, with or without
+
-// modification, are permitted provided that the following conditions are
+//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-// met: redistributions of source code must retain the above copyright
+//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-// notice, this list of conditions and the following disclaimer;
+//  TO THESE TERMS AND CONDITIONS.
-// redistributions in binary form must reproduce the above copyright
+
-// notice, this list of conditions and the following disclaimer in the
+//  Permission is granted to use, copy, create derivative works and
-// documentation and/or other materials provided with the distribution;
+//  distribute this software and such derivative works for any purpose,
-// neither the name of the copyright holders nor the names of its
+//  so long as (1) the copyright notice above, this grant of permission,
-// contributors may be used to endorse or promote products derived from
+//  and the disclaimer below appear in all copies and derivative works
-// this software without specific prior written permission.
+//  made, (2) the copyright notice above is augmented as appropriate to
-//
+//  reflect the addition of any new copyrightable work in a derivative
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  advertising or publicity pertaining to the use or distribution of
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  this software without specific, written prior authorization.
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//
+//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-// Authors: Korey Sewell
+//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
+//         Brett Miller
 
 ////////////////////////////////////////////////////////////////////
 //
@@ -177,6 +184,8 @@ def format DspIntOp(code, *opt_flags) {{
 
     code = decl_code + code + write_code
 
+    opt_flags += ('IsDspOp',)
+
     iop = InstObjParams(name, Name, 'DspIntOp', code, opt_flags)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
@@ -206,6 +215,8 @@ def format DspHiLoOp(code, *opt_flags) {{
 
     code = decl_code + fetch_code + code + write_code
 
+    opt_flags += ('IsDspOp',)
+
     iop = InstObjParams(name, Name, 'DspHiLoOp', code, opt_flags)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)

src/arch/mips/isa/formats/formats.isa

@@ -1,32 +1,38 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2003-2006 The Regents of The University of Michigan
+// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-// All rights reserved.
+
-//
+//  This software is part of the M5 simulator.
-// Redistribution and use in source and binary forms, with or without
+
-// modification, are permitted provided that the following conditions are
+//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-// met: redistributions of source code must retain the above copyright
+//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-// notice, this list of conditions and the following disclaimer;
+//  TO THESE TERMS AND CONDITIONS.
-// redistributions in binary form must reproduce the above copyright
+
-// notice, this list of conditions and the following disclaimer in the
+//  Permission is granted to use, copy, create derivative works and
-// documentation and/or other materials provided with the distribution;
+//  distribute this software and such derivative works for any purpose,
-// neither the name of the copyright holders nor the names of its
+//  so long as (1) the copyright notice above, this grant of permission,
-// contributors may be used to endorse or promote products derived from
+//  and the disclaimer below appear in all copies and derivative works
-// this software without specific prior written permission.
+//  made, (2) the copyright notice above is augmented as appropriate to
-//
+//  reflect the addition of any new copyrightable work in a derivative
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  advertising or publicity pertaining to the use or distribution of
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  this software without specific, written prior authorization.
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//
+//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-// Authors: Korey Sewell
+//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
 
 //Templates from this format are used later
 //Include the basic format

src/arch/mips/isa/formats/fp.isa

@@ -1,32 +1,38 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
-// All rights reserved.
+
-//
+//  This software is part of the M5 simulator.
-// Redistribution and use in source and binary forms, with or without
+
-// modification, are permitted provided that the following conditions are
+//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-// met: redistributions of source code must retain the above copyright
+//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-// notice, this list of conditions and the following disclaimer;
+//  TO THESE TERMS AND CONDITIONS.
-// redistributions in binary form must reproduce the above copyright
+
-// notice, this list of conditions and the following disclaimer in the
+//  Permission is granted to use, copy, create derivative works and
-// documentation and/or other materials provided with the distribution;
+//  distribute this software and such derivative works for any purpose,
-// neither the name of the copyright holders nor the names of its
+//  so long as (1) the copyright notice above, this grant of permission,
-// contributors may be used to endorse or promote products derived from
+//  and the disclaimer below appear in all copies and derivative works
-// this software without specific prior written permission.
+//  made, (2) the copyright notice above is augmented as appropriate to
-//
+//  reflect the addition of any new copyrightable work in a derivative
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  advertising or publicity pertaining to the use or distribution of
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  this software without specific, written prior authorization.
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//
+//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-// Authors: Korey Sewell
+//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
 
 ////////////////////////////////////////////////////////////////////
 //
@@ -91,6 +97,9 @@ output exec {{
         {
             //@TODO: Implement correct CP0 checks to see if the CP1
             // unit is enable or not
+          if (!isCoprocessorEnabled(xc, 1))
+             return new CoprocessorUnusableFault(1);
+
           return NoFault;
         }
 
@@ -183,6 +192,7 @@ def template FloatingPointExecute {{
 
                 %(fp_enable_check)s;
 
+
                 //When is the right time to reset cause bits?
                 //start of every instruction or every cycle?
 #if FULL_SYSTEM

src/arch/mips/isa/formats/int.isa

@@ -1,32 +1,38 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-// All rights reserved.
+
-//
+//  This software is part of the M5 simulator.
-// Redistribution and use in source and binary forms, with or without
+
-// modification, are permitted provided that the following conditions are
+//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-// met: redistributions of source code must retain the above copyright
+//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-// notice, this list of conditions and the following disclaimer;
+//  TO THESE TERMS AND CONDITIONS.
-// redistributions in binary form must reproduce the above copyright
+
-// notice, this list of conditions and the following disclaimer in the
+//  Permission is granted to use, copy, create derivative works and
-// documentation and/or other materials provided with the distribution;
+//  distribute this software and such derivative works for any purpose,
-// neither the name of the copyright holders nor the names of its
+//  so long as (1) the copyright notice above, this grant of permission,
-// contributors may be used to endorse or promote products derived from
+//  and the disclaimer below appear in all copies and derivative works
-// this software without specific prior written permission.
+//  made, (2) the copyright notice above is augmented as appropriate to
-//
+//  reflect the addition of any new copyrightable work in a derivative
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  advertising or publicity pertaining to the use or distribution of
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  this software without specific, written prior authorization.
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//
+//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-// Authors: Korey Sewell
+//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
 
 ////////////////////////////////////////////////////////////////////
 //
@@ -119,7 +125,7 @@ output header {{
                 {
                     //If Bit 15 is 1 then Sign Extend
                     int32_t temp = sextImm & 0x00008000;
-                    if (temp > 0 && strcmp(mnemonic, "lui") != 0) {
+                    if (temp > 0 && mnemonic != "lui") {
                         sextImm |= 0xFFFF0000;
                     }
                 }
@@ -313,7 +319,7 @@ output decoder {{
                 ss << ", ";
             }
 
-            if (strcmp(mnemonic, "lui") == 0)
+            if( mnemonic == "lui")
                 ccprintf(ss, "0x%x ", sextImm);
             else
                 ss << (int) sextImm;

src/arch/mips/isa/formats/mem.isa

@@ -1,33 +1,39 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-// All rights reserved.
+
-//
+//  This software is part of the M5 simulator.
-// Redistribution and use in source and binary forms, with or without
+
-// modification, are permitted provided that the following conditions are
+//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-// met: redistributions of source code must retain the above copyright
+//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-// notice, this list of conditions and the following disclaimer;
+//  TO THESE TERMS AND CONDITIONS.
-// redistributions in binary form must reproduce the above copyright
+
-// notice, this list of conditions and the following disclaimer in the
+//  Permission is granted to use, copy, create derivative works and
-// documentation and/or other materials provided with the distribution;
+//  distribute this software and such derivative works for any purpose,
-// neither the name of the copyright holders nor the names of its
+//  so long as (1) the copyright notice above, this grant of permission,
-// contributors may be used to endorse or promote products derived from
+//  and the disclaimer below appear in all copies and derivative works
-// this software without specific prior written permission.
+//  made, (2) the copyright notice above is augmented as appropriate to
-//
+//  reflect the addition of any new copyrightable work in a derivative
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  advertising or publicity pertaining to the use or distribution of
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  this software without specific, written prior authorization.
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//
+//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-// Authors: Steve Reinhardt
+//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
-//          Korey Sewell
+//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Steve Reinhardt
+//         Korey L. Sewell
 
 ////////////////////////////////////////////////////////////////////
 //
@@ -117,19 +123,19 @@ output exec {{
     /** return data in cases where there the size of data is only
         known in the packet
     */
-    uint64_t getStoreData(%(CPU_exec_context)s *xc, Packet *packet) {
+    uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet) {
         switch (packet->getSize())
         {
-          case 8:
+          case 1:
             return packet->get<uint8_t>();
 
-          case 16:
+          case 2:
             return packet->get<uint16_t>();
 
-          case 32:
+          case 4:
             return packet->get<uint32_t>();
 
-          case 864:
+          case 8:
             return packet->get<uint64_t>();
 
           default:
@@ -204,6 +210,15 @@ def template MemAccSizeDeclare {{
     int memAccSize(%(CPU_exec_context)s *xc);
 }};
 
+
+def template MiscMemAccSize {{
+    int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
+    {
+        panic("Misc instruction does not support split access method!");
+        return 0;
+    }
+}};
+
 def template EACompConstructor {{
     /** TODO: change op_class to AddrGenOp or something (requires
      * creating new member of OpClass enum in op_class.hh, updating
@@ -243,7 +258,13 @@ def template EACompExecute {{
         Addr EA;
         Fault fault = NoFault;
 
+        if (this->isFloating()) {
             %(fp_enable_check)s;
+
+            if(fault != NoFault)
+                return fault;
+        }
+
         %(op_decl)s;
         %(op_rd)s;
         %(ea_code)s;
@@ -257,14 +278,47 @@ def template EACompExecute {{
     }
 }};
 
+def template LoadStoreFPEACompExecute {{
+    Fault
+    %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
+                                   Trace::InstRecord *traceData) const
+    {
+        Addr EA;
+        Fault fault = NoFault;
+
+        %(fp_enable_check)s;
+        if(fault != NoFault)
+          return fault;
+        %(op_decl)s;
+        %(op_rd)s;
+        %(ea_code)s;
+
+        // NOTE: Trace Data is written using execute or completeAcc templates
+        if (fault == NoFault) {
+            xc->setEA(EA);
+        }
+
+        return fault;
+    }
+}};
+
+
 def template LoadMemAccExecute {{
     Fault
     %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
                                    Trace::InstRecord *traceData) const
     {
         Addr EA;
+
         Fault fault = NoFault;
 
+        if (this->isFloating()) {
+            %(fp_enable_check)s;
+
+            if(fault != NoFault)
+                return fault;
+        }
+
         %(op_decl)s;
         %(op_rd)s;
 
@@ -288,7 +342,13 @@ def template LoadExecute {{
         Addr EA;
         Fault fault = NoFault;
 
+        if (this->isFloating()) {
             %(fp_enable_check)s;
+
+            if(fault != NoFault)
+                return fault;
+        }
+
         %(op_decl)s;
         %(op_rd)s;
         %(ea_code)s;
@@ -314,7 +374,13 @@ def template LoadInitiateAcc {{
         Addr EA;
         Fault fault = NoFault;
 
+        if (this->isFloating()) {
             %(fp_enable_check)s;
+
+            if(fault != NoFault)
+                return fault;
+        }
+
         %(op_src_decl)s;
         %(op_rd)s;
         %(ea_code)s;
@@ -334,7 +400,13 @@ def template LoadCompleteAcc {{
     {
         Fault fault = NoFault;
 
+        if (this->isFloating()) {
             %(fp_enable_check)s;
+
+            if(fault != NoFault)
+                return fault;
+        }
+
         %(op_decl)s;
         %(op_rd)s;
 
@@ -353,7 +425,6 @@ def template LoadCompleteAcc {{
 }};
 
 
-
 def template LoadStoreMemAccSize {{
     int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
     {
@@ -461,6 +532,43 @@ def template StoreExecute {{
     }
 }};
 
+
+def template StoreFPExecute {{
+    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+                                  Trace::InstRecord *traceData) const
+    {
+        Addr EA;
+        Fault fault = NoFault;
+
+        %(fp_enable_check)s;
+        if(fault != NoFault)
+          return fault;
+        %(op_decl)s;
+        %(op_rd)s;
+        %(ea_code)s;
+
+        if (fault == NoFault) {
+            %(memacc_code)s;
+        }
+
+        if (fault == NoFault) {
+            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
+                              memAccessFlags, NULL);
+            if (traceData) { traceData->setData(Mem); }
+        }
+
+        if (fault == NoFault) {
+            %(postacc_code)s;
+        }
+
+        if (fault == NoFault) {
+            %(op_wb)s;
+        }
+
+        return fault;
+    }
+}};
+
 def template StoreCondExecute {{
     Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
@@ -540,7 +648,31 @@ def template StoreCompleteAcc {{
         if (fault == NoFault) {
             %(op_wb)s;
 
-            if (traceData) { traceData->setData(getStoreData(xc, pkt)); }
+            if (traceData) { traceData->setData(getMemData(xc, pkt)); }
+        }
+
+        return fault;
+    }
+}};
+
+
+def template StoreCompleteAcc {{
+    Fault %(class_name)s::completeAcc(Packet *pkt,
+                                      %(CPU_exec_context)s *xc,
+                                      Trace::InstRecord *traceData) const
+    {
+        Fault fault = NoFault;
+
+        %(op_dest_decl)s;
+
+        if (fault == NoFault) {
+            %(postacc_code)s;
+        }
+
+        if (fault == NoFault) {
+            %(op_wb)s;
+
+            if (traceData) { traceData->setData(getMemData(xc, pkt)); }
         }
 
         return fault;
@@ -650,6 +782,7 @@ def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
                       exec_template_base = 'Load')
 }};
 
+
 def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
                      mem_flags = [], inst_flags = []) {{
     (header_output, decoder_output, decode_block, exec_output) = \
@@ -659,6 +792,7 @@ def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
 
 def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
                      mem_flags = [], inst_flags = []) {{
+    inst_flags += ['IsIndexed']
     (header_output, decoder_output, decode_block, exec_output) = \
         LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
                       decode_template = ImmNopCheckDecode,
@@ -667,11 +801,30 @@ def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
 
 def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
                      mem_flags = [], inst_flags = []) {{
+    inst_flags += ['IsIndexed']
     (header_output, decoder_output, decode_block, exec_output) = \
         LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
                       exec_template_base = 'Store')
 }};
 
+def format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
+                     mem_flags = [], inst_flags = []) {{
+    inst_flags += ['IsIndexed', 'IsFloating']
+    (header_output, decoder_output, decode_block, exec_output) = \
+        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+                      decode_template = ImmNopCheckDecode,
+                      exec_template_base = 'Load')
+}};
+
+def format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
+                     mem_flags = [], inst_flags = []) {{
+    inst_flags += ['IsIndexed', 'IsFloating']
+    (header_output, decoder_output, decode_block, exec_output) = \
+        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+                      exec_template_base = 'Store')
+}};
+
+
 def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
                      mem_flags = [], inst_flags = []) {{
     decl_code = 'uint32_t mem_word = Mem.uw;\n'

src/arch/mips/isa/formats/mt.isa

@@ -1,32 +1,38 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-// All rights reserved.
+
-//
+//  This software is part of the M5 simulator.
-// Redistribution and use in source and binary forms, with or without
+
-// modification, are permitted provided that the following conditions are
+//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-// met: redistributions of source code must retain the above copyright
+//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-// notice, this list of conditions and the following disclaimer;
+//  TO THESE TERMS AND CONDITIONS.
-// redistributions in binary form must reproduce the above copyright
+
-// notice, this list of conditions and the following disclaimer in the
+//  Permission is granted to use, copy, create derivative works and
-// documentation and/or other materials provided with the distribution;
+//  distribute this software and such derivative works for any purpose,
-// neither the name of the copyright holders nor the names of its
+//  so long as (1) the copyright notice above, this grant of permission,
-// contributors may be used to endorse or promote products derived from
+//  and the disclaimer below appear in all copies and derivative works
-// this software without specific prior written permission.
+//  made, (2) the copyright notice above is augmented as appropriate to
-//
+//  reflect the addition of any new copyrightable work in a derivative
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  advertising or publicity pertaining to the use or distribution of
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  this software without specific, written prior authorization.
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//
+//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-// Authors: Korey Sewell
+//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
 
 ////////////////////////////////////////////////////////////////////
 //
@@ -72,9 +78,9 @@ output decoder {{
     {
         std::stringstream ss;
 
-        if (strcmp(mnemonic, "mttc0") == 0 || strcmp(mnemonic, "mftc0") == 0) {
+        if (mnemonic == "mttc0" || mnemonic == "mftc0") {
             ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL);
-        } else if (strcmp(mnemonic, "mftgpr") == 0) {
+        } else if (mnemonic == "mftgpr") {
             ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT);
         } else {
             ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD);
@@ -96,7 +102,7 @@ output exec {{
 
     void getMTExValues(%(CPU_exec_context)s *xc, unsigned &config3)
     {
-        config3 = xc->readMiscReg(Config3_MT);
+        config3 = xc->readMiscReg(Config3);
     }
 }};
 
@@ -135,7 +141,7 @@ def template ThreadRegisterExecute {{
                     %(code)s;
                 }
             } else {
-                fault = new CoprocessorUnusableFault();
+                fault = new CoprocessorUnusableFault(0);
             }
 
             if(fault == NoFault)
@@ -165,7 +171,7 @@ def template MTExecute{{
                         fault = new ReservedInstructionFault();
                     }
                 } else {
-                    fault = new CoprocessorUnusableFault();
+                    fault = new CoprocessorUnusableFault(0);
                 }
 
                 if(fault == NoFault)

src/arch/mips/isa/formats/noop.isa

@@ -1,32 +1,38 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-// All rights reserved.
+
-//
+//  This software is part of the M5 simulator.
-// Redistribution and use in source and binary forms, with or without
+
-// modification, are permitted provided that the following conditions are
+//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-// met: redistributions of source code must retain the above copyright
+//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-// notice, this list of conditions and the following disclaimer;
+//  TO THESE TERMS AND CONDITIONS.
-// redistributions in binary form must reproduce the above copyright
+
-// notice, this list of conditions and the following disclaimer in the
+//  Permission is granted to use, copy, create derivative works and
-// documentation and/or other materials provided with the distribution;
+//  distribute this software and such derivative works for any purpose,
-// neither the name of the copyright holders nor the names of its
+//  so long as (1) the copyright notice above, this grant of permission,
-// contributors may be used to endorse or promote products derived from
+//  and the disclaimer below appear in all copies and derivative works
-// this software without specific prior written permission.
+//  made, (2) the copyright notice above is augmented as appropriate to
-//
+//  reflect the addition of any new copyrightable work in a derivative
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  advertising or publicity pertaining to the use or distribution of
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  this software without specific, written prior authorization.
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//
+//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-// Authors: Korey Sewell
+//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
 
 ////////////////////////////////////////////////////////////////////
 //

src/arch/mips/isa/formats/tlbop.isa

@@ -1,32 +1,38 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-// All rights reserved.
+
-//
+//  This software is part of the M5 simulator.
-// Redistribution and use in source and binary forms, with or without
+
-// modification, are permitted provided that the following conditions are
+//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-// met: redistributions of source code must retain the above copyright
+//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-// notice, this list of conditions and the following disclaimer;
+//  TO THESE TERMS AND CONDITIONS.
-// redistributions in binary form must reproduce the above copyright
+
-// notice, this list of conditions and the following disclaimer in the
+//  Permission is granted to use, copy, create derivative works and
-// documentation and/or other materials provided with the distribution;
+//  distribute this software and such derivative works for any purpose,
-// neither the name of the copyright holders nor the names of its
+//  so long as (1) the copyright notice above, this grant of permission,
-// contributors may be used to endorse or promote products derived from
+//  and the disclaimer below appear in all copies and derivative works
-// this software without specific prior written permission.
+//  made, (2) the copyright notice above is augmented as appropriate to
-//
+//  reflect the addition of any new copyrightable work in a derivative
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  advertising or publicity pertaining to the use or distribution of
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  this software without specific, written prior authorization.
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//
+//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-// Authors: Korey Sewell
+//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
 
 ////////////////////////////////////////////////////////////////////
 //

src/arch/mips/isa/formats/trap.isa

@@ -1,32 +1,39 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-// All rights reserved.
+
-//
+//  This software is part of the M5 simulator.
-// Redistribution and use in source and binary forms, with or without
+
-// modification, are permitted provided that the following conditions are
+//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-// met: redistributions of source code must retain the above copyright
+//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-// notice, this list of conditions and the following disclaimer;
+//  TO THESE TERMS AND CONDITIONS.
-// redistributions in binary form must reproduce the above copyright
+
-// notice, this list of conditions and the following disclaimer in the
+//  Permission is granted to use, copy, create derivative works and
-// documentation and/or other materials provided with the distribution;
+//  distribute this software and such derivative works for any purpose,
-// neither the name of the copyright holders nor the names of its
+//  so long as (1) the copyright notice above, this grant of permission,
-// contributors may be used to endorse or promote products derived from
+//  and the disclaimer below appear in all copies and derivative works
-// this software without specific prior written permission.
+//  made, (2) the copyright notice above is augmented as appropriate to
-//
+//  reflect the addition of any new copyrightable work in a derivative
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  advertising or publicity pertaining to the use or distribution of
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  this software without specific, written prior authorization.
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//
+//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-// Authors: Korey Sewell
+//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
+//         Jaidev Patwardhan
 
 ////////////////////////////////////////////////////////////////////
 //
@@ -48,6 +55,23 @@ output header {{
 
                 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
         };
+        class TrapImm : public MipsStaticInst
+        {
+                protected:
+
+                int16_t imm;
+
+                /// Constructor
+                TrapImm(const char *mnem, MachInst _machInst, OpClass __opClass) :
+                    MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+
+
+        };
+
 }};
 
 output decoder {{
@@ -55,6 +79,10 @@ output decoder {{
         {
                 return "Disassembly of trap instruction\n";
         }
+        std::string TrapImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+                return "Disassembly of trap instruction\n";
+        }
 }};
 
 def template TrapExecute {{
@@ -68,11 +96,23 @@ def template TrapExecute {{
                 return No_Fault;
         }
 }};
-
 def format Trap(code, *flags) {{
-        code = 'warn(\"'
+
-        code += 'Trap Exception Handler Is Currently Not Implemented.'
+        code ='bool cond;\n' + code
-        code += '\");'
+        code += 'if (cond) {\n'
+        code += 'fault = new TrapFault();\n};'
+
+        iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecode.subst(iop)
+        exec_output = BasicExecute.subst(iop)
+}};
+def format TrapImm(code, *flags) {{
+
+        code ='bool cond;\n' + code
+        code += 'if (cond) {\n'
+        code += 'fault = new TrapFault();\n};'
         iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)

src/arch/mips/isa/formats/unimp.isa

@@ -1,33 +1,39 @@
 // -*- mode:c++ -*-
 
+// Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
+
+//  This software is part of the M5 simulator.
+
+//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
+//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+//  TO THESE TERMS AND CONDITIONS.
+
+//  Permission is granted to use, copy, create derivative works and
+//  distribute this software and such derivative works for any purpose,
+//  so long as (1) the copyright notice above, this grant of permission,
+//  and the disclaimer below appear in all copies and derivative works
+//  made, (2) the copyright notice above is augmented as appropriate to
+//  reflect the addition of any new copyrightable work in a derivative
+//  work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+//  the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+//  advertising or publicity pertaining to the use or distribution of
+//  this software without specific, written prior authorization.
+
+//  THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
+//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
 
-// Copyright (c) 2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Korey Sewell
 
 ////////////////////////////////////////////////////////////////////
 //
@@ -59,6 +65,57 @@ output header {{
         std::string
         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
     };
+    class CP0Unimplemented : public MipsStaticInst
+    {
+      public:
+        /// Constructor
+        CP0Unimplemented(const char *_mnemonic, MachInst _machInst)
+            : MipsStaticInst(_mnemonic, _machInst, No_OpClass)
+        {
+            // don't call execute() (which panics) if we're on a
+            // speculative path
+            flags[IsNonSpeculative] = true;
+        }
+
+        %(BasicExecDeclare)s
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+    class CP1Unimplemented : public MipsStaticInst
+    {
+      public:
+        /// Constructor
+        CP1Unimplemented(const char *_mnemonic, MachInst _machInst)
+            : MipsStaticInst(_mnemonic, _machInst, No_OpClass)
+        {
+            // don't call execute() (which panics) if we're on a
+            // speculative path
+            flags[IsNonSpeculative] = true;
+        }
+
+        %(BasicExecDeclare)s
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+    class CP2Unimplemented : public MipsStaticInst
+    {
+      public:
+        /// Constructor
+        CP2Unimplemented(const char *_mnemonic, MachInst _machInst)
+            : MipsStaticInst(_mnemonic, _machInst, No_OpClass)
+        {
+            // don't call execute() (which panics) if we're on a
+            // speculative path
+            flags[IsNonSpeculative] = true;
+        }
+
+        %(BasicExecDeclare)s
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
 
     /**
      * Base class for unimplemented instructions that cause a warning
@@ -100,6 +157,26 @@ output decoder {{
         return csprintf("%-10s (unimplemented)", mnemonic);
     }
 
+    std::string
+    CP0Unimplemented::generateDisassembly(Addr pc,
+                                           const SymbolTable *symtab) const
+    {
+        return csprintf("%-10s (unimplemented)", mnemonic);
+    }
+
+    std::string
+    CP1Unimplemented::generateDisassembly(Addr pc,
+                                           const SymbolTable *symtab) const
+    {
+        return csprintf("%-10s (unimplemented)", mnemonic);
+    }
+    std::string
+    CP2Unimplemented::generateDisassembly(Addr pc,
+                                           const SymbolTable *symtab) const
+    {
+        return csprintf("%-10s (unimplemented)", mnemonic);
+    }
+
     std::string
     WarnUnimplemented::generateDisassembly(Addr pc,
                                            const SymbolTable *symtab) const
@@ -119,6 +196,56 @@ output exec {{
         return new UnimplementedOpcodeFault;
     }
 
+    Fault
+    CP0Unimplemented::execute(%(CPU_exec_context)s *xc,
+                               Trace::InstRecord *traceData) const
+    {
+#if  FULL_SYSTEM
+      if (!isCoprocessorEnabled(xc, 0)) {
+        return new CoprocessorUnusableFault(0);
+      }
+      return new ReservedInstructionFault;
+#else
+        panic("attempt to execute unimplemented instruction '%s' "
+              "(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, OPCODE,
+              inst2string(machInst));
+        return new UnimplementedOpcodeFault;
+#endif
+    }
+
+    Fault
+    CP1Unimplemented::execute(%(CPU_exec_context)s *xc,
+                               Trace::InstRecord *traceData) const
+    {
+#if  FULL_SYSTEM
+      if (!isCoprocessorEnabled(xc, 1)) {
+        return new CoprocessorUnusableFault(1);
+      }
+      return new ReservedInstructionFault;
+#else
+        panic("attempt to execute unimplemented instruction '%s' "
+              "(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, OPCODE,
+              inst2string(machInst));
+        return new UnimplementedOpcodeFault;
+#endif
+    }
+    Fault
+    CP2Unimplemented::execute(%(CPU_exec_context)s *xc,
+                               Trace::InstRecord *traceData) const
+    {
+#if  FULL_SYSTEM
+      if (!isCoprocessorEnabled(xc, 2)) {
+        return new CoprocessorUnusableFault(2);
+      }
+      return new ReservedInstructionFault;
+#else
+        panic("attempt to execute unimplemented instruction '%s' "
+              "(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, OPCODE,
+              inst2string(machInst));
+        return new UnimplementedOpcodeFault;
+#endif
+    }
+
     Fault
     WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
                                Trace::InstRecord *traceData) const
@@ -136,8 +263,20 @@ output exec {{
 def format FailUnimpl() {{
     iop = InstObjParams(name, 'FailUnimplemented')
     decode_block = BasicDecodeWithMnemonic.subst(iop)
-}};
 
+}};
+def format CP0Unimpl() {{
+    iop = InstObjParams(name, 'CP0Unimplemented')
+    decode_block = BasicDecodeWithMnemonic.subst(iop)
+}};
+def format CP1Unimpl() {{
+    iop = InstObjParams(name, 'CP1Unimplemented')
+    decode_block = BasicDecodeWithMnemonic.subst(iop)
+}};
+def format CP2Unimpl() {{
+    iop = InstObjParams(name, 'CP2Unimplemented')
+    decode_block = BasicDecodeWithMnemonic.subst(iop)
+}};
 def format WarnUnimpl() {{
     iop = InstObjParams(name, 'WarnUnimplemented')
     decode_block = BasicDecodeWithMnemonic.subst(iop)

src/arch/mips/isa/formats/unknown.isa

@@ -72,9 +72,7 @@ output exec {{
     Unknown::execute(%(CPU_exec_context)s *xc,
                      Trace::InstRecord *traceData) const
     {
-        panic("attempt to execute unknown instruction "
+        return new ReservedInstructionFault;
-              "(inst 0x%08x, opcode 0x%x, binary: %s)", machInst, OPCODE, inst2string(machInst));
-        return new UnimplementedOpcodeFault;
     }
 }};
 

src/arch/mips/isa/formats/util.isa

@@ -1,33 +1,39 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-// All rights reserved.
+
-//
+//  This software is part of the M5 simulator.
-// Redistribution and use in source and binary forms, with or without
+
-// modification, are permitted provided that the following conditions are
+//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-// met: redistributions of source code must retain the above copyright
+//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-// notice, this list of conditions and the following disclaimer;
+//  TO THESE TERMS AND CONDITIONS.
-// redistributions in binary form must reproduce the above copyright
+
-// notice, this list of conditions and the following disclaimer in the
+//  Permission is granted to use, copy, create derivative works and
-// documentation and/or other materials provided with the distribution;
+//  distribute this software and such derivative works for any purpose,
-// neither the name of the copyright holders nor the names of its
+//  so long as (1) the copyright notice above, this grant of permission,
-// contributors may be used to endorse or promote products derived from
+//  and the disclaimer below appear in all copies and derivative works
-// this software without specific prior written permission.
+//  made, (2) the copyright notice above is augmented as appropriate to
-//
+//  reflect the addition of any new copyrightable work in a derivative
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  advertising or publicity pertaining to the use or distribution of
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  this software without specific, written prior authorization.
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//
+//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-// Authors: Steve Reinhardt
+//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
-//          Korey Sewell
+//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Steven K. Reinhardt
+//         Korey L. Sewell
 
 let {{
 def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
@@ -74,6 +80,12 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
     fullExecTemplate = eval(exec_template_base + 'Execute')
     initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
     completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
+    eaCompExecuteTemplate = eval('EACompExecute')
+
+    if (exec_template_base == 'Load' or exec_template_base == 'Store'):
+      memAccSizeTemplate = eval('LoadStoreMemAccSize')
+    else:
+      memAccSizeTemplate = eval('MiscMemAccSize')
 
     # (header_output, decoder_output, decode_block, exec_output)
     return (LoadStoreDeclare.subst(iop),
@@ -81,11 +93,12 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
             + MemAccConstructor.subst(memacc_iop)
             + LoadStoreConstructor.subst(iop),
             decode_template.subst(iop),
-            EACompExecute.subst(ea_iop)
+            eaCompExecuteTemplate.subst(ea_iop)
             + memAccExecTemplate.subst(memacc_iop)
             + fullExecTemplate.subst(iop)
             + initiateAccTemplate.subst(iop)
-            + completeAccTemplate.subst(iop))
+            + completeAccTemplate.subst(iop)
+            + memAccSizeTemplate.subst(memacc_iop))
 }};
 
 output header {{

src/arch/mips/isa/includes.isa

@@ -1,32 +1,38 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-// All rights reserved.
+
-//
+//  This software is part of the M5 simulator.
-// Redistribution and use in source and binary forms, with or without
+
-// modification, are permitted provided that the following conditions are
+//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-// met: redistributions of source code must retain the above copyright
+//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-// notice, this list of conditions and the following disclaimer;
+//  TO THESE TERMS AND CONDITIONS.
-// redistributions in binary form must reproduce the above copyright
+
-// notice, this list of conditions and the following disclaimer in the
+//  Permission is granted to use, copy, create derivative works and
-// documentation and/or other materials provided with the distribution;
+//  distribute this software and such derivative works for any purpose,
-// neither the name of the copyright holders nor the names of its
+//  so long as (1) the copyright notice above, this grant of permission,
-// contributors may be used to endorse or promote products derived from
+//  and the disclaimer below appear in all copies and derivative works
-// this software without specific prior written permission.
+//  made, (2) the copyright notice above is augmented as appropriate to
-//
+//  reflect the addition of any new copyrightable work in a derivative
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  advertising or publicity pertaining to the use or distribution of
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  this software without specific, written prior authorization.
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//
+//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-// Authors: Korey Sewell
+//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
 
 ////////////////////////////////////////////////////////////////////
 //
@@ -72,7 +78,6 @@ output exec {{
 #include "arch/mips/dsp.hh"
 #include "arch/mips/pra_constants.hh"
 #include "arch/mips/dt_constants.hh"
-#include "arch/mips/mt.hh"
 #include "arch/mips/mt_constants.hh"
 
 #include <math.h>

src/arch/mips/isa/main.isa

@@ -1,32 +1,38 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-// All rights reserved.
+
-//
+//  This software is part of the M5 simulator.
-// Redistribution and use in source and binary forms, with or without
+
-// modification, are permitted provided that the following conditions are
+//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-// met: redistributions of source code must retain the above copyright
+//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-// notice, this list of conditions and the following disclaimer;
+//  TO THESE TERMS AND CONDITIONS.
-// redistributions in binary form must reproduce the above copyright
+
-// notice, this list of conditions and the following disclaimer in the
+//  Permission is granted to use, copy, create derivative works and
-// documentation and/or other materials provided with the distribution;
+//  distribute this software and such derivative works for any purpose,
-// neither the name of the copyright holders nor the names of its
+//  so long as (1) the copyright notice above, this grant of permission,
-// contributors may be used to endorse or promote products derived from
+//  and the disclaimer below appear in all copies and derivative works
-// this software without specific prior written permission.
+//  made, (2) the copyright notice above is augmented as appropriate to
-//
+//  reflect the addition of any new copyrightable work in a derivative
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  advertising or publicity pertaining to the use or distribution of
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  this software without specific, written prior authorization.
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//
+//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-// Authors: Korey Sewell
+//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
 
 ////////////////////////////////////////////////////////////////////
 //

src/arch/mips/isa/operands.isa

@@ -1,32 +1,39 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-// All rights reserved.
+
-//
+//  This software is part of the M5 simulator.
-// Redistribution and use in source and binary forms, with or without
+
-// modification, are permitted provided that the following conditions are
+//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-// met: redistributions of source code must retain the above copyright
+//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-// notice, this list of conditions and the following disclaimer;
+//  TO THESE TERMS AND CONDITIONS.
-// redistributions in binary form must reproduce the above copyright
+
-// notice, this list of conditions and the following disclaimer in the
+//  Permission is granted to use, copy, create derivative works and
-// documentation and/or other materials provided with the distribution;
+//  distribute this software and such derivative works for any purpose,
-// neither the name of the copyright holders nor the names of its
+//  so long as (1) the copyright notice above, this grant of permission,
-// contributors may be used to endorse or promote products derived from
+//  and the disclaimer below appear in all copies and derivative works
-// this software without specific prior written permission.
+//  made, (2) the copyright notice above is augmented as appropriate to
-//
+//  reflect the addition of any new copyrightable work in a derivative
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+//  advertising or publicity pertaining to the use or distribution of
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+//  this software without specific, written prior authorization.
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//
+//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-// Authors: Korey Sewell
+//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
+//         Jaidev Patwardhan
 
 def operand_types {{
     'sb' : ('signed int', 8),
@@ -39,7 +46,6 @@ def operand_types {{
     'ud' : ('unsigned int', 64),
     'sf' : ('float', 32),
     'df' : ('float', 64),
-    'qf' : ('float', 128)
 }};
 
 def operands {{
@@ -106,9 +112,17 @@ def operands {{
     #Status Control Reg
     'Status': ('ControlReg', 'uw', 'MipsISA::Status', None, 1),
 
+    #LL Flag
+    'LLFlag': ('ControlReg', 'uw', 'MipsISA::LLFlag', None, 1),
+
+    # Index Register
+    'Index':('ControlReg','uw','MipsISA::Index',None,1),
+
+
     #Special cases for when a Control Register Access is dependent on
     #a combination of bitfield indices (handles MTCO & MFCO)
-    'CP0_RD_SEL': ('ControlReg', 'uw', 'RD << 3 | SEL', None, 1),
+    # Fixed to allow CP0 Register Offset
+    'CP0_RD_SEL': ('IControlReg', 'uw', '(RD << 3 | SEL) + Ctrl_Base_DepTag', None, 1),
 
     #MT Control Regs
     'MVPConf0': ('ControlReg', 'uw', 'MipsISA::MVPConf0', None, 1),
@@ -120,10 +134,28 @@ def operands {{
     'VPEControl': ('ControlReg', 'uw', 'MipsISA::VPEControl', None, 1),
     'YQMask': ('ControlReg', 'uw', 'MipsISA::YQMask', None, 1),
 
+    #CP0 Control Regs
+    'EntryHi': ('ControlReg','uw', 'MipsISA::EntryHi',None,1),
+    'EntryLo0': ('ControlReg','uw', 'MipsISA::EntryLo0',None,1),
+    'EntryLo1': ('ControlReg','uw', 'MipsISA::EntryLo1',None,1),
+    'PageMask': ('ControlReg','uw', 'MipsISA::PageMask',None,1),
+    'Random': ('ControlReg','uw', 'MipsISA::CP0_Random',None,1),
+    'ErrorEPC': ('ControlReg','uw', 'MipsISA::ErrorEPC',None,1),
+    'EPC': ('ControlReg','uw', 'MipsISA::EPC',None,1),
+    'DEPC': ('ControlReg','uw', 'MipsISA::DEPC',None,1),
+    'SRSCtl': ('ControlReg','uw', 'MipsISA::SRSCtl',None,1),
+    'Config': ('ControlReg','uw', 'MipsISA::Config',None,1),
+    'Config3': ('ControlReg','uw', 'MipsISA::Config3',None,1),
+    'Config1': ('ControlReg','uw', 'MipsISA::Config1',None,1),
+    'Config2': ('ControlReg','uw', 'MipsISA::Config2',None,1),
+    'PageGrain': ('ControlReg','uw', 'MipsISA::PageGrain',None,1),
+
+
     # named bitfields of Control Regs
     'Status_IE': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
     'Status_ERL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
     'Status_EXL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
+    'Status_BEV': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
     'Status_CU3': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
     'Status_CU2': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
     'Status_CU1': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
@@ -132,6 +164,24 @@ def operands {{
     'SRSCtl_PSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4),
     'SRSCtl_CSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4),
     'Config_AR': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 3),
+    'Config_MT': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 1),
+    'Config1_CA': ('ControlBitfield', 'uw', 'MipsISA::Config1', None, 1),
+    'Config3_SP': ('ControlBitfield', 'uw', 'MipsISA::Config3', None, 1),
+    'PageGrain_ESP': ('ControlBitfield', 'uw', 'MipsISA::PageGrain', None, 1),
+    'Cause_EXCCODE': ('ControlBitfield', 'uw', 'MipsISA::Cause', None, 4),
+    'Cause_TI': ('ControlBitfield', 'uw', 'MipsISA::Cause', None, 4),
+    'IntCtl_IPTI': ('ControlBitfield', 'uw', 'MipsISA::IntCtl', None, 4),
+    'EntryHi_ASID': ('ControlBitfield', 'uw', 'MipsISA::EntryHi', None, 1),
+    'EntryLo0_PFN': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1),
+    'EntryLo0_C': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 3),
+    'EntryLo0_D': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1),
+    'EntryLo0_V': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1),
+    'EntryLo0_G': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1),
+    'EntryLo1_PFN': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1),
+    'EntryLo1_C': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 3),
+    'EntryLo1_D': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1),
+    'EntryLo1_V': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1),
+    'EntryLo1_G': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1),
 
     # named bitfields of Debug Regs
     'Debug_DM': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1),

src/arch/mips/isa_traits.hh

@@ -1,38 +1,46 @@
 /*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
+ * This software is part of the M5 simulator.
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * TO THESE TERMS AND CONDITIONS.
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Gabe Black
+ * Permission is granted to use, copy, create derivative works and
- *          Korey Sewell
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Gabe M. Black
+ *          Korey L. Sewell
+ *          Jaidev Patwardhan
  */
 
 #ifndef __ARCH_MIPS_ISA_TRAITS_HH__
 #define __ARCH_MIPS_ISA_TRAITS_HH__
 
 #include "arch/mips/types.hh"
+#include "config/full_system.hh"
 #include "sim/host.hh"
 
 namespace LittleEndianGuest {};
@@ -47,14 +55,112 @@ namespace MipsISA
 
     StaticInstPtr decodeInst(ExtMachInst);
 
-    // MIPS DOES a delay slot
+    // MIPS DOES have a delay slot
     #define ISA_HAS_DELAY_SLOT 1
 
     const Addr PageShift = 13;
     const Addr PageBytes = ULL(1) << PageShift;
-    const Addr PageMask = ~(PageBytes - 1);
+    const Addr Page_Mask = ~(PageBytes - 1);
     const Addr PageOffset = PageBytes - 1;
 
+
+    ////////////////////////////////////////////////////////////////////////
+    //
+    //  Translation stuff
+    //
+
+    const Addr PteShift = 3;
+    const Addr NPtePageShift = PageShift - PteShift;
+    const Addr NPtePage = ULL(1) << NPtePageShift;
+    const Addr PteMask = NPtePage - 1;
+
+    //// All 'Mapped' segments go through the TLB
+    //// All other segments are translated by dropping the MSB, to give
+    //// the corresponding physical address
+    // User Segment - Mapped
+    const Addr USegBase = ULL(0x0);
+    const Addr USegEnd = ULL(0x7FFFFFFF);
+
+    // Kernel Segment 0 - Unmapped
+    const Addr KSeg0End = ULL(0x9FFFFFFF);
+    const Addr KSeg0Base =  ULL(0x80000000);
+    const Addr KSeg0Mask = ULL(0x1FFFFFFF);
+
+    // Kernel Segment 1 - Unmapped, Uncached
+    const Addr KSeg1End = ULL(0xBFFFFFFF);
+    const Addr KSeg1Base = ULL(0xA0000000);
+    const Addr KSeg1Mask = ULL(0x1FFFFFFF);
+
+    // Kernel/Supervisor Segment - Mapped
+    const Addr KSSegEnd = ULL(0xDFFFFFFF);
+    const Addr KSSegBase = ULL(0xC0000000);
+
+    // Kernel Segment 3 - Mapped
+    const Addr KSeg3End = ULL(0xFFFFFFFF);
+    const Addr KSeg3Base = ULL(0xE0000000);
+
+
+    // For loading... XXX This maybe could be USegEnd?? --ali
+    const Addr LoadAddrMask = ULL(0xffffffffff);
+
+    inline Addr Phys2K0Seg(Addr addr)
+    {
+   //  if (addr & PAddrUncachedBit43) {
+//         addr &= PAddrUncachedMask;
+//         addr |= PAddrUncachedBit40;
+//     }
+        return addr | KSeg0Base;
+    }
+
+    ////////////////////////////////////////////////////////////////////////
+    //
+    //  Interrupt levels
+    //
+    enum InterruptLevels
+    {
+        INTLEVEL_SOFTWARE_MIN = 4,
+        INTLEVEL_SOFTWARE_MAX = 19,
+
+        INTLEVEL_EXTERNAL_MIN = 20,
+        INTLEVEL_EXTERNAL_MAX = 34,
+
+        INTLEVEL_IRQ0 = 20,
+        INTLEVEL_IRQ1 = 21,
+        INTINDEX_ETHERNET = 0,
+        INTINDEX_SCSI = 1,
+        INTLEVEL_IRQ2 = 22,
+        INTLEVEL_IRQ3 = 23,
+
+        INTLEVEL_SERIAL = 33,
+
+        NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
+    };
+
+
+    // MIPS modes
+    enum mode_type
+    {
+        mode_kernel = 0,		// kernel
+        mode_supervisor = 1,	// supervisor
+        mode_user = 2,		// user mode
+        mode_debug = 3,         // debug mode
+        mode_number			// number of modes
+    };
+
+  inline mode_type getOperatingMode(MiscReg Stat)
+  {
+    if((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0)
+      return mode_kernel;
+    else{
+      if((Stat & 0x18) == 0x8)
+        return mode_supervisor;
+      else if((Stat & 0x18) == 0x10)
+        return mode_user;
+      else return mode_number;
+    }
+  }
+
+
     // return a no-op instruction... used for instruction fetch faults
     const ExtMachInst NoopMachInst = 0x00000000;
 
@@ -64,9 +170,13 @@ namespace MipsISA
     const int NumFloatArchRegs = 32;
     const int NumFloatSpecialRegs = 5;
 
+    const int NumShadowRegSets = 16; // Maximum number of shadow register sets
+    const int NumIntRegs = NumIntArchRegs*NumShadowRegSets + NumIntSpecialRegs;        //HI & LO Regs
+    const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
+
     // Static instruction parameters
-    const int MaxInstSrcRegs = 5;
+    const int MaxInstSrcRegs = 10;
-    const int MaxInstDestRegs = 4;
+    const int MaxInstDestRegs = 8;
 
     // semantically meaningful register indices
     const int ZeroReg = 0;
@@ -74,10 +184,10 @@ namespace MipsISA
     const int ReturnValueReg = 2;
     const int ReturnValueReg1 = 2;
     const int ReturnValueReg2 = 3;
-
+    const int ArgumentReg0 = 4;
-    const int ArgumentReg[] = {4, 5, 6, 7};
+    const int ArgumentReg1 = 5;
-    const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
+    const int ArgumentReg2 = 6;
-
+    const int ArgumentReg3 = 7;
     const int KernelReg0 = 26;
     const int KernelReg1 = 27;
     const int GlobalPointerReg = 28;
@@ -85,9 +195,12 @@ namespace MipsISA
     const int FramePointerReg = 30;
     const int ReturnAddressReg = 31;
 
+    const int ArgumentReg[] = {4, 5, 6, 7};
+    const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
+
     const int SyscallNumReg = ReturnValueReg1;
     const int SyscallPseudoReturnReg = ReturnValueReg2;
-    const int SyscallSuccessReg = ArgumentReg[3];
+    const int SyscallSuccessReg = ArgumentReg3;
 
     const int LogVMPageSize = 13;	// 8K bytes
     const int VMPageSize = (1 << LogVMPageSize);
@@ -102,6 +215,10 @@ namespace MipsISA
     const int ANNOTE_NONE = 0;
     const uint32_t ITOUCH_ANNOTE = 0xffffffff;
 
+    // These help enumerate all the registers for dependence tracking.
+    const int FP_Base_DepTag = NumIntRegs;
+    const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
+
     // Enumerate names for 'Control' Registers in the CPU
     // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
     // (Register Number-Register Select) Summary of Register
@@ -110,12 +227,12 @@ namespace MipsISA
     // for easy indexing when using the 'RD + SEL' index combination
     // in CP0 instructions.
     enum MiscRegTags {
-        Index = 0,       //Bank 0: 0 - 3
+        Index = Ctrl_Base_DepTag + 0,       //Bank 0: 0 - 3
         MVPControl,
         MVPConf0,
         MVPConf1,
 
-        Random = 8,      //Bank 1: 8 - 15
+        CP0_Random = Ctrl_Base_DepTag + 8,      //Bank 1: 8 - 15
         VPEControl,
         VPEConf0,
         VPEConf1,
@@ -124,7 +241,7 @@ namespace MipsISA
         VPEScheFBack,
         VPEOpt,
 
-        EntryLo0 = 16,   //Bank 2: 16 - 23
+        EntryLo0 = Ctrl_Base_DepTag + 16,   //Bank 2: 16 - 23
         TCStatus,
         TCBind,
         TCRestart,
@@ -133,44 +250,44 @@ namespace MipsISA
         TCSchedule,
         TCScheFBack,
 
-        EntryLo1 = 24,   // Bank 3: 24
+        EntryLo1 = Ctrl_Base_DepTag + 24,   // Bank 3: 24
 
-        Context = 32,    // Bank 4: 32 - 33
+        Context = Ctrl_Base_DepTag + 32,    // Bank 4: 32 - 33
         ContextConfig,
 
-        //PageMask = 40, //Bank 5: 40 - 41
+        PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41
-        PageGrain = 41,
+        PageGrain = Ctrl_Base_DepTag + 41,
 
-        Wired = 48,          //Bank 6:48-55
+        Wired = Ctrl_Base_DepTag + 48,          //Bank 6:48-55
         SRSConf0,
         SRSConf1,
         SRSConf2,
         SRSConf3,
         SRSConf4,
 
-        HWRena = 56,         //Bank 7: 56-63
+        HWRena = Ctrl_Base_DepTag + 56,         //Bank 7: 56-63
 
-        BadVAddr = 64,       //Bank 8: 64-71
+        BadVAddr = Ctrl_Base_DepTag + 64,       //Bank 8: 64-71
 
-        Count = 72,          //Bank 9: 72-79
+        Count = Ctrl_Base_DepTag + 72,          //Bank 9: 72-79
 
-        EntryHi = 80,        //Bank 10: 80-87
+        EntryHi = Ctrl_Base_DepTag + 80,        //Bank 10: 80-87
 
-        Compare = 88,        //Bank 11: 88-95
+        Compare = Ctrl_Base_DepTag + 88,        //Bank 11: 88-95
 
-        Status = 96,         //Bank 12: 96-103
+        Status = Ctrl_Base_DepTag + 96,         //Bank 12: 96-103
         IntCtl,
         SRSCtl,
         SRSMap,
 
-        Cause = 104,         //Bank 13: 104-111
+        Cause = Ctrl_Base_DepTag + 104,         //Bank 13: 104-111
 
-        EPC = 112,           //Bank 14: 112-119
+        EPC = Ctrl_Base_DepTag + 112,           //Bank 14: 112-119
 
-        PRId = 120,          //Bank 15: 120-127,
+        PRId = Ctrl_Base_DepTag + 120,          //Bank 15: 120-127,
         EBase,
 
-        Config = 128,        //Bank 16: 128-135
+        Config = Ctrl_Base_DepTag + 128,        //Bank 16: 128-135
         Config1,
         Config2,
         Config3,
@@ -180,9 +297,9 @@ namespace MipsISA
         Config7,
 
 
-        LLAddr = 136,        //Bank 17: 136-143
+        LLAddr = Ctrl_Base_DepTag + 136,        //Bank 17: 136-143
 
-        WatchLo0 = 144,      //Bank 18: 144-151
+        WatchLo0 = Ctrl_Base_DepTag + 144,      //Bank 18: 144-151
         WatchLo1,
         WatchLo2,
         WatchLo3,
@@ -191,7 +308,7 @@ namespace MipsISA
         WatchLo6,
         WatchLo7,
 
-        WatchHi0 = 152,     //Bank 19: 152-159
+        WatchHi0 = Ctrl_Base_DepTag + 152,     //Bank 19: 152-159
         WatchHi1,
         WatchHi2,
         WatchHi3,
@@ -200,21 +317,21 @@ namespace MipsISA
         WatchHi6,
         WatchHi7,
 
-        XCContext64 = 160, //Bank 20: 160-167
+        XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167
 
                            //Bank 21: 168-175
 
                            //Bank 22: 176-183
 
-        Debug = 184,       //Bank 23: 184-191
+        Debug = Ctrl_Base_DepTag + 184,       //Bank 23: 184-191
         TraceControl1,
         TraceControl2,
         UserTraceData,
         TraceBPC,
 
-        DEPC = 192,        //Bank 24: 192-199
+        DEPC = Ctrl_Base_DepTag + 192,        //Bank 24: 192-199
 
-        PerfCnt0 = 200,    //Bank 25: 200-207
+        PerfCnt0 = Ctrl_Base_DepTag + 200,    //Bank 25: 200-207
         PerfCnt1,
         PerfCnt2,
         PerfCnt3,
@@ -223,14 +340,14 @@ namespace MipsISA
         PerfCnt6,
         PerfCnt7,
 
-        ErrCtl = 208,      //Bank 26: 208-215
+        ErrCtl = Ctrl_Base_DepTag + 208,      //Bank 26: 208-215
 
-        CacheErr0 = 216,   //Bank 27: 216-223
+        CacheErr0 = Ctrl_Base_DepTag + 216,   //Bank 27: 216-223
         CacheErr1,
         CacheErr2,
         CacheErr3,
 
-        TagLo0 = 224,      //Bank 28: 224-231
+        TagLo0 = Ctrl_Base_DepTag + 224,      //Bank 28: 224-231
         DataLo1,
         TagLo2,
         DataLo3,
@@ -239,7 +356,7 @@ namespace MipsISA
         TagLo6,
         DataLo7,
 
-        TagHi0 = 232,      //Bank 29: 232-239
+        TagHi0 = Ctrl_Base_DepTag + 232,      //Bank 29: 232-239
         DataHi1,
         TagHi2,
         DataHi3,
@@ -249,26 +366,22 @@ namespace MipsISA
         DataHi7,
 
 
-        ErrorEPC = 240,    //Bank 30: 240-247
+        ErrorEPC = Ctrl_Base_DepTag + 240,    //Bank 30: 240-247
 
-        DESAVE = 248,       //Bank 31: 248-256
+        DESAVE = Ctrl_Base_DepTag + 248,       //Bank 31: 248-256
 
-        LLFlag = 257,
+        LLFlag = Ctrl_Base_DepTag + 257,
 
         NumControlRegs
     };
 
-    const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;        //HI & LO Regs
+    const int TotalDataRegs = NumIntRegs + NumFloatRegs;
-    const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
+
     const int NumMiscRegs = NumControlRegs;
 
     const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
 
-    const int TotalDataRegs = NumIntRegs + NumFloatRegs;
 
-    // These help enumerate all the registers for dependence tracking.
-    const int FP_Base_DepTag = NumIntRegs;
-    const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
 };
 
 using namespace MipsISA;

src/arch/mips/kernel_stats.hh

@@ -0,0 +1,65 @@
+/*
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ *
+ * This software is part of the M5 simulator.
+ *
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+ * TO THESE TERMS AND CONDITIONS.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Lisa R. Hsu
+ *          Nathan L. Binkert
+ */
+
+#ifndef __ARCH_MIPS_KERNEL_STATS_HH__
+#define __ARCH_MIPS_KERNEL_STATS_HH__
+
+#include <map>
+#include <stack>
+#include <string>
+#include <vector>
+
+#include "kern/kernel_stats.hh"
+
+namespace MipsISA {
+namespace Kernel {
+
+enum cpu_mode { kernel, user, idle, cpu_mode_num };
+extern const char *modestr[];
+
+class Statistics : public ::Kernel::Statistics
+{
+  public:
+    Statistics(System *system) : ::Kernel::Statistics(system)
+    {}
+};
+
+
+} /* end namespace MipsISA::Kernel */
+} /* end namespace MipsISA */
+
+#endif // __ARCH_MIPS_KERNEL_STATS_HH__

src/arch/mips/linux/aligned.hh

@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2004 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ *          Nathan Binkert
+ */
+
+#ifndef __ARCH_MIPS_LINUX_ALIGNED_HH__
+#define __ARCH_MIPS_LINUX_ALIGNED_HH__
+
+
+/* GCC 3.3.X has a bug in which attributes+typedefs don't work. 3.2.X is fine
+ * as in 3.4.X, but the bug is marked will not fix in 3.3.X so here is
+ * the work around.
+ */
+#if (__GNUC__ == 3 && __GNUC_MINOR__  != 3) || __GNUC__ > 3
+typedef uint64_t uint64_ta __attribute__ ((aligned (8))) ;
+typedef int64_t int64_ta __attribute__ ((aligned (8))) ;
+typedef Addr Addr_a __attribute__ ((aligned (8))) ;
+#else
+#define uint64_ta uint64_t __attribute__ ((aligned (8)))
+#define int64_ta int64_t __attribute__ ((aligned (8)))
+#define Addr_a Addr __attribute__ ((aligned (8)))
+#endif /* __GNUC__ __GNUC_MINOR__ */
+
+#endif /* __ARCH_MIPS_LINUX_ALIGNED_HH__ */

src/arch/mips/linux/hwrpb.hh

@@ -0,0 +1,42 @@
+/*
+ * Copyright 1990 Hewlett-Packard Development Company, L.P.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef __ARCH_MIPS_LINUX_HWRPB_HH__
+#define __ARCH_MIPS_LINUX_HWRPB_HH__
+
+#include "arch/mips/linux/aligned.hh"
+
+namespace Linux {
+    struct pcb_struct {
+        uint64_ta rpb_ksp;
+        uint64_ta rpb_usp;
+        uint64_ta rpb_ptbr;
+        uint32_t rpb_cc;
+        uint32_t rpb_psn;
+        uint64_ta rpb_unique;
+        uint64_ta rpb_fen;
+        uint64_ta res1, res2;
+    };
+}
+#endif // __ARCH_MIPS_LINUX_HWRPB_HH__

src/arch/mips/linux/linux.cc

@@ -1,31 +1,38 @@
 /*
- * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
+ * This software is part of the M5 simulator.
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * TO THESE TERMS AND CONDITIONS.
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * Permission is granted to use, copy, create derivative works and
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * distribute this software and such derivative works for any purpose,
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * so long as (1) the copyright notice above, this grant of permission,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * and the disclaimer below appear in all copies and derivative works
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * made, (2) the copyright notice above is augmented as appropriate to
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * reflect the addition of any new copyrightable work in a derivative
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Korey L. Sewell
  *
- * Authors: Korey Sewell
  */
 
 #include "arch/mips/linux/linux.hh"

src/arch/mips/linux/linux.hh

@@ -1,31 +1,37 @@
 /*
- * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
+ * This software is part of the M5 simulator.
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * TO THESE TERMS AND CONDITIONS.
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Korey Sewell
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Korey L. Sewell
  */
 
 #ifndef __ARCH_MIPS_LINUX_LINUX_HH__

src/arch/mips/linux/process.cc

@@ -1,31 +1,38 @@
 /*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
+ * This software is part of the M5 simulator.
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * TO THESE TERMS AND CONDITIONS.
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Korey Sewell
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ *
+ * Authors: Korey L. Sewell
  */
 
 #include "arch/mips/linux/linux.hh"

src/arch/mips/linux/process.hh

@@ -1,29 +1,39 @@
 /*
- * Copyright (c) 2003-2004 The Regents of The University of Michigan
+ * Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
+ * This software is part of the M5 simulator.
- * modification, are permitted provided that the following conditions are
+ *
- * met: redistributions of source code must retain the above copyright
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * notice, this list of conditions and the following disclaimer;
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * redistributions in binary form must reproduce the above copyright
+ * TO THESE TERMS AND CONDITIONS.
- * notice, this list of conditions and the following disclaimer in the
+ *
- * documentation and/or other materials provided with the distribution;
+ * Permission is granted to use, copy, create derivative works and
- * neither the name of the copyright holders nor the names of its
+ * distribute this software and such derivative works for any purpose,
- * contributors may be used to endorse or promote products derived from
+ * so long as (1) the copyright notice above, this grant of permission,
- * this software without specific prior written permission.
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Gabe Black
+ *          Korey Sewell
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 #ifndef __MIPS_LINUX_PROCESS_HH__

src/arch/mips/linux/system.cc

@@ -0,0 +1,205 @@
+/*
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ *
+ * This software is part of the M5 simulator.
+ *
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+ * TO THESE TERMS AND CONDITIONS.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ *
+ * Authors: Ali G. Saidi
+ *          Lisa R. Hsu
+ *          Nathan L. Binkert
+ *          Steven K. Reinhardt
+ */
+
+/**
+ * @file
+ * This code loads the linux kernel, console, pal and patches certain
+ * functions.  The symbol tables are loaded so that traces can show
+ * the executing function and we can skip functions. Various delay
+ * loops are skipped and their final values manually computed to speed
+ * up boot time.
+ */
+
+#include "arch/vtophys.hh"
+#include "arch/mips/idle_event.hh"
+#include "arch/mips/linux/system.hh"
+#include "arch/mips/linux/threadinfo.hh"
+#include "arch/mips/system.hh"
+#include "base/loader/symtab.hh"
+#include "cpu/thread_context.hh"
+#include "cpu/base.hh"
+#include "dev/platform.hh"
+#include "kern/linux/printk.hh"
+#include "kern/linux/events.hh"
+#include "mem/physical.hh"
+#include "mem/port.hh"
+#include "sim/arguments.hh"
+#include "sim/byteswap.hh"
+
+using namespace std;
+using namespace MipsISA;
+using namespace Linux;
+
+LinuxMipsSystem::LinuxMipsSystem(Params *p)
+    : MipsSystem(p)
+{
+    Addr addr = 0;
+
+    /**
+     * The symbol swapper_pg_dir marks the beginning of the kernel and
+     * the location of bootloader passed arguments
+     */
+    if (!kernelSymtab->findAddress("swapper_pg_dir", KernelStart)) {
+        panic("Could not determine start location of kernel");
+    }
+
+    /**
+     * Since we aren't using a bootloader, we have to copy the
+     * kernel arguments directly into the kernel's memory.
+     */
+    virtPort.writeBlob(CommandLine(), (uint8_t*)params()->boot_osflags.c_str(),
+                params()->boot_osflags.length()+1);
+
+    /**
+     * find the address of the est_cycle_freq variable and insert it
+     * so we don't through the lengthly process of trying to
+     * calculated it by using the PIT, RTC, etc.
+     */
+    if (kernelSymtab->findAddress("est_cycle_freq", addr))
+        virtPort.write(addr, (uint64_t)(Clock::Frequency /
+                    p->boot_cpu_frequency));
+
+
+    /**
+     * EV5 only supports 127 ASNs so we are going to tell the kernel that the
+     * paritiuclar EV6 we have only supports 127 asns.
+     * @todo At some point we should change ev5.hh and the palcode to support
+     * 255 ASNs.
+     */
+    if (kernelSymtab->findAddress("dp264_mv", addr))
+        virtPort.write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127));
+    else
+        panic("could not find dp264_mv\n");
+
+#ifndef NDEBUG
+    kernelPanicEvent = addKernelFuncEvent<BreakPCEvent>("panic");
+    if (!kernelPanicEvent)
+        panic("could not find kernel symbol \'panic\'");
+
+#if 0
+    kernelDieEvent = addKernelFuncEvent<BreakPCEvent>("die_if_kernel");
+    if (!kernelDieEvent)
+        panic("could not find kernel symbol \'die_if_kernel\'");
+#endif
+
+#endif
+
+    /**
+     * Any time ide_delay_50ms, calibarte_delay or
+     * determine_cpu_caches is called just skip the
+     * function. Currently determine_cpu_caches only is used put
+     * information in proc, however if that changes in the future we
+     * will have to fill in the cache size variables appropriately.
+     */
+
+    skipIdeDelay50msEvent =
+        addKernelFuncEvent<SkipFuncEvent>("ide_delay_50ms");
+    skipDelayLoopEvent =
+        addKernelFuncEvent<SkipDelayLoopEvent>("calibrate_delay");
+    skipCacheProbeEvent =
+        addKernelFuncEvent<SkipFuncEvent>("determine_cpu_caches");
+    debugPrintkEvent = addKernelFuncEvent<DebugPrintkEvent>("dprintk");
+    idleStartEvent = addKernelFuncEvent<IdleStartEvent>("cpu_idle");
+
+    // Disable for now as it runs into panic() calls in VPTr methods
+    // (see sim/vptr.hh).  Once those bugs are fixed, we can
+    // re-enable, but we should find a better way to turn it on than
+    // using DTRACE(Thread), since looking at a trace flag at tick 0
+    // leads to non-intuitive behavior with --trace-start.
+    if (false && kernelSymtab->findAddress("mips_switch_to", addr)) {
+        printThreadEvent = new PrintThreadInfo(&pcEventQueue, "threadinfo",
+                                               addr + sizeof(MachInst) * 6);
+    } else {
+        printThreadEvent = NULL;
+    }
+}
+
+LinuxMipsSystem::~LinuxMipsSystem()
+{
+#ifndef NDEBUG
+    delete kernelPanicEvent;
+#endif
+    delete skipIdeDelay50msEvent;
+    delete skipDelayLoopEvent;
+    delete skipCacheProbeEvent;
+    delete debugPrintkEvent;
+    delete idleStartEvent;
+    delete printThreadEvent;
+}
+
+
+void
+LinuxMipsSystem::setDelayLoop(ThreadContext *tc)
+{
+    Addr addr = 0;
+    if (kernelSymtab->findAddress("loops_per_jiffy", addr)) {
+        Tick cpuFreq = tc->getCpuPtr()->frequency();
+        Tick intrFreq = platform->intrFrequency();
+        VirtualPort *vp;
+
+        vp = tc->getVirtPort();
+        vp->writeHtoG(addr, (uint32_t)((cpuFreq / intrFreq) * 0.9988));
+        tc->delVirtPort(vp);
+    }
+}
+
+
+void
+LinuxMipsSystem::SkipDelayLoopEvent::process(ThreadContext *tc)
+{
+    SkipFuncEvent::process(tc);
+    // calculate and set loops_per_jiffy
+    ((LinuxMipsSystem *)tc->getSystemPtr())->setDelayLoop(tc);
+}
+
+void
+LinuxMipsSystem::PrintThreadInfo::process(ThreadContext *tc)
+{
+    Linux::ThreadInfo ti(tc);
+
+    DPRINTF(Thread, "Currently Executing Thread %s, pid %d, started at: %d\n",
+            ti.curTaskName(), ti.curTaskPID(), ti.curTaskStart());
+}
+
+LinuxMipsSystem *
+LinuxMipsSystemParams::create()
+{
+    return new LinuxMipsSystem(this);
+}

src/arch/mips/linux/system.hh

@@ -0,0 +1,146 @@
+/*
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ *
+ * This software is part of the M5 simulator.
+ *
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+ * TO THESE TERMS AND CONDITIONS.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Ali G. Saidi
+ *          Lisa R. Hsu
+ *          Nathan L. Binkert
+ */
+
+#ifndef __ARCH_MIPS_LINUX_SYSTEM_HH__
+#define __ARCH_MIPS_LINUX_SYSTEM_HH__
+
+class ThreadContext;
+
+class BreakPCEvent;
+class IdleStartEvent;
+
+#include "arch/mips/idle_event.hh"
+#include "arch/mips/system.hh"
+#include "kern/linux/events.hh"
+#include "params/LinuxMipsSystem.hh"
+
+using namespace MipsISA;
+using namespace Linux;
+
+/**
+ * This class contains linux specific system code (Loading, Events).
+ * It points to objects that are the system binaries to load and patches them
+ * appropriately to work in simulator.
+ */
+class LinuxMipsSystem : public MipsSystem
+{
+  private:
+    class SkipDelayLoopEvent : public SkipFuncEvent
+    {
+      public:
+        SkipDelayLoopEvent(PCEventQueue *q, const std::string &desc, Addr addr)
+            : SkipFuncEvent(q, desc, addr) {}
+        virtual void process(ThreadContext *tc);
+    };
+
+    class PrintThreadInfo : public PCEvent
+    {
+      public:
+        PrintThreadInfo(PCEventQueue *q, const std::string &desc, Addr addr)
+            : PCEvent(q, desc, addr) {}
+        virtual void process(ThreadContext *tc);
+    };
+
+
+    /**
+     * Addresses defining where the kernel bootloader places various
+     * elements.  Details found in include/asm-mips/system.h
+     */
+    Addr KernelStart; // Lookup the symbol swapper_pg_dir
+
+  public:
+    Addr InitStack() const { return KernelStart + 0x02000; }
+    Addr EmptyPGT() const  { return KernelStart + 0x04000; }
+    Addr EmptyPGE() const  { return KernelStart + 0x08000; }
+    Addr ZeroPGE() const   { return KernelStart + 0x0A000; }
+    Addr StartAddr() const { return KernelStart + 0x10000; }
+
+    Addr Param() const { return ZeroPGE() + 0x0; }
+    Addr CommandLine() const { return Param() + 0x0; }
+    Addr InitrdStart() const { return Param() + 0x100; }
+    Addr InitrdSize() const { return Param() + 0x108; }
+    static const int CommandLineSize = 256;
+
+  private:
+#ifndef NDEBUG
+    /** Event to halt the simulator if the kernel calls panic()  */
+    BreakPCEvent *kernelPanicEvent;
+
+    /** Event to halt the simulator if the kernel calls die_if_kernel  */
+    BreakPCEvent *kernelDieEvent;
+#endif
+
+    /**
+     * Event to skip determine_cpu_caches() because we don't support
+     * the IPRs that the code can access to figure out cache sizes
+     */
+    SkipFuncEvent *skipCacheProbeEvent;
+
+    /** PC based event to skip the ide_delay_50ms() call */
+    SkipFuncEvent *skipIdeDelay50msEvent;
+
+    /**
+     * PC based event to skip the dprink() call and emulate its
+     * functionality
+     */
+    DebugPrintkEvent *debugPrintkEvent;
+
+    /**
+     * Skip calculate_delay_loop() rather than waiting for this to be
+     * calculated
+     */
+    SkipDelayLoopEvent *skipDelayLoopEvent;
+
+    /**
+     * Event to print information about thread switches if the trace flag
+     * Thread is set
+     */
+    PrintThreadInfo *printThreadEvent;
+
+    /** Grab the PCBB of the idle process when it starts */
+    IdleStartEvent *idleStartEvent;
+
+  public:
+    typedef LinuxMipsSystemParams Params;
+    LinuxMipsSystem(Params *p);
+    ~LinuxMipsSystem();
+
+    void setDelayLoop(ThreadContext *tc);
+};
+
+#endif // __ARCH_MIPS_LINUX_SYSTEM_HH__

src/arch/mips/linux/thread_info.hh

@@ -0,0 +1,51 @@
+/*
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ *
+ * This software is part of the M5 simulator.
+ *
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+ * TO THESE TERMS AND CONDITIONS.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ *
+ * Authors: Ali G. Saidi
+ *          Nathan L. Binkert
+ */
+
+#ifndef __ARCH_MIPS_LINUX_THREAD_INFO_H__
+#define __ARCH_MIPS_LINUX_THREAD_INFO_H__
+
+#include "arch/mips/linux/hwrpb.hh"
+
+namespace Linux {
+    struct thread_info {
+        struct pcb_struct       pcb;
+        Addr_a                  task;
+    };
+}
+
+#endif // __ARCH_MIPS_LINUX_THREAD_INFO_H__

src/arch/mips/linux/threadinfo.hh

@@ -0,0 +1,160 @@
+/*
+ * Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ *
+ * This software is part of the M5 simulator.
+ *
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+ * TO THESE TERMS AND CONDITIONS.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Ali G. Saidi
+ *          Nathan L. Binkert
+ */
+
+
+#ifndef __ARCH_MIPS_LINUX_LINUX_TREADNIFO_HH__
+#define __ARCH_MIPS_LINUX_LINUX_TREADNIFO_HH__
+
+#include "cpu/thread_context.hh"
+#include "sim/system.hh"
+#include "sim/vptr.hh"
+
+namespace Linux {
+
+class ThreadInfo
+{
+  private:
+    ThreadContext *tc;
+    System *sys;
+    Addr pcbb;
+
+    template <typename T>
+    bool
+    get_data(const char *symbol, T &data)
+    {
+        Addr addr = 0;
+        if (!sys->kernelSymtab->findAddress(symbol, addr))
+            return false;
+
+        CopyOut(tc, &data, addr, sizeof(T));
+
+        data = TheISA::gtoh(data);
+
+        return true;
+    }
+
+  public:
+    ThreadInfo(ThreadContext *_tc, Addr _pcbb = 0)
+        : tc(_tc), sys(tc->getSystemPtr()), pcbb(_pcbb)
+    {
+
+    }
+    ~ThreadInfo()
+    {}
+
+    inline Addr
+    curThreadInfo()
+    {
+        panic("curThreadInfo not implemented for MIPS");
+        Addr addr = pcbb;
+        Addr sp;
+
+        if (!addr)
+            addr = tc->readMiscRegNoEffect(0/*TheISA::IPR_PALtemp23*/);
+
+        FunctionalPort *p = tc->getPhysPort();
+        p->readBlob(addr, (uint8_t *)&sp, sizeof(Addr));
+
+        return sp & ~ULL(0x3fff);
+    }
+
+    inline Addr
+    curTaskInfo(Addr thread_info = 0)
+    {
+        int32_t offset;
+        if (!get_data("thread_info_task", offset))
+            return 0;
+
+        if (!thread_info)
+            thread_info = curThreadInfo();
+
+        Addr addr;
+        CopyOut(tc, &addr, thread_info + offset, sizeof(addr));
+
+        return addr;
+    }
+
+    int32_t
+    curTaskPID(Addr thread_info = 0)
+    {
+        Addr offset;
+        if (!get_data("task_struct_pid", offset))
+            return -1;
+
+        int32_t pid;
+        CopyOut(tc, &pid, curTaskInfo(thread_info) + offset, sizeof(pid));
+
+        return pid;
+    }
+
+    int64_t
+    curTaskStart(Addr thread_info = 0)
+    {
+        Addr offset;
+        if (!get_data("task_struct_start_time", offset))
+            return -1;
+
+        int64_t data;
+        // start_time is actually of type timespec, but if we just
+        // grab the first long, we'll get the seconds out of it
+        CopyOut(tc, &data, curTaskInfo(thread_info) + offset, sizeof(data));
+
+        return data;
+    }
+
+    std::string
+    curTaskName(Addr thread_info = 0)
+    {
+        int32_t offset;
+        int32_t size;
+
+        if (!get_data("task_struct_comm", offset))
+            return "FailureIn_curTaskName";
+
+        if (!get_data("task_struct_comm_size", size))
+            return "FailureIn_curTaskName";
+
+        char buffer[size + 1];
+        CopyStringOut(tc, buffer, curTaskInfo(thread_info) + offset, size);
+
+        return buffer;
+    }
+};
+
+/* namespace Linux */ }
+
+#endif // __ARCH_MIPS_LINUX_LINUX_THREADINFO_HH__

src/arch/mips/locked_mem.hh

@@ -1,31 +1,37 @@
 /*
- * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
+ * This software is part of the M5 simulator.
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * TO THESE TERMS AND CONDITIONS.
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Steve Reinhardt
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Steven K. Reinhardt
  */
 
 #ifndef __ARCH_MIPS_LOCKED_MEM_HH__
@@ -50,8 +56,8 @@ inline void
 handleLockedRead(XC *xc, Request *req)
 {
     unsigned tid = req->getThreadNum();
-    xc->setMiscReg(LLAddr, req->getPaddr() & ~0xf, tid);
+    xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf, tid);
-    xc->setMiscReg(LLFlag, true, tid);
+    xc->setMiscRegNoEffect(LLFlag, true, tid);
     DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to %x.\n",
             tid, req->getPaddr() & ~0xf);
 }
@@ -69,14 +75,14 @@ handleLockedWrite(XC *xc, Request *req)
         req->setExtraData(2);
     } else {
         // standard store conditional
-        bool lock_flag = xc->readMiscReg(LLFlag, tid);
+        bool lock_flag = xc->readMiscRegNoEffect(LLFlag, tid);
-        Addr lock_addr = xc->readMiscReg(LLAddr, tid);
+        Addr lock_addr = xc->readMiscRegNoEffect(LLAddr, tid);
 
         if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
             // Lock flag not set or addr mismatch in CPU;
             // don't even bother sending to memory system
             req->setExtraData(0);
-            xc->setMiscReg(LLFlag, false, tid);
+            xc->setMiscRegNoEffect(LLFlag, false, tid);
 
             // the rest of this code is not architectural;
             // it's just a debugging aid to help detect

src/arch/mips/mips_core_specific.cc

@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2002, 2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ *          Steve Reinhardt
+ */
+
+#include "arch/mips/faults.hh"
+#include "arch/mips/isa_traits.hh"
+#include "arch/mips/tlb.hh"
+//#include "base/kgdb.h"
+#include "base/remote_gdb.hh"
+#include "base/stats/events.hh"
+#include "config/full_system.hh"
+#include "cpu/base.hh"
+#include "cpu/simple_thread.hh"
+#include "cpu/thread_context.hh"
+#include "kern/kernel_stats.hh"
+#include "sim/debug.hh"
+#include "sim/sim_exit.hh"
+#include "arch/mips/mips_core_specific.hh"
+
+#if FULL_SYSTEM
+
+using namespace MipsCore;
+
+////////////////////////////////////////////////////////////////////////
+//
+//  Machine dependent functions
+//
+void
+MipsISA::initCPU(ThreadContext *tc, int cpuId)
+{
+
+ //    MipsFault *reset = new ResetFault;
+//     tc->setPC(reset->vect());
+//     tc->setNextPC(tc->readPC() + sizeof(MachInst));
+
+//     delete reset;
+}
+
+template <class CPU>
+void
+MipsISA::processInterrupts(CPU *cpu)
+{
+    //Check if there are any outstanding interrupts
+    //Handle the interrupts
+  /*    int ipl = 0;
+    int summary = 0;
+
+    cpu->checkInterrupts = false;
+
+    if (cpu->readMiscReg(IPR_ASTRR))
+        panic("asynchronous traps not implemented\n");
+
+    if (cpu->readMiscReg(IPR_SIRR)) {
+        for (int i = INTLEVEL_SOFTWARE_MIN;
+             i < INTLEVEL_SOFTWARE_MAX; i++) {
+            if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
+                // See table 4-19 of the 21164 hardware reference
+                ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
+                summary |= (ULL(1) << i);
+            }
+        }
+    }
+
+    uint64_t interrupts = cpu->intr_status();
+
+    if (interrupts) {
+        for (int i = INTLEVEL_EXTERNAL_MIN;
+             i < INTLEVEL_EXTERNAL_MAX; i++) {
+            if (interrupts & (ULL(1) << i)) {
+                // See table 4-19 of the 21164 hardware reference
+                ipl = i;
+                summary |= (ULL(1) << i);
+            }
+        }
+    }
+
+    if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
+        cpu->setMiscReg(IPR_ISR, summary);
+        cpu->setMiscReg(IPR_INTID, ipl);
+        cpu->trap(new InterruptFault);
+        DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
+                cpu->readMiscReg(IPR_IPLR), ipl, summary);
+    }
+  */
+}
+
+
+/*int
+MipsISA::MiscRegFile::getInstAsid()
+{
+    return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
+}
+
+int
+MipsISA::MiscRegFile::getDataAsid()
+{
+    return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
+    }*/
+
+
+
+#endif // FULL_SYSTEM || BARE_IRON

src/arch/mips/mips_core_specific.hh

@@ -0,0 +1,62 @@
+/*
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ *
+ * This software is part of the M5 simulator.
+ *
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+ * TO THESE TERMS AND CONDITIONS.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Jaidev Patwardhan
+ *
+ */
+
+
+#ifndef __ARCH_MIPS_CORE_SPECIFIC_HH__
+#define __ARCH_MIPS_CORE_SPECIFIC_HH__
+
+#include "arch/mips/isa_traits.hh"
+
+namespace MipsCore {
+
+//It seems like a safe assumption MipsCore only applies to mips
+using namespace MipsISA;
+
+const unsigned VABits = 32;
+const unsigned PABits = 32; // Is this correct?
+const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
+const Addr VAddrUnImplMask = ~VAddrImplMask;
+inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
+inline Addr VAddrVPN(Addr a) { return a >> MipsISA::PageShift; }
+inline Addr VAddrOffset(Addr a) { return a & MipsISA::PageOffset; }
+
+const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
+
+
+/* namespace MipsCore */ }
+
+#endif // __ARCH_MIPS_CORE_SPECIFIC_HH__

src/arch/mips/mmaped_ipr.hh

@@ -1,31 +1,38 @@
 /*
- * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
+ * This software is part of the M5 simulator.
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * TO THESE TERMS AND CONDITIONS.
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * Permission is granted to use, copy, create derivative works and
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * distribute this software and such derivative works for any purpose,
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * so long as (1) the copyright notice above, this grant of permission,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * and the disclaimer below appear in all copies and derivative works
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * made, (2) the copyright notice above is augmented as appropriate to
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * reflect the addition of any new copyrightable work in a derivative
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Jaidev Patwardhan
  *
- * Authors: Ali Saidi
  */
 
 #ifndef __ARCH_MIPS_MMAPED_IPR_HH__

src/arch/mips/mt.hh

@@ -1,31 +1,38 @@
 /*
- * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
+ * This software is part of the M5 simulator.
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * TO THESE TERMS AND CONDITIONS.
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * Permission is granted to use, copy, create derivative works and
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * distribute this software and such derivative works for any purpose,
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * so long as (1) the copyright notice above, this grant of permission,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * and the disclaimer below appear in all copies and derivative works
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * made, (2) the copyright notice above is augmented as appropriate to
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * reflect the addition of any new copyrightable work in a derivative
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Jaidev Patwardhan
  *
- * Authors: Korey Sewell
  */
 
 #ifndef __ARCH_MIPS_MT_HH__

src/arch/mips/mt_constants.hh

@@ -1,36 +1,44 @@
 /*
- * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
+ * This software is part of the M5 simulator.
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * TO THESE TERMS AND CONDITIONS.
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * Permission is granted to use, copy, create derivative works and
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * distribute this software and such derivative works for any purpose,
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * so long as (1) the copyright notice above, this grant of permission,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * and the disclaimer below appear in all copies and derivative works
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * made, (2) the copyright notice above is augmented as appropriate to
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * reflect the addition of any new copyrightable work in a derivative
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Jaidev Patwardhan
  *
- * Authors: Korey Sewell
  */
 
 #ifndef __ARCH_MIPS_MT_CONSTANTS_HH__
 #define __ARCH_MIPS_MT_CONSTANTS_HH__
 
+#include "arch/mips/types.hh"
 //#include "config/full_system.hh"
 
 namespace MipsISA

src/arch/mips/pagetable.cc

@@ -0,0 +1,82 @@
+/*
+ * Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ *
+ * This software is part of the M5 simulator.
+ *
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+ * TO THESE TERMS AND CONDITIONS.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Jaidev Patwardhan
+ *
+ */
+
+#include "arch/mips/pagetable.hh"
+#include "sim/serialize.hh"
+
+namespace MipsISA
+{
+
+
+    void
+    PTE::serialize(std::ostream &os)
+    {
+        SERIALIZE_SCALAR(Mask);
+        SERIALIZE_SCALAR(VPN);
+        SERIALIZE_SCALAR(asid);
+        SERIALIZE_SCALAR(G);
+        SERIALIZE_SCALAR(PFN0);
+        SERIALIZE_SCALAR(D0);
+        SERIALIZE_SCALAR(V0);
+        SERIALIZE_SCALAR(C0);
+        SERIALIZE_SCALAR(PFN1);
+        SERIALIZE_SCALAR(D1);
+        SERIALIZE_SCALAR(V1);
+        SERIALIZE_SCALAR(C1);
+        SERIALIZE_SCALAR(AddrShiftAmount);
+        SERIALIZE_SCALAR(OffsetMask);
+    }
+
+    void
+    PTE::unserialize(Checkpoint *cp, const std::string &section)
+    {
+        UNSERIALIZE_SCALAR(Mask);
+        UNSERIALIZE_SCALAR(VPN);
+        UNSERIALIZE_SCALAR(asid);
+        UNSERIALIZE_SCALAR(G);
+        UNSERIALIZE_SCALAR(PFN0);
+        UNSERIALIZE_SCALAR(D0);
+        UNSERIALIZE_SCALAR(V0);
+        UNSERIALIZE_SCALAR(C0);
+        UNSERIALIZE_SCALAR(PFN1);
+        UNSERIALIZE_SCALAR(D1);
+        UNSERIALIZE_SCALAR(V1);
+        UNSERIALIZE_SCALAR(C1);
+        UNSERIALIZE_SCALAR(AddrShiftAmount);
+        UNSERIALIZE_SCALAR(OffsetMask);
+    }
+}

src/arch/mips/pagetable.hh

@@ -0,0 +1,103 @@
+/*
+ * Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ *
+ * This software is part of the M5 simulator.
+ *
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+ * TO THESE TERMS AND CONDITIONS.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Jaidev Patwardhan
+ *
+ */
+
+#ifndef __ARCH_MIPS_PAGETABLE_H__
+#define __ARCH_MIPS_PAGETABLE_H__
+
+#include "arch/mips/isa_traits.hh"
+#include "arch/mips/utility.hh"
+#include "config/full_system.hh"
+
+namespace MipsISA {
+
+    struct VAddr
+    {
+        static const int ImplBits = 43;
+        static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
+        static const Addr UnImplMask = ~ImplMask;
+
+        VAddr(Addr a) : addr(a) {}
+        Addr addr;
+        operator Addr() const { return addr; }
+        const VAddr &operator=(Addr a) { addr = a; return *this; }
+
+        Addr vpn() const { return (addr & ImplMask) >> PageShift; }
+        Addr page() const { return addr & Page_Mask; }
+        Addr offset() const { return addr & PageOffset; }
+
+        Addr level3() const
+        { return MipsISA::PteAddr(addr >> PageShift); }
+        Addr level2() const
+        { return MipsISA::PteAddr(addr >> NPtePageShift + PageShift); }
+        Addr level1() const
+        { return MipsISA::PteAddr(addr >> 2 * NPtePageShift + PageShift); }
+    };
+
+    // ITB/DTB page table entry
+    struct PTE
+    {
+      Addr Mask; // What parts of the VAddr (from bits 28..11) should be used in translation (includes Mask and MaskX from PageMask)
+      Addr VPN; // Virtual Page Number (/2) (Includes VPN2 + VPN2X .. bits 31..11 from EntryHi)
+      uint8_t asid; // Address Space ID (8 bits) // Lower 8 bits of EntryHi
+
+      bool G;    // Global Bit - Obtained by an *AND* of EntryLo0 and EntryLo1 G bit
+
+      /* Contents of Entry Lo0 */
+      Addr PFN0; // Physical Frame Number - Even
+      bool D0;   // Even entry Dirty Bit
+      bool V0;   // Even entry Valid Bit
+      uint8_t C0; // Cache Coherency Bits - Even
+
+      /* Contents of Entry Lo1 */
+      Addr PFN1; // Physical Frame Number - Odd
+      bool D1;   // Odd entry Dirty Bit
+      bool V1;   // Odd entry Valid Bit
+      uint8_t C1; // Cache Coherency Bits (3 bits)
+
+      /* The next few variables are put in as optimizations to reduce TLB lookup overheads */
+      /* For a given Mask, what is the address shift amount, and what is the OffsetMask */
+      int AddrShiftAmount;
+      int OffsetMask;
+
+      bool Valid() { return (V0 | V1);};
+        void serialize(std::ostream &os);
+        void unserialize(Checkpoint *cp, const std::string &section);
+    };
+
+};
+#endif // __ARCH_MIPS_PAGETABLE_H__
+

src/arch/mips/pra_constants.hh

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -63,18 +63,24 @@ namespace MipsISA
   const unsigned EntryLo0_PFN_LO  =  6;
   const unsigned EntryLo0_C_HI    =  5; // Coherency attribute of a Page (see Table 8-8, ARM Vol III)
   const unsigned EntryLo0_C_LO    =  3;
-  const unsigned EntryLo0_D       =  2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception
+  const unsigned EntryLo0_D_HI    =  2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception
-  const unsigned EntryLo0_V       =  1; // Valid Bit
+  const unsigned EntryLo0_D_LO    =  2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception
-  const unsigned EntryLo0_G       =  0; // Global Bit. From the ARM Vol-III, Table 8-5:
+  const unsigned EntryLo0_V_HI    =  1; // Valid Bit
+  const unsigned EntryLo0_V_LO    =  1; // Valid Bit
+  const unsigned EntryLo0_G_HI    =  0; // Global Bit. From the ARM Vol-III, Table 8-5:
+  const unsigned EntryLo0_G_LO    =  0; // Global Bit. From the ARM Vol-III, Table 8-5:
                                         // On a TLB write, the logical AND of the G bits from EntryLo0 and EntryLo1
                                         // becomes the G bit in the TLB entry. If the TLB entry G bit is 1, ASID comparisons are
                                         // ignored during TLB matches. On a read from a TLB entry, the G bits of both Lo0 and Lo1
                                         // reflect the state of the TLB G bit.
 
   // EntryLo1 - CP0 Reg3, Sel 0
-  const unsigned EntryLo1_G       =  0;
+  const unsigned EntryLo1_G_HI       =  0;
-  const unsigned EntryLo1_V       =  1; // Valid Bit
+  const unsigned EntryLo1_G_LO       =  0;
-  const unsigned EntryLo1_D       =  2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception
+  const unsigned EntryLo1_V_HI       =  1; // Valid Bit
+  const unsigned EntryLo1_V_LO       =  1; // Valid Bit
+  const unsigned EntryLo1_D_HI       =  2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception
+  const unsigned EntryLo1_D_LO       =  2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception
   const unsigned EntryLo1_C_HI    =  5; // Coherency attribute of a Page (see Table 8-8, ARM Vol III)
   const unsigned EntryLo1_C_LO    =  3;
   const unsigned EntryLo1_PFN_HI  = 29; //PFN defines the Page Frame Number (see Table 8-7, ARM Vol III)
@@ -104,6 +110,8 @@ namespace MipsISA
   const unsigned PageGrain_ASE_UP_LO = 30; //
   const unsigned PageGrain_ELPA = 29; // Used to enable support for large physical addresses in MIPS64 processors, unused in MIPS32
   const unsigned PageGrain_ESP = 28; // Enables support for 1KB pages (1==enabled,0==disabled), See ARM Vol-III, Table 8-12
+  const unsigned PageGrain_ESP_HI = 28; // Enables support for 1KB pages (1==enabled,0==disabled), See ARM Vol-III, Table 8-12
+  const unsigned PageGrain_ESP_LO = 28; // Enables support for 1KB pages (1==enabled,0==disabled), See ARM Vol-III, Table 8-12
   const unsigned PageGrain_ASE_DN_HI = 12;
   const unsigned PageGrain_ASE_DN_LO = 8;
   // Bits 27-13, 7-0 are zeros
@@ -130,12 +138,12 @@ namespace MipsISA
   const unsigned Count_LO = 0;
 
   // EntryHI Register - CP0 Reg 10, Sel 0
-  const unsigned Entry_HI_VPN2_HI = 31;  // This field is written by hardware on a TLB exception or on a TLB read
+  const unsigned EntryHi_VPN2_HI = 31;  // This field is written by hardware on a TLB exception or on a TLB read
-  const unsigned Entry_HI_VPN2_LO = 13;  // and is written by software before a TLB write
+  const unsigned EntryHi_VPN2_LO = 13;  // and is written by software before a TLB write
-  const unsigned Entry_HI_VPN2X_HI = 12; // Extension to support 1KB pages
+  const unsigned EntryHi_VPN2X_HI = 12; // Extension to support 1KB pages
-  const unsigned Entry_HI_VPN2X_LO = 11;
+  const unsigned EntryHi_VPN2X_LO = 11;
-  const unsigned Entry_HI_ASID_HI = 7; // Address space identifier
+  const unsigned EntryHi_ASID_HI = 7; // Address space identifier
-  const unsigned Entry_HI_ASID_LO = 0;
+  const unsigned EntryHi_ASID_LO = 0;
 
   // Compare Register - CP0 Reg 11, Sel 0
   const unsigned Compare_HI = 31; // Used in conjunction with Count
@@ -145,6 +153,7 @@ namespace MipsISA
   const unsigned Status_IE_HI = 0;
   const unsigned Status_IE_LO = 0;
 
+  const unsigned Status_EXL = 1;
   const unsigned Status_EXL_HI = 1;
   const unsigned Status_EXL_LO = 1;
   const unsigned Status_ERL_HI = 2;
@@ -172,6 +181,8 @@ namespace MipsISA
   const unsigned Status_SR = 20;
   const unsigned Status_TS = 21;
   const unsigned Status_BEV = 22;
+  const unsigned Status_BEV_HI = 22;
+  const unsigned Status_BEV_LO = 22;
   const unsigned Status_PX = 23;
   const unsigned Status_MX = 24;
   const unsigned Status_RE = 25;
@@ -229,8 +240,10 @@ namespace MipsISA
   const unsigned SRSMap_SSV0_LO = 20;
 
   // Cause Register - CP0 Reg 13, Sel 0
-  const unsigned Cause_BD = 31;
+  const unsigned Cause_BD_HI = 31;
-  const unsigned Cause_TI = 30;
+  const unsigned Cause_BD_LO = 31;
+  const unsigned Cause_TI_HI = 30;
+  const unsigned Cause_TI_LO = 30;
   const unsigned Cause_CE_HI = 29;
   const unsigned Cause_CE_LO = 28;
   const unsigned Cause_DC = 27;
@@ -286,14 +299,16 @@ namespace MipsISA
   const unsigned Config_KU_LO = 25;
   const unsigned Config_IMPL_HI = 24;
   const unsigned Config_IMPL_LO = 16;
-  const unsigned Config_BE = 15;
+  const unsigned Config_BE_HI = 15;
+  const unsigned Config_BE_LO = 15;
   const unsigned Config_AT_HI = 14;
   const unsigned Config_AT_LO = 13;
   const unsigned Config_AR_HI = 12;
   const unsigned Config_AR_LO = 10;
   const unsigned Config_MT_HI = 9;
   const unsigned Config_MT_LO = 7;
-  const unsigned Config_VI = 3;
+  const unsigned Config_VI_HI = 3;
+  const unsigned Config_VI_LO = 3;
   const unsigned Config_K0_HI = 2;
   const unsigned Config_K0_LO = 0;
 
@@ -313,13 +328,20 @@ namespace MipsISA
   const unsigned Config1_DL_LO = 10;
   const unsigned Config1_DA_HI = 9;
   const unsigned Config1_DA_LO = 7;
-  const unsigned Config1_C2 = 6;
+  const unsigned Config1_C2_HI = 6;
-  const unsigned Config1_MD = 5;
+  const unsigned Config1_C2_LO = 6;
-  const unsigned Config1_PC = 4;
+  const unsigned Config1_MD_HI = 5;
-  const unsigned Config1_WR = 3;
+  const unsigned Config1_MD_LO = 5;
-  const unsigned Config1_CA = 2;
+  const unsigned Config1_PC_HI = 4;
-  const unsigned Config1_EP = 1;
+  const unsigned Config1_PC_LO = 4;
-  const unsigned Config1_FP = 0;
+  const unsigned Config1_WR_HI = 3;
+  const unsigned Config1_WR_LO = 3;
+  const unsigned Config1_CA_HI = 2;
+  const unsigned Config1_CA_LO = 2;
+  const unsigned Config1_EP_HI = 1;
+  const unsigned Config1_EP_LO = 1;
+  const unsigned Config1_FP_HI = 0;
+  const unsigned Config1_FP_LO = 0;
 
 
   // Config2 Register - CP0 Reg 16, Sel 2
@@ -343,14 +365,23 @@ namespace MipsISA
 
   // Config3 Register - CP0 Reg 16, Sel 3
   const unsigned Config3_M = 31;
-  const unsigned Config3_DSPP = 10;
+  const unsigned Config3_DSPP_HI = 10;
-  const unsigned Config3_LPA=7;
+  const unsigned Config3_DSPP_LO = 10;
-  const unsigned Config3_VEIC=6;
+  const unsigned Config3_LPA_HI=7;
-  const unsigned Config3_VINT=5;
+  const unsigned Config3_LPA_LO=7;
+  const unsigned Config3_VEIC_HI=6;
+  const unsigned Config3_VEIC_LO=6;
+  const unsigned Config3_VINT_HI=5;
+  const unsigned Config3_VINT_LO=5;
   const unsigned Config3_SP=4;
-  const unsigned Config3_MT=2;
+  const unsigned Config3_SP_HI=4;
-  const unsigned Config3_SM=1;
+  const unsigned Config3_SP_LO=4;
-  const unsigned Config3_TL=0;
+  const unsigned Config3_MT_HI=2;
+  const unsigned Config3_MT_LO=2;
+  const unsigned Config3_SM_HI=1;
+  const unsigned Config3_SM_LO=1;
+  const unsigned Config3_TL_HI=0;
+  const unsigned Config3_TL_LO=0;
 
 
   // LLAddr Register - CP0 Reg 17, Sel 0

src/arch/mips/predecoder.hh

@@ -1,3 +1,4 @@
+
 /*
  * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.

src/arch/mips/process.cc

@@ -1,34 +1,39 @@
-
 /*
- * Copyright (c) 2003-2004 The Regents of The University of Michigan
+ * Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
+ * This software is part of the M5 simulator.
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * TO THESE TERMS AND CONDITIONS.
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Gabe Black
+ * Permission is granted to use, copy, create derivative works and
- *          Ali Saidi
+ * distribute this software and such derivative works for any purpose,
- *          Korey Sewell
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Gabe M. Black
+ *          Ali G. Saidi
+ *          Korey L. Sewell
  */
 
 #include "arch/mips/isa_traits.hh"
@@ -63,8 +68,5 @@ MipsLiveProcess::MipsLiveProcess(LiveProcessParams * params,
 void
 MipsLiveProcess::startup()
 {
-    if (checkpointRestored)
-        return;
-
     argsInit(MachineBytes, VMPageSize);
 }

src/arch/mips/process.hh

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003-2004 The Regents of The University of Michigan
+ * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without

src/arch/mips/regfile.cc

@@ -0,0 +1,221 @@
+/*
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ *
+ * This software is part of the M5 simulator.
+ *
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+ * TO THESE TERMS AND CONDITIONS.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Korey L. Sewell
+ */
+
+#ifndef __ARCH_MIPS_REGFILE_REGFILE_HH__
+#define __ARCH_MIPS_REGFILE_REGFILE_HH__
+
+#include "arch/mips/types.hh"
+#include "arch/mips/isa_traits.hh"
+#include "arch/mips/mt.hh"
+#include "arch/mips/regfile/int_regfile.hh"
+#include "arch/mips/regfile/float_regfile.hh"
+#include "arch/mips/regfile/misc_regfile.hh"
+#include "sim/faults.hh"
+
+class Checkpoint;
+class ThreadContext;
+
+using namespace MipsISA;
+
+void RegFile::clear()
+{
+    intRegFile.clear();
+    floatRegFile.clear();
+    miscRegFile.clear();
+}
+
+void RegFile::reset(std::string core_name, unsigned num_threads, unsigned num_vpes)
+{
+    bzero(&intRegFile, sizeof(intRegFile));
+    bzero(&floatRegFile, sizeof(floatRegFile));
+    miscRegFile.reset(core_name, num_threads, num_vpes);
+}
+
+IntReg RegFile::readIntReg(int intReg)
+{
+    return intRegFile.readReg(intReg);
+}
+
+Fault RegFile::setIntReg(int intReg, const IntReg &val)
+{
+    return intRegFile.setReg(intReg, val);
+}
+
+MiscReg RegFile::readMiscRegNoEffect(int miscReg, unsigned tid = 0)
+{
+    return miscRegFile.readRegNoEffect(miscReg, tid);
+}
+
+MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc,
+                             unsigned tid = 0)
+{
+    return miscRegFile.readReg(miscReg, tc, tid);
+}
+
+void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val, unsigned tid = 0)
+{
+    miscRegFile.setRegNoEffect(miscReg, val, tid);
+}
+
+void RegFile::setMiscReg(int miscReg, const MiscReg &val,
+                         ThreadContext * tc, unsigned tid = 0)
+{
+    miscRegFile.setReg(miscReg, val, tc, tid);
+}
+
+FloatRegVal RegFile::readFloatReg(int floatReg)
+{
+    return floatRegFile.readReg(floatReg,SingleWidth);
+}
+
+FloatRegVal RegFile::readFloatReg(int floatReg, int width)
+{
+    return floatRegFile.readReg(floatReg,width);
+}
+
+FloatRegBits RegFile::readFloatRegBits(int floatReg)
+{
+    return floatRegFile.readRegBits(floatReg,SingleWidth);
+}
+
+FloatRegBits RegFile::readFloatRegBits(int floatReg, int width)
+{
+    return floatRegFile.readRegBits(floatReg,width);
+}
+
+Fault RegFile::setFloatReg(int floatReg, const FloatRegVal &val)
+{
+    return floatRegFile.setReg(floatReg, val, SingleWidth);
+}
+
+Fault RegFile::setFloatReg(int floatReg, const FloatRegVal &val, int width)
+{
+    return floatRegFile.setReg(floatReg, val, width);
+}
+
+Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
+{
+    return floatRegFile.setRegBits(floatReg, val, SingleWidth);
+}
+
+Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
+{
+    return floatRegFile.setRegBits(floatReg, val, width);
+}
+
+Addr RegFile::readPC()
+{
+    return pc;
+}
+
+void RegFile::setPC(Addr val)
+{
+    pc = val;
+}
+
+Addr RegFile::readNextPC()
+{
+    return npc;
+}
+
+void RegFile::setNextPC(Addr val)
+{
+    npc = val;
+}
+
+Addr RegFile::readNextNPC()
+{
+    return nnpc;
+}
+
+void RegFile::setNextNPC(Addr val)
+{
+    nnpc = val;
+}
+
+void
+RegFile::serialize(std::ostream &os)
+{
+    intRegFile.serialize(os);
+    floatRegFile.serialize(os);
+    miscRegFile.serialize(os);
+
+    SERIALIZE_SCALAR(pc);
+    SERIALIZE_SCALAR(npc);
+    SERIALIZE_SCALAR(nnpc);
+}
+
+
+void
+RegFile::unserialize(Checkpoint *cp, const std::string &section)
+{
+    intRegFile.unserialize(cp, section);
+    floatRegFile.unserialize(cp, section);
+    miscRegFile.unserialize(cp, section);
+    UNSERIALIZE_SCALAR(pc);
+    UNSERIALIZE_SCALAR(npc);
+    UNSERIALIZE_SCALAR(nnpc);
+
+}
+
+
+void RegFile::changeContext(RegContextParam param, RegContextVal val)
+{
+    panic("Change Context Not Implemented for MipsISA");
+}
+
+static inline int flattenIntIndex(ThreadContext * tc, int reg)
+{
+    return reg;
+}
+
+void
+MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+    panic("Copy Regs Not Implemented Yet\n");
+}
+
+void
+MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest);
+{
+    panic("Copy Regs Not Implemented Yet\n");
+}
+
+void
+MipsISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+    panic("Copy Misc. Regs Not Implemented Yet\n");
+}

src/arch/mips/regfile.hh

@@ -1,33 +1,41 @@
 /*
- * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
+ * This software is part of the M5 simulator.
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * TO THESE TERMS AND CONDITIONS.
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * Permission is granted to use, copy, create derivative works and
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * distribute this software and such derivative works for any purpose,
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * so long as (1) the copyright notice above, this grant of permission,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * and the disclaimer below appear in all copies and derivative works
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * made, (2) the copyright notice above is augmented as appropriate to
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * reflect the addition of any new copyrightable work in a derivative
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Jaidev Patwardhan
  *
- * Authors: Korey Sewell
  */
 
+
 #ifndef __ARCH_MIPS_REGFILE_HH__
 #define __ARCH_MIPS_REGFILE_HH__
 

src/arch/mips/regfile/float_regfile.cc

@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ *          Korey Sewell
+ */
+
+#include "arch/mips/regfile/float_regfile.hh"
+#include "sim/serialize.hh"
+
+using namespace MipsISA;
+using namespace std;
+
+void
+FloatRegFile::clear()
+{
+    bzero(&regs, sizeof(regs));
+}
+
+double
+FloatRegFile::readReg(int floatReg, int width, unsigned tid)
+{
+    switch(width)
+    {
+      case SingleWidth:
+        {
+            void *float_ptr = &regs[floatReg];
+            return *(float *) float_ptr;
+        }
+
+      case DoubleWidth:
+        {
+            uint64_t double_val = (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg];
+            void *double_ptr = &double_val;
+            return *(double *) double_ptr;
+        }
+
+      default:
+        panic("Attempted to read a %d bit floating point register!", width);
+    }
+}
+
+FloatRegBits
+FloatRegFile::readRegBits(int floatReg, int width, unsigned tid)
+{
+    if (floatReg < NumFloatArchRegs - 1) {
+        switch(width)
+        {
+          case SingleWidth:
+            return regs[floatReg];
+
+          case DoubleWidth:
+            return (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg];
+
+          default:
+            panic("Attempted to read a %d bit floating point register!", width);
+        }
+    } else {
+        if (width > SingleWidth)
+            assert("Control Regs are only 32 bits wide");
+
+        return regs[floatReg];
+    }
+}
+
+Fault
+FloatRegFile::setReg(int floatReg, const FloatRegVal &val, int width, unsigned tid)
+{
+    using namespace std;
+    switch(width)
+    {
+      case SingleWidth:
+        {
+            float temp = val;
+            void *float_ptr = &temp;
+            regs[floatReg] = *(FloatReg32 *) float_ptr;
+            break;
+        }
+
+      case DoubleWidth:
+        {
+            const void *double_ptr = &val;
+            FloatReg64 temp_double = *(FloatReg64 *) double_ptr;
+            regs[floatReg + 1] = bits(temp_double, 63, 32);
+            regs[floatReg] = bits(temp_double, 31, 0);
+            break;
+        }
+
+      default:
+        panic("Attempted to read a %d bit floating point register!", width);
+    }
+
+    return NoFault;
+}
+
+Fault
+FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width, unsigned tid)
+{
+    using namespace std;
+
+    switch(width)
+    {
+      case SingleWidth:
+        regs[floatReg] = val;
+        break;
+
+      case DoubleWidth:
+        regs[floatReg + 1] = bits(val, 63, 32);
+        regs[floatReg] = bits(val, 31, 0);
+        break;
+
+      default:
+        panic("Attempted to read a %d bit floating point register!", width);
+    }
+    return NoFault;
+}
+
+void
+FloatRegFile::serialize(std::ostream &os)
+{
+    SERIALIZE_ARRAY(regs, NumFloatRegs);
+}
+
+void
+FloatRegFile::unserialize(Checkpoint *cp, const std::string &section)
+{
+    UNSERIALIZE_ARRAY(regs, NumFloatRegs);
+}

src/arch/mips/regfile/float_regfile.hh

@@ -88,104 +88,13 @@ namespace MipsISA
 
       public:
 
-        void clear() { bzero(&regs, sizeof(regs)); }
+        void clear();
-
+        double readReg(int floatReg, int width, unsigned tid = 0);
-        double readReg(int floatReg, int width, unsigned tid = 0)
+        FloatRegBits readRegBits(int floatReg, int width, unsigned tid = 0);
-        {
+        Fault setReg(int floatReg, const FloatRegVal &val, int width, unsigned tid = 0);
-            switch(width)
+        Fault setRegBits(int floatReg, const FloatRegBits &val, int width, unsigned tid = 0);
-            {
-              case SingleWidth:
-                {
-                    void *float_ptr = &regs[floatReg];
-                    return *(float *) float_ptr;
-                }
-
-              case DoubleWidth:
-                {
-                    uint64_t double_val = (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg];
-                    void *double_ptr = &double_val;
-                    return *(double *) double_ptr;
-                }
-
-              default:
-                panic("Attempted to read a %d bit floating point register!", width);
-            }
-        }
-
-        FloatRegBits readRegBits(int floatReg, int width, unsigned tid = 0)
-        {
-            if (floatReg < NumFloatArchRegs - 1) {
-                switch(width)
-                {
-                  case SingleWidth:
-                    return regs[floatReg];
-
-                  case DoubleWidth:
-                    return (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg];
-
-                  default:
-                    panic("Attempted to read a %d bit floating point register!", width);
-                }
-            } else {
-                if (width > SingleWidth)
-                    assert("Control Regs are only 32 bits wide");
-
-                return regs[floatReg];
-            }
-        }
-
-        Fault setReg(int floatReg, const FloatRegVal &val, int width, unsigned tid = 0)
-        {
-            using namespace std;
-            switch(width)
-            {
-              case SingleWidth:
-                {
-                    float temp = val;
-                    void *float_ptr = &temp;
-                    regs[floatReg] = *(FloatReg32 *) float_ptr;
-                    break;
-                }
-
-              case DoubleWidth:
-                {
-                    const void *double_ptr = &val;
-                    FloatReg64 temp_double = *(FloatReg64 *) double_ptr;
-                    regs[floatReg + 1] = bits(temp_double, 63, 32);
-                    regs[floatReg] = bits(temp_double, 31, 0);
-                    break;
-                }
-
-              default:
-                panic("Attempted to read a %d bit floating point register!", width);
-            }
-
-            return NoFault;
-        }
-
-        Fault setRegBits(int floatReg, const FloatRegBits &val, int width, unsigned tid = 0)
-        {
-            using namespace std;
-
-            switch(width)
-            {
-              case SingleWidth:
-                regs[floatReg] = val;
-                break;
-
-              case DoubleWidth:
-                regs[floatReg + 1] = bits(val, 63, 32);
-                regs[floatReg] = bits(val, 31, 0);
-                break;
-
-              default:
-                panic("Attempted to read a %d bit floating point register!", width);
-            }
-            return NoFault;
-        }
 
         void serialize(std::ostream &os);
-
         void unserialize(Checkpoint *cp, const std::string &section);
     };
 

src/arch/mips/regfile/int_regfile.cc

@@ -35,6 +35,61 @@
 using namespace MipsISA;
 using namespace std;
 
+
+void
+IntRegFile::clear()
+{
+    bzero(&regs, sizeof(regs));
+    currShadowSet=0;
+}
+
+void
+IntRegFile::setShadowSet(int css)
+{
+    DPRINTF(MipsPRA,"Setting Shadow Set to :%d (%s)\n",css,currShadowSet);
+    currShadowSet = css;
+}
+
+IntReg
+IntRegFile::readReg(int intReg)
+{
+    if(intReg < NumIntRegs)
+    { // Regular GPR Read
+        DPRINTF(MipsPRA,"Reading Reg: %d, CurrShadowSet: %d\n",intReg,currShadowSet);
+        if(intReg >= NumIntArchRegs*NumShadowRegSets){
+            return regs[intReg+NumIntRegs*currShadowSet];
+        }
+        else {
+            return regs[(intReg + NumIntArchRegs*currShadowSet) % NumIntArchRegs];
+        }
+    }
+    else
+    { // Read from shadow GPR .. probably called by RDPGPR
+        return regs[intReg];
+    }
+}
+
+Fault
+IntRegFile::setReg(int intReg, const IntReg &val)
+{
+    if (intReg != ZeroReg) {
+
+        if(intReg < NumIntRegs)
+        {
+            if(intReg >= NumIntArchRegs*NumShadowRegSets){
+                regs[intReg] = val;
+            }
+            else{
+                regs[intReg+NumIntRegs*currShadowSet] = val;
+            }
+        }
+        else{
+            regs[intReg] = val;
+        }
+    }
+    return NoFault;
+}
+
 void
 IntRegFile::serialize(std::ostream &os)
 {
@@ -46,3 +101,4 @@ IntRegFile::unserialize(Checkpoint *cp, const std::string &section)
 {
     UNSERIALIZE_ARRAY(regs, NumIntRegs);
 }
+

src/arch/mips/regfile/int_regfile.hh

@@ -34,10 +34,10 @@
 #include "arch/mips/types.hh"
 #include "arch/mips/isa_traits.hh"
 #include "base/misc.hh"
+#include "base/trace.hh"
 #include "sim/faults.hh"
 
 class Checkpoint;
-class ThreadContext;
 
 namespace MipsISA
 {
@@ -47,7 +47,7 @@ namespace MipsISA
     }
 
     enum MiscIntRegNums {
-       LO = NumIntArchRegs,
+       LO = NumIntArchRegs*NumShadowRegSets,
        HI,
        DSPACX0,
        DSPLo1,
@@ -68,26 +68,14 @@ namespace MipsISA
     {
       protected:
         IntReg regs[NumIntRegs];
-
+        int currShadowSet;
       public:
-        void clear() { bzero(&regs, sizeof(regs)); }
+        void clear();
-
+        void setShadowSet(int css);
-        IntReg readReg(int intReg)
+        IntReg readReg(int intReg);
-        {
+        Fault setReg(int intReg, const IntReg &val);
-            return regs[intReg];
-        }
-
-        Fault setReg(int intReg, const IntReg &val)
-        {
-            if (intReg != ZeroReg) {
-                regs[intReg] = val;
-            }
-
-            return NoFault;
-        }
 
         void serialize(std::ostream &os);
-
         void unserialize(Checkpoint *cp, const std::string &section);
 
     };

src/arch/mips/regfile/misc_regfile.cc

@@ -26,18 +26,18 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Korey Sewell
+ *          Jaidev Patwardhan
  */
 
 #include "base/bitfield.hh"
 
-#include "arch/mips/faults.hh"
-#include "arch/mips/mt.hh"
-#include "arch/mips/mt_constants.hh"
 #include "arch/mips/regfile/misc_regfile.hh"
+#include "arch/mips/mt_constants.hh"
+#include "arch/mips/pra_constants.hh"
 
-#include "cpu/base.hh"
 #include "cpu/thread_context.hh"
-//#include "cpu/mixie/cpu.hh"
+#include "cpu/base.hh"
+#include "cpu/exetrace.hh"
 
 using namespace std;
 
@@ -99,6 +99,11 @@ MiscRegFile::init()
         bankType[i] = perProcessor;
     }
 
+    miscRegFile_WriteMask.resize(NumMiscRegs);
+
+    for (int i=0; i < NumMiscRegs; i++) {
+      miscRegFile_WriteMask[i].push_back(0);
+    }
     clear(0);
 }
 
@@ -107,6 +112,7 @@ MiscRegFile::clear(unsigned tid_or_vpn)
 {
     for(int i = 0; i < NumMiscRegs; i++) {
         miscRegFile[i][tid_or_vpn] = 0;
+        miscRegFile_WriteMask[i][tid_or_vpn] = (long unsigned int)(-1);
     }
 }
 
@@ -147,39 +153,195 @@ MiscRegFile::expandForMultithreading(unsigned num_threads, unsigned num_vpes)
     }
 
 }
+int MiscRegFile::getInstAsid()
+{
+  MiscReg Entry_Hi = readRegNoEffect(EntryHi);
+  return bits(Entry_Hi,EntryHi_ASID_HI,EntryHi_ASID_LO);
+}
 
+int MiscRegFile:: getDataAsid()
+{
+  MiscReg EHi = readRegNoEffect(EntryHi);
+  return bits(EHi,EntryHi_ASID_HI,EntryHi_ASID_LO);
+}
 //@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
 void
 MiscRegFile::reset(std::string core_name, unsigned num_threads,
-                   unsigned num_vpes)
+                   unsigned num_vpes, BaseCPU *_cpu)
 {
+
     DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
             num_threads, num_vpes);
-
+    cpu = _cpu;
+    const BaseCPU::Params *p = _cpu->params;
     // Do Default CP0 initialization HERE
 
     // Do Initialization for MT cores here (eventually use
     // core_name parameter to toggle this initialization)
     // ===================================================
+    DPRINTF(MipsPRA, "Initializing CP0 State.... ");
+
+    MiscReg ProcID = readRegNoEffect(PRId);
+    replaceBits(ProcID,PRIdCoOp_HI,PRIdCoOp_LO,p->CP0_PRId_CompanyOptions);
+    replaceBits(ProcID,PRIdCoID_HI,PRIdCoID_LO,p->CP0_PRId_CompanyID);
+    replaceBits(ProcID,PRIdProc_ID_HI,PRIdProc_ID_LO,p->CP0_PRId_ProcessorID);
+    replaceBits(ProcID,PRIdRev_HI,PRIdRev_LO,p->CP0_PRId_Revision);
+    setRegNoEffect(PRId,ProcID);
+    // Now, create Write Mask for ProcID register
+    MiscReg ProcID_Mask = 0; // Read-Only register
+    replaceBits(ProcID_Mask,0,32,0);
+    setRegMask(PRId,ProcID_Mask);
+
     // Config
     MiscReg cfg = readRegNoEffect(Config);
-    replaceBits(cfg, CFG_M, 1);
+    replaceBits(cfg, Config_BE_HI, Config_BE_LO, p->CP0_Config_BE);
+    replaceBits(cfg, Config_AT_HI, Config_AT_LO, p->CP0_Config_AT);
+    replaceBits(cfg, Config_AR_HI, Config_AR_LO, p->CP0_Config_AR);
+    replaceBits(cfg, Config_MT_HI, Config_MT_LO, p->CP0_Config_MT);
+    replaceBits(cfg, Config_VI_HI, Config_VI_LO, p->CP0_Config_VI);
+    replaceBits(cfg, Config_M, 1);
     setRegNoEffect(Config, cfg);
+    // Now, create Write Mask for Config register
+    MiscReg cfg_Mask = 0x7FFF0007;
+    replaceBits(cfg_Mask,0,32,0);
+    setRegMask(Config,cfg_Mask);
 
     // Config1
     MiscReg cfg1 = readRegNoEffect(Config1);
-    replaceBits(cfg1, CFG1_M, 1);
+    replaceBits(cfg1, Config1_MMUSize_HI, Config1_MMUSize_LO, p->CP0_Config1_MMU);
+    replaceBits(cfg1, Config1_IS_HI, Config1_IS_LO, p->CP0_Config1_IS);
+    replaceBits(cfg1, Config1_IL_HI, Config1_IL_LO, p->CP0_Config1_IL);
+    replaceBits(cfg1, Config1_IA_HI, Config1_IA_LO, p->CP0_Config1_IA);
+    replaceBits(cfg1, Config1_DS_HI, Config1_DS_LO, p->CP0_Config1_DS);
+    replaceBits(cfg1, Config1_DL_HI, Config1_DL_LO, p->CP0_Config1_DL);
+    replaceBits(cfg1, Config1_DA_HI, Config1_DA_LO, p->CP0_Config1_DA);
+    replaceBits(cfg1, Config1_FP_HI, Config1_FP_LO, p->CP0_Config1_FP);
+    replaceBits(cfg1, Config1_EP_HI, Config1_EP_LO, p->CP0_Config1_EP);
+    replaceBits(cfg1, Config1_WR_HI, Config1_WR_LO, p->CP0_Config1_WR);
+    replaceBits(cfg1, Config1_MD_HI, Config1_MD_LO, p->CP0_Config1_MD);
+    replaceBits(cfg1, Config1_C2_HI, Config1_C2_LO, p->CP0_Config1_C2);
+    replaceBits(cfg1, Config1_PC_HI, Config1_PC_LO, p->CP0_Config1_PC);
+    replaceBits(cfg1, Config1_M, p->CP0_Config1_M);
     setRegNoEffect(Config1, cfg1);
+    // Now, create Write Mask for Config register
+    MiscReg cfg1_Mask = 0; // Read Only Register
+    replaceBits(cfg1_Mask,0,32,0);
+    setRegMask(Config1,cfg1_Mask);
 
     // Config2
     MiscReg cfg2 = readRegNoEffect(Config2);
-    replaceBits(cfg2, CFG2_M, 1);
+    replaceBits(cfg2, Config2_TU_HI, Config2_TU_LO, p->CP0_Config2_TU);
+    replaceBits(cfg2, Config2_TS_HI, Config2_TS_LO, p->CP0_Config2_TS);
+    replaceBits(cfg2, Config2_TL_HI, Config2_TL_LO, p->CP0_Config2_TL);
+    replaceBits(cfg2, Config2_TA_HI, Config2_TA_LO, p->CP0_Config2_TA);
+    replaceBits(cfg2, Config2_SU_HI, Config2_SU_LO, p->CP0_Config2_SU);
+    replaceBits(cfg2, Config2_SS_HI, Config2_SS_LO, p->CP0_Config2_SS);
+    replaceBits(cfg2, Config2_SL_HI, Config2_SL_LO, p->CP0_Config2_SL);
+    replaceBits(cfg2, Config2_SA_HI, Config2_SA_LO, p->CP0_Config2_SA);
+    replaceBits(cfg2, Config2_M, p->CP0_Config2_M);
     setRegNoEffect(Config2, cfg2);
+    // Now, create Write Mask for Config register
+    MiscReg cfg2_Mask = 0x7000F000; // Read Only Register
+    replaceBits(cfg2_Mask,0,32,0);
+    setRegMask(Config2,cfg2_Mask);
 
     // Config3
     MiscReg cfg3 = readRegNoEffect(Config3);
-    replaceBits(cfg3, CFG3_MT, 1);
+    replaceBits(cfg3, Config3_DSPP_HI, Config3_DSPP_LO, p->CP0_Config3_DSPP);
+    replaceBits(cfg3, Config3_LPA_HI, Config3_LPA_LO, p->CP0_Config3_LPA);
+    replaceBits(cfg3, Config3_VEIC_HI, Config3_VEIC_LO, p->CP0_Config3_VEIC);
+    replaceBits(cfg3, Config3_VINT_HI, Config3_VINT_LO, p->CP0_Config3_VInt);
+    replaceBits(cfg3, Config3_SP_HI, Config3_SP_LO, p->CP0_Config3_SP);
+    replaceBits(cfg3, Config3_MT_HI, Config3_MT_LO, p->CP0_Config3_MT);
+    replaceBits(cfg3, Config3_SM_HI, Config3_SM_LO, p->CP0_Config3_SM);
+    replaceBits(cfg3, Config3_TL_HI, Config3_TL_LO, p->CP0_Config3_TL);
     setRegNoEffect(Config3, cfg3);
+    // Now, create Write Mask for Config register
+    MiscReg cfg3_Mask = 0; // Read Only Register
+    replaceBits(cfg3_Mask,0,32,0);
+    setRegMask(Config3,cfg3_Mask);
+
+    // EBase - CPUNum
+    MiscReg EB = readRegNoEffect(EBase);
+    replaceBits(EB, EBase_CPUNum_HI, EBase_CPUNum_LO, p->CP0_EBase_CPUNum);
+    replaceBits(EB, 31, 31, 1);
+    setRegNoEffect(EBase, EB);
+    // Now, create Write Mask for Config register
+    MiscReg EB_Mask = 0x3FFFF000;// Except Exception Base, the
+                                 // entire register is read only
+    replaceBits(EB_Mask,0,32,0);
+    setRegMask(EBase,EB_Mask);
+
+    // SRS Control - HSS (Highest Shadow Set)
+    MiscReg SC = readRegNoEffect(SRSCtl);
+    replaceBits(SC, SRSCtl_HSS_HI,SRSCtl_HSS_LO,p->CP0_SrsCtl_HSS);
+    setRegNoEffect(SRSCtl, SC);
+    // Now, create Write Mask for the SRS Ctl register
+    MiscReg SC_Mask = 0x0000F3C0;
+    replaceBits(SC_Mask,0,32,0);
+    setRegMask(SRSCtl,SC_Mask);
+
+    // IntCtl - IPTI, IPPCI
+    MiscReg IC = readRegNoEffect(IntCtl);
+    replaceBits(IC, IntCtl_IPTI_HI,IntCtl_IPTI_LO,p->CP0_IntCtl_IPTI);
+    replaceBits(IC, IntCtl_IPPCI_HI,IntCtl_IPPCI_LO,p->CP0_IntCtl_IPPCI);
+    setRegNoEffect(IntCtl, IC);
+    // Now, create Write Mask for the IntCtl register
+    MiscReg IC_Mask = 0x000003E0;
+    replaceBits(IC_Mask,0,32,0);
+    setRegMask(IntCtl,IC_Mask);
+
+    // Watch Hi - M - FIXME (More than 1 Watch register)
+    MiscReg WHi = readRegNoEffect(WatchHi0);
+    replaceBits(WHi, WatchHi_M, p->CP0_WatchHi_M);
+    setRegNoEffect(WatchHi0, WHi);
+    // Now, create Write Mask for the IntCtl register
+    MiscReg wh_Mask = 0x7FFF0FFF;
+    replaceBits(wh_Mask,0,32,0);
+    setRegMask(WatchHi0,wh_Mask);
+
+    // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
+    MiscReg PCtr = readRegNoEffect(PerfCnt0);
+    replaceBits(PCtr, PerfCntCtl_M, p->CP0_PerfCtr_M);
+    replaceBits(PCtr, PerfCntCtl_W, p->CP0_PerfCtr_W);
+    setRegNoEffect(PerfCnt0, PCtr);
+    // Now, create Write Mask for the IntCtl register
+    MiscReg pc_Mask = 0x00007FF;
+    replaceBits(pc_Mask,0,32,0);
+    setRegMask(PerfCnt0,pc_Mask);
+
+    // Random
+    MiscReg random = readRegNoEffect(CP0_Random);
+    random = 63;
+    setRegNoEffect(CP0_Random, random);
+    // Now, create Write Mask for the IntCtl register
+    MiscReg random_Mask = 0;
+    replaceBits(random_Mask,0,32,0);
+    setRegMask(CP0_Random,random_Mask);
+
+    // PageGrain
+    MiscReg pagegrain = readRegNoEffect(PageGrain);
+    replaceBits(pagegrain,PageGrain_ESP,p->CP0_Config3_SP);
+    setRegNoEffect(PageGrain, pagegrain);
+    // Now, create Write Mask for the IntCtl register
+    MiscReg pg_Mask = 0x10000000;
+    replaceBits(pg_Mask,0,32,0);
+    setRegMask(PageGrain,pg_Mask);
+
+    // Status
+    MiscReg stat = readRegNoEffect(Status);
+    // Only CU0 and IE are modified on a reset - everything else needs to be controlled
+       // on a per CPU model basis
+    //    replaceBits(stat, Status_CU0_HI,Status_CU0_LO, 1); // Enable CP0 on reset
+
+    replaceBits(stat, Status_ERL_HI, Status_ERL_LO, 1); // Enable ERL bit on a reset
+    replaceBits(stat, Status_BEV_HI, Status_BEV_LO, 1); // Enable BEV bit on a reset
+    setRegNoEffect(Status, stat);
+    // Now, create Write Mask for the Status register
+    MiscReg stat_Mask = 0xFF78FF17;
+    replaceBits(stat_Mask,0,32,0);
+    setRegMask(Status,stat_Mask);
+
 
     // MVPConf0
     MiscReg mvp_conf0 = readRegNoEffect(MVPConf0);
@@ -199,7 +361,6 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
         replaceBits(tc_bind, TCB_CUR_TC_HI, TCB_CUR_TC_LO, tid);
         setRegNoEffect(TCBind, tc_bind, tid);
     }
-
     // TCHalt
     MiscReg tc_halt = readRegNoEffect(TCHalt);
     replaceBits(tc_halt, TCH_H, 0);
@@ -218,11 +379,41 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
     setRegNoEffect(TCStatus, tc_status);
 
     // Set Dynamically Allocatable bit to 1 for all other threads
-    for (int tid = 0; tid < num_threads; tid++) {
+    for (int tid = 1; tid < num_threads; tid++) {
         tc_status = readRegNoEffect(TCStatus, tid);
         replaceBits(tc_status, TCSTATUS_DA, 1);
         setRegNoEffect(TCStatus, tc_status, tid);
     }
+
+
+    MiscReg Mask = 0x7FFFFFFF;
+
+    // Now, create Write Mask for the Index register
+    replaceBits(Mask,0,32,0);
+    setRegMask(Index,Mask);
+
+    Mask = 0x3FFFFFFF;
+    replaceBits(Mask,0,32,0);
+    setRegMask(EntryLo0,Mask);
+    setRegMask(EntryLo1,Mask);
+
+    Mask = 0xFF800000;
+    replaceBits(Mask,0,32,0);
+    setRegMask(Context,Mask);
+
+    Mask = 0x1FFFF800;
+    replaceBits(Mask,0,32,0);
+    setRegMask(PageMask,Mask);
+
+    Mask = 0x0;
+    replaceBits(Mask,0,32,0);
+    setRegMask(BadVAddr,Mask);
+    setRegMask(LLAddr,Mask);
+
+    Mask = 0x08C00300;
+    replaceBits(Mask,0,32,0);
+    setRegMask(Cause,Mask);
+
 }
 
 inline std::string
@@ -234,30 +425,34 @@ MipsISA::getMiscRegName(unsigned reg_idx)
 inline unsigned
 MiscRegFile::getVPENum(unsigned tid)
 {
-    unsigned tc_bind = miscRegFile[TCBind][tid];
+    unsigned tc_bind = miscRegFile[TCBind - Ctrl_Base_DepTag][tid];
     return bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
 }
 
 MiscReg
-MiscRegFile::readRegNoEffect(int misc_reg, unsigned tid)
+MiscRegFile::readRegNoEffect(int reg_idx, unsigned tid)
 {
+    int misc_reg = reg_idx - Ctrl_Base_DepTag;
     unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
         ? tid : getVPENum(tid);
-
+    DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
+            misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg),miscRegFile[misc_reg][reg_sel]);
     return miscRegFile[misc_reg][reg_sel];
 }
 
 //@TODO: MIPS MT's register view automatically connects
 //       Status to TCStatus depending on current thread
+//template <class TC>
 MiscReg
-MiscRegFile::readReg(int misc_reg,
+MiscRegFile::readReg(int reg_idx,
                                ThreadContext *tc,  unsigned tid)
 {
-    DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) with effect.\n",
+    int misc_reg = reg_idx - Ctrl_Base_DepTag;
-            misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg));
-
     unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
         ? tid : getVPENum(tid);
+    DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
+            misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg),miscRegFile[misc_reg][reg_sel]);
+
 
     switch (misc_reg)
     {
@@ -267,35 +462,61 @@ MiscRegFile::readReg(int misc_reg,
 }
 
 void
-MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid)
+MiscRegFile::setRegNoEffect(int reg_idx, const MiscReg &val, unsigned tid)
 {
+    int misc_reg = reg_idx - Ctrl_Base_DepTag;
     unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
         ? tid : getVPENum(tid);
+    DPRINTF(MipsPRA, "[tid:%i]: Setting (direct set) CP0 Register:%u Select:%u (%s) to %#x.\n",
+            tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val);
 
     miscRegFile[misc_reg][reg_sel] = val;
 }
+void
+MiscRegFile::setRegMask(int reg_idx, const MiscReg &val, unsigned tid)
+{
+  //  return;
+  int misc_reg = reg_idx - Ctrl_Base_DepTag;
+    unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
+        ? tid : getVPENum(tid);
+    DPRINTF(MipsPRA,"[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n",tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val);
+    miscRegFile_WriteMask[misc_reg][reg_sel] = val;
+}
 
 // PROGRAMMER'S NOTES:
 // (1) Some CP0 Registers have fields that cannot
 // be overwritten. Make sure to handle those particular registers
 // with care!
+//template <class TC>
 void
-MiscRegFile::setReg(int misc_reg, const MiscReg &val,
+MiscRegFile::setReg(int reg_idx, const MiscReg &val,
                               ThreadContext *tc, unsigned tid)
 {
-    unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
+    int misc_reg = reg_idx - Ctrl_Base_DepTag;
+    int reg_sel = (bankType[misc_reg] == perThreadContext)
         ? tid : getVPENum(tid);
 
     DPRINTF(MipsPRA, "[tid:%i]: Setting CP0 Register:%u Select:%u (%s) to %#x, with effect.\n",
             tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val);
 
-    MiscReg cp0_val = filterCP0Write(misc_reg, val);
+    MiscReg cp0_val = filterCP0Write(misc_reg, reg_sel, val);
 
     miscRegFile[misc_reg][reg_sel] = cp0_val;
 
-    scheduleCP0Update();
+    scheduleCP0Update(1);
+}
+/** This method doesn't need to adjust the Control Register Offset since
+    it has already been done in the calling method (setRegWithEffect) */
+MiscReg MiscRegFile::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
+{
+  MiscReg retVal = val;
+  retVal &= miscRegFile_WriteMask[misc_reg][reg_sel]; // Mask off read-only regions
+  MiscReg curVal = miscRegFile[misc_reg][reg_sel];
+  curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]); // Mask off current alue with inverse mask (clear writeable bits)
+  retVal |= curVal; // Combine the two
+  DPRINTF(MipsPRA,"filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, current val: %lx, written val: %x\n",miscRegFile_WriteMask[misc_reg][reg_sel],~miscRegFile_WriteMask[misc_reg][reg_sel],val,miscRegFile[misc_reg][reg_sel],retVal);
+  return retVal;
 }
-
 void
 MiscRegFile::scheduleCP0Update(int delay)
 {
@@ -357,7 +578,7 @@ MiscRegFile::CP0Event::process()
 const char *
 MiscRegFile::CP0Event::description()
 {
-    return "Coprocessor-0";
+    return "Coprocessor-0 event";
 }
 
 void

src/arch/mips/regfile/misc_regfile.hh

@@ -26,6 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Korey Sewell
+ *          Jaidev Patwardhan
  */
 
 #ifndef __ARCH_MIPS_REGFILE_MISC_REGFILE_HH__
@@ -33,11 +34,13 @@
 
 #include "arch/mips/isa_traits.hh"
 #include "arch/mips/types.hh"
+#include "arch/mips/mt.hh"
+#include "arch/mips/mt_constants.hh"
+#include "base/bitfield.hh"
 #include "sim/eventq.hh"
-#include "sim/faults.hh"
 #include <queue>
 
-class ThreadContext;
+class Params;
 class BaseCPU;
 
 namespace MipsISA
@@ -58,6 +61,7 @@ namespace MipsISA
         };
 
         std::vector<std::vector<MiscReg> > miscRegFile;
+        std::vector<std::vector<MiscReg> > miscRegFile_WriteMask;
         std::vector<BankType> bankType;
 
         BaseCPU *cpu;
@@ -70,15 +74,10 @@ namespace MipsISA
 
         void clear(unsigned tid_or_vpn = 0);
 
-        void reset(std::string core_name, unsigned num_threads, unsigned num_vpes);
+        void reset(std::string core_name, unsigned num_threads, unsigned num_vpes, BaseCPU *_cpu);
 
         void expandForMultithreading(unsigned num_threads, unsigned num_vpes);
 
-        void copyMiscRegs(ThreadContext *tc)
-        {
-            panic("Copy Misc. Regs Not Implemented Yet\n");
-        }
-
         inline unsigned getVPENum(unsigned tid);
 
         //////////////////////////////////////////////////////////
@@ -91,14 +90,22 @@ namespace MipsISA
         //       Status to TCStatus depending on current thread
         void updateCP0ReadView(int misc_reg, unsigned tid) { }
         MiscReg readRegNoEffect(int misc_reg, unsigned tid = 0);
+
+        //template <class TC>
         MiscReg readReg(int misc_reg,
                         ThreadContext *tc,  unsigned tid = 0);
 
-        MiscReg filterCP0Write(int misc_reg, MiscReg val) { return val; }
+        MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val);
+        void setRegMask(int misc_reg, const MiscReg &val, unsigned tid = 0);
         void setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0);
+
+        //template <class TC>
         void setReg(int misc_reg, const MiscReg &val,
                      ThreadContext *tc, unsigned tid = 0);
 
+        int getInstAsid();
+        int getDataAsid();
+
         //////////////////////////////////////////////////////////
         //
         // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0)

src/arch/mips/regfile/regfile.cc

@@ -32,9 +32,166 @@
 #include "arch/mips/regfile/regfile.hh"
 #include "sim/serialize.hh"
 
-using namespace MipsISA;
 using namespace std;
 
+namespace MipsISA
+{
+
+void
+RegFile::clear()
+{
+    intRegFile.clear();
+    floatRegFile.clear();
+    miscRegFile.clear();
+}
+
+void
+RegFile::reset(std::string core_name, unsigned num_threads, unsigned num_vpes, BaseCPU *_cpu)
+{
+    bzero(&intRegFile, sizeof(intRegFile));
+    bzero(&floatRegFile, sizeof(floatRegFile));
+    miscRegFile.reset(core_name, num_threads, num_vpes, _cpu);
+}
+
+IntReg
+RegFile::readIntReg(int intReg)
+{
+    return intRegFile.readReg(intReg);
+}
+
+Fault
+RegFile::setIntReg(int intReg, const IntReg &val)
+{
+    return intRegFile.setReg(intReg, val);
+}
+
+MiscReg
+RegFile::readMiscRegNoEffect(int miscReg, unsigned tid)
+{
+    return miscRegFile.readRegNoEffect(miscReg, tid);
+}
+
+MiscReg
+RegFile::readMiscReg(int miscReg, ThreadContext *tc,
+                    unsigned tid)
+{
+    return miscRegFile.readReg(miscReg, tc, tid);
+}
+
+void
+RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val, unsigned tid)
+{
+    miscRegFile.setRegNoEffect(miscReg, val, tid);
+}
+
+void
+RegFile::setMiscReg(int miscReg, const MiscReg &val,
+                ThreadContext * tc, unsigned tid)
+{
+    miscRegFile.setReg(miscReg, val, tc, tid);
+}
+
+FloatRegVal
+RegFile::readFloatReg(int floatReg)
+{
+    return floatRegFile.readReg(floatReg,SingleWidth);
+}
+
+FloatRegVal
+RegFile::readFloatReg(int floatReg, int width)
+{
+    return floatRegFile.readReg(floatReg,width);
+}
+
+FloatRegBits
+RegFile::readFloatRegBits(int floatReg)
+{
+    return floatRegFile.readRegBits(floatReg,SingleWidth);
+}
+
+FloatRegBits
+RegFile::readFloatRegBits(int floatReg, int width)
+{
+    return floatRegFile.readRegBits(floatReg,width);
+}
+
+Fault
+RegFile::setFloatReg(int floatReg, const FloatRegVal &val)
+{
+    return floatRegFile.setReg(floatReg, val, SingleWidth);
+}
+
+Fault
+RegFile::setFloatReg(int floatReg, const FloatRegVal &val, int width)
+{
+    return floatRegFile.setReg(floatReg, val, width);
+}
+
+Fault
+RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
+{
+    return floatRegFile.setRegBits(floatReg, val, SingleWidth);
+}
+
+Fault
+RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
+{
+    return floatRegFile.setRegBits(floatReg, val, width);
+}
+
+void
+RegFile::setShadowSet(int css){
+    intRegFile.setShadowSet(css);
+}
+
+int
+RegFile::instAsid()
+{
+    return miscRegFile.getInstAsid();
+}
+
+int
+RegFile::dataAsid()
+{
+    return miscRegFile.getDataAsid();
+}
+
+Addr
+RegFile::readPC()
+{
+    return pc;
+}
+
+void
+RegFile::setPC(Addr val)
+{
+    pc = val;
+}
+
+Addr
+RegFile::readNextPC()
+{
+    return npc;
+}
+
+void
+RegFile::setNextPC(Addr val)
+{
+    npc = val;
+}
+
+Addr
+RegFile::readNextNPC()
+{
+    return nnpc;
+}
+
+void
+RegFile::setNextNPC(Addr val)
+{
+    nnpc = val;
+}
+
 void
 RegFile::serialize(std::ostream &os)
 {
@@ -64,14 +221,4 @@ RegFile::unserialize(Checkpoint *cp, const std::string &section)
 
 }
 
-void
+} // namespace MipsISA
-MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
-{
-    panic("Copy Regs Not Implemented Yet\n");
-}
-
-void
-MipsISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
-    panic("Copy Misc. Regs Not Implemented Yet\n");
-}

src/arch/mips/regfile/regfile.hh

@@ -32,147 +32,71 @@
 #define __ARCH_MIPS_REGFILE_REGFILE_HH__
 
 #include "arch/mips/types.hh"
+#include "arch/mips/isa_traits.hh"
+//#include "arch/mips/mt.hh"
 #include "arch/mips/regfile/int_regfile.hh"
 #include "arch/mips/regfile/float_regfile.hh"
 #include "arch/mips/regfile/misc_regfile.hh"
+//#include "cpu/base.hh"
 #include "sim/faults.hh"
 
 class Checkpoint;
-class ThreadContext;
+class BaseCPU;
 
 namespace MipsISA
 {
     class RegFile {
       protected:
-        IntRegFile intRegFile;		// (signed) integer register file
-        FloatRegFile floatRegFile;	// floating point register file
-        MiscRegFile miscRegFile;	// control register file
-
-      public:
-        void clear()
-        {
-            intRegFile.clear();
-            floatRegFile.clear();
-            miscRegFile.clear();
-        }
-
-        void reset(std::string core_name, unsigned num_threads, unsigned num_vpes)
-        {
-            bzero(&intRegFile, sizeof(intRegFile));
-            bzero(&floatRegFile, sizeof(floatRegFile));
-            miscRegFile.reset(core_name, num_threads, num_vpes);
-        }
-
-        IntReg readIntReg(int intReg)
-        {
-            return intRegFile.readReg(intReg);
-        }
-
-        Fault setIntReg(int intReg, const IntReg &val)
-        {
-            return intRegFile.setReg(intReg, val);
-        }
-
-        MiscReg readMiscRegNoEffect(int miscReg, unsigned tid = 0)
-        {
-            return miscRegFile.readRegNoEffect(miscReg, tid);
-        }
-
-        MiscReg readMiscReg(int miscReg, ThreadContext *tc,
-                                      unsigned tid = 0)
-        {
-            return miscRegFile.readReg(miscReg, tc, tid);
-        }
-
-        void setMiscRegNoEffect(int miscReg, const MiscReg &val, unsigned tid = 0)
-        {
-            miscRegFile.setRegNoEffect(miscReg, val, tid);
-        }
-
-        void setMiscReg(int miscReg, const MiscReg &val,
-                ThreadContext * tc, unsigned tid = 0)
-        {
-            miscRegFile.setReg(miscReg, val, tc, tid);
-        }
-
-        FloatRegVal readFloatReg(int floatReg)
-        {
-            return floatRegFile.readReg(floatReg,SingleWidth);
-        }
-
-        FloatRegVal readFloatReg(int floatReg, int width)
-        {
-            return floatRegFile.readReg(floatReg,width);
-        }
-
-        FloatRegBits readFloatRegBits(int floatReg)
-        {
-            return floatRegFile.readRegBits(floatReg,SingleWidth);
-        }
-
-        FloatRegBits readFloatRegBits(int floatReg, int width)
-        {
-            return floatRegFile.readRegBits(floatReg,width);
-        }
-
-        Fault setFloatReg(int floatReg, const FloatRegVal &val)
-        {
-            return floatRegFile.setReg(floatReg, val, SingleWidth);
-        }
-
-        Fault setFloatReg(int floatReg, const FloatRegVal &val, int width)
-        {
-            return floatRegFile.setReg(floatReg, val, width);
-        }
-
-        Fault setFloatRegBits(int floatReg, const FloatRegBits &val)
-        {
-            return floatRegFile.setRegBits(floatReg, val, SingleWidth);
-        }
-
-        Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
-        {
-            return floatRegFile.setRegBits(floatReg, val, width);
-        }
-
-      protected:
-
         Addr pc;			// program counter
         Addr npc;			// next-cycle program counter
         Addr nnpc;			// next-next-cycle program counter
                                         // used to implement branch delay slot
                                         // not real register
 
+        IntRegFile intRegFile;		// (signed) integer register file
+        FloatRegFile floatRegFile;	// floating point register file
+        MiscRegFile miscRegFile;	// control register file
+
       public:
-        Addr readPC()
+        void clear();
-        {
+        void reset(std::string core_name, unsigned num_threads, unsigned num_vpes, BaseCPU *_cpu);
-            return pc;
+        MiscRegFile *getMiscRegFilePtr();
-        }
 
-        void setPC(Addr val)
+        IntReg readIntReg(int intReg);
-        {
+        Fault setIntReg(int intReg, const IntReg &val);
-            pc = val;
-        }
 
-        Addr readNextPC()
-        {
-            return npc;
-        }
 
-        void setNextPC(Addr val)
+        MiscReg readMiscRegNoEffect(int miscReg, unsigned tid = 0);
-        {
+        MiscReg readMiscReg(int miscReg, ThreadContext *tc,
-            npc = val;
+                            unsigned tid = 0);
-        }
+        void setMiscRegNoEffect(int miscReg, const MiscReg &val, unsigned tid = 0);
+        void setMiscReg(int miscReg, const MiscReg &val,
+                        ThreadContext * tc, unsigned tid = 0);
 
-        Addr readNextNPC()
+        FloatRegVal readFloatReg(int floatReg);
-        {
+        FloatRegVal readFloatReg(int floatReg, int width);
-            return nnpc;
+        FloatRegBits readFloatRegBits(int floatReg);
-        }
+        FloatRegBits readFloatRegBits(int floatReg, int width);
+        Fault setFloatReg(int floatReg, const FloatRegVal &val);
+        Fault setFloatReg(int floatReg, const FloatRegVal &val, int width);
+        Fault setFloatRegBits(int floatReg, const FloatRegBits &val);
+        Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width);
 
-        void setNextNPC(Addr val)
+
-        {
+        void setShadowSet(int css);
-            nnpc = val;
+
-        }
+        int instAsid();
+        int dataAsid();
+
+      public:
+        Addr readPC();
+        void setPC(Addr val);
+
+        Addr readNextPC();
+        void setNextPC(Addr val);
+
+        Addr readNextNPC();
+        void setNextNPC(Addr val);
 
         void serialize(std::ostream &os);
         void unserialize(Checkpoint *cp, const std::string &section);
@@ -180,24 +104,9 @@ namespace MipsISA
         void changeContext(RegContextParam param, RegContextVal val)
         {
         }
+
     };
 
-    static inline int flattenIntIndex(ThreadContext * tc, int reg)
-    {
-        return reg;
-    }
-
-    static inline int flattenFloatIndex(ThreadContext * tc, int reg)
-    {
-        return reg;
-    }
-
-    void
-    copyRegs(ThreadContext *src, ThreadContext *dest);
-
-    void
-    copyMiscRegs(ThreadContext *src, ThreadContext *dest);
-
 } // namespace MipsISA
 
 #endif

src/arch/mips/remote_gdb.hh

@@ -1,31 +1,38 @@
 /*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
+ * This software is part of the M5 simulator.
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * TO THESE TERMS AND CONDITIONS.
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Nathan Binkert
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ *
+ * Authors: Nathan L. Binkert
  */
 
 #ifndef __ARCH_MIPS_REMOTE_GDB_HH__

src/arch/mips/stacktrace.cc

@@ -0,0 +1,360 @@
+/*
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ *
+ * This software is part of the M5 simulator.
+ *
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+ * TO THESE TERMS AND CONDITIONS.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Nathan L. Binkert
+ */
+
+#include <string>
+
+#include "arch/mips/isa_traits.hh"
+#include "arch/mips/stacktrace.hh"
+#include "arch/mips/vtophys.hh"
+#include "base/bitfield.hh"
+#include "base/trace.hh"
+#include "cpu/base.hh"
+#include "cpu/thread_context.hh"
+#include "sim/system.hh"
+
+using namespace std;
+using namespace MipsISA;
+
+ProcessInfo::ProcessInfo(ThreadContext *_tc)
+    : tc(_tc)
+{
+//     Addr addr = 0;
+
+    VirtualPort *vp;
+
+    vp = tc->getVirtPort();
+
+//     if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr))
+//         panic("thread info not compiled into kernel\n");
+//     thread_info_size = vp->readGtoH<int32_t>(addr);
+
+//     if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_size", addr))
+//         panic("thread info not compiled into kernel\n");
+//     task_struct_size = vp->readGtoH<int32_t>(addr);
+
+//     if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_task", addr))
+//         panic("thread info not compiled into kernel\n");
+//     task_off = vp->readGtoH<int32_t>(addr);
+
+//     if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_pid", addr))
+//         panic("thread info not compiled into kernel\n");
+//     pid_off = vp->readGtoH<int32_t>(addr);
+
+//     if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr))
+//         panic("thread info not compiled into kernel\n");
+//     name_off = vp->readGtoH<int32_t>(addr);
+
+    tc->delVirtPort(vp);
+}
+
+Addr
+ProcessInfo::task(Addr ksp) const
+{
+    Addr base = ksp & ~0x3fff;
+    if (base == ULL(0xfffffc0000000000))
+        return 0;
+
+    Addr tsk;
+
+    VirtualPort *vp;
+
+    vp = tc->getVirtPort();
+    tsk = vp->readGtoH<Addr>(base + task_off);
+    tc->delVirtPort(vp);
+
+    return tsk;
+}
+
+int
+ProcessInfo::pid(Addr ksp) const
+{
+    Addr task = this->task(ksp);
+    if (!task)
+        return -1;
+
+    uint16_t pd;
+
+    VirtualPort *vp;
+
+    vp = tc->getVirtPort();
+    pd = vp->readGtoH<uint16_t>(task + pid_off);
+    tc->delVirtPort(vp);
+
+    return pd;
+}
+
+string
+ProcessInfo::name(Addr ksp) const
+{
+    Addr task = this->task(ksp);
+    if (!task)
+        return "console";
+
+    char comm[256];
+    CopyStringOut(tc, comm, task + name_off, sizeof(comm));
+    if (!comm[0])
+        return "startup";
+
+    return comm;
+}
+
+StackTrace::StackTrace()
+    : tc(0), stack(64)
+{
+}
+
+StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst)
+    : tc(0), stack(64)
+{
+    trace(_tc, inst);
+}
+
+StackTrace::~StackTrace()
+{
+}
+
+void
+StackTrace::trace(ThreadContext *_tc, bool is_call)
+{
+    tc = _tc;
+    /* FIXME - Jaidev - What is IPR_DTB_CM in Alpha? */
+    bool usermode = 0;
+      //(tc->readMiscReg(MipsISA::IPR_DTB_CM) & 0x18) != 0;
+
+//     Addr pc = tc->readNextPC();
+//     bool kernel = tc->getSystemPtr()->kernelStart <= pc &&
+//         pc <= tc->getSystemPtr()->kernelEnd;
+
+    if (usermode) {
+        stack.push_back(user);
+        return;
+    }
+
+//     if (!kernel) {
+//         stack.push_back(console);
+//         return;
+//     }
+
+//     SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;
+//     Addr ksp = tc->readIntReg(TheISA::StackPointerReg);
+//     Addr bottom = ksp & ~0x3fff;
+//     Addr addr;
+
+//     if (is_call) {
+//         if (!symtab->findNearestAddr(pc, addr))
+//             panic("could not find address %#x", pc);
+
+//         stack.push_back(addr);
+//         pc = tc->readPC();
+//     }
+
+//     Addr ra;
+//     int size;
+
+//     while (ksp > bottom) {
+//         if (!symtab->findNearestAddr(pc, addr))
+//             panic("could not find symbol for pc=%#x", pc);
+//         assert(pc >= addr && "symbol botch: callpc < func");
+
+//         stack.push_back(addr);
+
+//         if (isEntry(addr))
+//             return;
+
+//         if (decodePrologue(ksp, pc, addr, size, ra)) {
+//             if (!ra)
+//                 return;
+
+//             if (size <= 0) {
+//                 stack.push_back(unknown);
+//                 return;
+//             }
+
+//             pc = ra;
+//             ksp += size;
+//         } else {
+//             stack.push_back(unknown);
+//             return;
+//         }
+
+//         bool kernel = tc->getSystemPtr()->kernelStart <= pc &&
+//             pc <= tc->getSystemPtr()->kernelEnd;
+//         if (!kernel)
+//             return;
+
+//         if (stack.size() >= 1000)
+//             panic("unwinding too far");
+//     }
+
+//     panic("unwinding too far");
+}
+
+bool
+StackTrace::isEntry(Addr addr)
+{
+  /*    if (addr == tc->readMiscReg(MipsISA::IPR_PALtemp2))
+        return true;*/
+
+    return false;
+}
+
+bool
+StackTrace::decodeStack(MachInst inst, int &disp)
+{
+    // lda $sp, -disp($sp)
+    //
+    // Opcode<31:26> == 0x08
+    // RA<25:21> == 30
+    // RB<20:16> == 30
+    // Disp<15:0>
+    const MachInst mem_mask = 0xffff0000;
+    const MachInst lda_pattern = 0x23de0000;
+    const MachInst lda_disp_mask = 0x0000ffff;
+
+    // subq $sp, disp, $sp
+    // addq $sp, disp, $sp
+    //
+    // Opcode<31:26> == 0x10
+    // RA<25:21> == 30
+    // Lit<20:13>
+    // One<12> = 1
+    // Func<11:5> == 0x20 (addq)
+    // Func<11:5> == 0x29 (subq)
+    // RC<4:0> == 30
+    const MachInst intop_mask = 0xffe01fff;
+    const MachInst addq_pattern = 0x43c0141e;
+    const MachInst subq_pattern = 0x43c0153e;
+    const MachInst intop_disp_mask = 0x001fe000;
+    const int intop_disp_shift = 13;
+
+    if ((inst & mem_mask) == lda_pattern)
+        disp = -sext<16>(inst & lda_disp_mask);
+    else if ((inst & intop_mask) == addq_pattern)
+        disp = -int((inst & intop_disp_mask) >> intop_disp_shift);
+    else if ((inst & intop_mask) == subq_pattern)
+        disp = int((inst & intop_disp_mask) >> intop_disp_shift);
+    else
+        return false;
+
+    return true;
+}
+
+bool
+StackTrace::decodeSave(MachInst inst, int &reg, int &disp)
+{
+    // lda $stq, disp($sp)
+    //
+    // Opcode<31:26> == 0x08
+    // RA<25:21> == ?
+    // RB<20:16> == 30
+    // Disp<15:0>
+    const MachInst stq_mask = 0xfc1f0000;
+    const MachInst stq_pattern = 0xb41e0000;
+    const MachInst stq_disp_mask = 0x0000ffff;
+    const MachInst reg_mask = 0x03e00000;
+    const int reg_shift = 21;
+
+    if ((inst & stq_mask) == stq_pattern) {
+        reg = (inst & reg_mask) >> reg_shift;
+        disp = sext<16>(inst & stq_disp_mask);
+    } else {
+        return false;
+    }
+
+    return true;
+}
+
+/*
+ * Decode the function prologue for the function we're in, and note
+ * which registers are stored where, and how large the stack frame is.
+ */
+bool
+StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func,
+                           int &size, Addr &ra)
+{
+    size = 0;
+    ra = 0;
+
+    for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) {
+        MachInst inst;
+        CopyOut(tc, (uint8_t *)&inst, pc, sizeof(MachInst));
+
+        int reg, disp;
+        if (decodeStack(inst, disp)) {
+            if (size) {
+                // panic("decoding frame size again");
+                return true;
+            }
+            size += disp;
+        } else if (decodeSave(inst, reg, disp)) {
+            if (!ra && reg == ReturnAddressReg) {
+                CopyOut(tc, (uint8_t *)&ra, sp + disp, sizeof(Addr));
+                if (!ra) {
+                    // panic("no return address value pc=%#x\n", pc);
+                    return false;
+                }
+            }
+        }
+    }
+
+    return true;
+}
+
+#if TRACING_ON
+void
+StackTrace::dump()
+{
+    StringWrap name(tc->getCpuPtr()->name());
+//     SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;
+
+    DPRINTFN("------ Stack ------\n");
+
+//     string symbol;
+//     for (int i = 0, size = stack.size(); i < size; ++i) {
+//         Addr addr = stack[size - i - 1];
+//         if (addr == user)
+//             symbol = "user";
+//         else if (addr == console)
+//             symbol = "console";
+//         else if (addr == unknown)
+//             symbol = "unknown";
+//         else
+//             symtab->findSymbol(addr, symbol);
+
+//         DPRINTFN("%#x: %s\n", addr, symbol);
+//     }
+}
+#endif

src/arch/mips/stacktrace.hh

@@ -1,31 +1,38 @@
 /*
- * Copyright (c) 2005 The Regents of The University of Michigan
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
+ * This software is part of the M5 simulator.
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * TO THESE TERMS AND CONDITIONS.
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * Permission is granted to use, copy, create derivative works and
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * distribute this software and such derivative works for any purpose,
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * so long as (1) the copyright notice above, this grant of permission,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * and the disclaimer below appear in all copies and derivative works
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * made, (2) the copyright notice above is augmented as appropriate to
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * reflect the addition of any new copyrightable work in a derivative
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Ali G. Saidi
  *
- * Authors: Ali Saidi
  */
 
 #ifndef __ARCH_MIPS_STACKTRACE_HH__
@@ -35,7 +42,6 @@
 #include "cpu/static_inst.hh"
 
 class ThreadContext;
-class StackTrace;
 
 namespace MipsISA
 {

src/arch/mips/syscallreturn.hh

@@ -1,32 +1,38 @@
 /*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
+ * This software is part of the M5 simulator.
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * TO THESE TERMS AND CONDITIONS.
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Gabe Black
+ * Permission is granted to use, copy, create derivative works and
- *          Korey Sewell
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Gabe M. Black
+ *          Korey L. Sewell
  */
 
 #ifndef __ARCH_MIPS_SYSCALLRETURN_HH__

src/arch/mips/system.cc

@@ -0,0 +1,228 @@
+/*
+ * Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ *
+ * This software is part of the M5 simulator.
+ *
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+ * TO THESE TERMS AND CONDITIONS.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ *
+ * Authors: Ali G. Saidi
+ *          Nathan L. Binkert
+ *          Jaidev Patwardhan
+ */
+
+#include "arch/mips/system.hh"
+#include "arch/vtophys.hh"
+#include "base/remote_gdb.hh"
+#include "base/loader/object_file.hh"
+#include "base/loader/hex_file.hh"
+#include "base/loader/symtab.hh"
+#include "base/trace.hh"
+#include "mem/physical.hh"
+#include "params/MipsSystem.hh"
+#include "sim/byteswap.hh"
+
+
+using namespace LittleEndianGuest;
+
+MipsSystem::MipsSystem(Params *p)
+    : System(p)
+{
+
+#if FULL_SYSTEM
+    if (p->bare_iron == true) {
+        hexFile = new HexFile(params()->hex_file_name);
+        if(!hexFile->loadSections(&functionalPort,MipsISA::LoadAddrMask))
+            panic("Could not load hex file\n");
+    }
+
+    Addr addr = 0;
+    /* Comment out old Alpha Based Code
+
+     Don't need the console before we start looking at booting linux */
+
+
+    consoleSymtab = new SymbolTable;
+
+
+    /**
+     * Load the console code into memory
+     */
+    //    Load Console Code
+    console = createObjectFile(params()->console);
+
+    warn("console code is located at: %s\n", params()->console);
+
+    if (console == NULL)
+        fatal("Could not load console file %s", params()->console);
+    //Load program sections into memory
+     console->loadSections(&functionalPort, MipsISA::LoadAddrMask);
+
+    //load symbols
+    if (!console->loadGlobalSymbols(consoleSymtab))
+        panic("could not load console symbols\n");
+
+    if (!console->loadGlobalSymbols(debugSymbolTable))
+        panic("could not load console symbols\n");
+
+
+#ifndef NDEBUG
+    consolePanicEvent = addConsoleFuncEvent<BreakPCEvent>("panic");
+#endif
+
+    /**
+     * Copy the osflags (kernel arguments) into the consoles
+     * memory. (Presently Linux does not use the console service
+     * routine to get these command line arguments, but Tru64 and
+     * others do.)
+     */
+    if (consoleSymtab->findAddress("env_booted_osflags", addr)) {
+        warn("writing addr starting from %#x", addr);
+        cout << "-" << endl;
+        virtPort.writeBlob(addr, (uint8_t*)params()->boot_osflags.c_str(),
+                strlen(params()->boot_osflags.c_str()));
+    }
+
+    /**
+     * Set the hardware reset parameter block system type and revision
+     * information to Tsunami.
+     */
+    if (consoleSymtab->findAddress("m5_rpb", addr)) {
+        uint64_t data;
+        data = htog(params()->system_type);
+        virtPort.write(addr+0x50, data);
+        data = htog(params()->system_rev);
+        virtPort.write(addr+0x58, data);
+    } else
+        panic("could not find hwrpb\n");
+#endif
+}
+
+MipsSystem::~MipsSystem()
+{
+}
+#if FULL_SYSTEM
+/**
+ * This function fixes up addresses that are used to match PCs for
+ * hooking simulator events on to target function executions.
+ *
+ * Mips binaries may have multiple global offset table (GOT)
+ * sections.  A function that uses the GOT starts with a
+ * two-instruction prolog which sets the global pointer (gp == r29) to
+ * the appropriate GOT section.  The proper gp value is calculated
+ * based on the function address, which must be passed by the caller
+ * in the procedure value register (pv aka t12 == r27).  This sequence
+ * looks like the following:
+ *
+ *			opcode Ra Rb offset
+ *	ldah gp,X(pv)     09   29 27   X
+ *	lda  gp,Y(gp)     08   29 29   Y
+ *
+ * for some constant offsets X and Y.  The catch is that the linker
+ * (or maybe even the compiler, I'm not sure) may recognize that the
+ * caller and callee are using the same GOT section, making this
+ * prolog redundant, and modify the call target to skip these
+ * instructions.  If we check for execution of the first instruction
+ * of a function (the one the symbol points to) to detect when to skip
+ * it, we'll miss all these modified calls.  It might work to
+ * unconditionally check for the third instruction, but not all
+ * functions have this prolog, and there's some chance that those
+ * first two instructions could have undesired consequences.  So we do
+ * the Right Thing and pattern-match the first two instructions of the
+ * function to decide where to patch.
+ *
+ * Eventually this code should be moved into an ISA-specific file.
+ */
+
+Addr
+MipsSystem::fixFuncEventAddr(Addr addr)
+{
+  /*
+    // mask for just the opcode, Ra, and Rb fields (not the offset)
+    const uint32_t inst_mask = 0xffff0000;
+    // ldah gp,X(pv): opcode 9, Ra = 29, Rb = 27
+    const uint32_t gp_ldah_pattern = (9 << 26) | (29 << 21) | (27 << 16);
+    // lda  gp,Y(gp): opcode 8, Ra = 29, rb = 29
+    const uint32_t gp_lda_pattern  = (8 << 26) | (29 << 21) | (29 << 16);
+
+    uint32_t i1 = virtPort.read<uint32_t>(addr);
+    uint32_t i2 = virtPort.read<uint32_t>(addr + sizeof(MipsISA::MachInst));
+
+    if ((i1 & inst_mask) == gp_ldah_pattern &&
+        (i2 & inst_mask) == gp_lda_pattern) {
+        Addr new_addr = addr + 2* sizeof(MipsISA::MachInst);
+        DPRINTF(Loader, "fixFuncEventAddr: %p -> %p", addr, new_addr);
+        return new_addr;
+    } else {
+        return addr;
+        }*/
+  return addr;
+}
+
+
+void
+MipsSystem::setMipsAccess(Addr access)
+{
+    Addr addr = 0;
+    if (consoleSymtab->findAddress("m5MipsAccess", addr)) {
+      //        virtPort.write(addr, htog(EV5::Phys2K0Seg(access)));
+    } else
+    panic("could not find m5MipsAccess\n");
+    }
+
+#endif
+
+bool
+MipsSystem::breakpoint()
+{
+  return 0;
+  //    return remoteGDB[0]->trap(MIPS_KENTRY_INT);
+}
+
+void
+MipsSystem::serialize(std::ostream &os)
+{
+    System::serialize(os);
+    //    consoleSymtab->serialize("console_symtab", os);
+}
+
+
+void
+MipsSystem::unserialize(Checkpoint *cp, const std::string &section)
+{
+    System::unserialize(cp,section);
+    //    consoleSymtab->unserialize("console_symtab", cp, section);
+}
+
+MipsSystem *
+MipsSystemParams::create()
+{
+    return new MipsSystem(this);
+}
+

src/arch/mips/system.hh

@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ *          Nathan Binkert
+ *          Jaidev Patwardhan
+ */
+
+#ifndef __ARCH_MIPS_SYSTEM_HH__
+#define __ARCH_MIPS_SYSTEM_HH__
+
+#include <string>
+#include <vector>
+
+#include "sim/system.hh"
+#include "base/loader/symtab.hh"
+#include "base/loader/hex_file.hh"
+#include "cpu/pc_event.hh"
+#include "kern/system_events.hh"
+#include "params/MipsSystem.hh"
+#include "sim/sim_object.hh"
+
+class MipsSystem : public System
+{
+  public:
+    typedef MipsSystemParams Params;
+    MipsSystem(Params *p);
+    ~MipsSystem();
+
+    virtual bool breakpoint();
+
+/**
+ * Serialization stuff
+ */
+  public:
+    virtual void serialize(std::ostream &os);
+    virtual void unserialize(Checkpoint *cp, const std::string &section);
+
+    /**
+     * Set the m5MipsAccess pointer in the console
+     */
+    void setMipsAccess(Addr access);
+
+#if FULL_SYSTEM
+    /** console symbol table */
+    SymbolTable *consoleSymtab;
+
+    /** Object pointer for the console code */
+    ObjectFile *console;
+
+    /** Used by some Bare Iron Configurations */
+    HexFile *hexFile;
+#endif
+
+#ifndef NDEBUG
+  /** Event to halt the simulator if the console calls panic() */
+    BreakPCEvent *consolePanicEvent;
+#endif
+
+  protected:
+    const Params *params() const { return (const Params *)_params; }
+
+
+#if FULL_SYSTEM
+  /** Add a function-based event to the console code. */
+    template <class T>
+    T *addConsoleFuncEvent(const char *lbl)
+    {
+        return addFuncEvent<T>(consoleSymtab, lbl);
+    }
+
+    virtual Addr fixFuncEventAddr(Addr addr);
+#endif
+
+};
+
+#endif
+

src/arch/mips/tlb.cc

@@ -1,68 +1,609 @@
 /*
- * Copyright (c) 2001-2005 The Regents of The University of Michigan
+ * Copyright 2007 MIPS Technologies, Inc.  All Rights Reserved
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
+ * This software is part of the M5 simulator.
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * TO THESE TERMS AND CONDITIONS.
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * Permission is granted to use, copy, create derivative works and
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * distribute this software and such derivative works for any purpose,
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * so long as (1) the copyright notice above, this grant of permission,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * and the disclaimer below appear in all copies and derivative works
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * made, (2) the copyright notice above is augmented as appropriate to
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * reflect the addition of any new copyrightable work in a derivative
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Jaidev P. Patwardhan
  *
- * Authors: Gabe Black
  */
 
-#include <cstring>
+#include <string>
+#include <vector>
 
+#include "arch/mips/pra_constants.hh"
+#include "arch/mips/pagetable.hh"
 #include "arch/mips/tlb.hh"
+#include "arch/mips/faults.hh"
+#include "arch/mips/utility.hh"
+#include "base/inifile.hh"
+#include "base/str.hh"
+#include "base/trace.hh"
+#include "cpu/thread_context.hh"
+#include "params/MipsDTB.hh"
+#include "params/MipsITB.hh"
+#include "params/MipsTLB.hh"
+#include "params/MipsUTB.hh"
 
-namespace MipsISA {
-    Fault
-    TLB::translate(RequestPtr req, ThreadContext *tc, bool)
-    {
-        Fault fault = GenericTLB::translate(req, tc);
-        if (fault != NoFault)
-            return fault;
 
-        typeof(req->getSize()) size = req->getSize();
+using namespace std;
-        Addr paddr = req->getPaddr();
+using namespace MipsISA;
 
-        if (!isPowerOf2(size))
+///////////////////////////////////////////////////////////////////////
-            panic("Invalid request size!\n");
+//
-        if ((size - 1) & paddr)
+//  MIPS TLB
-            return new GenericAlignmentFault(paddr);
+//
 
+#define MODE2MASK(X)			(1 << (X))
+
+TLB::TLB(const Params *p)
+    : SimObject(p), size(p->size), nlu(0)
+{
+    table = new MipsISA::PTE[size];
+    memset(table, 0, sizeof(MipsISA::PTE[size]));
+    smallPages=0;
+}
+
+TLB::~TLB()
+{
+    if (table)
+        delete [] table;
+}
+
+// look up an entry in the TLB
+MipsISA::PTE *
+TLB::lookup(Addr vpn, uint8_t asn) const
+{
+    // assume not found...
+    MipsISA::PTE *retval = NULL;
+    PageTable::const_iterator i = lookupTable.find(vpn);
+    if (i != lookupTable.end()) {
+        while (i->first == vpn) {
+            int index = i->second;
+            MipsISA::PTE *pte = &table[index];
+
+            /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
+            Addr Mask = pte->Mask;
+            Addr InvMask = ~Mask;
+            Addr VPN  = pte->VPN;
+            //	    warn("Valid: %d - %d\n",pte->V0,pte->V1);
+            if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G  || (asn == pte->asid)))
+              { // We have a VPN + ASID Match
+                retval = pte;
+                break;
+              }
+            ++i;
+        }
+    }
+
+    DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
+            retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
+    return retval;
+}
+
+MipsISA::PTE* TLB::getEntry(unsigned Index) const
+{
+    // Make sure that Index is valid
+    assert(Index<size);
+    return &table[Index];
+}
+
+int TLB::probeEntry(Addr vpn,uint8_t asn) const
+{
+    // assume not found...
+    MipsISA::PTE *retval = NULL;
+    int Ind=-1;
+    PageTable::const_iterator i = lookupTable.find(vpn);
+    if (i != lookupTable.end()) {
+        while (i->first == vpn) {
+            int index = i->second;
+            MipsISA::PTE *pte = &table[index];
+
+            /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
+            Addr Mask = pte->Mask;
+            Addr InvMask = ~Mask;
+            Addr VPN  = pte->VPN;
+            if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G  || (asn == pte->asid)))
+              { // We have a VPN + ASID Match
+                retval = pte;
+                Ind = index;
+                break;
+              }
+
+            ++i;
+        }
+    }
+    DPRINTF(MipsPRA,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind);
+    return Ind;
+}
+Fault inline
+TLB::checkCacheability(RequestPtr &req)
+{
+  Addr VAddrUncacheable = 0xA0000000;
+  // In MIPS, cacheability is controlled by certain bits of the virtual address
+  // or by the TLB entry
+  if((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
+    // mark request as uncacheable
+    req->setFlags(req->getFlags() | UNCACHEABLE);
+  }
   return NoFault;
+}
+void TLB::insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages)
+{
+  smallPages=_smallPages;
+  if(Index > size){
+    warn("Attempted to write at index (%d) beyond TLB size (%d)",Index,size);
+  } else {
+    // Update TLB
+    DPRINTF(TLB,"TLB[%d]: %x %x %x %x\n",Index,pte.Mask<<11,((pte.VPN << 11) | pte.asid),((pte.PFN0 <<6) | (pte.C0 << 3) | (pte.D0 << 2) | (pte.V0 <<1) | pte.G),
+            ((pte.PFN1 <<6) | (pte.C1 << 3) | (pte.D1 << 2) | (pte.V1 <<1) | pte.G));
+    if(table[Index].V0 == true || table[Index].V1 == true){ // Previous entry is valid
+      PageTable::iterator i = lookupTable.find(table[Index].VPN);
+      lookupTable.erase(i);
+    }
+    table[Index]=pte;
+    // Update fast lookup table
+    lookupTable.insert(make_pair(table[Index].VPN, Index));
+    //    int TestIndex=probeEntry(pte.VPN,pte.asid);
+    //    warn("Inserted at: %d, Found at: %d (%x)\n",Index,TestIndex,pte.Mask);
   }
 
-    void
+}
-    TlbEntry::serialize(std::ostream &os)
+
-    {
+// insert a new TLB entry
-        SERIALIZE_SCALAR(_pageStart);
+void
+TLB::insert(Addr addr, MipsISA::PTE &pte)
+{
+  fatal("TLB Insert not yet implemented\n");
+
+
+  /*    MipsISA::VAddr vaddr = addr;
+    if (table[nlu].valid) {
+        Addr oldvpn = table[nlu].tag;
+        PageTable::iterator i = lookupTable.find(oldvpn);
+
+        if (i == lookupTable.end())
+            panic("TLB entry not found in lookupTable");
+
+        int index;
+        while ((index = i->second) != nlu) {
+            if (table[index].tag != oldvpn)
+                panic("TLB entry not found in lookupTable");
+
+            ++i;
         }
 
-    void
+        DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
-    TlbEntry::unserialize(Checkpoint *cp, const std::string &section)
+
-    {
+        lookupTable.erase(i);
-        UNSERIALIZE_SCALAR(_pageStart);
     }
-};
+
+    DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn);
+
+    table[nlu] = pte;
+    table[nlu].tag = vaddr.vpn();
+    table[nlu].valid = true;
+
+    lookupTable.insert(make_pair(vaddr.vpn(), nlu));
+    nextnlu();
+  */
+}
+
+void
+TLB::flushAll()
+{
+    DPRINTF(TLB, "flushAll\n");
+    memset(table, 0, sizeof(MipsISA::PTE[size]));
+    lookupTable.clear();
+    nlu = 0;
+}
+
+void
+TLB::serialize(ostream &os)
+{
+    SERIALIZE_SCALAR(size);
+    SERIALIZE_SCALAR(nlu);
+
+    for (int i = 0; i < size; i++) {
+        nameOut(os, csprintf("%s.PTE%d", name(), i));
+        table[i].serialize(os);
+    }
+}
+
+void
+TLB::unserialize(Checkpoint *cp, const string &section)
+{
+    UNSERIALIZE_SCALAR(size);
+    UNSERIALIZE_SCALAR(nlu);
+
+    for (int i = 0; i < size; i++) {
+        table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
+        if (table[i].V0 || table[i].V1) {
+            lookupTable.insert(make_pair(table[i].VPN, i));
+        }
+    }
+}
+
+void
+TLB::regStats()
+{
+    read_hits
+        .name(name() + ".read_hits")
+        .desc("DTB read hits")
+        ;
+
+    read_misses
+        .name(name() + ".read_misses")
+        .desc("DTB read misses")
+        ;
+
+
+    read_accesses
+        .name(name() + ".read_accesses")
+        .desc("DTB read accesses")
+        ;
+
+    write_hits
+        .name(name() + ".write_hits")
+        .desc("DTB write hits")
+        ;
+
+    write_misses
+        .name(name() + ".write_misses")
+        .desc("DTB write misses")
+        ;
+
+
+    write_accesses
+        .name(name() + ".write_accesses")
+        .desc("DTB write accesses")
+        ;
+
+    hits
+        .name(name() + ".hits")
+        .desc("DTB hits")
+        ;
+
+    misses
+        .name(name() + ".misses")
+        .desc("DTB misses")
+        ;
+
+    invalids
+        .name(name() + ".invalids")
+        .desc("DTB access violations")
+        ;
+
+    accesses
+        .name(name() + ".accesses")
+        .desc("DTB accesses")
+        ;
+
+    hits = read_hits + write_hits;
+    misses = read_misses + write_misses;
+    accesses = read_accesses + write_accesses;
+}
+
+Fault
+ITB::translate(RequestPtr &req, ThreadContext *tc)
+{
+  if(MipsISA::IsKSeg0(req->getVaddr()))
+    {
+      // Address will not be translated through TLB, set response, and go!
+      req->setPaddr(MipsISA::KSeg02Phys(req->getVaddr()));
+      if(MipsISA::getOperatingMode(tc->readMiscReg(MipsISA::Status)) != mode_kernel || req->isMisaligned())
+        {
+          AddressErrorFault *Flt = new AddressErrorFault();
+          /* BadVAddr must be set */
+          Flt->BadVAddr = req->getVaddr();
+          return Flt;
+        }
+    }
+  else if(MipsISA::IsKSeg1(req->getVaddr()))
+    {
+      // Address will not be translated through TLB, set response, and go!
+      req->setPaddr(MipsISA::KSeg02Phys(req->getVaddr()));
+    }
+  else
+    {
+      /* This is an optimization - smallPages is updated every time a TLB operation is performed
+         That way, we don't need to look at Config3 _ SP and PageGrain _ ESP every time we
+         do a TLB lookup */
+      Addr VPN;
+      if(smallPages==1){
+        VPN=((req->getVaddr() >> 11));
+      } else {
+        VPN=((req->getVaddr() >> 11) & 0xFFFFFFFC);
+      }
+      uint8_t Asid = req->getAsid();
+      if(req->isMisaligned()){ // Unaligned address!
+        AddressErrorFault *Flt = new AddressErrorFault();
+        /* BadVAddr must be set */
+        Flt->BadVAddr = req->getVaddr();
+        return Flt;
+      }
+      MipsISA::PTE *pte = lookup(VPN,Asid);
+      if(pte != NULL)
+        {// Ok, found something
+          /* Check for valid bits */
+          int EvenOdd;
+          bool Valid;
+          if((((req->getVaddr()) >> pte->AddrShiftAmount) & 1) ==0){
+            // Check even bits
+            Valid = pte->V0;
+            EvenOdd = 0;
+          } else {
+            // Check odd bits
+            Valid = pte->V1;
+            EvenOdd = 1;
+          }
+
+          if(Valid == false)
+            {//Invalid entry
+              ItbInvalidFault *Flt = new ItbInvalidFault();
+              /* EntryHi VPN, ASID fields must be set */
+              Flt->EntryHi_Asid = Asid;
+              Flt->EntryHi_VPN2 = (VPN>>2);
+              Flt->EntryHi_VPN2X = (VPN & 0x3);
+
+              /* BadVAddr must be set */
+              Flt->BadVAddr = req->getVaddr();
+
+              /* Context must be set */
+              Flt->Context_BadVPN2 = (VPN >> 2);
+              return Flt;
+            }
+          else
+            {// Ok, this is really a match, set paddr
+              //	      hits++;
+              Addr PAddr;
+              if(EvenOdd == 0){
+                PAddr = pte->PFN0;
+              }else{
+                PAddr = pte->PFN1;
+              }
+              PAddr >>= (pte->AddrShiftAmount-12);
+              PAddr <<= pte->AddrShiftAmount;
+              PAddr |= ((req->getVaddr()) & pte->OffsetMask);
+              req->setPaddr(PAddr);
+
+
+            }
+        }
+      else
+        { // Didn't find any match, return a TLB Refill Exception
+          //	  misses++;
+          ItbRefillFault *Flt=new ItbRefillFault();
+          /* EntryHi VPN, ASID fields must be set */
+          Flt->EntryHi_Asid = Asid;
+          Flt->EntryHi_VPN2 = (VPN>>2);
+          Flt->EntryHi_VPN2X = (VPN & 0x3);
+
+
+          /* BadVAddr must be set */
+          Flt->BadVAddr = req->getVaddr();
+
+          /* Context must be set */
+          Flt->Context_BadVPN2 = (VPN >> 2);
+          return Flt;
+        }
+    }
+  return checkCacheability(req);
+}
+
+Fault
+DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
+{
+  if(MipsISA::IsKSeg0(req->getVaddr()))
+    {
+      // Address will not be translated through TLB, set response, and go!
+      req->setPaddr(MipsISA::KSeg02Phys(req->getVaddr()));
+      if(MipsISA::getOperatingMode(tc->readMiscReg(MipsISA::Status)) != mode_kernel || req->isMisaligned())
+        {
+          StoreAddressErrorFault *Flt = new StoreAddressErrorFault();
+          /* BadVAddr must be set */
+          Flt->BadVAddr = req->getVaddr();
+
+          return Flt;
+        }
+    }
+  else if(MipsISA::IsKSeg1(req->getVaddr()))
+    {
+      // Address will not be translated through TLB, set response, and go!
+      req->setPaddr(MipsISA::KSeg02Phys(req->getVaddr()));
+    }
+  else
+    {
+      /* This is an optimization - smallPages is updated every time a TLB operation is performed
+         That way, we don't need to look at Config3 _ SP and PageGrain _ ESP every time we
+         do a TLB lookup */
+      Addr VPN=((req->getVaddr() >> 11) & 0xFFFFFFFC);
+      if(smallPages==1){
+        VPN=((req->getVaddr() >> 11));
+      }
+      uint8_t Asid = req->getAsid();
+      MipsISA::PTE *pte = lookup(VPN,Asid);
+      if(req->isMisaligned()){ // Unaligned address!
+        StoreAddressErrorFault *Flt = new StoreAddressErrorFault();
+        /* BadVAddr must be set */
+        Flt->BadVAddr = req->getVaddr();
+        return Flt;
+      }
+      if(pte != NULL)
+        {// Ok, found something
+          /* Check for valid bits */
+          int EvenOdd;
+          bool Valid;
+          bool Dirty;
+          if(((((req->getVaddr()) >> pte->AddrShiftAmount) & 1)) ==0){
+            // Check even bits
+            Valid = pte->V0;
+            Dirty = pte->D0;
+            EvenOdd = 0;
+
+          } else {
+            // Check odd bits
+            Valid = pte->V1;
+            Dirty = pte->D1;
+            EvenOdd = 1;
+          }
+
+          if(Valid == false)
+            {//Invalid entry
+              //	      invalids++;
+              DtbInvalidFault *Flt = new DtbInvalidFault();
+              /* EntryHi VPN, ASID fields must be set */
+              Flt->EntryHi_Asid = Asid;
+              Flt->EntryHi_VPN2 = (VPN>>2);
+              Flt->EntryHi_VPN2X = (VPN & 0x3);
+
+
+              /* BadVAddr must be set */
+              Flt->BadVAddr = req->getVaddr();
+
+              /* Context must be set */
+              Flt->Context_BadVPN2 = (VPN >> 2);
+
+              return Flt;
+            }
+          else
+            {// Ok, this is really a match, set paddr
+              //	      hits++;
+              if(!Dirty)
+                {
+                  TLBModifiedFault *Flt = new TLBModifiedFault();
+                  /* EntryHi VPN, ASID fields must be set */
+                  Flt->EntryHi_Asid = Asid;
+                  Flt->EntryHi_VPN2 = (VPN>>2);
+                  Flt->EntryHi_VPN2X = (VPN & 0x3);
+
+
+                  /* BadVAddr must be set */
+                  Flt->BadVAddr = req->getVaddr();
+
+                  /* Context must be set */
+                  Flt->Context_BadVPN2 = (VPN >> 2);
+                  return Flt;
+
+                }
+              Addr PAddr;
+              if(EvenOdd == 0){
+                PAddr = pte->PFN0;
+              }else{
+                PAddr = pte->PFN1;
+              }
+              PAddr >>= (pte->AddrShiftAmount-12);
+              PAddr <<= pte->AddrShiftAmount;
+              PAddr |= ((req->getVaddr()) & pte->OffsetMask);
+              req->setPaddr(PAddr);
+            }
+        }
+      else
+        { // Didn't find any match, return a TLB Refill Exception
+          //	  misses++;
+          DtbRefillFault *Flt=new DtbRefillFault();
+          /* EntryHi VPN, ASID fields must be set */
+          Flt->EntryHi_Asid = Asid;
+          Flt->EntryHi_VPN2 = (VPN>>2);
+          Flt->EntryHi_VPN2X = (VPN & 0x3);
+
+
+          /* BadVAddr must be set */
+          Flt->BadVAddr = req->getVaddr();
+
+          /* Context must be set */
+          Flt->Context_BadVPN2 = (VPN >> 2);
+          return Flt;
+        }
+    }
+    return checkCacheability(req);
+}
+
+///////////////////////////////////////////////////////////////////////
+//
+//  Mips ITB
+//
+ITB::ITB(const Params *p)
+    : TLB(p)
+{}
+
+
+// void
+// ITB::regStats()
+// {
+//   /*    hits - causes failure for some reason
+// 	.name(name() + ".hits")
+// 	.desc("ITB hits");
+//     misses
+// 	.name(name() + ".misses")
+// 	.desc("ITB misses");
+//     acv
+// 	.name(name() + ".acv")
+// 	.desc("ITB acv");
+//     accesses
+// 	.name(name() + ".accesses")
+// 	.desc("ITB accesses");
+
+// 	accesses = hits + misses + invalids; */
+// }
+
+
+
+///////////////////////////////////////////////////////////////////////
+//
+//  Mips DTB
+//
+DTB::DTB(const Params *p)
+    : TLB(p)
+{}
+
+///////////////////////////////////////////////////////////////////////
+//
+//  Mips UTB
+//
+UTB::UTB(const Params *p)
+    : ITB(p), DTB(p)
+{}
+
+
+
+MipsISA::PTE &
+TLB::index(bool advance)
+{
+    MipsISA::PTE *pte = &table[nlu];
+
+    if (advance)
+        nextnlu();
+
+    return *pte;
+}
 
 MipsISA::ITB *
 MipsITBParams::create()
@@ -75,3 +616,9 @@ MipsDTBParams::create()
 {
     return new MipsISA::DTB(this);
 }
+
+MipsISA::UTB *
+MipsUTBParams::create()
+{
+    return new MipsISA::UTB(this);
+}

src/arch/mips/tlb.hh

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -25,20 +25,37 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Gabe Black
+ * Authors: Jaidev Patwardhan
  */
 
 #ifndef __ARCH_MIPS_TLB_HH__
 #define __ARCH_MIPS_TLB_HH__
 
+#include <map>
+
+#include "arch/mips/isa_traits.hh"
+#include "arch/mips/utility.hh"
+#include "arch/mips/vtophys.hh"
+#include "arch/mips/pagetable.hh"
+#include "base/statistics.hh"
+#include "mem/request.hh"
 #include "params/MipsDTB.hh"
 #include "params/MipsITB.hh"
+#include "sim/faults.hh"
 #include "sim/tlb.hh"
+#include "sim/sim_object.hh"
 
-namespace MipsISA
+class ThreadContext;
+
+/* MIPS does not distinguish between a DTLB and an ITLB -> unified TLB
+   However, to maintain compatibility with other architectures, we'll
+   simply create an ITLB and DTLB that will point to the real TLB */
+namespace MipsISA {
+
+// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
+// We just need this to make compiler happy. Use "PTE" type for real entry.
+struct TlbEntry
 {
-    struct TlbEntry
-    {
     Addr _pageStart;
     TlbEntry() {}
     TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
@@ -48,35 +65,96 @@ namespace MipsISA
         return _pageStart;
     }
 
-        void serialize(std::ostream &os);
+    void serialize(std::ostream &os)
-        void unserialize(Checkpoint *cp, const std::string &section);
-    };
-
-    class TLB : public GenericTLB
     {
-      public:
+        SERIALIZE_SCALAR(_pageStart);
-        typedef MipsTLBParams Params;
+    }
-        TLB(const Params *p) : GenericTLB(p)
-        {}
 
-        Fault translate(RequestPtr req, ThreadContext *tc, bool=false);
+    void unserialize(Checkpoint *cp, const std::string &section)
-    };
-
-    class ITB : public TLB
     {
-      public:
+        UNSERIALIZE_SCALAR(_pageStart);
-        typedef MipsITBParams Params;
+    }
-        ITB(const Params *p) : TLB(p)
-        {}
-    };
 
-    class DTB : public TLB
-    {
-      public:
-        typedef MipsDTBParams Params;
-        DTB(const Params *p) : TLB(p)
-        {}
-    };
 };
 
-#endif // __ARCH_MIPS_TLB_HH__
+class TLB : public SimObject
+{
+  protected:
+    typedef std::multimap<Addr, int> PageTable;
+    PageTable lookupTable;	// Quick lookup into page table
+
+    MipsISA::PTE *table;	// the Page Table
+    int size;			// TLB Size
+    int nlu;			// not last used entry (for replacement)
+
+    void nextnlu() { if (++nlu >= size) nlu = 0; }
+    MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const;
+
+    mutable Stats::Scalar<> read_hits;
+    mutable Stats::Scalar<> read_misses;
+    mutable Stats::Scalar<> read_acv;
+    mutable Stats::Scalar<> read_accesses;
+    mutable Stats::Scalar<> write_hits;
+    mutable Stats::Scalar<> write_misses;
+    mutable Stats::Scalar<> write_acv;
+    mutable Stats::Scalar<> write_accesses;
+    Stats::Formula hits;
+    Stats::Formula misses;
+    Stats::Formula invalids;
+    Stats::Formula accesses;
+
+  public:
+    typedef MipsTLBParams Params;
+    TLB(const Params *p);
+
+    int probeEntry(Addr vpn,uint8_t) const;
+    MipsISA::PTE *getEntry(unsigned) const;
+    virtual ~TLB();
+    int smallPages;
+    int getsize() const { return size; }
+
+    MipsISA::PTE &index(bool advance = true);
+    void insert(Addr vaddr, MipsISA::PTE &pte);
+    void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages);
+    void flushAll();
+
+    // static helper functions... really
+    static bool validVirtualAddress(Addr vaddr);
+
+    static Fault checkCacheability(RequestPtr &req);
+
+    // Checkpointing
+    void serialize(std::ostream &os);
+    void unserialize(Checkpoint *cp, const std::string &section);
+
+    void regStats();
+};
+
+class ITB : public TLB {
+  public:
+    typedef MipsTLBParams Params;
+    ITB(const Params *p);
+
+    Fault translate(RequestPtr &req, ThreadContext *tc);
+};
+
+class DTB : public TLB {
+  public:
+    typedef MipsTLBParams Params;
+    DTB(const Params *p);
+
+    Fault translate(RequestPtr &req, ThreadContext *tc, bool write = false);
+};
+
+class UTB : public ITB, public DTB {
+  public:
+    typedef MipsTLBParams Params;
+    UTB(const Params *p);
+
+};
+
+}
+
+
+
+#endif // __MIPS_MEMORY_HH__

src/arch/mips/types.hh

@@ -1,31 +1,37 @@
 /*
- * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
+ * This software is part of the M5 simulator.
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * TO THESE TERMS AND CONDITIONS.
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Korey Sewell
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Korey L. Sewell
  */
 
 #ifndef __ARCH_MIPS_TYPES_HH__
@@ -37,7 +43,7 @@ namespace MipsISA
 {
     typedef uint32_t MachInst;
     typedef uint64_t ExtMachInst;
-    typedef uint8_t  RegIndex;
+    typedef uint16_t  RegIndex;
 
     typedef uint32_t IntReg;
     typedef uint64_t LargestRead;

src/arch/mips/utility.cc

@@ -1,36 +1,41 @@
 /*
- * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
+ * This software is part of the M5 simulator.
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * TO THESE TERMS AND CONDITIONS.
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Korey Sewell
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Korey L. Sewell
  */
 
 #include "arch/mips/isa_traits.hh"
 #include "arch/mips/utility.hh"
-#include "arch/mips/constants.hh"
 #include "config/full_system.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/static_inst.hh"
@@ -38,11 +43,42 @@
 #include "base/bitfield.hh"
 #include "base/misc.hh"
 
+#if FULL_SYSTEM
+#include "arch/mips/vtophys.hh"
+#include "mem/vport.hh"
+#endif
+
+
 using namespace MipsISA;
 using namespace std;
 
+namespace MipsISA {
+
 uint64_t
-MipsISA::fpConvert(ConvertType cvt_type, double fp_val)
+getArgument(ThreadContext *tc, int number, bool fp)
+{
+#if FULL_SYSTEM
+    if (number < NumArgumentRegs) {
+        if (fp)
+            return tc->readFloatRegBits(ArgumentReg[number]);
+        else
+            return tc->readIntReg(ArgumentReg[number]);
+    } else {
+        Addr sp = tc->readIntReg(StackPointerReg);
+        VirtualPort *vp = tc->getVirtPort(tc);
+        uint64_t arg = vp->read<uint64_t>(sp +
+                           (number-NumArgumentRegs) * sizeof(uint64_t));
+        tc->delVirtPort(vp);
+        return arg;
+    }
+#else
+    panic("getArgument() is Full system only\n");
+    M5_DUMMY_RETURN
+#endif
+}
+
+uint64_t
+fpConvert(ConvertType cvt_type, double fp_val)
 {
 
     switch (cvt_type)
@@ -86,7 +122,7 @@ MipsISA::fpConvert(ConvertType cvt_type, double fp_val)
 }
 
 double
-MipsISA::roundFP(double val, int digits)
+roundFP(double val, int digits)
 {
     double digit_offset = pow(10.0,digits);
     val = val * digit_offset;
@@ -97,14 +133,14 @@ MipsISA::roundFP(double val, int digits)
 }
 
 double
-MipsISA::truncFP(double val)
+truncFP(double val)
 {
     int trunc_val = (int) val;
     return (double) trunc_val;
 }
 
 bool
-MipsISA::getCondCode(uint32_t fcsr, int cc_idx)
+getCondCode(uint32_t fcsr, int cc_idx)
 {
     int shift = (cc_idx == 0) ? 23 : cc_idx + 24;
     bool cc_val = (fcsr >> shift) & 0x00000001;
@@ -112,7 +148,7 @@ MipsISA::getCondCode(uint32_t fcsr, int cc_idx)
 }
 
 uint32_t
-MipsISA::genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
+genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
 {
     int cc_idx = (cc_num == 0) ? 23 : cc_num + 24;
 
@@ -124,7 +160,7 @@ MipsISA::genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
 }
 
 uint32_t
-MipsISA::genInvalidVector(uint32_t fcsr_bits)
+genInvalidVector(uint32_t fcsr_bits)
 {
     //Set FCSR invalid in "flag" field
     int invalid_offset = Invalid + Flag_Field;
@@ -138,7 +174,7 @@ MipsISA::genInvalidVector(uint32_t fcsr_bits)
 }
 
 bool
-MipsISA::isNan(void *val_ptr, int size)
+isNan(void *val_ptr, int size)
 {
     switch (size)
     {
@@ -161,7 +197,7 @@ MipsISA::isNan(void *val_ptr, int size)
 
 
 bool
-MipsISA::isQnan(void *val_ptr, int size)
+isQnan(void *val_ptr, int size)
 {
     switch (size)
     {
@@ -183,7 +219,7 @@ MipsISA::isQnan(void *val_ptr, int size)
 }
 
 bool
-MipsISA::isSnan(void *val_ptr, int size)
+isSnan(void *val_ptr, int size)
 {
     switch (size)
     {
@@ -204,8 +240,40 @@ MipsISA::isSnan(void *val_ptr, int size)
     }
 }
 
-void
+int
-MipsISA::startupCPU(ThreadContext *tc, int cpuId)
+flattenIntIndex(ThreadContext * tc, int reg)
 {
-        tc->activate(0);
+    return reg;
 }
+
+
+void
+copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+    panic("Copy Regs Not Implemented Yet\n");
+}
+
+void
+copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+    panic("Copy Misc. Regs Not Implemented Yet\n");
+}
+
+template <class CPU>
+void
+zeroRegisters(CPU *cpu)
+{
+    // Insure ISA semantics
+    // (no longer very clean due to the change in setIntReg() in the
+    // cpu model.  Consider changing later.)
+    cpu->thread->setIntReg(ZeroReg, 0);
+    cpu->thread->setFloatReg(ZeroReg, 0.0);
+}
+
+void
+startupCPU(ThreadContext *tc, int cpuId)
+{
+    tc->activate(0/*tc->getThreadNum()*/);
+}
+
+} // namespace MipsISA

src/arch/mips/utility.hh

@@ -1,39 +1,42 @@
 /*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
- * Copyright (c) 2007 MIPS Technologies, Inc.
- * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
+ * This software is part of the M5 simulator.
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * TO THESE TERMS AND CONDITIONS.
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Nathan Binkert
+ * Permission is granted to use, copy, create derivative works and
- *          Steve Reinhardt
+ * distribute this software and such derivative works for any purpose,
- *          Korey Sewell
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Korey L. Sewell
  */
 
 #ifndef __ARCH_MIPS_UTILITY_HH__
 #define __ARCH_MIPS_UTILITY_HH__
-
+#include "config/full_system.hh"
 #include "arch/mips/types.hh"
 #include "arch/mips/isa_traits.hh"
 #include "base/misc.hh"
@@ -48,11 +51,7 @@ class ThreadContext;
 
 namespace MipsISA {
 
-    inline uint64_t
+    uint64_t getArgument(ThreadContext *tc, int number, bool fp);
-    getArgument(ThreadContext *tc, bool fp)
-    {
-        panic("getArgument() not implemented for MIPS\n");
-    }
 
     //Floating Point Utility Functions
     uint64_t fpConvert(ConvertType cvt_type, double fp_val);
@@ -67,15 +66,24 @@ namespace MipsISA {
     bool isQnan(void *val_ptr, int size);
     bool isSnan(void *val_ptr, int size);
 
-    /**
-     * Function to insure ISA semantics about 0 registers.
-     * @param tc The thread context.
-     */
-    template <class TC>
-    void zeroRegisters(TC *tc);
-
     void startupCPU(ThreadContext *tc, int cpuId);
 
+    static inline bool
+    inUserMode(ThreadContext *tc)
+    {
+        MiscReg Stat = tc->readMiscReg(MipsISA::Status);
+        MiscReg Dbg = tc->readMiscReg(MipsISA::Debug);
+
+        if((Stat & 0x10000006) == 0  // EXL, ERL or CU0 set, CP0 accessible
+           && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
+           && (Stat & 0x00000018) != 0) {  // KSU = 0, kernel mode is base mode
+            // Unable to use Status_CU0, etc directly, using bitfields & masks
+            return true;
+        } else {
+            return false;
+        }
+    }
+
     // Instruction address compression hooks
     static inline Addr realPCToFetchPC(const Addr &addr) {
         return addr;
@@ -96,18 +104,61 @@ namespace MipsISA {
         return 0;
     }
 
-    static inline ExtMachInst
+    static inline int flattenFloatIndex(ThreadContext * tc, int reg)
-    makeExtMI(MachInst inst, ThreadContext * xc) {
+    {
-#if FULL_SYSTEM
+        return reg;
-        ExtMachInst ext_inst = inst;
-        if (xc->readPC() && 0x1)
-            return ext_inst|=(static_cast<ExtMachInst>(xc->readPC() & 0x1) << 32);
-        else
-            return ext_inst;
-#else
-        return ExtMachInst(inst);
-#endif
     }
+
+    int flattenIntIndex(ThreadContext * tc, int reg);
+
+    void copyRegs(ThreadContext *src, ThreadContext *dest);
+
+    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+
+
+    template <class CPU>
+    void zeroRegisters(CPU *cpu);
+
+    ////////////////////////////////////////////////////////////////////////
+    //
+    //  Translation stuff
+    //
+
+    inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
+
+    // User Virtual
+    inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
+
+    inline bool IsKSeg0(Addr a) { return KSeg0Base <= a && a <= KSeg0End; }
+
+    inline Addr KSeg02Phys(Addr addr) { return addr & KSeg0Mask; }
+
+    inline Addr KSeg12Phys(Addr addr) { return addr & KSeg1Mask; }
+
+    inline bool IsKSeg1(Addr a) { return KSeg1Base <= a && a <= KSeg1End; }
+
+    inline bool IsKSSeg(Addr a) { return KSSegBase <= a && a <= KSSegEnd; }
+
+    inline bool IsKSeg3(Addr a) { return KSeg3Base <= a && a <= KSeg3End; }
+
+    inline Addr
+    TruncPage(Addr addr)
+    { return addr & ~(PageBytes - 1); }
+
+    inline Addr
+    RoundPage(Addr addr)
+    { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
+
+    void initCPU(ThreadContext *tc, int cpuId);
+    void initIPRs(ThreadContext *tc, int cpuId);
+
+    /**
+     * Function to check for and process any interrupts.
+     * @param tc The thread context.
+     */
+    template <class TC>
+    void processInterrupts(TC *tc);
+
 };
 
 

src/arch/mips/vtophys.cc

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ *          Steve Reinhardt
+ *          Ali Saidi
+ */
+
+#include <string>
+
+#include "arch/mips/vtophys.hh"
+#include "base/chunk_generator.hh"
+#include "base/trace.hh"
+#include "cpu/thread_context.hh"
+#include "mem/vport.hh"
+using namespace std;
+using namespace MipsISA;
+
+Addr
+MipsISA::vtophys(Addr vaddr)
+{
+    Addr paddr = 0;
+    if (MipsISA::IsUSeg(vaddr))
+        DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
+    else if (MipsISA::IsKSeg0(vaddr))
+        paddr = MipsISA::KSeg02Phys(vaddr);
+    else if(MipsISA::IsKSeg1(vaddr))
+        paddr = MipsISA::KSeg12Phys(vaddr);
+    else
+        panic("vtophys: ptbr is not set on virtual lookup for vaddr %#x", vaddr);
+
+    DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
+
+    return paddr;
+}
+
+Addr
+MipsISA::vtophys(ThreadContext *tc, Addr addr)
+{
+
+  fatal("VTOPHYS: Unimplemented on MIPS\n");
+}
+

src/arch/mips/vtophys.hh

@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ *          Steve Reinhardt
+ *          Jaidev Patwardhan
+ */
+
+#ifndef __ARCH_MIPS_VTOPHYS_H__
+#define __ARCH_MIPS_VTOPHYS_H__
+
+#include "arch/mips/isa_traits.hh"
+#include "arch/mips/pagetable.hh"
+#include "arch/mips/utility.hh"
+
+
+class ThreadContext;
+class FunctionalPort;
+
+namespace MipsISA {
+
+
+    Addr vtophys(Addr vaddr);
+    Addr vtophys(ThreadContext *tc, Addr vaddr);
+
+};
+#endif // __ARCH_MIPS_VTOPHYS_H__
+

src/base/SConscript

@@ -65,6 +65,7 @@ Source('compression/lzss_compression.cc')
 Source('loader/aout_object.cc')
 Source('loader/ecoff_object.cc')
 Source('loader/elf_object.cc')
+Source('loader/hex_file.cc')
 Source('loader/object_file.cc')
 Source('loader/raw_object.cc')
 Source('loader/symtab.cc')

src/base/loader/hex_file.cc

@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Jaidev Patwardhan
+ */
+
+#include <list>
+#include <string>
+
+#include <sys/types.h>
+#include <sys/mman.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <unistd.h>
+
+#include "base/cprintf.hh"
+#include "base/loader/hex_file.hh"
+#include "base/loader/symtab.hh"
+
+
+#include "mem/translating_port.hh"
+
+using namespace std;
+/* Load a Hex File into memory.
+   Currently only used with MIPS BARE_IRON mode.
+   A hex file consists of [Address Data] tuples that get directly loaded into
+   physical memory. The address specified is a word address (i.e., to get the byte address, shift left by 2)
+   The data is a full 32-bit hex value.
+*/
+HexFile::HexFile(const string _filename)
+    : filename(_filename)
+{
+  fp = fopen(filename.c_str(),"r");
+  if(fp == NULL)
+    {
+      panic("Unable to open %s\n",filename.c_str());
+    }
+
+}
+
+HexFile::~HexFile()
+{
+}
+
+
+bool
+HexFile::loadSections(Port *memPort, Addr addrMask)
+{
+  char Line[64];
+  Addr MemAddr;
+  uint32_t Data;
+  while(!feof(fp))
+    {
+      fgets(Line,64,fp);
+      parseLine(Line,&MemAddr,&Data);
+      //      printf("Hex:%u\n",Data);
+
+      if(MemAddr != 0)
+        {
+          // Now, write to memory
+          memPort->writeBlob(MemAddr<<2,(uint8_t *)&Data,sizeof(Data));
+        }
+    }
+    return true;
+}
+void HexFile::parseLine(char *Str,Addr *A, uint32_t *D)
+{
+  int i=0;
+  bool Flag = false;
+  *A = 0;
+  *D = 0;
+  int Digit = 0;
+  unsigned Number = 0;
+  /* Skip white spaces */
+  while(Str[i] != '\0' && Str[i]==' ')
+    i++;
+
+  /* Ok, we're at some character...process things */
+  while(Str[i] != '\0')
+    {
+      if(Str[i]>='0' && Str[i]<='9')
+        {
+          Digit=Str[i]-'0';
+        }
+      else if(Str[i]>='a' && Str[i]<='f')
+        {
+          Digit=Str[i]-'a'+10;
+        }
+      else if(Str[i]>='A' && Str[i]<='F')
+        {
+          Digit=Str[i]-'A'+10;
+        }
+      else if(Str[i] == ' ' || Str[i]=='\n')
+        {
+          if(Number == 0)
+            return;
+          if(Flag == false)
+            {
+              *A = Number;
+              Number = 0;
+              Flag = true;
+            }
+          else
+            {
+              *D = Number;
+              return;
+            }
+        }
+      else
+        {
+          // Ok, we've encountered a non-hex character, cannot be a valid line, skip and return 0's
+          *A = 0;
+          *D = 0;
+          return;
+        }
+      Number<<=4;
+      Number+=Digit;
+      i++;
+
+    }
+  if(Flag != true)
+    {
+      *A = 0;
+      *D = 0;
+    }
+  else
+    *D = Number;
+
+}
+
+
+
+void
+HexFile::close()
+{
+  fclose(fp);
+}

src/base/loader/hex_file.cc~

@@ -0,0 +1,162 @@
+ /*
+ * Copyright (c) 2002, 2003, 2004
+ * The Regents of The University of Michigan
+ * All Rights Reserved
+ *
+ * This code is part of the M5 simulator.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * redistribute this software and such derivative works for any
+ * purpose, so long as the copyright notice above, this grant of
+ * permission, and the disclaimer below appear in all copies made; and
+ * so long as the name of The University of Michigan is not used in
+ * any advertising or publicity pertaining to the use or distribution
+ * of this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
+ * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND
+ * WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER
+ * EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE
+ * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT,
+ * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM
+ * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
+ * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGES.
+ *
+ * Authors: Jaidev Patwardhan
+ *
+ */
+
+#include <list>
+#include <string>
+
+#include <sys/types.h>
+#include <sys/mman.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <unistd.h>
+
+#include "base/cprintf.hh"
+#include "base/loader/hex_file.hh"
+#include "base/loader/symtab.hh"
+
+
+#include "mem/translating_port.hh"
+
+using namespace std;
+/* Load a Hex File into memory.
+   Currently only used with MIPS BARE_IRON mode.
+   A hex file consists of [Address Data] tuples that get directly loaded into
+   physical memory. The address specified is a word address (i.e., to get the byte address, shift left by 2)
+   The data is a full 32-bit hex value.
+*/
+HexFile::HexFile(const string _filename)
+    : filename(_filename)
+{
+  fp = fopen(filename.c_str(),"r");
+  if(fp == NULL)
+    {
+      fatal("Unable to open %s\n",filename.c_str());
+    }
+    
+}
+
+HexFile::~HexFile()
+{
+}
+
+
+bool
+HexFile::loadSections(Port *memPort, Addr addrMask)
+{
+  char Line[64];
+  Addr MemAddr;
+  uint32_t Data;
+  while(!feof(fp))
+    {
+      fgets(Line,64,fp);
+      parseLine(Line,&MemAddr,&Data);
+      //      printf("Hex:%u\n",Data);
+      
+      if(MemAddr != 0)
+	{
+	  // Now, write to memory
+	  memPort->writeBlob(MemAddr<<2,(uint8_t *)&Data,sizeof(Data));
+	}
+    }
+    return true;
+}
+void HexFile::parseLine(char *Str,Addr *A, uint32_t *D)
+{
+  int i=0;
+  bool Flag = false;
+  *A = 0;
+  *D = 0;
+  int Digit = 0;
+  unsigned Number = 0;
+  /* Skip white spaces */
+  while(Str[i] != '\0' && Str[i]==' ')
+    i++;
+
+  /* Ok, we're at some character...process things */
+  while(Str[i] != '\0')
+    {
+      if(Str[i]>='0' && Str[i]<='9')
+	{
+	  Digit=Str[i]-'0';
+	}
+      else if(Str[i]>='a' && Str[i]<='f')
+	{
+	  Digit=Str[i]-'a'+10;
+	}
+      else if(Str[i]>='A' && Str[i]<='F')
+	{
+	  Digit=Str[i]-'A'+10;
+	}
+      else if(Str[i] == ' ' || Str[i]=='\n')
+	{
+	  if(Number == 0)
+	    return;
+	  if(Flag == false)
+	    {
+	      *A = Number;
+	      Number = 0;
+	      Flag = true;
+	    }
+	  else
+	    {
+	      *D = Number;
+	      return;
+	    }
+	}
+      else
+	{
+	  // Ok, we've encountered a non-hex character, cannot be a valid line, skip and return 0's
+	  *A = 0;
+	  *D = 0;
+	  return;
+	}
+      Number<<=4;
+      Number+=Digit;
+      i++;
+      
+    }
+  if(Flag != true)
+    {
+      *A = 0;
+      *D = 0;
+    }
+  else
+    *D = Number;
+  
+}
+
+
+
+void
+HexFile::close()
+{
+  fclose(fp);
+}

src/base/loader/hex_file.hh

@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2002-2004 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Jaidev Patwardhan
+ */
+
+#ifndef __HEX_FILE_HH__
+#define __HEX_FILE_HH__
+
+#include <limits>
+#include <string>
+
+#include "sim/host.hh"	// for Addr
+#include <fstream>
+
+class Port;
+
+class HexFile
+{
+  public:
+
+
+  protected:
+    const std::string filename;
+    FILE *fp;
+
+  public:
+    virtual ~HexFile();
+    HexFile(const std::string _filename);
+
+    void close();
+
+    bool loadSections(Port *memPort, Addr addrMask =
+            std::numeric_limits<Addr>::max());
+
+  protected:
+
+  typedef struct {
+    Addr MemAddr;
+    uint32_t Data;
+  } HexLine;
+
+    Addr entry;
+    Addr globalPtr;
+
+  public:
+    void parseLine(char *,Addr *,uint32_t *);
+    Addr entryPoint() const { return entry; }
+    Addr globalPointer() const { return globalPtr; }
+
+};
+
+#endif // __HEX_FILE_HH__

src/base/loader/object_file.cc

@@ -71,6 +71,7 @@ ObjectFile::loadSection(Section *sec, Port *memPort, Addr addrMask)
 {
     if (sec->size != 0) {
         Addr addr = sec->baseAddr & addrMask;
+        warn("attempting load @ section addr: %#x", addr);
         if (sec->fileImage) {
             memPort->writeBlob(addr, sec->fileImage, sec->size);
         }

src/cpu/BaseCPU.py

@@ -44,7 +44,7 @@ elif build_env['TARGET_ISA'] == 'sparc':
 elif build_env['TARGET_ISA'] == 'x86':
     from X86TLB import X86DTB, X86ITB
 elif build_env['TARGET_ISA'] == 'mips':
-    from MipsTLB import MipsDTB, MipsITB
+    from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB
 
 class BaseCPU(SimObject):
     type = 'BaseCPU'
@@ -72,8 +72,10 @@ class BaseCPU(SimObject):
         dtb = Param.X86DTB(X86DTB(), "Data TLB")
         itb = Param.X86ITB(X86ITB(), "Instruction TLB")
     elif build_env['TARGET_ISA'] == 'mips':
+        UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
         dtb = Param.MipsDTB(MipsDTB(), "Data TLB")
         itb = Param.MipsITB(MipsITB(), "Instruction TLB")
+        tlb = Param.MipsUTB(MipsUTB(), "Unified TLB")
     else:
         print "Don't know what TLB to use for ISA %s" % \
             build_env['TARGET_ISA']
@@ -120,3 +122,59 @@ class BaseCPU(SimObject):
         self.l2cache = l2c
         self.l2cache.cpu_side = self.toL2Bus.port
         self._mem_ports = ['l2cache.mem_side']
+
+    if build_env['TARGET_ISA'] == 'mips':
+        CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description")
+        CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description")
+        CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description")
+        CP0_EBase_CPUNum = Param.Unsigned(0,"No Description")
+        CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register")
+        CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register")
+        CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company")
+        CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register")
+        CP0_Config_BE = Param.Unsigned(0,"Big Endian?")
+        CP0_Config_AT = Param.Unsigned(0,"No Description")
+        CP0_Config_AR = Param.Unsigned(0,"No Description")
+        CP0_Config_MT = Param.Unsigned(0,"No Description")
+        CP0_Config_VI = Param.Unsigned(0,"No Description")
+        CP0_Config1_M = Param.Unsigned(0,"Config2 Implemented?")
+        CP0_Config1_MMU = Param.Unsigned(0,"MMU Type")
+        CP0_Config1_IS = Param.Unsigned(0,"No Description")
+        CP0_Config1_IL = Param.Unsigned(0,"No Description")
+        CP0_Config1_IA = Param.Unsigned(0,"No Description")
+        CP0_Config1_DS = Param.Unsigned(0,"No Description")
+        CP0_Config1_DL = Param.Unsigned(0,"No Description")
+        CP0_Config1_DA = Param.Unsigned(0,"No Description")
+        CP0_Config1_C2 = Param.Bool(False,"No Description")
+        CP0_Config1_MD = Param.Bool(False,"No Description")
+        CP0_Config1_PC = Param.Bool(False,"No Description")
+        CP0_Config1_WR = Param.Bool(False,"No Description")
+        CP0_Config1_CA = Param.Bool(False,"No Description")
+        CP0_Config1_EP = Param.Bool(False,"No Description")
+        CP0_Config1_FP = Param.Bool(False,"FPU Implemented?")
+        CP0_Config2_M = Param.Bool(False,"Config3 Implemented?")
+        CP0_Config2_TU = Param.Unsigned(0,"No Description")
+        CP0_Config2_TS = Param.Unsigned(0,"No Description")
+        CP0_Config2_TL = Param.Unsigned(0,"No Description")
+        CP0_Config2_TA = Param.Unsigned(0,"No Description")
+        CP0_Config2_SU = Param.Unsigned(0,"No Description")
+        CP0_Config2_SS = Param.Unsigned(0,"No Description")
+        CP0_Config2_SL = Param.Unsigned(0,"No Description")
+        CP0_Config2_SA = Param.Unsigned(0,"No Description")
+        CP0_Config3_M = Param.Bool(False,"Config4 Implemented?")
+        CP0_Config3_DSPP = Param.Bool(False,"DSP Extensions Present?")
+        CP0_Config3_LPA = Param.Bool(False,"No Description")
+        CP0_Config3_VEIC = Param.Bool(False,"No Description")
+        CP0_Config3_VInt = Param.Bool(False,"No Description")
+        CP0_Config3_SP = Param.Bool(False,"No Description")
+        CP0_Config3_MT = Param.Bool(False,"Multithreading Extensions Present?")
+        CP0_Config3_SM = Param.Bool(False,"No Description")
+        CP0_Config3_TL = Param.Bool(False,"No Description")
+        CP0_WatchHi_M = Param.Bool(False,"No Description")
+        CP0_PerfCtr_M = Param.Bool(False,"No Description")
+        CP0_PerfCtr_W = Param.Bool(False,"No Description")
+        CP0_PRId = Param.Unsigned(0,"CP0 Status Register")
+        CP0_Config = Param.Unsigned(0,"CP0 Config Register")
+        CP0_Config1 = Param.Unsigned(0,"CP0 Config1 Register")
+        CP0_Config2 = Param.Unsigned(0,"CP0 Config2 Register")
+        CP0_Config3 = Param.Unsigned(0,"CP0 Config3 Register")

src/cpu/base.hh

@@ -189,6 +189,77 @@ class BaseCPU : public MemObject
         Tick progress_interval;
         BaseCPU *checker;
 
+#if THE_ISA == MIPS_ISA
+      /* Note: It looks like it will be better to allow simulator users
+         to specify the values of individual variables instead of requiring
+         users to define the values of entire registers
+         Especially since a lot of these variables can be created from other
+         user parameters  (cache descriptions)
+                                               -jpp
+      */
+      // MIPS CP0 State - First individual variables
+      // Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM, Volume III (PRA)
+      unsigned CP0_IntCtl_IPTI; // Page 93, IP Timer Interrupt
+      unsigned CP0_IntCtl_IPPCI; // Page 94, IP Performance Counter Interrupt
+      unsigned CP0_SrsCtl_HSS; // Page 95, Highest Implemented Shadow Set
+      unsigned CP0_PRId_CompanyOptions; // Page 105, Manufacture options
+      unsigned CP0_PRId_CompanyID; // Page 105, Company ID - (0-255, 1=>MIPS)
+      unsigned CP0_PRId_ProcessorID; // Page 105
+      unsigned CP0_PRId_Revision; // Page 105
+      unsigned CP0_EBase_CPUNum; // Page 106, CPU Number in a multiprocessor system
+      unsigned CP0_Config_BE; // Page 108, Big/Little Endian mode
+      unsigned CP0_Config_AT; //Page 109
+      unsigned CP0_Config_AR; //Page 109
+      unsigned CP0_Config_MT; //Page 109
+      unsigned CP0_Config_VI; //Page 109
+      unsigned CP0_Config1_M; // Page 110
+      unsigned CP0_Config1_MMU; // Page 110
+      unsigned CP0_Config1_IS; // Page 110
+      unsigned CP0_Config1_IL; // Page 111
+      unsigned CP0_Config1_IA; // Page 111
+      unsigned CP0_Config1_DS; // Page 111
+      unsigned CP0_Config1_DL; // Page 112
+      unsigned CP0_Config1_DA; // Page 112
+      bool CP0_Config1_C2; // Page 112
+      bool CP0_Config1_MD;// Page 112 - Technically not used in MIPS32
+      bool CP0_Config1_PC;// Page 112
+      bool CP0_Config1_WR;// Page 113
+      bool CP0_Config1_CA;// Page 113
+      bool CP0_Config1_EP;// Page 113
+      bool CP0_Config1_FP;// Page 113
+      bool CP0_Config2_M; // Page 114
+      unsigned CP0_Config2_TU;// Page 114
+      unsigned CP0_Config2_TS;// Page 114
+      unsigned CP0_Config2_TL;// Page 115
+      unsigned CP0_Config2_TA;// Page 115
+      unsigned CP0_Config2_SU;// Page 115
+      unsigned CP0_Config2_SS;// Page 115
+      unsigned CP0_Config2_SL;// Page 116
+      unsigned CP0_Config2_SA;// Page 116
+      bool CP0_Config3_M; //// Page 117
+      bool CP0_Config3_DSPP;// Page 117
+      bool CP0_Config3_LPA;// Page 117
+      bool CP0_Config3_VEIC;// Page 118
+      bool CP0_Config3_VInt; // Page 118
+      bool CP0_Config3_SP;// Page 118
+      bool CP0_Config3_MT;// Page 119
+      bool CP0_Config3_SM;// Page 119
+      bool CP0_Config3_TL;// Page 119
+
+      bool CP0_WatchHi_M; // Page 124
+      bool CP0_PerfCtr_M; // Page 130
+      bool CP0_PerfCtr_W; // Page 130
+
+
+      // Then, whole registers
+      unsigned CP0_PRId;
+      unsigned CP0_Config;
+      unsigned CP0_Config1;
+      unsigned CP0_Config2;
+      unsigned CP0_Config3;
+
+#endif
+
         Params();
     };
 

src/cpu/o3/thread_context.hh

@@ -236,6 +236,7 @@ class O3ThreadContext : public ThreadContext
      * misspeculating, this is set as false. */
     virtual bool misspeculating() { return false; }
 
+    virtual void setShadowSet(int ss) { };
 #if !FULL_SYSTEM
     /** Gets a syscall argument by index. */
     virtual IntReg getSyscallArg(int i);

src/cpu/simple/base.cc

@@ -503,3 +503,37 @@ BaseSimpleCPU::advancePC(Fault fault)
     } while (oldpc != thread->readPC());
 }
 
+Fault
+BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
+{
+    // translate to physical address
+    Fault fault = NoFault;
+    int CacheID = Op & 0x3; // Lower 3 bits identify Cache
+    int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
+    if(CacheID > 1)
+      {
+        warn("CacheOps not implemented for secondary/tertiary caches\n");
+      }
+    else
+      {
+        switch(CacheOP)
+          { // Fill Packet Type
+          case 0: warn("Invalidate Cache Op\n");
+            break;
+          case 1: warn("Index Load Tag Cache Op\n");
+            break;
+          case 2: warn("Index Store Tag Cache Op\n");
+            break;
+          case 4: warn("Hit Invalidate Cache Op\n");
+            break;
+          case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n");
+            break;
+          case 6: warn("Hit Writeback\n");
+            break;
+          case 7: warn("Fetch & Lock Cache Op\n");
+            break;
+          default: warn("Unimplemented Cache Op\n");
+          }
+      }
+    return fault;
+}