imported patch squash_from_next_stage
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parent
f0f33ae2b9
commit
264e8178ff
6 changed files with 62 additions and 40 deletions
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@ -1130,6 +1130,7 @@ InOrderCPU::getPipeStage(int stage_num)
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return pipelineStage[stage_num];
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}
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RegIndex
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InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegType ®_type, ThreadID tid)
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{
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@ -1455,29 +1456,31 @@ InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
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inline void
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InOrderCPU::squashInstIt(const ListIt &instIt, ThreadID tid)
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InOrderCPU::squashInstIt(const ListIt inst_it, ThreadID tid)
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{
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if ((*instIt)->threadNumber == tid) {
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DynInstPtr inst = (*inst_it);
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if (inst->threadNumber == tid) {
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DPRINTF(InOrderCPU, "Squashing instruction, "
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"[tid:%i] [sn:%lli] PC %s\n",
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(*instIt)->threadNumber,
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(*instIt)->seqNum,
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(*instIt)->pcState());
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inst->threadNumber,
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inst->seqNum,
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inst->pcState());
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(*instIt)->setSquashed();
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inst->setSquashed();
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archRegDepMap[tid].remove(inst);
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if (!(*instIt)->isRemoveList()) {
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if (!inst->isRemoveList()) {
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DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
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"[sn:%lli] to remove list\n",
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(*instIt)->threadNumber, (*instIt)->pcState(),
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(*instIt)->seqNum);
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(*instIt)->setRemoveList();
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removeList.push(instIt);
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inst->threadNumber, inst->pcState(),
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inst->seqNum);
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inst->setRemoveList();
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removeList.push(inst_it);
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} else {
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DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i]"
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" PC %s [sn:%lli], already on remove list\n",
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(*instIt)->threadNumber, (*instIt)->pcState(),
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(*instIt)->seqNum);
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inst->threadNumber, inst->pcState(),
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inst->seqNum);
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}
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}
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@ -1499,7 +1502,7 @@ InOrderCPU::cleanUpRemovedInsts()
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ThreadID tid = inst->threadNumber;
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// Remove From Register Dependency Map, If Necessary
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archRegDepMap[tid].remove(inst);
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// archRegDepMap[tid].remove(inst);
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// Clear if Non-Speculative
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if (inst->staticInst &&
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@ -547,6 +547,16 @@ class InOrderCPU : public BaseCPU
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void setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid);
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RegType inline getRegType(RegIndex reg_idx)
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{
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if (reg_idx < TheISA::FP_Base_DepTag)
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return IntType;
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else if (reg_idx < TheISA::Ctrl_Base_DepTag)
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return FloatType;
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else
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return MiscType;
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}
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RegIndex flattenRegIdx(RegIndex reg_idx, RegType ®_type, ThreadID tid);
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/** Reads a miscellaneous register. */
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@ -617,7 +627,7 @@ class InOrderCPU : public BaseCPU
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void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
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/** Removes the instruction pointed to by the iterator. */
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inline void squashInstIt(const ListIt &instIt, ThreadID tid);
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inline void squashInstIt(const ListIt inst_it, ThreadID tid);
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/** Cleans up all instructions on the instruction remove list. */
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void cleanUpRemovedInsts();
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@ -351,9 +351,11 @@ PipelineStage::setupSquash(DynInstPtr inst, ThreadID tid)
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inst->seqNum, cpu->squashSeqNum[tid]);
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} else {
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InstSeqNum squash_seq_num = inst->squashSeqNum;
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unsigned squash_stage = (nextStageValid) ? stageNum + 1
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: stageNum;
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toPrevStages->stageInfo[stageNum][tid].squash = true;
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toPrevStages->stageInfo[stageNum][tid].doneSeqNum =
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toPrevStages->stageInfo[squash_stage][tid].squash = true;
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toPrevStages->stageInfo[squash_stage][tid].doneSeqNum =
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squash_seq_num;
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DPRINTF(InOrderStage, "[tid:%i]: Squashing after [sn:%i], "
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@ -89,7 +89,7 @@ RegDepMap::insert(DynInstPtr inst)
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DPRINTF(RegDepMap, "Setting Output Dependencies for [sn:%i] "
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", %s (dest. regs = %i).\n",
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inst->seqNum,
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inst->staticInst->getName(),
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inst->instName(),
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dest_regs);
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for (int i = 0; i < dest_regs; i++) {
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@ -98,6 +98,10 @@ RegDepMap::insert(DynInstPtr inst)
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TheISA::RegIndex flat_idx = cpu->flattenRegIdx(raw_idx,
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reg_type,
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inst->threadNumber);
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DPRINTF(RegDepMap, "[sn:%i] #%i flattened %i to %i.\n",
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inst->seqNum, i, raw_idx, flat_idx);
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inst->flattenDestReg(i, flat_idx);
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insert(reg_type, flat_idx, inst);
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}
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@ -120,32 +124,40 @@ void
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RegDepMap::remove(DynInstPtr inst)
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{
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if (inst->isRegDepEntry()) {
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DPRINTF(RegDepMap, "Removing [sn:%i]'s entries from reg. dep. map.\n",
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inst->seqNum);
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int dest_regs = inst->numDestRegs();
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for (int i = 0; i < dest_regs; i++)
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remove(inst->destRegIdx(i), inst);
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DPRINTF(RegDepMap, "Removing [sn:%i]'s entries from reg. dep. map. for "
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", %s (dest. regs = %i).\n",
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inst->seqNum,
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inst->instName(),
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dest_regs);
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for (int i = 0; i < dest_regs; i++) {
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InOrderCPU::RegType reg_type = cpu->getRegType(inst->destRegIdx(i));
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remove(reg_type, inst->flattenedDestRegIdx(i), inst);
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}
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}
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}
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void
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RegDepMap::remove(RegIndex idx, DynInstPtr inst)
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RegDepMap::remove(uint8_t reg_type, RegIndex idx, DynInstPtr inst)
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{
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InOrderCPU::RegType reg_type;
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TheISA::RegIndex flat_idx = cpu->flattenRegIdx(idx, reg_type,
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inst->threadNumber);
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std::list<DynInstPtr>::iterator list_it = regMap[reg_type][idx].begin();
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std::list<DynInstPtr>::iterator list_end = regMap[reg_type][idx].end();
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std::list<DynInstPtr>::iterator list_it = regMap[reg_type][flat_idx].begin();
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std::list<DynInstPtr>::iterator list_end = regMap[reg_type][flat_idx].end();
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while (list_it != list_end) {
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if((*list_it) == inst) {
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regMap[reg_type][flat_idx].erase(list_it);
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break;
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DPRINTF(RegDepMap, "Removing [sn:%i] from %s dep. list for "
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"reg. idx %i.\n", inst->seqNum, mapNames[reg_type],
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idx);
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regMap[reg_type][idx].erase(list_it);
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return;
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}
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list_it++;
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}
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panic("[sn:%i] Did not find entry for %i ", inst->seqNum, idx);
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}
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void
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@ -153,7 +165,7 @@ RegDepMap::removeFront(uint8_t reg_type, RegIndex idx, DynInstPtr inst)
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{
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std::list<DynInstPtr>::iterator list_it = regMap[reg_type][idx].begin();
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DPRINTF(RegDepMap, "[tid:%u]: Removing dependency entry on reg. idx"
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DPRINTF(RegDepMap, "[tid:%u]: Removing dependency entry on reg. idx "
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"%i for [sn:%i].\n", inst->readTid(), idx, inst->seqNum);
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assert(list_it != regMap[reg_type][idx].end());
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@ -98,10 +98,8 @@ class RegDepMap
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*/
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void insert(uint8_t reg_type, RegIndex idx, DynInstPtr inst);
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/** Remove a specific instruction and dest. register index from map
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* This must be called w/the unflattened registered index
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*/
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void remove(RegIndex idx, DynInstPtr inst);
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/** Remove a specific instruction and dest. register index from map */
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void remove(uint8_t reg_type, RegIndex idx, DynInstPtr inst);
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typedef std::vector<std::list<DynInstPtr> > DepMap;
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std::vector<DepMap> regMap;
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@ -66,11 +66,8 @@ DecodeUnit::execute(int slot_num)
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if (inst->backSked != NULL) {
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DPRINTF(InOrderDecode,
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"[tid:%i]: %s Setting Destination Register(s) for [sn:%i].\n",
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"[tid:%i]: Back End Schedule created for %s [sn:%i].\n",
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tid, inst->instName(), inst->seqNum);
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//inst->printSked();
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decode_req->done();
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} else {
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DPRINTF(Resource,
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