mem: Add HMC Timing Parameters
A single HMC-2500 x32 model based on: [1] DRAMSpec: a high-level DRAM bank modelling tool developed at the University of Kaiserslautern. This high level tool uses RC (resistance-capacitance) and CV (capacitance-voltage) models to estimate the DRAM bank latency and power numbers. [2] A Logic-base Interconnect for Supporting Near Memory Computation in the Hybrid Memory Cube (E. Azarkhish et. al) Assumed for the HMC model is a 30 nm technology node. The modelled HMC consists of a 4 Gbit part with 4 layers connected with TSVs. Each layer has 16 vaults and each vault consists of 2 banks per layer. In order to be able to use the same controller used for 2D DRAM generations for HMC, the following analogy is done: Channel (DDR) => Vault (HMC) device_size (DDR) => size of a single layer in a vault ranks per channel (DDR) => number of layers banks per rank (DDR) => banks per layer devices per rank (DDR) => devices per layer ( 1 for HMC). The parameters for which no input is available are inherited from the DDR3 configuration.
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@ -11,6 +11,7 @@
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# modified or unmodified, in source code or in binary form.
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# modified or unmodified, in source code or in binary form.
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#
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#
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# Copyright (c) 2013 Amin Farmahini-Farahani
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# Copyright (c) 2013 Amin Farmahini-Farahani
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# Copyright (c) 2015 University of Kaiserslautern
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# All rights reserved.
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# All rights reserved.
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#
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#
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# Redistribution and use in source and binary forms, with or without
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# Redistribution and use in source and binary forms, with or without
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@ -38,6 +39,8 @@
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#
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#
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# Authors: Andreas Hansson
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# Authors: Andreas Hansson
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# Ani Udipi
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# Ani Udipi
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# Omar Naji
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# Matthias Jung
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from m5.params import *
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from m5.params import *
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from AbstractMemory import *
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from AbstractMemory import *
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@ -374,6 +377,92 @@ class DDR3_1600_x64(DRAMCtrl):
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IDD5 = '220mA'
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IDD5 = '220mA'
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VDD = '1.5V'
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VDD = '1.5V'
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# A single HMC-2500 x32 model based on:
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# [1] DRAMSpec: a high-level DRAM bank modelling tool
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# developed at the University of Kaiserslautern. This high level tool
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# uses RC (resistance-capacitance) and CV (capacitance-voltage) models to
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# estimate the DRAM bank latency and power numbers.
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# [2] A Logic-base Interconnect for Supporting Near Memory Computation in the
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# Hybrid Memory Cube (E. Azarkhish et. al)
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# Assumed for the HMC model is a 30 nm technology node.
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# The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4
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# layers).
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# Each layer has 16 vaults and each vault consists of 2 banks per layer.
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# In order to be able to use the same controller used for 2D DRAM generations
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# for HMC, the following analogy is done:
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# Channel (DDR) => Vault (HMC)
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# device_size (DDR) => size of a single layer in a vault
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# ranks per channel (DDR) => number of layers
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# banks per rank (DDR) => banks per layer
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# devices per rank (DDR) => devices per layer ( 1 for HMC).
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# The parameters for which no input is available are inherited from the DDR3
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# configuration.
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# This configuration includes the latencies from the DRAM to the logic layer of
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# the HMC
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class HMC_2500_x32(DDR3_1600_x64):
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# size of device
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# two banks per device with each bank 4MB [2]
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device_size = '8MB'
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# 1x32 configuration, 1 device with 32 TSVs [2]
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device_bus_width = 32
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# HMC is a BL8 device [2]
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burst_length = 8
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# Each device has a page (row buffer) size of 256 bytes [2]
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device_rowbuffer_size = '256B'
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# 1x32 configuration, so 1 device [2]
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devices_per_rank = 1
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# 4 layers so 4 ranks [2]
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ranks_per_channel = 4
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# HMC has 2 banks per layer [2]
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# Each layer represents a rank. With 4 layers and 8 banks in total, each
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# layer has 2 banks; thus 2 banks per rank.
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banks_per_rank = 2
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# 1250 MHz [2]
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tCK = '0.8ns'
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# 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz
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tBURST = '3.2ns'
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# Values using DRAMSpec HMC model [1]
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tRCD = '10.2ns'
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tCL = '9.9ns'
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tRP = '7.7ns'
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tRAS = '21.6ns'
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# tRRD depends on the power supply network for each vendor.
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# We assume a tRRD of a double bank approach to be equal to 4 clock
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# cycles (Assumption)
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tRRD = '3.2ns'
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# activation limit is set to 0 since there are only 2 banks per vault layer.
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activation_limit = 0
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# Values using DRAMSpec HMC model [1]
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tRFC = '59ns'
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tWR = '8ns'
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tRTP = '4.9ns'
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# Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz = 0.8
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# ns (Assumption)
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tCS = '0.8ns'
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# Value using DRAMSpec HMC model [1]
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tREFI = '3.9us'
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# Set default controller parameters
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page_policy = 'close'
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write_buffer_size = 8
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read_buffer_size = 8
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addr_mapping = 'RoCoRaBaCh'
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min_writes_per_switch = 8
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# A single DDR3-2133 x64 channel refining a selected subset of the
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# A single DDR3-2133 x64 channel refining a selected subset of the
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# options for the DDR-1600 configuration, based on the same DDR3-1600
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# options for the DDR-1600 configuration, based on the same DDR3-1600
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# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
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# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
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