back out ron's memory system changes because they break dma
--HG-- extra : convert_revision : 3e0af11cd9dc97743f288cee5248fa44013baddd
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2a649076a4
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25890b9404
2 changed files with 8 additions and 56 deletions
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@ -28,10 +28,9 @@
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// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
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// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
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#include <iomanip>
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#include <set>
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#include <sstream>
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#include <string>
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#include <string>
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#include <sstream>
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#include <iomanip>
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#include <vector>
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#include <vector>
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#include "base/misc.hh"
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#include "base/misc.hh"
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@ -45,8 +44,6 @@
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using namespace std;
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using namespace std;
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int TESTER_ALLOCATOR=0;
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MemTest::MemTest(const string &name,
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MemTest::MemTest(const string &name,
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MemInterface *_cache_interface,
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MemInterface *_cache_interface,
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FunctionalMemory *main_mem,
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FunctionalMemory *main_mem,
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@ -114,8 +111,6 @@ MemTest::MemTest(const string &name,
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noResponseCycles = 0;
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noResponseCycles = 0;
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numReads = 0;
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numReads = 0;
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tickEvent.schedule(0);
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tickEvent.schedule(0);
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id = TESTER_ALLOCATOR++;
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}
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}
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static void
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static void
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@ -132,11 +127,6 @@ printData(ostream &os, uint8_t *data, int nbytes)
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void
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void
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MemTest::completeRequest(MemReqPtr &req, uint8_t *data)
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MemTest::completeRequest(MemReqPtr &req, uint8_t *data)
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{
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{
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//Remove the address from the list of outstanding
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std::set<unsigned>::iterator removeAddr = outstandingAddrs.find(req->paddr);
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assert(removeAddr != outstandingAddrs.end());
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outstandingAddrs.erase(removeAddr);
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switch (req->cmd) {
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switch (req->cmd) {
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case Read:
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case Read:
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if (memcmp(req->data, data, req->size) != 0) {
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if (memcmp(req->data, data, req->size) != 0) {
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@ -168,10 +158,6 @@ MemTest::completeRequest(MemReqPtr &req, uint8_t *data)
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break;
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break;
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case Copy:
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case Copy:
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//Also remove dest from outstanding list
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removeAddr = outstandingAddrs.find(req->dest);
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assert(removeAddr != outstandingAddrs.end());
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outstandingAddrs.erase(removeAddr);
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numCopiesStat++;
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numCopiesStat++;
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break;
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break;
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@ -226,7 +212,7 @@ MemTest::tick()
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if (!tickEvent.scheduled())
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if (!tickEvent.scheduled())
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tickEvent.schedule(curTick + 1);
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tickEvent.schedule(curTick + 1);
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if (++noResponseCycles >= 500000) {
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if (++noResponseCycles >= 5000) {
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cerr << name() << ": deadlocked at cycle " << curTick << endl;
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cerr << name() << ": deadlocked at cycle " << curTick << endl;
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fatal("");
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fatal("");
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}
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}
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@ -246,16 +232,6 @@ MemTest::tick()
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unsigned source_align = rand() % 100;
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unsigned source_align = rand() % 100;
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unsigned dest_align = rand() % 100;
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unsigned dest_align = rand() % 100;
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//If we aren't doing copies, use id as offset, and do a false sharing
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//mem tester
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if (percentCopies == 0) {
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//We can eliminate the lower bits of the offset, and then use the id
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//to offset within the blks
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offset1 &= ~63; //Not the low order bits
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offset1 += id;
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access_size = 0;
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}
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MemReqPtr req = new MemReq();
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MemReqPtr req = new MemReq();
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if (cacheable < percentUncacheable) {
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if (cacheable < percentUncacheable) {
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@ -275,13 +251,6 @@ MemTest::tick()
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if (cmd < percentReads) {
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if (cmd < percentReads) {
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// read
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// read
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//For now we only allow one outstanding request per addreess per tester
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//This means we assume CPU does write forwarding to reads that alias something
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//in the cpu store buffer.
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if (outstandingAddrs.find(req->paddr) != outstandingAddrs.end()) return;
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else outstandingAddrs.insert(req->paddr);
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req->cmd = Read;
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req->cmd = Read;
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uint8_t *result = new uint8_t[8];
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uint8_t *result = new uint8_t[8];
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checkMem->access(Read, req->paddr, result, req->size);
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checkMem->access(Read, req->paddr, result, req->size);
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@ -304,13 +273,6 @@ MemTest::tick()
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}
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}
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} else if (cmd < (100 - percentCopies)){
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} else if (cmd < (100 - percentCopies)){
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// write
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// write
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//For now we only allow one outstanding request per addreess per tester
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//This means we assume CPU does write forwarding to reads that alias something
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//in the cpu store buffer.
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if (outstandingAddrs.find(req->paddr) != outstandingAddrs.end()) return;
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else outstandingAddrs.insert(req->paddr);
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req->cmd = Write;
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req->cmd = Write;
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memcpy(req->data, &data, req->size);
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memcpy(req->data, &data, req->size);
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checkMem->access(Write, req->paddr, req->data, req->size);
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checkMem->access(Write, req->paddr, req->data, req->size);
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@ -336,11 +298,6 @@ MemTest::tick()
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// copy
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// copy
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Addr source = ((base) ? baseAddr1 : baseAddr2) + offset1;
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Addr source = ((base) ? baseAddr1 : baseAddr2) + offset1;
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Addr dest = ((base) ? baseAddr2 : baseAddr1) + offset2;
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Addr dest = ((base) ? baseAddr2 : baseAddr1) + offset2;
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if (outstandingAddrs.find(source) != outstandingAddrs.end()) return;
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else outstandingAddrs.insert(source);
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if (outstandingAddrs.find(dest) != outstandingAddrs.end()) return;
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else outstandingAddrs.insert(dest);
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if (source_align >= percentSourceUnaligned) {
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if (source_align >= percentSourceUnaligned) {
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source = blockAddr(source);
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source = blockAddr(source);
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}
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}
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@ -29,14 +29,13 @@
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#ifndef __MEMTEST_HH__
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#ifndef __MEMTEST_HH__
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#define __MEMTEST_HH__
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#define __MEMTEST_HH__
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#include <set>
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#include "sim/sim_object.hh"
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#include "mem/mem_interface.hh"
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#include "base/statistics.hh"
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#include "mem/functional_mem/functional_memory.hh"
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#include "cpu/base_cpu.hh"
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#include "cpu/base_cpu.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/exec_context.hh"
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#include "mem/functional_mem/functional_memory.hh"
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#include "mem/mem_interface.hh"
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#include "base/statistics.hh"
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#include "sim/sim_object.hh"
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#include "sim/stats.hh"
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#include "sim/stats.hh"
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class MemTest : public BaseCPU
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class MemTest : public BaseCPU
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unsigned percentCopies; // target percentage of copy accesses
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unsigned percentCopies; // target percentage of copy accesses
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unsigned percentUncacheable;
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unsigned percentUncacheable;
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int id;
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std::set<unsigned> outstandingAddrs;
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unsigned blockSize;
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unsigned blockSize;
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Addr blockAddrMask;
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Addr blockAddrMask;
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