Registers: Get rid of the float register width parameter.

src/arch/alpha/floatregfile.hh

@@ -42,18 +42,9 @@ class Checkpoint;
 
 namespace AlphaISA {
 
-const int SingleWidth = 32;
-const int SingleBytes = SingleWidth / 4;
-const int DoubleWidth = 64;
-const int DoubleBytes = DoubleWidth / 4;
-const int QuadWidth = 128;
-const int QuadBytes = QuadWidth / 4;
-
 class FloatRegFile
 {
   public:
-    static const int regWidth = DoubleWidth;
-
     union {
         uint64_t q[NumFloatRegs];   // integer qword view
         double d[NumFloatRegs];     // double-precision floating point view
@@ -70,48 +61,24 @@ class FloatRegFile
         return d[floatReg];
     }
 
-    FloatReg
-    readReg(int floatReg, int width)
-    {
-        return readReg(floatReg);
-    }
-
     FloatRegBits
     readRegBits(int floatReg)
     {
         return q[floatReg];
     }
 
-    FloatRegBits
-    readRegBits(int floatReg, int width)
-    {
-        return readRegBits(floatReg);
-    }
-
     void
     setReg(int floatReg, const FloatReg &val)
     {
         d[floatReg] = val;
     }
 
-    void
-    setReg(int floatReg, const FloatReg &val, int width)
-    {
-        setReg(floatReg, val);
-    }
-
     void
     setRegBits(int floatReg, const FloatRegBits &val)
     {
         q[floatReg] = val;
     }
 
-    void
-    setRegBits(int floatReg, const FloatRegBits &val, int width)
-    {
-        setRegBits(floatReg, val);
-    }
-
 };
 
 } // namespace AlphaISA

src/arch/alpha/regfile.hh

@@ -112,48 +112,24 @@ class RegFile {
         return floatRegFile.d[floatReg];
     }
 
-    FloatReg
-    readFloatReg(int floatReg, int width)
-    {
-        return readFloatReg(floatReg);
-    }
-
     FloatRegBits
     readFloatRegBits(int floatReg)
     {
         return floatRegFile.q[floatReg];
     }
 
-    FloatRegBits
-    readFloatRegBits(int floatReg, int width)
-    {
-        return readFloatRegBits(floatReg);
-    }
-
     void
     setFloatReg(int floatReg, const FloatReg &val)
     {
         floatRegFile.d[floatReg] = val;
     }
 
-    void
-    setFloatReg(int floatReg, const FloatReg &val, int width)
-    {
-        setFloatReg(floatReg, val);
-    }
-
     void
     setFloatRegBits(int floatReg, const FloatRegBits &val)
     {
         floatRegFile.q[floatReg] = val;
     }
 
-    void
-    setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
-    {
-        setFloatRegBits(floatReg, val);
-    }
-
     IntReg
     readIntReg(int intReg)
     {

src/arch/arm/regfile/float_regfile.hh

@@ -75,21 +75,12 @@ namespace ArmISA
         Cause_Field = 11
     };
 
-    const int SingleWidth = 32;
-    const int SingleBytes = SingleWidth / 4;
-
-    const int DoubleWidth = 64;
-    const int DoubleBytes = DoubleWidth / 4;
-
-    const int QuadWidth = 128;
-    const int QuadBytes = QuadWidth / 4;
-
     class FloatRegFile
     {
       protected:
           union {
             FloatRegBits qregs[NumFloatRegs];
-            FloatRegVal regs[NumFloatRegs];
+            FloatReg regs[NumFloatRegs];
           };
 
       public:
@@ -107,38 +98,17 @@ namespace ArmISA
             regs[15] = 10.0;
         }
 
-        FloatRegVal readReg(int floatReg, int width)
+        FloatReg readReg(int floatReg)
         {
             return regs[floatReg];
         }
 
-        FloatRegBits readRegBits(int floatReg, int width)
+        FloatRegBits readRegBits(int floatReg)
         {
-            //return qregs[floatReg];
+            return qregs[floatReg];
-            switch(width)
-            {
-                case SingleWidth:
-                {
-                    union {
-                        float f;
-                        uint32_t i;
-                    } s;
-                    s.f = (float) regs[floatReg];
-                    return s.i;
-                }
-                case DoubleWidth:
-                {
-                    uint64_t tmp = (qregs[floatReg]<<32|qregs[floatReg]>>32);
-                    return tmp;
-                }
-                default:
-                    panic("Attempted to read a %d bit floating point "
-                        "register!", width);
-
-            }
         }
 
-        Fault setReg(int floatReg, const FloatRegVal &val, int width)
+        Fault setReg(int floatReg, const FloatReg &val)
         {
             if (floatReg > 7)
                 panic("Writing to a hard-wired FP register");
@@ -146,23 +116,12 @@ namespace ArmISA
             return NoFault;
         }
 
-        Fault setRegBits(int floatReg, const FloatRegBits &val, int width)
+        Fault setRegBits(int floatReg, const FloatRegBits &val)
         {
             if (floatReg > 7)
                 panic("Writing to a hard-wired FP register");
-            switch(width)
+            qregs[floatReg] = val;
-            {
+            return NoFault;
-                case DoubleWidth:
-                {
-                    uint64_t tmp = (val << 32 | val >> 32);
-                    qregs[floatReg] = tmp;
-                    return NoFault;
-                }
-                case SingleWidth:
-                default:
-                    panic("Attempted to write a %d bit floating point "
-                        "register!", width);
-            }
         }
 
         void serialize(std::ostream &os)

src/arch/arm/regfile/regfile.hh

@@ -57,44 +57,24 @@ namespace ArmISA
             floatRegFile.clear();
         }
 
-        FloatRegVal readFloatReg(int floatReg)
+        FloatReg readFloatReg(int floatReg)
         {
-            return floatRegFile.readReg(floatReg,SingleWidth);
+            return floatRegFile.readReg(floatReg);
-        }
-
-        FloatRegVal readFloatReg(int floatReg, int width)
-        {
-            return floatRegFile.readReg(floatReg,width);
         }
 
         FloatRegBits readFloatRegBits(int floatReg)
         {
-            return floatRegFile.readRegBits(floatReg,SingleWidth);
+            return floatRegFile.readRegBits(floatReg);
         }
 
-        FloatRegBits readFloatRegBits(int floatReg, int width)
+        void setFloatReg(int floatReg, const FloatReg &val)
         {
-            return floatRegFile.readRegBits(floatReg,width);
+            floatRegFile.setReg(floatReg, val);
-        }
-
-        void setFloatReg(int floatReg, const FloatRegVal &val)
-        {
-            floatRegFile.setReg(floatReg, val, SingleWidth);
-        }
-
-        void setFloatReg(int floatReg, const FloatRegVal &val, int width)
-        {
-            floatRegFile.setReg(floatReg, val, width);
         }
 
         void setFloatRegBits(int floatReg, const FloatRegBits &val)
         {
-            floatRegFile.setRegBits(floatReg, val, SingleWidth);
+            floatRegFile.setRegBits(floatReg, val);
-        }
-
-        void setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
-        {
-            floatRegFile.setRegBits(floatReg, val, width);
         }
 
         IntReg readIntReg(int intReg)

src/arch/arm/types.hh

@@ -120,12 +120,8 @@ namespace ArmISA
     // Need to use 64 bits to make sure that read requests get handled properly
 
     // floating point register file entry type
-    typedef uint32_t FloatReg32;
+    typedef uint32_t FloatRegBits;
-    typedef uint64_t FloatReg64;
+    typedef float FloatReg;
-    typedef uint64_t FloatRegBits;
-
-    typedef double FloatRegVal;
-    typedef double FloatReg;
 
     // cop-0/cop-1 system control register
     typedef uint64_t MiscReg;

src/arch/isa_parser.py

@@ -1173,10 +1173,9 @@ def buildOperandTypeMap(userDict, lineno):
 # (e.g., "32-bit integer register").
 #
 class Operand(object):
-    def buildReadCode(self, func = None, width = None):
+    def buildReadCode(self, func = None):
         code = self.read_code % {"name": self.base_name,
                                  "func": func,
-                                 "width": width,
                                  "op_idx": self.src_reg_idx,
                                  "reg_idx": self.reg_spec,
                                  "size": self.size,
@@ -1188,14 +1187,13 @@ class Operand(object):
             return '%s = %s;\n' % \
                    (self.base_name, code)
 
-    def buildWriteCode(self, func = None, width = None):
+    def buildWriteCode(self, func = None):
         if (self.size != self.dflt_size and self.is_signed):
             final_val = 'sext<%d>(%s)' % (self.size, self.base_name)
         else:
             final_val = self.base_name
         code = self.write_code % {"name": self.base_name,
                                   "func": func,
-                                  "width": width,
                                   "op_idx": self.dest_reg_idx,
                                   "reg_idx": self.reg_spec,
                                   "size": self.size,
@@ -1358,29 +1356,15 @@ class FloatRegOperand(Operand):
 
     def makeRead(self):
         bit_select = 0
-        width = 0;
+        if (self.ctype == 'float' or self.ctype == 'double'):
-        if (self.ctype == 'float'):
             func = 'readFloatRegOperand'
-            width = 32;
-        elif (self.ctype == 'double'):
-            func = 'readFloatRegOperand'
-            width = 64;
         else:
             func = 'readFloatRegOperandBits'
-            if (self.ctype == 'uint32_t'):
-                width = 32;
-            elif (self.ctype == 'uint64_t'):
-                width = 64;
             if (self.size != self.dflt_size):
                 bit_select = 1
-        if width:
+        base = 'xc->%s(this, %d)' % (func, self.src_reg_idx)
-            base = 'xc->%s(this, %d, %d)' % \
-                   (func, self.src_reg_idx, width)
-        else:
-            base = 'xc->%s(this, %d)' % \
-                   (func, self.src_reg_idx)
         if self.read_code != None:
-            return self.buildReadCode(func, width)
+            return self.buildReadCode(func)
         if bit_select:
             return '%s = bits(%s, %d, 0);\n' % \
                    (self.base_name, base, self.size-1)
@@ -1390,36 +1374,23 @@ class FloatRegOperand(Operand):
     def makeWrite(self):
         final_val = self.base_name
         final_ctype = self.ctype
-        widthSpecifier = ''
+        if (self.ctype == 'float' or self.ctype == 'double'):
-        width = 0
-        if (self.ctype == 'float'):
-            width = 32
             func = 'setFloatRegOperand'
-        elif (self.ctype == 'double'):
+        elif (self.ctype == 'uint32_t' or self.ctype == 'uint64_t'):
-            width = 64
-            func = 'setFloatRegOperand'
-        elif (self.ctype == 'uint32_t'):
             func = 'setFloatRegOperandBits'
-            width = 32
-        elif (self.ctype == 'uint64_t'):
-            func = 'setFloatRegOperandBits'
-            width = 64
         else:
             func = 'setFloatRegOperandBits'
             final_ctype = 'uint%d_t' % self.dflt_size
             if (self.size != self.dflt_size and self.is_signed):
                 final_val = 'sext<%d>(%s)' % (self.size, self.base_name)
         if self.write_code != None:
-            return self.buildWriteCode(func, width)
+            return self.buildWriteCode(func)
-        if width:
-            widthSpecifier = ', %d' % width
         wb = '''
         {
             %s final_val = %s;
-            xc->%s(this, %d, final_val%s);\n
+            xc->%s(this, %d, final_val);\n
             if (traceData) { traceData->setData(final_val); }
-        }''' % (final_ctype, final_val, func, self.dest_reg_idx,
+        }''' % (final_ctype, final_val, func, self.dest_reg_idx)
-                widthSpecifier)
         return wb
 
 class ControlRegOperand(Operand):

src/arch/mips/isa/formats/fp.isa

@@ -104,25 +104,14 @@ output exec {{
                       Trace::InstRecord *traceData)
         {
             uint64_t mips_nan = 0;
-            T src_op = 0;
+            assert(sizeof(T) == 4);
-            int size = sizeof(src_op) * 8;
 
             for (int i = 0; i < inst->numSrcRegs(); i++) {
-                uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0, size);
+                uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0);
 
-                if (isNan(&src_bits, size) ) {
+                if (isNan(&src_bits, 32) ) {
-                    if (isSnan(&src_bits, size)) {
+                    mips_nan = MIPS32_QNAN;
-                        switch (size)
+                    xc->setFloatRegOperandBits(inst, 0, mips_nan);
-                        {
-                          case 32: mips_nan = MIPS32_QNAN; break;
-                          case 64: mips_nan = MIPS64_QNAN; break;
-                          default: panic("Unsupported Floating Point Size (%d)", size);
-                        }
-                    } else {
-                        mips_nan = src_bits;
-                    }
-
-                    xc->setFloatRegOperandBits(inst, 0, mips_nan, size);
                     if (traceData) { traceData->setData(mips_nan); }
                     return true;
                 }
@@ -137,18 +126,13 @@ output exec {{
         {
             uint64_t mips_nan = 0;
             T src_op = dest_val;
-            int size = sizeof(src_op) * 8;
+            assert(sizeof(T) == 4);
 
-            if (isNan(&src_op, size)) {
+            if (isNan(&src_op, 32)) {
-                switch (size)
+                mips_nan = MIPS32_QNAN;
-                {
-                  case 32: mips_nan = MIPS32_QNAN; break;
-                  case 64: mips_nan = MIPS64_QNAN; break;
-                  default: panic("Unsupported Floating Point Size (%d)", size);
-                }
 
                 //Set value to QNAN
-                cpu->setFloatRegOperandBits(inst, 0, mips_nan, size);
+                cpu->setFloatRegOperandBits(inst, 0, mips_nan);
 
                 //Read FCSR from FloatRegFile
                 uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);

src/arch/mips/regfile.cc

@@ -100,42 +100,22 @@ RegFile::setMiscReg(int miscReg, const MiscReg &val,
 
 FloatRegVal RegFile::readFloatReg(int floatReg)
 {
-    return floatRegFile.readReg(floatReg,SingleWidth);
+    return floatRegFile.readReg(floatReg);
-}
-
-FloatRegVal RegFile::readFloatReg(int floatReg, int width)
-{
-    return floatRegFile.readReg(floatReg,width);
 }
 
 FloatRegBits RegFile::readFloatRegBits(int floatReg)
 {
-    return floatRegFile.readRegBits(floatReg,SingleWidth);
+    return floatRegFile.readRegBits(floatReg);
-}
-
-FloatRegBits RegFile::readFloatRegBits(int floatReg, int width)
-{
-    return floatRegFile.readRegBits(floatReg,width);
 }
 
 Fault RegFile::setFloatReg(int floatReg, const FloatRegVal &val)
 {
-    return floatRegFile.setReg(floatReg, val, SingleWidth);
+    return floatRegFile.setReg(floatReg, val);
-}
-
-Fault RegFile::setFloatReg(int floatReg, const FloatRegVal &val, int width)
-{
-    return floatRegFile.setReg(floatReg, val, width);
 }
 
 Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
 {
-    return floatRegFile.setRegBits(floatReg, val, SingleWidth);
+    return floatRegFile.setRegBits(floatReg, val);
-}
-
-Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
-{
-    return floatRegFile.setRegBits(floatReg, val, width);
 }
 
 Addr RegFile::readPC()

src/arch/mips/regfile/float_regfile.cc

@@ -38,114 +38,43 @@ using namespace std;
 void
 FloatRegFile::clear()
 {
-    bzero(&regs, sizeof(regs));
+    bzero(regs.q, sizeof(regs.q));
 }
 
-double
+FloatReg
-FloatRegFile::readReg(int floatReg, int width, ThreadID tid)
+FloatRegFile::readReg(int floatReg)
 {
-    switch(width)
+    return regs.s[floatReg];
-    {
-      case SingleWidth:
-        {
-            void *float_ptr = &regs[floatReg];
-            return *(float *) float_ptr;
-        }
-
-      case DoubleWidth:
-        {
-            uint64_t double_val = (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg];
-            void *double_ptr = &double_val;
-            return *(double *) double_ptr;
-        }
-
-      default:
-        panic("Attempted to read a %d bit floating point register!", width);
-    }
 }
 
 FloatRegBits
-FloatRegFile::readRegBits(int floatReg, int width, ThreadID tid)
+FloatRegFile::readRegBits(int floatReg)
 {
-    if (floatReg < NumFloatArchRegs - 1) {
+    return regs.q[floatReg];
-        switch(width)
-        {
-          case SingleWidth:
-            return regs[floatReg];
-
-          case DoubleWidth:
-            return (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg];
-
-          default:
-            panic("Attempted to read a %d bit floating point register!", width);
-        }
-    } else {
-        if (width > SingleWidth)
-            assert("Control Regs are only 32 bits wide");
-
-        return regs[floatReg];
-    }
 }
 
 Fault
-FloatRegFile::setReg(int floatReg, const FloatRegVal &val, int width,
+FloatRegFile::setReg(int floatReg, const FloatReg &val)
-                     ThreadID tid)
 {
-    switch(width)
+    regs.s[floatReg] = val;
-    {
-      case SingleWidth:
-        {
-            float temp = val;
-            void *float_ptr = &temp;
-            regs[floatReg] = *(FloatReg32 *) float_ptr;
-            break;
-        }
-
-      case DoubleWidth:
-        {
-            const void *double_ptr = &val;
-            FloatReg64 temp_double = *(FloatReg64 *) double_ptr;
-            regs[floatReg + 1] = bits(temp_double, 63, 32);
-            regs[floatReg] = bits(temp_double, 31, 0);
-            break;
-        }
-
-      default:
-        panic("Attempted to read a %d bit floating point register!", width);
-    }
-
     return NoFault;
 }
 
 Fault
-FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width,
+FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val)
-                         ThreadID tid)
 {
-    switch(width)
+    regs.q[floatReg] = val;
-    {
-      case SingleWidth:
-        regs[floatReg] = val;
-        break;
-
-      case DoubleWidth:
-        regs[floatReg + 1] = bits(val, 63, 32);
-        regs[floatReg] = bits(val, 31, 0);
-        break;
-
-      default:
-        panic("Attempted to read a %d bit floating point register!", width);
-    }
     return NoFault;
 }
 
 void
 FloatRegFile::serialize(std::ostream &os)
 {
-    SERIALIZE_ARRAY(regs, NumFloatRegs);
+    SERIALIZE_ARRAY(regs.q, NumFloatRegs);
 }
 
 void
 FloatRegFile::unserialize(Checkpoint *cp, const std::string &section)
 {
-    UNSERIALIZE_ARRAY(regs, NumFloatRegs);
+    UNSERIALIZE_ARRAY(regs.q, NumFloatRegs);
 }

src/arch/mips/regfile/float_regfile.hh

@@ -70,30 +70,20 @@ namespace MipsISA
         Cause_Field = 11
     };
 
-    const int SingleWidth = 32;
-    const int SingleBytes = SingleWidth / 4;
-
-    const int DoubleWidth = 64;
-    const int DoubleBytes = DoubleWidth / 4;
-
-    const int QuadWidth = 128;
-    const int QuadBytes = QuadWidth / 4;
-
     class FloatRegFile
     {
       protected:
-        FloatReg32 regs[NumFloatRegs];
+        union {
+            FloatReg s[NumFloatRegs];
+            FloatRegBits q[NumFloatRegs];
+        } regs;
 
       public:
-        static const int regWidth = SingleWidth;
-
         void clear();
-        double readReg(int floatReg, int width, ThreadID tid = 0);
+        FloatReg readReg(int floatReg);
-        FloatRegBits readRegBits(int floatReg, int width, ThreadID tid = 0);
+        FloatRegBits readRegBits(int floatReg);
-        Fault setReg(int floatReg, const FloatRegVal &val, int width,
+        Fault setReg(int floatReg, const FloatReg &val);
-                     ThreadID tid = 0);
+        Fault setRegBits(int floatReg, const FloatRegBits &val);
-        Fault setRegBits(int floatReg, const FloatRegBits &val, int width,
-                         ThreadID tid = 0);
 
         void serialize(std::ostream &os);
         void unserialize(Checkpoint *cp, const std::string &section);

src/arch/mips/regfile/regfile.cc

@@ -64,52 +64,28 @@ RegFile::setIntReg(int intReg, const IntReg &val)
     return intRegFile.setReg(intReg, val);
 }
 
-FloatRegVal
+FloatReg
 RegFile::readFloatReg(int floatReg)
 {
-    return floatRegFile.readReg(floatReg,SingleWidth);
+    return floatRegFile.readReg(floatReg);
-}
-
-FloatRegVal
-RegFile::readFloatReg(int floatReg, int width)
-{
-    return floatRegFile.readReg(floatReg,width);
 }
 
 FloatRegBits
 RegFile::readFloatRegBits(int floatReg)
 {
-    return floatRegFile.readRegBits(floatReg,SingleWidth);
+    return floatRegFile.readRegBits(floatReg);
-}
-
-FloatRegBits
-RegFile::readFloatRegBits(int floatReg, int width)
-{
-    return floatRegFile.readRegBits(floatReg,width);
 }
 
 Fault
-RegFile::setFloatReg(int floatReg, const FloatRegVal &val)
+RegFile::setFloatReg(int floatReg, const FloatReg &val)
 {
-    return floatRegFile.setReg(floatReg, val, SingleWidth);
+    return floatRegFile.setReg(floatReg, val);
-}
-
-Fault
-RegFile::setFloatReg(int floatReg, const FloatRegVal &val, int width)
-{
-    return floatRegFile.setReg(floatReg, val, width);
 }
 
 Fault
 RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
 {
-    return floatRegFile.setRegBits(floatReg, val, SingleWidth);
+    return floatRegFile.setRegBits(floatReg, val);
-}
-
-Fault
-RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
-{
-    return floatRegFile.setRegBits(floatReg, val, width);
 }
 
 void

src/arch/mips/regfile/regfile.hh

@@ -66,14 +66,10 @@ namespace MipsISA
         Fault setIntReg(int intReg, const IntReg &val);
 
 
-        FloatRegVal readFloatReg(int floatReg);
+        FloatReg readFloatReg(int floatReg);
-        FloatRegVal readFloatReg(int floatReg, int width);
         FloatRegBits readFloatRegBits(int floatReg);
-        FloatRegBits readFloatRegBits(int floatReg, int width);
+        Fault setFloatReg(int floatReg, const FloatReg &val);
-        Fault setFloatReg(int floatReg, const FloatRegVal &val);
-        Fault setFloatReg(int floatReg, const FloatRegVal &val, int width);
         Fault setFloatRegBits(int floatReg, const FloatRegBits &val);
-        Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width);
 
 
         void setShadowSet(int css);

src/arch/mips/types.hh

@@ -44,12 +44,8 @@ namespace MipsISA
 
 
     // floating point register file entry type
-    typedef uint32_t FloatReg32;
+    typedef uint32_t FloatRegBits;
-    typedef uint64_t FloatReg64;
+    typedef float FloatReg;
-    typedef uint64_t FloatRegBits;
-
-    typedef double FloatRegVal;
-    typedef double FloatReg;
 
     // cop-0/cop-1 system control register
     typedef uint64_t MiscReg;

src/arch/sparc/floatregfile.cc

@@ -43,155 +43,38 @@ class Checkpoint;
 
 void FloatRegFile::clear()
 {
-    memset(regSpace, 0, sizeof(regSpace));
+    memset(regs.q, 0, sizeof(regs.q));
 }
 
-FloatReg FloatRegFile::readReg(int floatReg, int width)
+FloatReg FloatRegFile::readReg(int floatReg)
 {
-    //In each of these cases, we have to copy the value into a temporary
+    return regs.s[floatReg];
-    //variable. This is because we may otherwise try to access an
-    //unaligned portion of memory.
-    FloatReg result;
-    switch(width)
-    {
-      case SingleWidth:
-        uint32_t result32;
-        float32_t fresult32;
-        memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32));
-        result32 = htog(result32);
-        memcpy(&fresult32, &result32, sizeof(result32));
-        result = fresult32;
-        DPRINTF(FloatRegs, "Read FP32 register %d = [%f]0x%x\n",
-                floatReg, result, result32);
-        break;
-      case DoubleWidth:
-        uint64_t result64;
-        float64_t fresult64;
-        memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64));
-        result64 = htog(result64);
-        memcpy(&fresult64, &result64, sizeof(result64));
-        result = fresult64;
-        DPRINTF(FloatRegs, "Read FP64 register %d = [%f]0x%x\n",
-                floatReg, result, result64);
-        break;
-      case QuadWidth:
-        panic("Quad width FP not implemented.");
-        break;
-      default:
-        panic("Attempted to read a %d bit floating point register!", width);
-    }
-    return result;
 }
 
-FloatRegBits FloatRegFile::readRegBits(int floatReg, int width)
+FloatRegBits FloatRegFile::readRegBits(int floatReg)
 {
-    //In each of these cases, we have to copy the value into a temporary
+    return regs.q[floatReg];
-    //variable. This is because we may otherwise try to access an
-    //unaligned portion of memory.
-    FloatRegBits result;
-    switch(width)
-    {
-      case SingleWidth:
-        uint32_t result32;
-        memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32));
-        result = htog(result32);
-        DPRINTF(FloatRegs, "Read FP32 bits register %d = 0x%x\n",
-                floatReg, result);
-        break;
-      case DoubleWidth:
-        uint64_t result64;
-        memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64));
-        result = htog(result64);
-        DPRINTF(FloatRegs, "Read FP64 bits register %d = 0x%x\n",
-                floatReg, result);
-        break;
-      case QuadWidth:
-        panic("Quad width FP not implemented.");
-        break;
-      default:
-        panic("Attempted to read a %d bit floating point register!", width);
-    }
-    return result;
 }
 
-Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width)
+Fault FloatRegFile::setReg(int floatReg, const FloatReg &val)
 {
-    //In each of these cases, we have to copy the value into a temporary
+    regs.s[floatReg] = val;
-    //variable. This is because we may otherwise try to access an
-    //unaligned portion of memory.
-
-    uint32_t result32;
-    uint64_t result64;
-    float32_t fresult32;
-    float64_t fresult64;
-    switch(width)
-    {
-      case SingleWidth:
-        fresult32 = val;
-        memcpy(&result32, &fresult32, sizeof(result32));
-        result32 = gtoh(result32);
-        memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32));
-        DPRINTF(FloatRegs, "Write FP64 register %d = 0x%x\n",
-                floatReg, result32);
-        break;
-      case DoubleWidth:
-        fresult64 = val;
-        memcpy(&result64, &fresult64, sizeof(result64));
-        result64 = gtoh(result64);
-        memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64));
-        DPRINTF(FloatRegs, "Write FP64 register %d = 0x%x\n",
-                floatReg, result64);
-        break;
-      case QuadWidth:
-        panic("Quad width FP not implemented.");
-        break;
-      default:
-        panic("Attempted to read a %d bit floating point register!", width);
-    }
     return NoFault;
 }
 
-Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width)
+Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val)
 {
-    //In each of these cases, we have to copy the value into a temporary
+    regs.q[floatReg] = val;
-    //variable. This is because we may otherwise try to access an
-    //unaligned portion of memory.
-    uint32_t result32;
-    uint64_t result64;
-    switch(width)
-    {
-      case SingleWidth:
-        result32 = gtoh((uint32_t)val);
-        memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32));
-        DPRINTF(FloatRegs, "Write FP64 bits register %d = 0x%x\n",
-                floatReg, result32);
-        break;
-      case DoubleWidth:
-        result64 = gtoh((uint64_t)val);
-        memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64));
-        DPRINTF(FloatRegs, "Write FP64 bits register %d = 0x%x\n",
-                floatReg, result64);
-        break;
-      case QuadWidth:
-        panic("Quad width FP not implemented.");
-        break;
-      default:
-        panic("Attempted to read a %d bit floating point register!", width);
-    }
     return NoFault;
 }
 
 void FloatRegFile::serialize(std::ostream &os)
 {
-    uint8_t *float_reg = (uint8_t*)regSpace;
+    SERIALIZE_ARRAY(regs.q, NumFloatRegs);
-    SERIALIZE_ARRAY(float_reg,
-            SingleWidth / 8 * NumFloatRegs);
 }
 
 void FloatRegFile::unserialize(Checkpoint *cp, const std::string &section)
 {
-    uint8_t *float_reg = (uint8_t*)regSpace;
+    UNSERIALIZE_ARRAY(regs.q, NumFloatRegs);
-    UNSERIALIZE_ARRAY(float_reg,
-            SingleWidth / 8 * NumFloatRegs);
 }
 

src/arch/sparc/floatregfile.hh

@@ -45,37 +45,25 @@ namespace SparcISA
     const int NumFloatArchRegs = 64;
     const int NumFloatRegs = 64;
 
-    typedef float float32_t;
-    typedef double float64_t;
-    //FIXME long double refers to a 10 byte float, rather than a
-    //16 byte float as required. This data type may have to be emulated.
-    typedef double float128_t;
-
     class FloatRegFile
     {
-      public:
-        static const int SingleWidth = 32;
-        static const int DoubleWidth = 64;
-        static const int QuadWidth = 128;
-
       protected:
-
+        union {
-        //Since the floating point registers overlap each other,
+            uint32_t q[NumFloatRegs];
-        //A generic storage space is used. The float to be returned is
+            float s[NumFloatRegs];
-        //pulled from the appropriate section of this region.
+        } regs;
-        char regSpace[(SingleWidth / 8) * NumFloatRegs];
 
       public:
 
         void clear();
 
-        FloatReg readReg(int floatReg, int width);
+        FloatReg readReg(int floatReg);
 
-        FloatRegBits readRegBits(int floatReg, int width);
+        FloatRegBits readRegBits(int floatReg);
 
-        Fault setReg(int floatReg, const FloatReg &val, int width);
+        Fault setReg(int floatReg, const FloatReg &val);
 
-        Fault setRegBits(int floatReg, const FloatRegBits &val, int width);
+        Fault setRegBits(int floatReg, const FloatRegBits &val);
 
         void serialize(std::ostream &os);
 

src/arch/sparc/regfile.cc

@@ -74,49 +74,24 @@ void RegFile::clear()
     intRegFile.clear();
 }
 
-FloatReg RegFile::readFloatReg(int floatReg, int width)
-{
-    return floatRegFile.readReg(floatReg, width);
-}
-
 FloatReg RegFile::readFloatReg(int floatReg)
 {
-    //Use the "natural" width of a single float
+    return floatRegFile.readReg(floatReg);
-    return floatRegFile.readReg(floatReg, FloatRegFile::SingleWidth);
-}
-
-FloatRegBits RegFile::readFloatRegBits(int floatReg, int width)
-{
-    return floatRegFile.readRegBits(floatReg, width);
 }
 
 FloatRegBits RegFile::readFloatRegBits(int floatReg)
 {
-    //Use the "natural" width of a single float
+    return floatRegFile.readRegBits(floatReg);
-    return floatRegFile.readRegBits(floatReg,
-            FloatRegFile::SingleWidth);
-}
-
-void RegFile::setFloatReg(int floatReg, const FloatReg &val, int width)
-{
-    floatRegFile.setReg(floatReg, val, width);
 }
 
 void RegFile::setFloatReg(int floatReg, const FloatReg &val)
 {
-    //Use the "natural" width of a single float
+    floatRegFile.setReg(floatReg, val);
-    setFloatReg(floatReg, val, FloatRegFile::SingleWidth);
-}
-
-void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
-{
-    floatRegFile.setRegBits(floatReg, val, width);
 }
 
 void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
 {
-    //Use the "natural" width of a single float
+    floatRegFile.setRegBits(floatReg, val);
-    floatRegFile.setRegBits(floatReg, val, FloatRegFile::SingleWidth);
 }
 
 IntReg RegFile::readIntReg(int intReg)

src/arch/sparc/regfile.hh

@@ -70,20 +70,12 @@ namespace SparcISA
 
         void clear();
 
-        FloatReg readFloatReg(int floatReg, int width);
-
         FloatReg readFloatReg(int floatReg);
 
-        FloatRegBits readFloatRegBits(int floatReg, int width);
-
         FloatRegBits readFloatRegBits(int floatReg);
 
-        void setFloatReg(int floatReg, const FloatReg &val, int width);
-
         void setFloatReg(int floatReg, const FloatReg &val);
 
-        void setFloatRegBits(int floatReg, const FloatRegBits &val, int width);
-
         void setFloatRegBits(int floatReg, const FloatRegBits &val);
 
         IntReg readIntReg(int intReg);

src/arch/sparc/types.hh

@@ -42,8 +42,8 @@ namespace SparcISA
     typedef uint64_t IntReg;
     typedef Twin64_t LargestRead;
     typedef uint64_t MiscReg;
-    typedef double FloatReg;
+    typedef float FloatReg;
-    typedef uint64_t FloatRegBits;
+    typedef uint32_t FloatRegBits;
     typedef union
     {
         IntReg intReg;

src/arch/x86/floatregfile.cc

@@ -101,28 +101,28 @@ void FloatRegFile::clear()
     memset(q, 0, sizeof(FloatReg) * NumFloatRegs);
 }
 
-FloatReg FloatRegFile::readReg(int floatReg, int width)
+FloatReg FloatRegFile::readReg(int floatReg)
 {
     FloatReg reg = d[floatReg];
     DPRINTF(FloatRegs, "Reading %f from register %d.\n", reg, floatReg);
     return reg;
 }
 
-FloatRegBits FloatRegFile::readRegBits(int floatReg, int width)
+FloatRegBits FloatRegFile::readRegBits(int floatReg)
 {
     FloatRegBits reg = q[floatReg];
     DPRINTF(FloatRegs, "Reading %#x from register %d.\n", reg, floatReg);
     return reg;
 }
 
-Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width)
+Fault FloatRegFile::setReg(int floatReg, const FloatReg &val)
 {
     DPRINTF(FloatRegs, "Writing %f to register %d.\n", val, floatReg);
     d[floatReg] = val;
     return NoFault;
 }
 
-Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width)
+Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val)
 {
     DPRINTF(FloatRegs, "Writing bits %#x to register %d.\n", val, floatReg);
     q[floatReg] = val;

src/arch/x86/floatregfile.hh

@@ -105,29 +105,23 @@ namespace X86ISA
 
     class FloatRegFile
     {
-      public:
-        static const int SingleWidth = 32;
-        static const int DoubleWidth = 64;
-        static const int QuadWidth = 128;
-
       protected:
         union
         {
             uint64_t q[NumFloatRegs];
             double d[NumFloatRegs];
-            float f[NumFloatRegs][2];
         };
 
       public:
         void clear();
 
-        FloatReg readReg(int floatReg, int width);
+        FloatReg readReg(int floatReg);
 
-        FloatRegBits readRegBits(int floatReg, int width);
+        FloatRegBits readRegBits(int floatReg);
 
-        Fault setReg(int floatReg, const FloatReg &val, int width);
+        Fault setReg(int floatReg, const FloatReg &val);
 
-        Fault setRegBits(int floatReg, const FloatRegBits &val, int width);
+        Fault setRegBits(int floatReg, const FloatRegBits &val);
 
         void serialize(std::ostream &os);
 

src/arch/x86/regfile.cc

@@ -133,49 +133,24 @@ void RegFile::clear()
     intRegFile.clear();
 }
 
-FloatReg RegFile::readFloatReg(int floatReg, int width)
-{
-    return floatRegFile.readReg(floatReg, width);
-}
-
 FloatReg RegFile::readFloatReg(int floatReg)
 {
-    //Use the "natural" width of a single float
+    return floatRegFile.readReg(floatReg);
-    return floatRegFile.readReg(floatReg, FloatRegFile::SingleWidth);
-}
-
-FloatRegBits RegFile::readFloatRegBits(int floatReg, int width)
-{
-    return floatRegFile.readRegBits(floatReg, width);
 }
 
 FloatRegBits RegFile::readFloatRegBits(int floatReg)
 {
-    //Use the "natural width of a single float
+    return floatRegFile.readRegBits(floatReg);
-    return floatRegFile.readRegBits(floatReg,
-            FloatRegFile::SingleWidth);
-}
-
-void RegFile::setFloatReg(int floatReg, const FloatReg &val, int width)
-{
-    floatRegFile.setReg(floatReg, val, width);
 }
 
 void RegFile::setFloatReg(int floatReg, const FloatReg &val)
 {
-    //Use the "natural" width of a single float
+    floatRegFile.setReg(floatReg, val);
-    setFloatReg(floatReg, val, FloatRegFile::SingleWidth);
-}
-
-void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
-{
-    floatRegFile.setRegBits(floatReg, val, width);
 }
 
 void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
 {
-    //Use the "natural" width of a single float
+    floatRegFile.setRegBits(floatReg, val);
-    floatRegFile.setRegBits(floatReg, val, FloatRegFile::SingleWidth);
 }
 
 IntReg RegFile::readIntReg(int intReg)

src/arch/x86/regfile.hh

@@ -99,20 +99,12 @@ namespace X86ISA
 
         void clear();
 
-        FloatReg readFloatReg(int floatReg, int width);
-
         FloatReg readFloatReg(int floatReg);
 
-        FloatRegBits readFloatRegBits(int floatReg, int width);
-
         FloatRegBits readFloatRegBits(int floatReg);
 
-        void setFloatReg(int floatReg, const FloatReg &val, int width);
-
         void setFloatReg(int floatReg, const FloatReg &val);
 
-        void setFloatRegBits(int floatReg, const FloatRegBits &val, int width);
-
         void setFloatRegBits(int floatReg, const FloatRegBits &val);
 
         IntReg readIntReg(int intReg);

src/cpu/checker/cpu.hh

@@ -211,25 +211,12 @@ class CheckerCPU : public BaseCPU
         return thread->readIntReg(si->srcRegIdx(idx));
     }
 
-    FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
-    {
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
-        return thread->readFloatReg(reg_idx, width);
-    }
-
     FloatReg readFloatRegOperand(const StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return thread->readFloatReg(reg_idx);
     }
 
-    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
-                                         int width)
-    {
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
-        return thread->readFloatRegBits(reg_idx, width);
-    }
-
     FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
@@ -242,21 +229,6 @@ class CheckerCPU : public BaseCPU
         result.integer = val;
     }
 
-    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
-                            int width)
-    {
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
-        thread->setFloatReg(reg_idx, val, width);
-        switch(width) {
-          case 32:
-            result.dbl = (double)val;
-            break;
-          case 64:
-            result.dbl = val;
-            break;
-        };
-    }
-
     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
@@ -264,14 +236,6 @@ class CheckerCPU : public BaseCPU
         result.dbl = (double)val;
     }
 
-    void setFloatRegOperandBits(const StaticInst *si, int idx,
-                                FloatRegBits val, int width)
-    {
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
-        thread->setFloatRegBits(reg_idx, val, width);
-        result.integer = val;
-    }
-
     void setFloatRegOperandBits(const StaticInst *si, int idx,
                                 FloatRegBits val)
     {

src/cpu/checker/thread_context.hh

@@ -174,15 +174,9 @@ class CheckerThreadContext : public ThreadContext
     uint64_t readIntReg(int reg_idx)
     { return actualTC->readIntReg(reg_idx); }
 
-    FloatReg readFloatReg(int reg_idx, int width)
-    { return actualTC->readFloatReg(reg_idx, width); }
-
     FloatReg readFloatReg(int reg_idx)
     { return actualTC->readFloatReg(reg_idx); }
 
-    FloatRegBits readFloatRegBits(int reg_idx, int width)
-    { return actualTC->readFloatRegBits(reg_idx, width); }
-
     FloatRegBits readFloatRegBits(int reg_idx)
     { return actualTC->readFloatRegBits(reg_idx); }
 
@@ -192,24 +186,12 @@ class CheckerThreadContext : public ThreadContext
         checkerTC->setIntReg(reg_idx, val);
     }
 
-    void setFloatReg(int reg_idx, FloatReg val, int width)
-    {
-        actualTC->setFloatReg(reg_idx, val, width);
-        checkerTC->setFloatReg(reg_idx, val, width);
-    }
-
     void setFloatReg(int reg_idx, FloatReg val)
     {
         actualTC->setFloatReg(reg_idx, val);
         checkerTC->setFloatReg(reg_idx, val);
     }
 
-    void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
-    {
-        actualTC->setFloatRegBits(reg_idx, val, width);
-        checkerTC->setFloatRegBits(reg_idx, val, width);
-    }
-
     void setFloatRegBits(int reg_idx, FloatRegBits val)
     {
         actualTC->setFloatRegBits(reg_idx, val);

src/cpu/exec_context.hh

@@ -50,17 +50,9 @@ class ExecContext {
     /** Reads an integer register. */
     uint64_t readIntRegOperand(const StaticInst *si, int idx);
 
-    /** Reads a floating point register of a specific width. */
-    FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width);
-
     /** Reads a floating point register of single register width. */
     FloatReg readFloatRegOperand(const StaticInst *si, int idx);
 
-    /** Reads a floating point register of a specific width in its
-     * binary format, instead of by value. */
-    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
-                                         int width);
-
     /** Reads a floating point register in its binary format, instead
      * of by value. */
     FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
@@ -68,18 +60,9 @@ class ExecContext {
     /** Sets an integer register to a value. */
     void setIntRegOperand(const StaticInst *si, int idx, uint64_t val);
 
-    /** Sets a floating point register of a specific width to a value. */
-    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
-                            int width);
-
     /** Sets a floating point register of single width to a value. */
     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
 
-    /** Sets the bits of a floating point register of a specific width
-     * to a binary value. */
-    void setFloatRegOperandBits(const StaticInst *si, int idx,
-                                FloatRegBits val, int width);
-
     /** Sets the bits of a floating point register of single width
      * to a binary value. */
     void setFloatRegOperandBits(const StaticInst *si, int idx,

src/cpu/inorder/cpu.cc

@@ -890,16 +890,15 @@ InOrderCPU::readIntReg(int reg_idx, ThreadID tid)
 }
 
 FloatReg
-InOrderCPU::readFloatReg(int reg_idx, ThreadID tid, int width)
+InOrderCPU::readFloatReg(int reg_idx, ThreadID tid)
 {
-
+    return floatRegFile[tid].readReg(reg_idx);
-    return floatRegFile[tid].readReg(reg_idx, width);
 }
 
 FloatRegBits
-InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid, int width)
+InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid)
 {;
-    return floatRegFile[tid].readRegBits(reg_idx, width);
+    return floatRegFile[tid].readRegBits(reg_idx);
 }
 
 void
@@ -910,17 +909,16 @@ InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid)
 
 
 void
-InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid, int width)
+InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid)
 {
-    floatRegFile[tid].setReg(reg_idx, val, width);
+    floatRegFile[tid].setReg(reg_idx, val);
 }
 
 
 void
-InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid,
+InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid)
-                            int width)
 {
-    floatRegFile[tid].setRegBits(reg_idx, val, width);
+    floatRegFile[tid].setRegBits(reg_idx, val);
 }
 
 uint64_t

src/cpu/inorder/cpu.hh

@@ -404,19 +404,15 @@ class InOrderCPU : public BaseCPU
     /** Register file accessors  */
     uint64_t readIntReg(int reg_idx, ThreadID tid);
 
-    FloatReg readFloatReg(int reg_idx, ThreadID tid,
+    FloatReg readFloatReg(int reg_idx, ThreadID tid);
-                          int width = TheISA::SingleWidth);
 
-    FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid,
+    FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid);
-                                  int width = TheISA::SingleWidth);
 
     void setIntReg(int reg_idx, uint64_t val, ThreadID tid);
 
-    void setFloatReg(int reg_idx, FloatReg val, ThreadID tid,
+    void setFloatReg(int reg_idx, FloatReg val, ThreadID tid);
-                     int width = TheISA::SingleWidth);
 
-    void setFloatRegBits(int reg_idx, FloatRegBits val,  ThreadID tid,
+    void setFloatRegBits(int reg_idx, FloatRegBits val,  ThreadID tid);
-                         int width = TheISA::SingleWidth);
 
     /** Reads a miscellaneous register. */
     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);

src/cpu/inorder/inorder_dyn_inst.cc

@@ -366,14 +366,9 @@ InOrderDynInst::setIntSrc(int idx, uint64_t val)
 
 /** Records an fp register being set to a value. */
 void
-InOrderDynInst::setFloatSrc(int idx, FloatReg val, int width)
+InOrderDynInst::setFloatSrc(int idx, FloatReg val)
 {
-    if (width == 32)
+    instSrc[idx].dbl = val;
-        instSrc[idx].dbl = val;
-    else if (width == 64)
-        instSrc[idx].dbl = val;
-    else
-        panic("Unsupported width!");
 }
 
 /** Records an fp register being set to an integer value. */
@@ -394,22 +389,15 @@ InOrderDynInst::readIntRegOperand(const StaticInst *si, int idx, ThreadID tid)
 
 /** Reads a FP register. */
 FloatReg
-InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx, int width)
+InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx)
 {
-    if (width == 32)
+    return instSrc[idx].dbl;
-        return (float)instSrc[idx].dbl;
-    else if (width == 64)
-        return instSrc[idx].dbl;
-    else {
-        panic("Unsupported Floating Point Width!");
-        return 0;
-    }
 }
 
 
 /** Reads a FP register as a integer. */
 FloatRegBits
-InOrderDynInst::readFloatRegOperandBits(const StaticInst *si, int idx, int width)
+InOrderDynInst::readFloatRegOperandBits(const StaticInst *si, int idx)
 {
     return instSrc[idx].integer;
 }
@@ -507,31 +495,22 @@ InOrderDynInst::setIntRegOperand(const StaticInst *si, int idx, IntReg val)
 
 /** Sets a FP register. */
 void
-InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, int width)
+InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
 {
-    if (width == 32) {
+    instResult[idx].val.dbl = val;
-        instResult[idx].val.dbl = (float)val;
+    instResult[idx].type = Float;
-        instResult[idx].type = Float;
-    } else if (width == 64) {
-        instResult[idx].val.dbl = val;
-        instResult[idx].type = Double;
-    } else {
-        panic("Unsupported Floating Point Width!");
-    }
 
     instResult[idx].tick = curTick;
-    instResult[idx].width = width;
 }
 
 /** Sets a FP register as a integer. */
 void
 InOrderDynInst::setFloatRegOperandBits(const StaticInst *si, int idx,
-                              FloatRegBits val, int width)
+                              FloatRegBits val)
 {
     instResult[idx].type = Integer;
     instResult[idx].val.integer = val;
     instResult[idx].tick = curTick;
-    instResult[idx].width = width;
 }
 
 /** Sets a misc. register. */

src/cpu/inorder/inorder_dyn_inst.hh

@@ -243,10 +243,9 @@ class InOrderDynInst : public FastAlloc, public RefCounted
         ResultType type;
         InstValue val;
         Tick tick;
-        int width;
 
         InstResult()
-            : type(None), tick(0), width(0)
+            : type(None), tick(0)
         {}
     };
 
@@ -817,7 +816,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     /** Functions that sets an integer or floating point
      *  source register to a value. */
     void setIntSrc(int idx, uint64_t val);
-    void setFloatSrc(int idx, FloatReg val, int width = 32);
+    void setFloatSrc(int idx, FloatReg val);
     void setFloatRegBitsSrc(int idx, uint64_t val);
 
     uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].integer; }
@@ -830,10 +829,8 @@ class InOrderDynInst : public FastAlloc, public RefCounted
      *  the source reg. value is set using the setSrcReg() function.
      */
     IntReg readIntRegOperand(const StaticInst *si, int idx, ThreadID tid = 0);
-    FloatReg readFloatRegOperand(const StaticInst *si, int idx,
+    FloatReg readFloatRegOperand(const StaticInst *si, int idx);
-                          int width = TheISA::SingleWidth);
+    TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
-    TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
-                                  int width = TheISA::SingleWidth);
     MiscReg readMiscReg(int misc_reg);
     MiscReg readMiscRegNoEffect(int misc_reg);
     MiscReg readMiscRegOperand(const StaticInst *si, int idx);
@@ -853,15 +850,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     /** Depending on type, return Float or Double */
     double readFloatResult(int idx)
     {
-        //Should this function have a parameter for what width of return?x
+       return instResult[idx].val.dbl;
-       return (instResult[idx].type == Float) ?
-           (float) instResult[idx].val.dbl : instResult[idx].val.dbl;
-    }
-
-    double readDoubleResult(int idx)
-    {
-        assert(instResult[idx].type == Double);
-        return instResult[idx].val.dbl;
     }
 
     Tick readResultTime(int idx) { return instResult[idx].tick; }
@@ -872,10 +861,9 @@ class InOrderDynInst : public FastAlloc, public RefCounted
      *  it's destination register.
      */
     void setIntRegOperand(const StaticInst *si, int idx, IntReg val);
-    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
-                     int width = TheISA::SingleWidth);
+    void setFloatRegOperandBits(const StaticInst *si, int idx,
-    void setFloatRegOperandBits(const StaticInst *si, int idx, TheISA::FloatRegBits val,
+            TheISA::FloatRegBits val);
-                         int width = TheISA::SingleWidth);
     void setMiscReg(int misc_reg, const MiscReg &val);
     void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
     void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val);

src/cpu/inorder/resources/execution_unit.cc

@@ -179,8 +179,7 @@ ExecutionUnit::execute(int slot_num)
 
                     DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result of execution is 0x%x.\n",
                             inst->readTid(), seq_num, (inst->resultType(0) == InOrderDynInst::Float) ?
-                            inst->readFloatResult(0) : (inst->resultType(0) == InOrderDynInst::Double) ?
+                            inst->readFloatResult(0) : inst->readIntResult(0));
-                            inst->readDoubleResult(0) : inst->readIntResult(0));
 
                     exec_req->done();
                 } else {

src/cpu/inorder/resources/use_def.cc

@@ -53,8 +53,6 @@ UseDefUnit::UseDefUnit(string res_name, int res_id, int res_width,
         outWriteSeqNum[tid] = maxSeqNum;
 
         regDepMap[tid] = &cpu->archRegDepMap[tid];
-
-        floatRegSize[tid] = cpu->floatRegFile[tid].regWidth;
     }
 
 }
@@ -138,12 +136,11 @@ UseDefUnit::execute(int slot_idx)
                         DPRINTF(InOrderUseDef, "[tid:%i]: Reading Float Reg %i from Register File:%x (%08f).\n",
                                 tid,
                                 reg_idx,
-                                cpu->readFloatRegBits(reg_idx, inst->readTid(), floatRegSize[tid]),
+                                cpu->readFloatRegBits(reg_idx, inst->readTid()),
-                                cpu->readFloatReg(reg_idx, inst->readTid(),floatRegSize[tid]));
+                                cpu->readFloatReg(reg_idx, inst->readTid()));
 
                         inst->setFloatSrc(ud_idx,
-                                          cpu->readFloatReg(reg_idx, inst->readTid(), floatRegSize[tid]),
+                                          cpu->readFloatReg(reg_idx, inst->readTid()));
-                                          floatRegSize[tid]);
                     } else {
                         reg_idx -= Ctrl_Base_DepTag;
                         DPRINTF(InOrderUseDef, "[tid:%i]: Reading Misc Reg %i from Register File:%i.\n",
@@ -183,8 +180,7 @@ UseDefUnit::execute(int slot_idx)
                                     tid, forward_inst->readFloatResult(dest_reg_idx) ,
                                     forward_inst->seqNum, inst->seqNum, ud_idx);
                             inst->setFloatSrc(ud_idx,
-                                              forward_inst->readFloatResult(dest_reg_idx),
+                                              forward_inst->readFloatResult(dest_reg_idx));
-                                              floatRegSize[tid]);
                         } else {
                             DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest. reg value 0x%x from "
                                     "[sn:%i] to [sn:%i] source #%i.\n",
@@ -244,24 +240,21 @@ UseDefUnit::execute(int slot_idx)
 
                             cpu->setFloatRegBits(reg_idx, // Check for FloatRegBits Here
                                              inst->readIntResult(ud_idx),
-                                             inst->readTid(),
+                                             inst->readTid());
-                                             floatRegSize[tid]);
                         } else if (inst->resultType(ud_idx) == InOrderDynInst::Float) {
                             DPRINTF(InOrderUseDef, "[tid:%i]: Writing Float Result 0x%x (bits:0x%x) to register idx %i.\n",
                                     tid, inst->readFloatResult(ud_idx), inst->readIntResult(ud_idx), reg_idx);
 
                             cpu->setFloatReg(reg_idx,
                                              inst->readFloatResult(ud_idx),
-                                             inst->readTid(),
+                                             inst->readTid());
-                                             floatRegSize[tid]);
                         } else if (inst->resultType(ud_idx) == InOrderDynInst::Double) {
                             DPRINTF(InOrderUseDef, "[tid:%i]: Writing Double Result 0x%x (bits:0x%x) to register idx %i.\n",
                                     tid, inst->readFloatResult(ud_idx), inst->readIntResult(ud_idx), reg_idx);
 
                             cpu->setFloatReg(reg_idx, // Check for FloatRegBits Here
-                                             inst->readDoubleResult(ud_idx),
+                                             inst->readFloatResult(ud_idx),
-                                             inst->readTid(),
+                                             inst->readTid());
-                                             floatRegSize[tid]);
                         } else {
                             panic("Result Type Not Set For [sn:%i] %s.\n", inst->seqNum, inst->instName());
                         }

src/cpu/inorder/thread_context.cc

@@ -150,24 +150,12 @@ InOrderThreadContext::readIntReg(int reg_idx)
     return cpu->readIntReg(reg_idx, thread->readTid());
 }
 
-FloatReg
-InOrderThreadContext::readFloatReg(int reg_idx, int width)
-{
-    return cpu->readFloatReg(reg_idx, thread->readTid(), width);
-}
-
 FloatReg
 InOrderThreadContext::readFloatReg(int reg_idx)
 {
     return cpu->readFloatReg(reg_idx, thread->readTid());
 }
 
-FloatRegBits
-InOrderThreadContext::readFloatRegBits(int reg_idx, int width)
-{
-    return cpu->readFloatRegBits(reg_idx, thread->readTid(), width);
-}
-
 FloatRegBits
 InOrderThreadContext::readFloatRegBits(int reg_idx)
 {
@@ -186,25 +174,12 @@ InOrderThreadContext::setIntReg(int reg_idx, uint64_t val)
     cpu->setIntReg(reg_idx, val, thread->readTid());
 }
 
-void
-InOrderThreadContext::setFloatReg(int reg_idx, FloatReg val, int width)
-{
-    cpu->setFloatReg(reg_idx, val, thread->readTid(), width);
-}
-
 void
 InOrderThreadContext::setFloatReg(int reg_idx, FloatReg val)
 {
     cpu->setFloatReg(reg_idx, val, thread->readTid());
 }
 
-void
-InOrderThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val,
-                                    int width)
-{
-    cpu->setFloatRegBits(reg_idx, val, thread->readTid(), width);
-}
-
 void
 InOrderThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val)
 {

src/cpu/inorder/thread_context.hh

@@ -152,12 +152,8 @@ class InOrderThreadContext : public ThreadContext
     /** Reads an integer register. */
     virtual uint64_t readIntReg(int reg_idx);
 
-    virtual FloatReg readFloatReg(int reg_idx, int width);
-
     virtual FloatReg readFloatReg(int reg_idx);
 
-    virtual FloatRegBits readFloatRegBits(int reg_idx, int width);
-
     virtual FloatRegBits readFloatRegBits(int reg_idx);
 
     virtual uint64_t readRegOtherThread(int misc_reg, ThreadID tid);
@@ -165,12 +161,8 @@ class InOrderThreadContext : public ThreadContext
     /** Sets an integer register to a value. */
     virtual void setIntReg(int reg_idx, uint64_t val);
 
-    virtual void setFloatReg(int reg_idx, FloatReg val, int width);
-
     virtual void setFloatReg(int reg_idx, FloatReg val);
 
-    virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
-
     virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
 
     virtual void setRegOtherThread(int misc_reg, const MiscReg &val,

src/cpu/legiontrace.cc

@@ -232,8 +232,7 @@ Trace::LegionTraceRecord::dump()
                     }
                 }
                 for (int i = 0; i < TheISA::NumFloatRegs/2; i++) {
-                    if (thread->readFloatRegBits(i*2,
+                    if (thread->readFloatRegBits(i*2) !=
-                                FloatRegFile::DoubleWidth) !=
                             shared_data->fpregs[i]) {
                         diffFpRegs = true;
                     }
@@ -539,8 +538,7 @@ Trace::LegionTraceRecord::dump()
                             char label[8];
                             sprintf(label, "%%f%d", x);
                             printRegPair(outs, label,
-                                thread->readFloatRegBits(x*2,
+                                thread->readFloatRegBits(x*2),
-                                    FloatRegFile::DoubleWidth),
                                 shared_data->fpregs[x]);
                         }
                     }

src/cpu/o3/cpu.cc

@@ -1213,13 +1213,6 @@ FullO3CPU<Impl>::readIntReg(int reg_idx)
     return regFile.readIntReg(reg_idx);
 }
 
-template <class Impl>
-FloatReg
-FullO3CPU<Impl>::readFloatReg(int reg_idx, int width)
-{
-    return regFile.readFloatReg(reg_idx, width);
-}
-
 template <class Impl>
 FloatReg
 FullO3CPU<Impl>::readFloatReg(int reg_idx)
@@ -1227,13 +1220,6 @@ FullO3CPU<Impl>::readFloatReg(int reg_idx)
     return regFile.readFloatReg(reg_idx);
 }
 
-template <class Impl>
-FloatRegBits
-FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width)
-{
-    return regFile.readFloatRegBits(reg_idx, width);
-}
-
 template <class Impl>
 FloatRegBits
 FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
@@ -1248,13 +1234,6 @@ FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
     regFile.setIntReg(reg_idx, val);
 }
 
-template <class Impl>
-void
-FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
-{
-    regFile.setFloatReg(reg_idx, val, width);
-}
-
 template <class Impl>
 void
 FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
@@ -1262,13 +1241,6 @@ FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
     regFile.setFloatReg(reg_idx, val);
 }
 
-template <class Impl>
-void
-FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width)
-{
-    regFile.setFloatRegBits(reg_idx, val, width);
-}
-
 template <class Impl>
 void
 FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
@@ -1287,7 +1259,7 @@ FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
 
 template <class Impl>
 float
-FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, ThreadID tid)
+FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
 {
     int idx = reg_idx + TheISA::NumIntRegs;
     PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
@@ -1295,16 +1267,6 @@ FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, ThreadID tid)
     return regFile.readFloatReg(phys_reg);
 }
 
-template <class Impl>
-double
-FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, ThreadID tid)
-{
-    int idx = reg_idx + TheISA::NumIntRegs;
-    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
-
-    return regFile.readFloatReg(phys_reg, 64);
-}
-
 template <class Impl>
 uint64_t
 FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
@@ -1326,7 +1288,7 @@ FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
 
 template <class Impl>
 void
-FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, ThreadID tid)
+FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
 {
     int idx = reg_idx + TheISA::NumIntRegs;
     PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
@@ -1334,16 +1296,6 @@ FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, ThreadID tid)
     regFile.setFloatReg(phys_reg, val);
 }
 
-template <class Impl>
-void
-FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, ThreadID tid)
-{
-    int idx = reg_idx + TheISA::NumIntRegs;
-    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
-
-    regFile.setFloatReg(phys_reg, val, 64);
-}
-
 template <class Impl>
 void
 FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)

src/cpu/o3/cpu.hh

@@ -435,27 +435,17 @@ class FullO3CPU : public BaseO3CPU
 
     TheISA::FloatReg readFloatReg(int reg_idx);
 
-    TheISA::FloatReg readFloatReg(int reg_idx, int width);
-
     TheISA::FloatRegBits readFloatRegBits(int reg_idx);
 
-    TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width);
-
     void setIntReg(int reg_idx, uint64_t val);
 
     void setFloatReg(int reg_idx, TheISA::FloatReg val);
 
-    void setFloatReg(int reg_idx, TheISA::FloatReg val, int width);
-
     void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
 
-    void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
-
     uint64_t readArchIntReg(int reg_idx, ThreadID tid);
 
-    float readArchFloatRegSingle(int reg_idx, ThreadID tid);
+    float readArchFloatReg(int reg_idx, ThreadID tid);
-
-    double readArchFloatRegDouble(int reg_idx, ThreadID tid);
 
     uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
 
@@ -466,9 +456,7 @@ class FullO3CPU : public BaseO3CPU
      */
     void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
 
-    void setArchFloatRegSingle(int reg_idx, float val, ThreadID tid);
+    void setArchFloatReg(int reg_idx, float val, ThreadID tid);
-
-    void setArchFloatRegDouble(int reg_idx, double val, ThreadID tid);
 
     void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
 

src/cpu/o3/dyn_inst.hh

@@ -196,22 +196,11 @@ class BaseO3DynInst : public BaseDynInst<Impl>
         return this->cpu->readIntReg(this->_srcRegIdx[idx]);
     }
 
-    FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
-    {
-        return this->cpu->readFloatReg(this->_srcRegIdx[idx], width);
-    }
-
     FloatReg readFloatRegOperand(const StaticInst *si, int idx)
     {
         return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
     }
 
-    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
-                                         int width)
-    {
-        return this->cpu->readFloatRegBits(this->_srcRegIdx[idx], width);
-    }
-
     FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
     {
         return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
@@ -226,26 +215,12 @@ class BaseO3DynInst : public BaseDynInst<Impl>
         BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
     }
 
-    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
-                            int width)
-    {
-        this->cpu->setFloatReg(this->_destRegIdx[idx], val, width);
-        BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width);
-    }
-
     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
     {
         this->cpu->setFloatReg(this->_destRegIdx[idx], val);
         BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
     }
 
-    void setFloatRegOperandBits(const StaticInst *si, int idx,
-                                FloatRegBits val, int width)
-    {
-        this->cpu->setFloatRegBits(this->_destRegIdx[idx], val, width);
-        BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
-    }
-
     void setFloatRegOperandBits(const StaticInst *si, int idx,
                                 FloatRegBits val)
     {

src/cpu/o3/regfile.hh

@@ -93,21 +93,6 @@ class PhysRegFile
         return intRegFile[reg_idx];
     }
 
-    FloatReg readFloatReg(PhysRegIndex reg_idx, int width)
-    {
-        // Remove the base Float reg dependency.
-        reg_idx = reg_idx - numPhysicalIntRegs;
-
-        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
-
-        FloatReg floatReg = floatRegFile[reg_idx].d;
-
-        DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has "
-                "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
-
-        return floatReg;
-    }
-
     /** Reads a floating point register (double precision). */
     FloatReg readFloatReg(PhysRegIndex reg_idx)
     {
@@ -124,22 +109,6 @@ class PhysRegFile
         return floatReg;
     }
 
-    /** Reads a floating point register as an integer. */
-    FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width)
-    {
-        // Remove the base Float reg dependency.
-        reg_idx = reg_idx - numPhysicalIntRegs;
-
-        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
-
-        FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
-
-        DPRINTF(IEW, "RegFile: Access to float register %i as int, "
-                "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
-
-        return floatRegBits;
-    }
-
     FloatRegBits readFloatRegBits(PhysRegIndex reg_idx)
     {
         // Remove the base Float reg dependency.
@@ -167,23 +136,6 @@ class PhysRegFile
             intRegFile[reg_idx] = val;
     }
 
-    /** Sets a single precision floating point register to the given value. */
-    void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width)
-    {
-        // Remove the base Float reg dependency.
-        reg_idx = reg_idx - numPhysicalIntRegs;
-
-        assert(reg_idx < numPhysicalFloatRegs);
-
-        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
-                int(reg_idx), (uint64_t)val);
-
-#if THE_ISA == ALPHA_ISA
-        if (reg_idx != TheISA::ZeroReg)
-#endif
-            floatRegFile[reg_idx].d = val;
-    }
-
     /** Sets a double precision floating point register to the given value. */
     void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
     {
@@ -201,20 +153,6 @@ class PhysRegFile
             floatRegFile[reg_idx].d = val;
     }
 
-    /** Sets a floating point register to the given integer value. */
-    void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width)
-    {
-        // Remove the base Float reg dependency.
-        reg_idx = reg_idx - numPhysicalIntRegs;
-
-        assert(reg_idx < numPhysicalFloatRegs);
-
-        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
-                int(reg_idx), (uint64_t)val);
-
-        floatRegFile[reg_idx].q = val;
-    }
-
     void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
     {
         // Remove the base Float reg dependency.

src/cpu/o3/thread_context.hh

@@ -167,23 +167,15 @@ class O3ThreadContext : public ThreadContext
     /** Reads an integer register. */
     virtual uint64_t readIntReg(int reg_idx);
 
-    virtual FloatReg readFloatReg(int reg_idx, int width);
-
     virtual FloatReg readFloatReg(int reg_idx);
 
-    virtual FloatRegBits readFloatRegBits(int reg_idx, int width);
-
     virtual FloatRegBits readFloatRegBits(int reg_idx);
 
     /** Sets an integer register to a value. */
     virtual void setIntReg(int reg_idx, uint64_t val);
 
-    virtual void setFloatReg(int reg_idx, FloatReg val, int width);
-
     virtual void setFloatReg(int reg_idx, FloatReg val);
 
-    virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
-
     virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
 
     /** Reads this thread's PC. */

src/cpu/o3/thread_context_impl.hh

@@ -276,37 +276,12 @@ O3ThreadContext<Impl>::readIntReg(int reg_idx)
     return cpu->readArchIntReg(reg_idx, thread->threadId());
 }
 
-template <class Impl>
-TheISA::FloatReg
-O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width)
-{
-    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
-    switch(width) {
-      case 32:
-        return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
-      case 64:
-        return cpu->readArchFloatRegDouble(reg_idx, thread->threadId());
-      default:
-        panic("Unsupported width!");
-        return 0;
-    }
-}
-
 template <class Impl>
 TheISA::FloatReg
 O3ThreadContext<Impl>::readFloatReg(int reg_idx)
 {
     reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
-    return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
+    return cpu->readArchFloatReg(reg_idx, thread->threadId());
-}
-
-template <class Impl>
-TheISA::FloatRegBits
-O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width)
-{
-    DPRINTF(Fault, "Reading floatint register through the TC!\n");
-    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
-    return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
 }
 
 template <class Impl>
@@ -330,53 +305,18 @@ O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
     }
 }
 
-template <class Impl>
-void
-O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
-{
-    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
-    switch(width) {
-      case 32:
-        cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
-        break;
-      case 64:
-        cpu->setArchFloatRegDouble(reg_idx, val, thread->threadId());
-        break;
-    }
-
-    // Squash if we're not already in a state update mode.
-    if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->threadId());
-    }
-}
-
 template <class Impl>
 void
 O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
 {
     reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
-    cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
+    cpu->setArchFloatReg(reg_idx, val, thread->threadId());
 
     if (!thread->trapPending && !thread->inSyscall) {
         cpu->squashFromTC(thread->threadId());
     }
 }
 
-template <class Impl>
-void
-O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val,
-                                             int width)
-{
-    DPRINTF(Fault, "Setting floatint register through the TC!\n");
-    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
-    cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
-
-    // Squash if we're not already in a state update mode.
-    if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromTC(thread->threadId());
-    }
-}
-
 template <class Impl>
 void
 O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)

src/cpu/ozone/cpu.hh

@@ -183,22 +183,14 @@ class OzoneCPU : public BaseCPU
 
         uint64_t readIntReg(int reg_idx);
 
-        FloatReg readFloatReg(int reg_idx, int width);
-
         FloatReg readFloatReg(int reg_idx);
 
-        FloatRegBits readFloatRegBits(int reg_idx, int width);
-
         FloatRegBits readFloatRegBits(int reg_idx);
 
         void setIntReg(int reg_idx, uint64_t val);
 
-        void setFloatReg(int reg_idx, FloatReg val, int width);
-
         void setFloatReg(int reg_idx, FloatReg val);
 
-        void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
-
         void setFloatRegBits(int reg_idx, FloatRegBits val);
 
         uint64_t readPC() { return thread->PC; }

src/cpu/ozone/cpu_impl.hh

@@ -917,22 +917,6 @@ OzoneCPU<Impl>::OzoneTC::readIntReg(int reg_idx)
     return thread->renameTable[reg_idx]->readIntResult();
 }
 
-template <class Impl>
-TheISA::FloatReg
-OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx, int width)
-{
-    int idx = reg_idx + TheISA::FP_Base_DepTag;
-    switch(width) {
-      case 32:
-        return thread->renameTable[idx]->readFloatResult();
-      case 64:
-        return thread->renameTable[idx]->readDoubleResult();
-      default:
-        panic("Unsupported width!");
-        return 0;
-    }
-}
-
 template <class Impl>
 double
 OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx)
@@ -941,14 +925,6 @@ OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx)
     return thread->renameTable[idx]->readFloatResult();
 }
 
-template <class Impl>
-uint64_t
-OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx, int width)
-{
-    int idx = reg_idx + TheISA::FP_Base_DepTag;
-    return thread->renameTable[idx]->readIntResult();
-}
-
 template <class Impl>
 uint64_t
 OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx)
@@ -968,27 +944,6 @@ OzoneCPU<Impl>::OzoneTC::setIntReg(int reg_idx, uint64_t val)
     }
 }
 
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val, int width)
-{
-    int idx = reg_idx + TheISA::FP_Base_DepTag;
-    switch(width) {
-      case 32:
-        panic("Unimplemented!");
-        break;
-      case 64:
-        thread->renameTable[idx]->setDoubleResult(val);
-        break;
-      default:
-        panic("Unsupported width!");
-    }
-
-    if (!thread->inSyscall) {
-        cpu->squashFromTC();
-    }
-}
-
 template <class Impl>
 void
 OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val)
@@ -1002,14 +957,6 @@ OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val)
     }
 }
 
-template <class Impl>
-void
-OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val,
-                                         int width)
-{
-    panic("Unimplemented!");
-}
-
 template <class Impl>
 void
 OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val)

src/cpu/ozone/dyn_inst.hh

@@ -151,28 +151,14 @@ class OzoneDynInst : public BaseDynInst<Impl>
         return srcInsts[idx]->readIntResult();
     }
 
-    FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
-    {
-        switch(width) {
-          case 32:
-            return srcInsts[idx]->readFloatResult();
-          case 64:
-            return srcInsts[idx]->readDoubleResult();
-          default:
-            panic("Width not supported");
-            return 0;
-        }
-    }
-
     FloatReg readFloatRegOperand(const StaticInst *si, int idx)
     {
         return srcInsts[idx]->readFloatResult();
     }
 
-    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+    FloatReg readFloatRegOperand(const StaticInst *si, int idx)
-                                         int width)
     {
-        return srcInsts[idx]->readIntResult();
+        return srcInsts[idx]->readFloatResult();
     }
 
     FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
@@ -188,23 +174,11 @@ class OzoneDynInst : public BaseDynInst<Impl>
         BaseDynInst<Impl>::setIntReg(si, idx, val);
     }
 
-    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
-                            int width)
-    {
-        BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
-    }
-
     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
     {
         BaseDynInst<Impl>::setFloatReg(si, idx, val);
     }
 
-    void setFloatRegOperandBits(const StaticInst *si, int idx,
-                                FloatRegBits val, int width)
-    {
-        BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
-    }
-
     void setFloatRegOperandBits(const StaticInst *si, int idx,
                                 FloatRegBits val)
     {

src/cpu/simple/base.hh

@@ -262,25 +262,12 @@ class BaseSimpleCPU : public BaseCPU
         return thread->readIntReg(si->srcRegIdx(idx));
     }
 
-    FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
-    {
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
-        return thread->readFloatReg(reg_idx, width);
-    }
-
     FloatReg readFloatRegOperand(const StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return thread->readFloatReg(reg_idx);
     }
 
-    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
-                                         int width)
-    {
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
-        return thread->readFloatRegBits(reg_idx, width);
-    }
-
     FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
@@ -292,26 +279,12 @@ class BaseSimpleCPU : public BaseCPU
         thread->setIntReg(si->destRegIdx(idx), val);
     }
 
-    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
-                            int width)
-    {
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
-        thread->setFloatReg(reg_idx, val, width);
-    }
-
     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
         thread->setFloatReg(reg_idx, val);
     }
 
-    void setFloatRegOperandBits(const StaticInst *si, int idx,
-                                FloatRegBits val, int width)
-    {
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
-        thread->setFloatRegBits(reg_idx, val, width);
-    }
-
     void setFloatRegOperandBits(const StaticInst *si, int idx,
                                 FloatRegBits val)
     {

src/cpu/simple_thread.hh

@@ -234,24 +234,12 @@ class SimpleThread : public ThreadState
         return regs.readIntReg(flatIndex);
     }
 
-    FloatReg readFloatReg(int reg_idx, int width)
-    {
-        int flatIndex = isa.flattenFloatIndex(reg_idx);
-        return regs.readFloatReg(flatIndex, width);
-    }
-
     FloatReg readFloatReg(int reg_idx)
     {
         int flatIndex = isa.flattenFloatIndex(reg_idx);
         return regs.readFloatReg(flatIndex);
     }
 
-    FloatRegBits readFloatRegBits(int reg_idx, int width)
-    {
-        int flatIndex = isa.flattenFloatIndex(reg_idx);
-        return regs.readFloatRegBits(flatIndex, width);
-    }
-
     FloatRegBits readFloatRegBits(int reg_idx)
     {
         int flatIndex = isa.flattenFloatIndex(reg_idx);
@@ -264,24 +252,12 @@ class SimpleThread : public ThreadState
         regs.setIntReg(flatIndex, val);
     }
 
-    void setFloatReg(int reg_idx, FloatReg val, int width)
-    {
-        int flatIndex = isa.flattenFloatIndex(reg_idx);
-        regs.setFloatReg(flatIndex, val, width);
-    }
-
     void setFloatReg(int reg_idx, FloatReg val)
     {
         int flatIndex = isa.flattenFloatIndex(reg_idx);
         regs.setFloatReg(flatIndex, val);
     }
 
-    void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
-    {
-        int flatIndex = isa.flattenFloatIndex(reg_idx);
-        regs.setFloatRegBits(flatIndex, val, width);
-    }
-
     void setFloatRegBits(int reg_idx, FloatRegBits val)
     {
         int flatIndex = isa.flattenFloatIndex(reg_idx);

src/cpu/thread_context.hh

@@ -187,24 +187,16 @@ class ThreadContext
     //
     virtual uint64_t readIntReg(int reg_idx) = 0;
 
-    virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
-
     virtual FloatReg readFloatReg(int reg_idx) = 0;
 
-    virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
-
     virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
 
     virtual void setIntReg(int reg_idx, uint64_t val) = 0;
 
-    virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
-
     virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
 
     virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
 
-    virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
-
     virtual uint64_t readPC() = 0;
 
     virtual void setPC(uint64_t val) = 0;
@@ -377,30 +369,18 @@ class ProxyThreadContext : public ThreadContext
     uint64_t readIntReg(int reg_idx)
     { return actualTC->readIntReg(reg_idx); }
 
-    FloatReg readFloatReg(int reg_idx, int width)
-    { return actualTC->readFloatReg(reg_idx, width); }
-
     FloatReg readFloatReg(int reg_idx)
     { return actualTC->readFloatReg(reg_idx); }
 
-    FloatRegBits readFloatRegBits(int reg_idx, int width)
-    { return actualTC->readFloatRegBits(reg_idx, width); }
-
     FloatRegBits readFloatRegBits(int reg_idx)
     { return actualTC->readFloatRegBits(reg_idx); }
 
     void setIntReg(int reg_idx, uint64_t val)
     { actualTC->setIntReg(reg_idx, val); }
 
-    void setFloatReg(int reg_idx, FloatReg val, int width)
-    { actualTC->setFloatReg(reg_idx, val, width); }
-
     void setFloatReg(int reg_idx, FloatReg val)
     { actualTC->setFloatReg(reg_idx, val); }
 
-    void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
-    { actualTC->setFloatRegBits(reg_idx, val, width); }
-
     void setFloatRegBits(int reg_idx, FloatRegBits val)
     { actualTC->setFloatRegBits(reg_idx, val); }