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Add in code to pass the ASI to translation.

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--HG--
extra : convert_revision : 4a985635cda7680abcddaf0bc9579fa03d5bc7c6
This commit is contained in:
Gabe Black 2006-12-04 19:55:52 -05:00
parent 36c03001bb
commit 251f4e1134
4 changed files with 49 additions and 47 deletions
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50
src/arch/sparc/isa/decoder.isa
View file

@ -1054,36 +1054,36 @@ decode OP default Unknown::unknown()
{{uReg0 = Rd.uw; {{uReg0 = Rd.uw;
Rd.uw = Mem.uw;}}, Rd.uw = Mem.uw;}},
{{Mem.uw = uReg0;}}); {{Mem.uw = uReg0;}});
format Load { format LoadAlt {
0x10: lduwa({{Rd = Mem.uw;}}); 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
0x11: lduba({{Rd = Mem.ub;}}); 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
0x12: lduha({{Rd = Mem.uhw;}}); 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
0x13: ldda({{ 0x13: ldda({{
uint64_t val = Mem.udw; uint64_t val = Mem.udw;
RdLow = val<31:0>; RdLow = val<31:0>;
RdHigh = val<63:32>; RdHigh = val<63:32>;
}}); }}, {{EXT_ASI}});
} }
format Store { format StoreAlt {
0x14: stwa({{Mem.uw = Rd;}}); 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
0x15: stba({{Mem.ub = Rd;}}); 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
0x16: stha({{Mem.uhw = Rd;}}); 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}); 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
} }
format Load { format LoadAlt {
0x18: ldswa({{Rd = (int32_t)Mem.sw;}}); 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
0x19: ldsba({{Rd = (int8_t)Mem.sb;}}); 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}); 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}); 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
} }
0x1D: LoadStore::ldstuba( 0x1D: LoadStoreAlt::ldstuba(
{{Rd = Mem.ub;}}, {{Rd = Mem.ub;}},
{{Mem.ub = 0xFF}}); {{Mem.ub = 0xFF}}, {{EXT_ASI}});
0x1E: Store::stxa({{Mem.udw = Rd}}); 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}});
0x1F: LoadStore::swapa( 0x1F: LoadStoreAlt::swapa(
{{uReg0 = Rd.uw; {{uReg0 = Rd.uw;
Rd.uw = Mem.uw;}}, Rd.uw = Mem.uw;}},
{{Mem.uw = uReg0;}}); {{Mem.uw = uReg0;}}, {{EXT_ASI}});
format Trap { format Trap {
0x20: Load::ldf({{Frd.uw = Mem.uw;}}); 0x20: Load::ldf({{Frd.uw = Mem.uw;}});
0x21: decode X { 0x21: decode X {
@ -1100,7 +1100,7 @@ decode OP default Unknown::unknown()
0x26: stqf({{fault = new FpDisabled;}}); 0x26: stqf({{fault = new FpDisabled;}});
0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
0x2D: Nop::prefetch({{ }}); 0x2D: Nop::prefetch({{ }});
0x30: Load::ldfa({{Frd.uw = Mem.uw;}}); 0x30: LoadAlt::ldfa({{Frd.uw = Mem.uw;}}, {{EXT_ASI}});
0x32: ldqfa({{fault = new FpDisabled;}}); 0x32: ldqfa({{fault = new FpDisabled;}});
format LoadAlt { format LoadAlt {
0x33: decode EXT_ASI { 0x33: decode EXT_ASI {
@ -1152,7 +1152,7 @@ decode OP default Unknown::unknown()
//ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
0x1F: FailUnimpl::ldblockf_aiusl(); 0x1F: FailUnimpl::ldblockf_aiusl();
//ASI_BLOCK_PRIMARY //ASI_BLOCK_PRIMARY
0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}); 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}});
//ASI_BLOCK_SECONDARY //ASI_BLOCK_SECONDARY
0xF1: FailUnimpl::ldblockf_s(); 0xF1: FailUnimpl::ldblockf_s();
//ASI_BLOCK_PRIMARY_LITTLE //ASI_BLOCK_PRIMARY_LITTLE
@ -1235,7 +1235,7 @@ decode OP default Unknown::unknown()
//ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
0x1F: FailUnimpl::stblockf_aiusl(); 0x1F: FailUnimpl::stblockf_aiusl();
//ASI_BLOCK_PRIMARY //ASI_BLOCK_PRIMARY
0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}); 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}});
//ASI_BLOCK_SECONDARY //ASI_BLOCK_SECONDARY
0xF1: FailUnimpl::stblockf_s(); 0xF1: FailUnimpl::stblockf_s();
//ASI_BLOCK_PRIMARY_LITTLE //ASI_BLOCK_PRIMARY_LITTLE
@ -1272,7 +1272,7 @@ decode OP default Unknown::unknown()
Mem.uw = Rd.uw; Mem.uw = Rd.uw;
else else
storeCond = false; storeCond = false;
Rd.uw = uReg0;}}); Rd.uw = uReg0;}}, {{EXT_ASI}});
0x3D: Nop::prefetcha({{ }}); 0x3D: Nop::prefetcha({{ }});
0x3E: Cas::casxa( 0x3E: Cas::casxa(
{{uReg0 = Mem.udw;}}, {{uReg0 = Mem.udw;}},
@ -1280,7 +1280,7 @@ decode OP default Unknown::unknown()
Mem.udw = Rd; Mem.udw = Rd;
else else
storeCond = false; storeCond = false;
Rd = uReg0;}}); Rd = uReg0;}}, {{EXT_ASI}});
} }
} }
} }

19
src/arch/sparc/isa/formats/mem/basicmem.isa
View file

@ -52,7 +52,7 @@ def template MemDeclare {{
}}; }};
let {{ let {{
def doMemFormat(code, execute, faultCode, name, Name, opt_flags): def doMemFormat(code, execute, faultCode, name, Name, asi, opt_flags):
addrCalcReg = 'EA = Rs1 + Rs2;' addrCalcReg = 'EA = Rs1 + Rs2;'
addrCalcImm = 'EA = Rs1 + imm;' addrCalcImm = 'EA = Rs1 + imm;'
iop = InstObjParams(name, Name, 'Mem', code, iop = InstObjParams(name, Name, 'Mem', code,
@ -62,25 +62,26 @@ let {{
header_output = MemDeclare.subst(iop) + MemDeclare.subst(iop_imm) header_output = MemDeclare.subst(iop) + MemDeclare.subst(iop_imm)
decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm) decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
decode_block = ROrImmDecode.subst(iop) decode_block = ROrImmDecode.subst(iop)
exec_output = doDualSplitExecute(code, addrCalcReg, addrCalcImm, execute, exec_output = doDualSplitExecute(code, addrCalcReg, addrCalcImm,
faultCode, name, name + "Imm", Name, Name + "Imm", opt_flags) execute, faultCode, name, name + "Imm", Name, Name + "Imm",
asi, opt_flags)
return (header_output, decoder_output, exec_output, decode_block) return (header_output, decoder_output, exec_output, decode_block)
}}; }};
def format LoadAlt(code, *opt_flags) {{ def format LoadAlt(code, asi, *opt_flags) {{
(header_output, (header_output,
decoder_output, decoder_output,
exec_output, exec_output,
decode_block) = doMemFormat(code, LoadExecute, decode_block) = doMemFormat(code, LoadExecute,
AlternateAsiPrivFaultCheck, name, Name, opt_flags) AlternateASIPrivFaultCheck, name, Name, asi, opt_flags)
}}; }};
def format StoreAlt(code, *opt_flags) {{ def format StoreAlt(code, asi, *opt_flags) {{
(header_output, (header_output,
decoder_output, decoder_output,
exec_output, exec_output,
decode_block) = doMemFormat(code, StoreExecute, decode_block) = doMemFormat(code, StoreExecute,
AlternateAsiPrivFaultCheck, name, Name, opt_flags) AlternateASIPrivFaultCheck, name, Name, asi, opt_flags)
}}; }};
def format Load(code, *opt_flags) {{ def format Load(code, *opt_flags) {{
@ -88,7 +89,7 @@ def format Load(code, *opt_flags) {{
decoder_output, decoder_output,
exec_output, exec_output,
decode_block) = doMemFormat(code, decode_block) = doMemFormat(code,
LoadExecute, '', name, Name, opt_flags) LoadExecute, '', name, Name, 0, opt_flags)
}}; }};
def format Store(code, *opt_flags) {{ def format Store(code, *opt_flags) {{
@ -96,5 +97,5 @@ def format Store(code, *opt_flags) {{
decoder_output, decoder_output,
exec_output, exec_output,
decode_block) = doMemFormat(code, decode_block) = doMemFormat(code,
StoreExecute, '', name, Name, opt_flags) StoreExecute, '', name, Name, 0, opt_flags)
}}; }};

12
src/arch/sparc/isa/formats/mem/blockmem.isa
View file

@ -273,7 +273,7 @@ def template BlockMemMicroConstructor {{
let {{ let {{
def doBlockMemFormat(code, faultCode, execute, name, Name, opt_flags): def doBlockMemFormat(code, faultCode, execute, name, Name, asi, opt_flags):
# XXX Need to take care of pstate.hpriv as well. The lower ASIs # XXX Need to take care of pstate.hpriv as well. The lower ASIs
# are split into ones that are available in priv and hpriv, and # are split into ones that are available in priv and hpriv, and
# those that are only available in hpriv # those that are only available in hpriv
@ -309,12 +309,12 @@ let {{
makeMicroName(name + "Imm", microPc), makeMicroName(name + "Imm", microPc),
makeMicroName(Name, microPc), makeMicroName(Name, microPc),
makeMicroName(Name + "Imm", microPc), makeMicroName(Name + "Imm", microPc),
opt_flags); asi, opt_flags);
faultCode = '' faultCode = ''
return (header_output, decoder_output, exec_output, decode_block) return (header_output, decoder_output, exec_output, decode_block)
}}; }};
def format BlockLoad(code, *opt_flags) {{ def format BlockLoad(code, asi, *opt_flags) {{
# We need to make sure to check the highest priority fault last. # We need to make sure to check the highest priority fault last.
# That way, if other faults have been detected, they'll be overwritten # That way, if other faults have been detected, they'll be overwritten
# rather than the other way around. # rather than the other way around.
@ -323,10 +323,10 @@ def format BlockLoad(code, *opt_flags) {{
decoder_output, decoder_output,
exec_output, exec_output,
decode_block) = doBlockMemFormat(code, faultCode, decode_block) = doBlockMemFormat(code, faultCode,
LoadExecute, name, Name, opt_flags) LoadExecute, name, Name, asi, opt_flags)
}}; }};
def format BlockStore(code, *opt_flags) {{ def format BlockStore(code, asi, *opt_flags) {{
# We need to make sure to check the highest priority fault last. # We need to make sure to check the highest priority fault last.
# That way, if other faults have been detected, they'll be overwritten # That way, if other faults have been detected, they'll be overwritten
# rather than the other way around. # rather than the other way around.
@ -335,5 +335,5 @@ def format BlockStore(code, *opt_flags) {{
decoder_output, decoder_output,
exec_output, exec_output,
decode_block) = doBlockMemFormat(code, faultCode, decode_block) = doBlockMemFormat(code, faultCode,
StoreExecute, name, Name, opt_flags) StoreExecute, name, Name, asi, opt_flags)
}}; }};

15
src/arch/sparc/isa/formats/mem/util.isa
View file

@ -202,7 +202,6 @@ def template StoreExecute {{
Trace::InstRecord *traceData) const Trace::InstRecord *traceData) const
{ {
Fault fault = NoFault; Fault fault = NoFault;
uint64_t write_result = 0;
//This is to support the conditional store in cas instructions. //This is to support the conditional store in cas instructions.
//It should be optomized out in all the others //It should be optomized out in all the others
bool storeCond = true; bool storeCond = true;
@ -218,7 +217,8 @@ def template StoreExecute {{
} }
if(storeCond && fault == NoFault) if(storeCond && fault == NoFault)
{ {
fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result); fault = xc->write((uint%(mem_acc_size)s_t)Mem,
EA, %(asi_val)s, 0);
} }
if(fault == NoFault) if(fault == NoFault)
{ {
@ -233,7 +233,6 @@ def template StoreExecute {{
Trace::InstRecord * traceData) const Trace::InstRecord * traceData) const
{ {
Fault fault = NoFault; Fault fault = NoFault;
uint64_t write_result = 0;
bool storeCond = true; bool storeCond = true;
Addr EA; Addr EA;
%(op_decl)s; %(op_decl)s;
@ -247,7 +246,8 @@ def template StoreExecute {{
} }
if(storeCond && fault == NoFault) if(storeCond && fault == NoFault)
{ {
fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result); fault = xc->write((uint%(mem_acc_size)s_t)Mem,
EA, %(asi_val)s, 0);
} }
if(fault == NoFault) if(fault == NoFault)
{ {
@ -309,7 +309,8 @@ let {{
//and in the other they're distributed across two. Also note that for //and in the other they're distributed across two. Also note that for
//execute functions, the name of the base class doesn't matter. //execute functions, the name of the base class doesn't matter.
let {{ let {{
def doSplitExecute(code, execute, name, Name, opt_flags, microParam): def doSplitExecute(code, execute, name, Name, asi, opt_flags, microParam):
microParam["asi_val"] = asi;
codeParam = microParam.copy() codeParam = microParam.copy()
codeParam["ea_code"] = '' codeParam["ea_code"] = ''
codeIop = InstObjParams(name, Name, '', code, opt_flags, codeParam) codeIop = InstObjParams(name, Name, '', code, opt_flags, codeParam)
@ -326,13 +327,13 @@ let {{
def doDualSplitExecute(code, eaRegCode, eaImmCode, execute, def doDualSplitExecute(code, eaRegCode, eaImmCode, execute,
faultCode, nameReg, nameImm, NameReg, NameImm, opt_flags): faultCode, nameReg, nameImm, NameReg, NameImm, asi, opt_flags):
executeCode = '' executeCode = ''
for (eaCode, name, Name) in ( for (eaCode, name, Name) in (
(eaRegCode, nameReg, NameReg), (eaRegCode, nameReg, NameReg),
(eaImmCode, nameImm, NameImm)): (eaImmCode, nameImm, NameImm)):
microParams = {"ea_code" : eaCode, "fault_check": faultCode} microParams = {"ea_code" : eaCode, "fault_check": faultCode}
executeCode += doSplitExecute(code, execute, name, Name, executeCode += doSplitExecute(code, execute, name, Name,
opt_flags, microParams) asi, opt_flags, microParams)
return executeCode return executeCode
}}; }};