another big step to a parsable ISA ... no errors after I used a symbolic link for
arch/alpha/main.isa to test my files ...
arch/mips/isa/operands.isa:
use sd and ud instead of sdw and udw
--HG--
extra : convert_revision : d66f3fd2c4a4d70e6015f0f1643c400cdfe73055
This commit is contained in:
Korey Sewell
parent
5830200d78
commit
23bbec6a34
5 changed files with 200 additions and 88 deletions
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@ -108,7 +108,7 @@ decode OPCODE_HI default Unknown::unknown() {
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xc->miscRegs.lo = Rs.uw / Rt.uw;
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}});
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}
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};
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}
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0x4: decode FUNCTION_LO {
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format IntOp {
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@ -128,7 +128,7 @@ decode OPCODE_HI default Unknown::unknown() {
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0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
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0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
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}
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};
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}
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0x6: decode FUNCTION_LO {
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format Trap {
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@ -144,13 +144,13 @@ decode OPCODE_HI default Unknown::unknown() {
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0x1: decode REGIMM_HI {
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0x0: decode REGIMM_LO {
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format Branch {
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0x0: bltz({{ cond = (Rs.sq < 0); }});
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0x1: bgez({{ cond = (Rs.sq >= 0); }});
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format CondBranch {
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0x0: bltz({{ cond = (Rs.sw < 0); }});
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0x1: bgez({{ cond = (Rs.sw >= 0); }});
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//MIPS obsolete instructions
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0x2: bltzl({{ cond = (Rs.sq < 0); }});
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0x3: bgezl({{ cond = (Rs.sq >= 0); }});
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0x2: bltzl({{ cond = (Rs.sw < 0); }});
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0x3: bgezl({{ cond = (Rs.sw >= 0); }});
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}
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}
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@ -166,19 +166,19 @@ decode OPCODE_HI default Unknown::unknown() {
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}
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0x2: decode REGIMM_LO {
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format Branch {
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0x0: bltzal({{ cond = (Rs.sq < 0); }});
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0x1: bgezal({{ cond = (Rs.sq >= 0); }});
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format CondBranch {
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0x0: bltzal({{ cond = (Rs.sw < 0); }});
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0x1: bgezal({{ cond = (Rs.sw >= 0); }});
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//MIPS obsolete instructions
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0x2: bltzall({{ cond = (Rs.sq < 0); }});
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0x3: bgezall({{ cond = (Rs.sq >= 0); }});
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0x2: bltzall({{ cond = (Rs.sw < 0); }});
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0x3: bgezall({{ cond = (Rs.sw >= 0); }});
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}
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}
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0x3: decode REGIMM_LO {
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format WarnUnimpl {
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0x7: synci({{ }});
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0x7: synci();
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}
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}
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}
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@ -188,13 +188,13 @@ decode OPCODE_HI default Unknown::unknown() {
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0x3: jal(IsCall);
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}
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format Branch {
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0x4: beq({{ cond = (Rs.sq == 0); }});
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0x5: bne({{ cond = (Rs.sq != 0); }});
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0x6: blez({{ cond = (Rs.sq <= 0); }});
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0x7: bgtz({{ cond = (Rs.sq > 0); }});
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format CondBranch {
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0x4: beq({{ cond = (Rs.sw == 0); }});
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0x5: bne({{ cond = (Rs.sw != 0); }});
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0x6: blez({{ cond = (Rs.sw <= 0); }});
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0x7: bgtz({{ cond = (Rs.sw > 0); }});
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}
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};
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}
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0x1: decode OPCODE_LO default FailUnimpl::reserved(){
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format IntOp {
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@ -206,8 +206,8 @@ decode OPCODE_HI default Unknown::unknown() {
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0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}});
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0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}});
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0x7: lui({{ Rt = INTIMM << 16}});
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};
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};
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}
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}
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0x2: decode OPCODE_LO default FailUnimpl::reserved(){
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@ -336,9 +336,9 @@ decode OPCODE_HI default Unknown::unknown() {
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}
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format WarnUnimpl {
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0x18: eret({{ }});
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0x1F: deret({{ }});
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0x20: wait({{ }});
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0x18: eret();
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0x1F: deret();
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0x20: wait();
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}
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}
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}
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@ -360,14 +360,14 @@ decode OPCODE_HI default Unknown::unknown() {
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0x1: decode ND {
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0x0: decode TF {
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format Branch {
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format CondBranch {
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0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }});
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0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }});
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}
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}
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0x1: decode TF {
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format Branch {
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format CondBranch {
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0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }});
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0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }});
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}
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@ -395,7 +395,7 @@ decode OPCODE_HI default Unknown::unknown() {
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}
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0x1: decode RS_LO {
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//only legal for 64 bit
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//only legal for 64 bit-FP
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format Float64Op {
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0x0: round_l_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_LONG,FP_SINGLE);}});
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0x1: trunc_l_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_LONG,FP_SINGLE);}});
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@ -426,18 +426,21 @@ decode OPCODE_HI default Unknown::unknown() {
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format Float64Op {
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0x2: recips({{ Fd = 1 / Fs; }});
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0x3: rsqrts{{ Fd = 1 / sqrt(Fs); }});
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0x3: rsqrts({{ Fd = 1 / sqrt(Fs.ud);}});
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}
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}
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0x4: decode RS_LO {
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0x1: cvt_d_s({{ int rnd_mode = xc->miscRegs.fcsr;
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format FloatOp {
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0x1: cvt_d_s({{ int rnd_mode = xc->miscRegs.fcsr;
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Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE);
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}});
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0x4: cvt_w_s({{ int rnd_mode = xc->miscRegs.fcsr;
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0x4: cvt_w_s({{ int rnd_mode = xc->miscRegs.fcsr;
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Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE);
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}});
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}
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//only legal for 64 bit
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format Float64Op {
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@ -467,7 +470,7 @@ decode OPCODE_HI default Unknown::unknown() {
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0x1: decode RS_LO {
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//only legal for 64 bit
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format FloatOp64 {
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format Float64Op {
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0x0: round_l_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }});
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0x1: trunc_l_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE);}});
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0x2: ceil_l_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE);}});
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@ -495,9 +498,9 @@ decode OPCODE_HI default Unknown::unknown() {
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0x3: movn({{ if (Rt != 0) Fd.df = Fs.df; }});
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}
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format FloatOp64 {
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format Float64Op {
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0x5: recipd({{ Fd.df = 1 / Fs.df}});
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0x6: rsqrtd{{ Fd.df = 1 / sqrt(Fs.df) }});
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0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }});
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}
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}
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@ -515,7 +518,7 @@ decode OPCODE_HI default Unknown::unknown() {
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}
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//only legal for 64 bit
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format FloatOp64 {
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format Float64Op {
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0x5: cvt_l_d({{
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int rnd_mode = xc->miscRegs.fcsr;
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Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE);
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@ -561,7 +564,7 @@ decode OPCODE_HI default Unknown::unknown() {
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//are enabled. "
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0x6: decode RS_HI {
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0x0: decode RS_LO {
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format FloatOp64 {
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format Float64Op {
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0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
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//Lower Halves Independently but we take simulator shortcut
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Fd.df = Fs.df + Ft.df;
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@ -596,23 +599,23 @@ decode OPCODE_HI default Unknown::unknown() {
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0x2: decode RS_LO {
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0x1: decode MOVCF {
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format FloatOp64 {
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0x0: movfps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}})
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0x1: movtps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}})
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format Float64Op {
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0x0: movfps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}});
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0x1: movtps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}});
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}
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}
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}
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0x4: decode RS_LO {
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0x0: FloatOp64::cvt_s_pu({{
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0x0: Float64Op::cvt_s_pu({{
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int rnd_mode = xc->miscRegs.fcsr;
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Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI);
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}});
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}
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0x5: decode RS_LO {
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format FloatOp64 {
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format Float64Op {
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0x0: cvt_s_pl({{
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int rnd_mode = xc->miscRegs.fcsr;
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Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO);
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@ -631,27 +634,27 @@ decode OPCODE_HI default Unknown::unknown() {
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0x0: decode RS_HI {
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0x0: decode RS_LO {
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format WarnUnimpl {
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0x0: mfc2({{ }});
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0x2: cfc2({{ }});
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0x3: mfhc2({{ }});
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0x4: mtc2({{ }});
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0x6: ctc2({{ }});
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0x7: mftc2({{ }});
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0x0: mfc2();
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0x2: cfc2();
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0x3: mfhc2();
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0x4: mtc2();
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0x6: ctc2();
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0x7: mftc2();
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}
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}
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0x1: decode ND {
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0x0: decode TF {
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format WarnUnimpl {
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0x0: bc2f({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2);
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0x1: bc2t({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
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0x0: bc2f();
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0x1: bc2t();
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}
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}
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0x1: decode TF {
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format WarnUnimpl {
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0x0: bc2fl({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2}});
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0x1: bc2tl({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
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0x0: bc2fl();
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0x1: bc2tl();
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}
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}
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}
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@ -681,12 +684,13 @@ decode OPCODE_HI default Unknown::unknown() {
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EA = Rs + Rt;
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}},
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{{ Mem.df = Ft<63:0>;}});
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0x7: prefx({{ }});
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}
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0x7: WarnUnimpl::prefx();
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}
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format FloatOp {
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0x3: WarnUnimpl::alnv_ps({{ }});
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0x3: WarnUnimpl::alnv_ps();
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format BasicOp {
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0x4: decode FUNCTION_LO {
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@ -733,13 +737,13 @@ decode OPCODE_HI default Unknown::unknown() {
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}
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//MIPS obsolete instructions
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format Branch {
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0x4: beql({{ cond = (Rs.sq == 0); }});
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0x5: bnel({{ cond = (Rs.sq != 0); }});
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0x6: blezl({{ cond = (Rs.sq <= 0); }});
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0x7: bgtzl({{ cond = (Rs.sq > 0); }});
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format CondBranch {
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0x4: beql({{ cond = (Rs.sw == 0); }});
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0x5: bnel({{ cond = (Rs.sw != 0); }});
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0x6: blezl({{ cond = (Rs.sw <= 0); }});
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0x7: bgtzl({{ cond = (Rs.sw > 0); }});
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}
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};
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}
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0x3: decode OPCODE_LO default FailUnimpl::reserved() {
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@ -807,7 +811,7 @@ decode OPCODE_HI default Unknown::unknown() {
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}
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0x7: decode FUNCTION_LO {
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0x7: WarnUnimpl::sdbbp({{ }});
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0x7: WarnUnimpl::sdbbp();
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}
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}
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@ -816,15 +820,15 @@ decode OPCODE_HI default Unknown::unknown() {
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0x0: decode FUNCTION_LO {
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format WarnUnimpl {
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0x1: ext({{ }});
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0x4: ins({{ }});
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0x1: ext();
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0x4: ins();
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}
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}
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0x1: decode FUNCTION_LO {
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format WarnUnimpl {
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0x0: fork({{ }});
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0x1: yield({{ }});
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0x0: fork();
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0x1: yield();
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}
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}
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@ -832,7 +836,7 @@ decode OPCODE_HI default Unknown::unknown() {
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//Table A-10 MIPS32 BSHFL Encoding of sa Field
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0x4: decode SA {
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0x02: WarnUnimpl::wsbh({{ }});
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0x02: WarnUnimpl::wsbh();
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format BasicOp {
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0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24) | */ Rt<7:0>}});
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@ -844,53 +848,53 @@ decode OPCODE_HI default Unknown::unknown() {
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0x7: BasicOp::rdhwr({{ Rt = xc->hwRegs[RD];}});
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}
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}
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};
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}
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0x4: decode OPCODE_LO default FailUnimpl::reserved() {
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format Memory {
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0x0: lb({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sb; }});
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0x1: lh({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sh; }});
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0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }}, WordAlign);
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0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }});//, WordAlign);
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0x3: lw({{ EA = Rs + disp; }}, {{ Rb.uq = Mem.sb; }});
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0x4: lbu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.ub; }});
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0x5: lhu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uh; }});
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0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }}, WordAlign);
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};
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0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }});//, WordAlign);
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}
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0x7: FailUnimpl::reserved({{ }});
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};
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0x7: FailUnimpl::reserved();
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}
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0x5: decode OPCODE_LO default FailUnimpl::reserved() {
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format Memory {
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0x0: sb({{ EA = Rs + disp; }}, {{ Mem.ub = Rt<7:0>; }});
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0x1: sh({{ EA = Rs + disp; }},{{ Mem.uh = Rt<15:0>; }});
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0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign);
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0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});//,WordAlign);
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0x3: sw({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});
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0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign);
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};
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0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});//,WordAlign);
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}
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format WarnUnimpl {
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0x7: cache({{ }});
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};
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0x7: cache();
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}
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};
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}
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0x6: decode OPCODE_LO default FailUnimpl::reserved() {
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0x0: WarnUnimpl::ll({{ }});
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0x0: WarnUnimpl::ll();
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format Memory {
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0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }});
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0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }});
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};
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};
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}
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}
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0x7: decode OPCODE_LO default FailUnimpl::reserved() {
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0x0: WarnUnimpl::sc({{ }});
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0x0: WarnUnimpl::sc();
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format Memory {
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0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }});
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0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }});
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};
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}
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}
|
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}
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@ output decoder {{
|
|||
}
|
||||
}};
|
||||
|
||||
def template FPExecute {{
|
||||
def template FloatingPointExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
||||
{
|
||||
//These are set to constants when the execute method
|
||||
|
|
@ -70,7 +70,7 @@ def template FPExecute {{
|
|||
}};
|
||||
|
||||
// Primary format for integer operate instructions:
|
||||
def format FPOp(code, *opt_flags) {{
|
||||
def format FloatOp(code, *opt_flags) {{
|
||||
orig_code = code
|
||||
cblk = CodeBlock(code)
|
||||
checkPriv = (code.find('checkPriv') != -1)
|
||||
|
|
@ -86,12 +86,33 @@ def format FPOp(code, *opt_flags) {{
|
|||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecodeWithMnemonic.subst(iop)
|
||||
exec_output = IntegerExecute.subst(iop)
|
||||
exec_output = FloatingPointExecute.subst(iop)
|
||||
}};
|
||||
|
||||
// Primary format for integer operate instructions:
|
||||
def format Float64Op(code, *opt_flags) {{
|
||||
orig_code = code
|
||||
cblk = CodeBlock(code)
|
||||
checkPriv = (code.find('checkPriv') != -1)
|
||||
code.replace('checkPriv', '')
|
||||
if checkPriv:
|
||||
code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
|
||||
else:
|
||||
code.replace('checkPriv;', '')
|
||||
for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
|
||||
('xvValue', '0'), ('xcValue', '0')):
|
||||
code.replace(marker, value)
|
||||
iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecodeWithMnemonic.subst(iop)
|
||||
exec_output = FloatingPointExecute.subst(iop)
|
||||
}};
|
||||
|
||||
// Primary format for integer operate instructions:
|
||||
def format FPOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
|
||||
orig_code = code
|
||||
|
||||
cblk = CodeBlock(code)
|
||||
checkPriv = (code.find('checkPriv') != -1)
|
||||
code.replace('checkPriv', '')
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@ def template MemExecute {{
|
|||
}};
|
||||
|
||||
// Primary format for integer operate instructions:
|
||||
def format Mem(code, *opt_flags) {{
|
||||
def format Memory(code, ea_code = {{ EA = Rb + disp; }},*opt_flags) {{
|
||||
orig_code = code
|
||||
cblk = CodeBlock(code)
|
||||
iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
|
||||
|
|
|
|||
|
|
@ -45,3 +45,90 @@ def format Noop(code, *opt_flags) {{
|
|||
decode_block = BasicDecodeWithMnemonic.subst(iop)
|
||||
exec_output = NoopExecute.subst(iop)
|
||||
}};
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Nop
|
||||
//
|
||||
|
||||
output header {{
|
||||
/**
|
||||
* Static instruction class for no-ops. This is a leaf class.
|
||||
*/
|
||||
class Nop : public AlphaStaticInst
|
||||
{
|
||||
/// Disassembly of original instruction.
|
||||
const std::string originalDisassembly;
|
||||
|
||||
public:
|
||||
/// Constructor
|
||||
Nop(const std::string _originalDisassembly, MachInst _machInst)
|
||||
: AlphaStaticInst("nop", _machInst, No_OpClass),
|
||||
originalDisassembly(_originalDisassembly)
|
||||
{
|
||||
flags[IsNop] = true;
|
||||
}
|
||||
|
||||
~Nop() { }
|
||||
|
||||
std::string
|
||||
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
|
||||
%(BasicExecDeclare)s
|
||||
};
|
||||
}};
|
||||
|
||||
output decoder {{
|
||||
std::string Nop::generateDisassembly(Addr pc,
|
||||
const SymbolTable *symtab) const
|
||||
{
|
||||
#ifdef SS_COMPATIBLE_DISASSEMBLY
|
||||
return originalDisassembly;
|
||||
#else
|
||||
return csprintf("%-10s (%s)", "nop", originalDisassembly);
|
||||
#endif
|
||||
}
|
||||
|
||||
/// Helper function for decoding nops. Substitute Nop object
|
||||
/// for original inst passed in as arg (and delete latter).
|
||||
inline
|
||||
AlphaStaticInst *
|
||||
makeNop(AlphaStaticInst *inst)
|
||||
{
|
||||
AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
|
||||
delete inst;
|
||||
return nop;
|
||||
}
|
||||
}};
|
||||
|
||||
output exec {{
|
||||
Fault
|
||||
Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
|
||||
{
|
||||
return No_Fault;
|
||||
}
|
||||
}};
|
||||
|
||||
// integer & FP operate instructions use Rc as dest, so check for
|
||||
// Rc == 31 to detect nops
|
||||
def template OperateNopCheckDecode {{
|
||||
{
|
||||
AlphaStaticInst *i = new %(class_name)s(machInst);
|
||||
if (RC == 31) {
|
||||
i = makeNop(i);
|
||||
}
|
||||
return i;
|
||||
}
|
||||
}};
|
||||
|
||||
|
||||
// Like BasicOperate format, but generates NOP if RC/FC == 31
|
||||
def format BasicOperateWithNopCheck(code, *opt_args) {{
|
||||
iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
|
||||
opt_args)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = OperateNopCheckDecode.subst(iop)
|
||||
exec_output = BasicExecute.subst(iop)
|
||||
}};
|
||||
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@ def operand_types {{
|
|||
'uhw' : ('unsigned int', 16),
|
||||
'sw' : ('signed int', 32),
|
||||
'uw' : ('unsigned int', 32),
|
||||
'sdw' : ('signed int', 64),
|
||||
'udw' : ('unsigned int', 64),
|
||||
'sd' : ('signed int', 64),
|
||||
'ud' : ('unsigned int', 64),
|
||||
'sf' : ('float', 32),
|
||||
'df' : ('float', 64),
|
||||
'qf' : ('float', 128)
|
||||
|
|
@ -24,7 +24,7 @@ def operands {{
|
|||
'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
|
||||
'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
|
||||
|
||||
'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4)
|
||||
'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4)
|
||||
|
||||
#'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
|
||||
#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
|
||||
|
|
|
|||
Loading…
Reference in a new issue