SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.
This commit is contained in:
parent
7b417d4188
commit
239b33e016
15 changed files with 190 additions and 244 deletions
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@ -56,11 +56,16 @@ if env['TARGET_ISA'] == 'arm':
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Source('insts/vfp.cc')
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Source('insts/vfp.cc')
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Source('interrupts.cc')
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Source('interrupts.cc')
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Source('isa.cc')
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Source('isa.cc')
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Source('linux/linux.cc')
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Source('linux/process.cc')
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Source('linux/system.cc')
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Source('miscregs.cc')
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Source('miscregs.cc')
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Source('nativetrace.cc')
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Source('nativetrace.cc')
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Source('predecoder.cc')
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Source('predecoder.cc')
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Source('process.cc')
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Source('remote_gdb.cc')
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Source('remote_gdb.cc')
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Source('stacktrace.cc')
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Source('stacktrace.cc')
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Source('system.cc')
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Source('table_walker.cc')
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Source('table_walker.cc')
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Source('tlb.cc')
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Source('tlb.cc')
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Source('utility.cc')
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Source('utility.cc')
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@ -68,21 +73,13 @@ if env['TARGET_ISA'] == 'arm':
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SimObject('ArmInterrupts.py')
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SimObject('ArmInterrupts.py')
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SimObject('ArmNativeTrace.py')
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SimObject('ArmNativeTrace.py')
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SimObject('ArmSystem.py')
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SimObject('ArmTLB.py')
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SimObject('ArmTLB.py')
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DebugFlag('Arm')
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DebugFlag('Arm')
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DebugFlag('TLBVerbose')
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DebugFlag('TLBVerbose')
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DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
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DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
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DebugFlag('Predecoder', "Instructions returned by the predecoder")
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DebugFlag('Predecoder', "Instructions returned by the predecoder")
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if env['FULL_SYSTEM']:
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Source('system.cc')
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Source('linux/system.cc')
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SimObject('ArmSystem.py')
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else:
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Source('process.cc')
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Source('linux/linux.cc')
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Source('linux/process.cc')
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# Add in files generated by the ISA description.
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# Add in files generated by the ISA description.
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isa_desc_files = env.ISADesc('isa/main.isa')
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isa_desc_files = env.ISADesc('isa/main.isa')
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@ -47,6 +47,7 @@
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#include "cpu/base.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/thread_context.hh"
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#include "debug/Faults.hh"
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#include "debug/Faults.hh"
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#include "sim/full_system.hh"
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namespace ArmISA
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namespace ArmISA
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{
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{
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@ -94,13 +95,13 @@ ArmFault::getVector(ThreadContext *tc)
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}
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}
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#if FULL_SYSTEM
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void
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void
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ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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{
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// ARM ARM B1.6.3
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// ARM ARM B1.6.3
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FaultBase::invoke(tc);
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FaultBase::invoke(tc);
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if (!FullSystem)
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return;
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countStat()++;
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countStat()++;
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SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
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SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
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@ -165,16 +166,19 @@ ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
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void
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void
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Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
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Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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{
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if (FullSystem) {
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tc->getCpuPtr()->clearInterrupts();
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tc->getCpuPtr()->clearInterrupts();
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tc->clearArchRegs();
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tc->clearArchRegs();
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}
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ArmFault::invoke(tc, inst);
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ArmFault::invoke(tc, inst);
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}
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}
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#else
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void
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void
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UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
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UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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{
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if (FullSystem) {
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ArmFault::invoke(tc, inst);
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} else {
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// If the mnemonic isn't defined this has to be an unknown instruction.
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// If the mnemonic isn't defined this has to be an unknown instruction.
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assert(unknown || mnemonic != NULL);
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assert(unknown || mnemonic != NULL);
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if (disabled) {
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if (disabled) {
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@ -187,11 +191,15 @@ UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
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panic("Attempted to execute unimplemented instruction "
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panic("Attempted to execute unimplemented instruction "
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"'%s' (inst 0x%08x)", mnemonic, machInst);
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"'%s' (inst 0x%08x)", mnemonic, machInst);
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}
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}
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}
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}
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}
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void
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void
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SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
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SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
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{
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{
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if (FullSystem) {
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ArmFault::invoke(tc, inst);
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} else {
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// As of now, there isn't a 32 bit thumb version of this instruction.
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// As of now, there isn't a 32 bit thumb version of this instruction.
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assert(!machInst.bigThumb);
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assert(!machInst.bigThumb);
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uint32_t callNum;
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uint32_t callNum;
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@ -203,10 +211,9 @@ SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
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assert(inst);
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assert(inst);
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inst->advancePC(pc);
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inst->advancePC(pc);
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tc->pcState(pc);
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tc->pcState(pc);
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}
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}
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}
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#endif // FULL_SYSTEM
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template<class T>
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template<class T>
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void
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void
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AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
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AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
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@ -245,13 +252,13 @@ template void AbortFault<DataAbort>::invoke(ThreadContext *tc,
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void
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void
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ArmSev::invoke(ThreadContext *tc, StaticInstPtr inst) {
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ArmSev::invoke(ThreadContext *tc, StaticInstPtr inst) {
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DPRINTF(Faults, "Invoking ArmSev Fault\n");
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DPRINTF(Faults, "Invoking ArmSev Fault\n");
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#if FULL_SYSTEM
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if (FullSystem) {
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// Set sev_mailbox to 1, clear the pending interrupt from remote
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// Set sev_mailbox to 1, clear the pending interrupt from remote
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// SEV execution and let pipeline continue as pcState is still
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// SEV execution and let pipeline continue as pcState is still
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// valid.
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// valid.
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tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
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tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
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tc->getCpuPtr()->clearInterrupt(INT_SEV, 0);
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tc->getCpuPtr()->clearInterrupt(INT_SEV, 0);
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#endif
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}
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}
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}
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// return via SUBS pc, lr, xxx; rfe, movs, ldm
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// return via SUBS pc, lr, xxx; rfe, movs, ldm
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@ -48,8 +48,8 @@
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#include "arch/arm/miscregs.hh"
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#include "arch/arm/miscregs.hh"
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#include "arch/arm/types.hh"
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#include "arch/arm/types.hh"
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#include "base/misc.hh"
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#include "base/misc.hh"
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#include "config/full_system.hh"
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#include "sim/faults.hh"
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#include "sim/faults.hh"
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#include "sim/full_system.hh"
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// The design of the "name" and "vect" functions is in sim/faults.hh
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// The design of the "name" and "vect" functions is in sim/faults.hh
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@ -108,10 +108,8 @@ class ArmFault : public FaultBase
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FaultStat count;
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FaultStat count;
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};
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};
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#if FULL_SYSTEM
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void invoke(ThreadContext *tc,
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void invoke(ThreadContext *tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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#endif
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virtual FaultStat& countStat() = 0;
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virtual FaultStat& countStat() = 0;
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virtual FaultOffset offset() = 0;
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virtual FaultOffset offset() = 0;
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virtual OperatingMode nextMode() = 0;
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virtual OperatingMode nextMode() = 0;
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@ -139,19 +137,14 @@ class ArmFaultVals : public ArmFault
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};
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};
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class Reset : public ArmFaultVals<Reset>
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class Reset : public ArmFaultVals<Reset>
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#if FULL_SYSTEM
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{
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{
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public:
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public:
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void invoke(ThreadContext *tc,
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void invoke(ThreadContext *tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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};
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};
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#else
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{};
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#endif //FULL_SYSTEM
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class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
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class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
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{
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{
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#if !FULL_SYSTEM
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protected:
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protected:
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ExtMachInst machInst;
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ExtMachInst machInst;
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bool unknown;
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bool unknown;
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@ -167,25 +160,27 @@ class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
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mnemonic(_mnemonic), disabled(_disabled)
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mnemonic(_mnemonic), disabled(_disabled)
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{
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{
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}
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}
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UndefinedInstruction() :
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machInst(0), unknown(false), mnemonic("undefined"), disabled(false)
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{}
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void invoke(ThreadContext *tc,
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void invoke(ThreadContext *tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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#endif
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};
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};
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class SupervisorCall : public ArmFaultVals<SupervisorCall>
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class SupervisorCall : public ArmFaultVals<SupervisorCall>
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{
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{
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#if !FULL_SYSTEM
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protected:
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protected:
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ExtMachInst machInst;
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ExtMachInst machInst;
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public:
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public:
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SupervisorCall(ExtMachInst _machInst) : machInst(_machInst)
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SupervisorCall(ExtMachInst _machInst) : machInst(_machInst)
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{}
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{}
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SupervisorCall() : machInst(0)
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{}
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void invoke(ThreadContext *tc,
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void invoke(ThreadContext *tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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#endif
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};
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};
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template <class T>
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template <class T>
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@ -46,6 +46,7 @@
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#include "arch/arm/utility.hh"
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#include "arch/arm/utility.hh"
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#include "base/trace.hh"
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#include "base/trace.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/static_inst.hh"
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#include "sim/full_system.hh"
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namespace ArmISA
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namespace ArmISA
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{
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{
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@ -294,11 +295,11 @@ class ArmStaticInst : public StaticInst
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inline Fault
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inline Fault
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disabledFault() const
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disabledFault() const
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{
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{
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#if FULL_SYSTEM
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if (FullSystem) {
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return new UndefinedInstruction();
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return new UndefinedInstruction();
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#else
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} else {
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return new UndefinedInstruction(machInst, false, mnemonic, true);
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return new UndefinedInstruction(machInst, false, mnemonic, true);
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#endif
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}
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}
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}
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};
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};
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}
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}
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@ -1103,7 +1103,6 @@ def format ArmMisc() {{
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switch (IMM) {
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switch (IMM) {
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case 0x0:
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case 0x0:
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return new NopInst(machInst);
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return new NopInst(machInst);
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#if FULL_SYSTEM
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case 0x1:
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case 0x1:
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return new YieldInst(machInst);
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return new YieldInst(machInst);
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case 0x2:
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case 0x2:
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@ -1112,7 +1111,6 @@ def format ArmMisc() {{
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return new WfiInst(machInst);
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return new WfiInst(machInst);
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case 0x4:
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case 0x4:
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return new SevInst(machInst);
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return new SevInst(machInst);
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#endif
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default:
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default:
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return new Unknown(machInst);
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return new Unknown(machInst);
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}
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}
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@ -42,35 +42,27 @@ def format M5ops() {{
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{
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{
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const uint32_t m5func = bits(machInst, 23, 16);
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const uint32_t m5func = bits(machInst, 23, 16);
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switch(m5func) {
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switch(m5func) {
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#if FULL_SYSTEM
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case 0x00: return new Arm(machInst);
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case 0x00: return new Arm(machInst);
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case 0x01: return new Quiesce(machInst);
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case 0x01: return new Quiesce(machInst);
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case 0x02: return new QuiesceNs(machInst);
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case 0x02: return new QuiesceNs(machInst);
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case 0x03: return new QuiesceCycles(machInst);
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case 0x03: return new QuiesceCycles(machInst);
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case 0x04: return new QuiesceTime(machInst);
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case 0x04: return new QuiesceTime(machInst);
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#endif
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case 0x07: return new Rpns(machInst);
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case 0x07: return new Rpns(machInst);
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case 0x09: return new WakeCPU(machInst);
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case 0x09: return new WakeCPU(machInst);
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case 0x10: return new Deprecated_ivlb(machInst);
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case 0x10: return new Deprecated_ivlb(machInst);
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case 0x11: return new Deprecated_ivle(machInst);
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case 0x11: return new Deprecated_ivle(machInst);
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case 0x20: return new Deprecated_exit (machInst);
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case 0x20: return new Deprecated_exit (machInst);
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case 0x21: return new M5exit(machInst);
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case 0x21: return new M5exit(machInst);
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#if FULL_SYSTEM
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case 0x31: return new Loadsymbol(machInst);
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case 0x31: return new Loadsymbol(machInst);
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case 0x30: return new Initparam(machInst);
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case 0x30: return new Initparam(machInst);
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#endif
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case 0x40: return new Resetstats(machInst);
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case 0x40: return new Resetstats(machInst);
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case 0x41: return new Dumpstats(machInst);
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case 0x41: return new Dumpstats(machInst);
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case 0x42: return new Dumpresetstats(machInst);
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case 0x42: return new Dumpresetstats(machInst);
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case 0x43: return new M5checkpoint(machInst);
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case 0x43: return new M5checkpoint(machInst);
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#if FULL_SYSTEM
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case 0x50: return new M5readfile(machInst);
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case 0x50: return new M5readfile(machInst);
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#endif
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case 0x51: return new M5break(machInst);
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case 0x51: return new M5break(machInst);
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case 0x52: return new M5switchcpu(machInst);
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case 0x52: return new M5switchcpu(machInst);
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#if FULL_SYSTEM
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case 0x53: return new M5addsymbol(machInst);
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case 0x53: return new M5addsymbol(machInst);
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#endif
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case 0x54: return new M5panic(machInst);
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case 0x54: return new M5panic(machInst);
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case 0x5a: return new M5workbegin(machInst);
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case 0x5a: return new M5workbegin(machInst);
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case 0x5b: return new M5workend(machInst);
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case 0x5b: return new M5workend(machInst);
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@ -147,11 +147,10 @@ output exec {{
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FailUnimplemented::execute(%(CPU_exec_context)s *xc,
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FailUnimplemented::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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Trace::InstRecord *traceData) const
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{
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{
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#if FULL_SYSTEM
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if (FullSystem)
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return new UndefinedInstruction;
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return new UndefinedInstruction;
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#else
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else
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return new UndefinedInstruction(machInst, false, mnemonic);
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return new UndefinedInstruction(machInst, false, mnemonic);
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#endif
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}
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}
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Fault
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Fault
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@ -41,11 +41,10 @@ let {{
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sdivCode = '''
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sdivCode = '''
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if (Op2_sw == 0) {
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if (Op2_sw == 0) {
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if (((SCTLR)Sctlr).dz) {
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if (((SCTLR)Sctlr).dz) {
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#if FULL_SYSTEM
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if (FullSystem)
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return new UndefinedInstruction;
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return new UndefinedInstruction;
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#else
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else
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return new UndefinedInstruction(false, mnemonic);
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return new UndefinedInstruction(false, mnemonic);
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||||||
#endif
|
|
||||||
}
|
}
|
||||||
Dest_sw = 0;
|
Dest_sw = 0;
|
||||||
} else if (Op1_sw == INT_MIN && Op2_sw == -1) {
|
} else if (Op1_sw == INT_MIN && Op2_sw == -1) {
|
||||||
|
@ -65,11 +64,10 @@ let {{
|
||||||
udivCode = '''
|
udivCode = '''
|
||||||
if (Op2_uw == 0) {
|
if (Op2_uw == 0) {
|
||||||
if (((SCTLR)Sctlr).dz) {
|
if (((SCTLR)Sctlr).dz) {
|
||||||
#if FULL_SYSTEM
|
if (FullSystem)
|
||||||
return new UndefinedInstruction;
|
return new UndefinedInstruction;
|
||||||
#else
|
else
|
||||||
return new UndefinedInstruction(false, mnemonic);
|
return new UndefinedInstruction(false, mnemonic);
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
Dest_uw = 0;
|
Dest_uw = 0;
|
||||||
} else {
|
} else {
|
||||||
|
|
|
@ -54,9 +54,7 @@ let {{
|
||||||
|
|
||||||
|
|
||||||
armCode = '''
|
armCode = '''
|
||||||
#if FULL_SYSTEM
|
|
||||||
PseudoInst::arm(xc->tcBase());
|
PseudoInst::arm(xc->tcBase());
|
||||||
#endif
|
|
||||||
'''
|
'''
|
||||||
armIop = InstObjParams("arm", "Arm", "PredOp",
|
armIop = InstObjParams("arm", "Arm", "PredOp",
|
||||||
{ "code": armCode,
|
{ "code": armCode,
|
||||||
|
@ -67,9 +65,7 @@ let {{
|
||||||
exec_output += PredOpExecute.subst(armIop)
|
exec_output += PredOpExecute.subst(armIop)
|
||||||
|
|
||||||
quiesceCode = '''
|
quiesceCode = '''
|
||||||
#if FULL_SYSTEM
|
|
||||||
PseudoInst::quiesce(xc->tcBase());
|
PseudoInst::quiesce(xc->tcBase());
|
||||||
#endif
|
|
||||||
'''
|
'''
|
||||||
quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp",
|
quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp",
|
||||||
{ "code": quiesceCode,
|
{ "code": quiesceCode,
|
||||||
|
@ -80,9 +76,7 @@ let {{
|
||||||
exec_output += QuiescePredOpExecute.subst(quiesceIop)
|
exec_output += QuiescePredOpExecute.subst(quiesceIop)
|
||||||
|
|
||||||
quiesceNsCode = '''
|
quiesceNsCode = '''
|
||||||
#if FULL_SYSTEM
|
|
||||||
PseudoInst::quiesceNs(xc->tcBase(), join32to64(R1, R0));
|
PseudoInst::quiesceNs(xc->tcBase(), join32to64(R1, R0));
|
||||||
#endif
|
|
||||||
'''
|
'''
|
||||||
|
|
||||||
quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp",
|
quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp",
|
||||||
|
@ -94,9 +88,7 @@ let {{
|
||||||
exec_output += QuiescePredOpExecute.subst(quiesceNsIop)
|
exec_output += QuiescePredOpExecute.subst(quiesceNsIop)
|
||||||
|
|
||||||
quiesceCyclesCode = '''
|
quiesceCyclesCode = '''
|
||||||
#if FULL_SYSTEM
|
|
||||||
PseudoInst::quiesceCycles(xc->tcBase(), join32to64(R1, R0));
|
PseudoInst::quiesceCycles(xc->tcBase(), join32to64(R1, R0));
|
||||||
#endif
|
|
||||||
'''
|
'''
|
||||||
|
|
||||||
quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles", "PredOp",
|
quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles", "PredOp",
|
||||||
|
@ -108,11 +100,9 @@ let {{
|
||||||
exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop)
|
exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop)
|
||||||
|
|
||||||
quiesceTimeCode = '''
|
quiesceTimeCode = '''
|
||||||
#if FULL_SYSTEM
|
|
||||||
uint64_t qt_val = PseudoInst::quiesceTime(xc->tcBase());
|
uint64_t qt_val = PseudoInst::quiesceTime(xc->tcBase());
|
||||||
R0 = bits(qt_val, 31, 0);
|
R0 = bits(qt_val, 31, 0);
|
||||||
R1 = bits(qt_val, 63, 32);
|
R1 = bits(qt_val, 63, 32);
|
||||||
#endif
|
|
||||||
'''
|
'''
|
||||||
|
|
||||||
quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp",
|
quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp",
|
||||||
|
@ -188,9 +178,7 @@ let {{
|
||||||
exec_output += PredOpExecute.subst(m5exitIop)
|
exec_output += PredOpExecute.subst(m5exitIop)
|
||||||
|
|
||||||
loadsymbolCode = '''
|
loadsymbolCode = '''
|
||||||
#if FULL_SYSTEM
|
|
||||||
PseudoInst::loadsymbol(xc->tcBase());
|
PseudoInst::loadsymbol(xc->tcBase());
|
||||||
#endif
|
|
||||||
'''
|
'''
|
||||||
|
|
||||||
loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp",
|
loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp",
|
||||||
|
@ -202,9 +190,7 @@ let {{
|
||||||
exec_output += PredOpExecute.subst(loadsymbolIop)
|
exec_output += PredOpExecute.subst(loadsymbolIop)
|
||||||
|
|
||||||
initparamCode = '''
|
initparamCode = '''
|
||||||
#if FULL_SYSTEM
|
|
||||||
Rt = PseudoInst::initParam(xc->tcBase());
|
Rt = PseudoInst::initParam(xc->tcBase());
|
||||||
#endif
|
|
||||||
'''
|
'''
|
||||||
|
|
||||||
initparamIop = InstObjParams("initparam", "Initparam", "PredOp",
|
initparamIop = InstObjParams("initparam", "Initparam", "PredOp",
|
||||||
|
@ -260,11 +246,9 @@ let {{
|
||||||
exec_output += PredOpExecute.subst(m5checkpointIop)
|
exec_output += PredOpExecute.subst(m5checkpointIop)
|
||||||
|
|
||||||
m5readfileCode = '''
|
m5readfileCode = '''
|
||||||
#if FULL_SYSTEM
|
|
||||||
int n = 4;
|
int n = 4;
|
||||||
uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false);
|
uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false);
|
||||||
R0 = PseudoInst::readfile(xc->tcBase(), R0, join32to64(R3,R2), offset);
|
R0 = PseudoInst::readfile(xc->tcBase(), R0, join32to64(R3,R2), offset);
|
||||||
#endif
|
|
||||||
'''
|
'''
|
||||||
m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp",
|
m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp",
|
||||||
{ "code": m5readfileCode,
|
{ "code": m5readfileCode,
|
||||||
|
@ -291,9 +275,7 @@ let {{
|
||||||
exec_output += PredOpExecute.subst(m5switchcpuIop)
|
exec_output += PredOpExecute.subst(m5switchcpuIop)
|
||||||
|
|
||||||
m5addsymbolCode = '''
|
m5addsymbolCode = '''
|
||||||
#if FULL_SYSTEM
|
|
||||||
PseudoInst::addsymbol(xc->tcBase(), join32to64(R1, R0), R2);
|
PseudoInst::addsymbol(xc->tcBase(), join32to64(R1, R0), R2);
|
||||||
#endif
|
|
||||||
'''
|
'''
|
||||||
m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp",
|
m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp",
|
||||||
{ "code": m5addsymbolCode,
|
{ "code": m5addsymbolCode,
|
||||||
|
|
|
@ -40,11 +40,11 @@
|
||||||
let {{
|
let {{
|
||||||
|
|
||||||
svcCode = '''
|
svcCode = '''
|
||||||
#if FULL_SYSTEM
|
if (FullSystem) {
|
||||||
fault = new SupervisorCall;
|
fault = new SupervisorCall;
|
||||||
#else
|
} else {
|
||||||
fault = new SupervisorCall(machInst);
|
fault = new SupervisorCall(machInst);
|
||||||
#endif
|
}
|
||||||
'''
|
'''
|
||||||
|
|
||||||
svcIop = InstObjParams("svc", "Svc", "PredOp",
|
svcIop = InstObjParams("svc", "Svc", "PredOp",
|
||||||
|
@ -501,7 +501,6 @@ let {{
|
||||||
exec_output += PredOpExecute.subst(yieldIop)
|
exec_output += PredOpExecute.subst(yieldIop)
|
||||||
|
|
||||||
wfeCode = '''
|
wfeCode = '''
|
||||||
#if FULL_SYSTEM
|
|
||||||
// WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending
|
// WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending
|
||||||
if (SevMailbox == 1) {
|
if (SevMailbox == 1) {
|
||||||
SevMailbox = 0;
|
SevMailbox = 0;
|
||||||
|
@ -511,14 +510,11 @@ let {{
|
||||||
} else {
|
} else {
|
||||||
PseudoInst::quiesce(xc->tcBase());
|
PseudoInst::quiesce(xc->tcBase());
|
||||||
}
|
}
|
||||||
#endif
|
|
||||||
'''
|
'''
|
||||||
wfePredFixUpCode = '''
|
wfePredFixUpCode = '''
|
||||||
#if FULL_SYSTEM
|
|
||||||
// WFE is predicated false, reset SevMailbox to reduce spurious sleeps
|
// WFE is predicated false, reset SevMailbox to reduce spurious sleeps
|
||||||
// and SEV interrupts
|
// and SEV interrupts
|
||||||
SevMailbox = 1;
|
SevMailbox = 1;
|
||||||
#endif
|
|
||||||
'''
|
'''
|
||||||
wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
|
wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
|
||||||
{ "code" : wfeCode,
|
{ "code" : wfeCode,
|
||||||
|
@ -530,14 +526,12 @@ let {{
|
||||||
exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
|
exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
|
||||||
|
|
||||||
wfiCode = '''
|
wfiCode = '''
|
||||||
#if FULL_SYSTEM
|
|
||||||
// WFI doesn't sleep if interrupts are pending (masked or not)
|
// WFI doesn't sleep if interrupts are pending (masked or not)
|
||||||
if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) {
|
if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) {
|
||||||
PseudoInst::quiesceSkip(xc->tcBase());
|
PseudoInst::quiesceSkip(xc->tcBase());
|
||||||
} else {
|
} else {
|
||||||
PseudoInst::quiesce(xc->tcBase());
|
PseudoInst::quiesce(xc->tcBase());
|
||||||
}
|
}
|
||||||
#endif
|
|
||||||
'''
|
'''
|
||||||
wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
|
wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
|
||||||
{ "code" : wfiCode, "predicate_test" : predicateTest },
|
{ "code" : wfiCode, "predicate_test" : predicateTest },
|
||||||
|
@ -547,7 +541,6 @@ let {{
|
||||||
exec_output += QuiescePredOpExecute.subst(wfiIop)
|
exec_output += QuiescePredOpExecute.subst(wfiIop)
|
||||||
|
|
||||||
sevCode = '''
|
sevCode = '''
|
||||||
#if FULL_SYSTEM
|
|
||||||
SevMailbox = 1;
|
SevMailbox = 1;
|
||||||
System *sys = xc->tcBase()->getSystemPtr();
|
System *sys = xc->tcBase()->getSystemPtr();
|
||||||
for (int x = 0; x < sys->numContexts(); x++) {
|
for (int x = 0; x < sys->numContexts(); x++) {
|
||||||
|
@ -560,7 +553,6 @@ let {{
|
||||||
oc->getCpuPtr()->postInterrupt(INT_SEV, 0);
|
oc->getCpuPtr()->postInterrupt(INT_SEV, 0);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
#endif
|
|
||||||
'''
|
'''
|
||||||
sevIop = InstObjParams("sev", "SevInst", "PredOp", \
|
sevIop = InstObjParams("sev", "SevInst", "PredOp", \
|
||||||
{ "code" : sevCode, "predicate_test" : predicateTest },
|
{ "code" : sevCode, "predicate_test" : predicateTest },
|
||||||
|
@ -577,11 +569,10 @@ let {{
|
||||||
decoder_output += BasicConstructor.subst(itIop)
|
decoder_output += BasicConstructor.subst(itIop)
|
||||||
exec_output += PredOpExecute.subst(itIop)
|
exec_output += PredOpExecute.subst(itIop)
|
||||||
unknownCode = '''
|
unknownCode = '''
|
||||||
#if FULL_SYSTEM
|
if (FullSystem)
|
||||||
return new UndefinedInstruction;
|
return new UndefinedInstruction;
|
||||||
#else
|
else
|
||||||
return new UndefinedInstruction(machInst, true);
|
return new UndefinedInstruction(machInst, true);
|
||||||
#endif
|
|
||||||
'''
|
'''
|
||||||
unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
|
unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
|
||||||
{ "code": unknownCode,
|
{ "code": unknownCode,
|
||||||
|
@ -634,12 +625,12 @@ let {{
|
||||||
|
|
||||||
mrc15code = '''
|
mrc15code = '''
|
||||||
CPSR cpsr = Cpsr;
|
CPSR cpsr = Cpsr;
|
||||||
if (cpsr.mode == MODE_USER)
|
if (cpsr.mode == MODE_USER) {
|
||||||
#if FULL_SYSTEM
|
if (FullSystem)
|
||||||
return new UndefinedInstruction;
|
return new UndefinedInstruction;
|
||||||
#else
|
else
|
||||||
return new UndefinedInstruction(false, mnemonic);
|
return new UndefinedInstruction(false, mnemonic);
|
||||||
#endif
|
}
|
||||||
Dest = MiscOp1;
|
Dest = MiscOp1;
|
||||||
'''
|
'''
|
||||||
|
|
||||||
|
@ -653,12 +644,12 @@ let {{
|
||||||
|
|
||||||
mcr15code = '''
|
mcr15code = '''
|
||||||
CPSR cpsr = Cpsr;
|
CPSR cpsr = Cpsr;
|
||||||
if (cpsr.mode == MODE_USER)
|
if (cpsr.mode == MODE_USER) {
|
||||||
#if FULL_SYSTEM
|
if (FullSystem)
|
||||||
return new UndefinedInstruction;
|
return new UndefinedInstruction;
|
||||||
#else
|
else
|
||||||
return new UndefinedInstruction(false, mnemonic);
|
return new UndefinedInstruction(false, mnemonic);
|
||||||
#endif
|
}
|
||||||
MiscDest = Op1;
|
MiscDest = Op1;
|
||||||
'''
|
'''
|
||||||
mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
|
mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
|
||||||
|
|
|
@ -872,11 +872,10 @@ let {{
|
||||||
readDestCode = 'destElem = gtoh(destReg.elements[i]);'
|
readDestCode = 'destElem = gtoh(destReg.elements[i]);'
|
||||||
eWalkCode += '''
|
eWalkCode += '''
|
||||||
if (imm < 0 && imm >= eCount) {
|
if (imm < 0 && imm >= eCount) {
|
||||||
#if FULL_SYSTEM
|
if (FullSystem)
|
||||||
fault = new UndefinedInstruction;
|
fault = new UndefinedInstruction;
|
||||||
#else
|
else
|
||||||
fault = new UndefinedInstruction(false, mnemonic);
|
fault = new UndefinedInstruction(false, mnemonic);
|
||||||
#endif
|
|
||||||
} else {
|
} else {
|
||||||
for (unsigned i = 0; i < eCount; i++) {
|
for (unsigned i = 0; i < eCount; i++) {
|
||||||
Element srcElem1 = gtoh(srcReg1.elements[i]);
|
Element srcElem1 = gtoh(srcReg1.elements[i]);
|
||||||
|
@ -927,11 +926,10 @@ let {{
|
||||||
readDestCode = 'destElem = gtoh(destReg.elements[i]);'
|
readDestCode = 'destElem = gtoh(destReg.elements[i]);'
|
||||||
eWalkCode += '''
|
eWalkCode += '''
|
||||||
if (imm < 0 && imm >= eCount) {
|
if (imm < 0 && imm >= eCount) {
|
||||||
#if FULL_SYSTEM
|
if (FullSystem)
|
||||||
fault = new UndefinedInstruction;
|
fault = new UndefinedInstruction;
|
||||||
#else
|
else
|
||||||
fault = new UndefinedInstruction(false, mnemonic);
|
fault = new UndefinedInstruction(false, mnemonic);
|
||||||
#endif
|
|
||||||
} else {
|
} else {
|
||||||
for (unsigned i = 0; i < eCount; i++) {
|
for (unsigned i = 0; i < eCount; i++) {
|
||||||
Element srcElem1 = gtoh(srcReg1.elements[i]);
|
Element srcElem1 = gtoh(srcReg1.elements[i]);
|
||||||
|
@ -980,11 +978,10 @@ let {{
|
||||||
readDestCode = 'destReg = destRegs[i];'
|
readDestCode = 'destReg = destRegs[i];'
|
||||||
eWalkCode += '''
|
eWalkCode += '''
|
||||||
if (imm < 0 && imm >= eCount) {
|
if (imm < 0 && imm >= eCount) {
|
||||||
#if FULL_SYSTEM
|
if (FullSystem)
|
||||||
fault = new UndefinedInstruction;
|
fault = new UndefinedInstruction;
|
||||||
#else
|
else
|
||||||
fault = new UndefinedInstruction(false, mnemonic);
|
fault = new UndefinedInstruction(false, mnemonic);
|
||||||
#endif
|
|
||||||
} else {
|
} else {
|
||||||
for (unsigned i = 0; i < rCount; i++) {
|
for (unsigned i = 0; i < rCount; i++) {
|
||||||
FloatReg srcReg1 = srcRegs1[i];
|
FloatReg srcReg1 = srcRegs1[i];
|
||||||
|
@ -3298,16 +3295,16 @@ let {{
|
||||||
destReg.elements[i] = srcReg1.elements[index];
|
destReg.elements[i] = srcReg1.elements[index];
|
||||||
} else {
|
} else {
|
||||||
index -= eCount;
|
index -= eCount;
|
||||||
if (index >= eCount)
|
if (index >= eCount) {
|
||||||
#if FULL_SYSTEM
|
if (FullSystem)
|
||||||
fault = new UndefinedInstruction;
|
fault = new UndefinedInstruction;
|
||||||
#else
|
|
||||||
fault = new UndefinedInstruction(false, mnemonic);
|
|
||||||
#endif
|
|
||||||
else
|
else
|
||||||
|
fault = new UndefinedInstruction(false, mnemonic);
|
||||||
|
} else {
|
||||||
destReg.elements[i] = srcReg2.elements[index];
|
destReg.elements[i] = srcReg2.elements[index];
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
}
|
||||||
'''
|
'''
|
||||||
buildVext("vext", "NVextD", "SimdMiscOp", ("uint8_t",), 2, vextCode)
|
buildVext("vext", "NVextD", "SimdMiscOp", ("uint8_t",), 2, vextCode)
|
||||||
buildVext("vext", "NVextQ", "SimdMiscOp", ("uint8_t",), 4, vextCode)
|
buildVext("vext", "NVextQ", "SimdMiscOp", ("uint8_t",), 4, vextCode)
|
||||||
|
|
|
@ -73,11 +73,10 @@ let {{
|
||||||
|
|
||||||
swpPreAccCode = '''
|
swpPreAccCode = '''
|
||||||
if (!((SCTLR)Sctlr).sw) {
|
if (!((SCTLR)Sctlr).sw) {
|
||||||
#if FULL_SYSTEM
|
if (FullSystem)
|
||||||
return new UndefinedInstruction;
|
return new UndefinedInstruction;
|
||||||
#else
|
else
|
||||||
return new UndefinedInstruction(false, mnemonic);
|
return new UndefinedInstruction(false, mnemonic);
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
'''
|
'''
|
||||||
|
|
||||||
|
|
|
@ -134,11 +134,6 @@
|
||||||
|
|
||||||
#include <string>
|
#include <string>
|
||||||
|
|
||||||
#include "config/full_system.hh"
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
#include "arch/arm/vtophys.hh"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#include "arch/arm/pagetable.hh"
|
#include "arch/arm/pagetable.hh"
|
||||||
#include "arch/arm/registers.hh"
|
#include "arch/arm/registers.hh"
|
||||||
#include "arch/arm/remote_gdb.hh"
|
#include "arch/arm/remote_gdb.hh"
|
||||||
|
@ -157,6 +152,7 @@
|
||||||
#include "mem/page_table.hh"
|
#include "mem/page_table.hh"
|
||||||
#include "mem/physical.hh"
|
#include "mem/physical.hh"
|
||||||
#include "mem/port.hh"
|
#include "mem/port.hh"
|
||||||
|
#include "sim/full_system.hh"
|
||||||
#include "sim/system.hh"
|
#include "sim/system.hh"
|
||||||
|
|
||||||
using namespace std;
|
using namespace std;
|
||||||
|
@ -173,7 +169,7 @@ RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
|
||||||
bool
|
bool
|
||||||
RemoteGDB::acc(Addr va, size_t len)
|
RemoteGDB::acc(Addr va, size_t len)
|
||||||
{
|
{
|
||||||
#if FULL_SYSTEM
|
if (FullSystem) {
|
||||||
Addr last_va;
|
Addr last_va;
|
||||||
va = truncPage(va);
|
va = truncPage(va);
|
||||||
last_va = roundPage(va + len);
|
last_va = roundPage(va + len);
|
||||||
|
@ -187,14 +183,14 @@ RemoteGDB::acc(Addr va, size_t len)
|
||||||
|
|
||||||
DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va);
|
DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va);
|
||||||
return true;
|
return true;
|
||||||
#else
|
} else {
|
||||||
TlbEntry entry;
|
TlbEntry entry;
|
||||||
//Check to make sure the first byte is mapped into the processes address
|
//Check to make sure the first byte is mapped into the processes address
|
||||||
//space.
|
//space.
|
||||||
if (context->getProcessPtr()->pTable->lookup(va, entry))
|
if (context->getProcessPtr()->pTable->lookup(va, entry))
|
||||||
return true;
|
return true;
|
||||||
return false;
|
return false;
|
||||||
#endif
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -47,6 +47,7 @@
|
||||||
|
|
||||||
#include "arch/arm/faults.hh"
|
#include "arch/arm/faults.hh"
|
||||||
#include "arch/arm/pagetable.hh"
|
#include "arch/arm/pagetable.hh"
|
||||||
|
#include "arch/arm/system.hh"
|
||||||
#include "arch/arm/table_walker.hh"
|
#include "arch/arm/table_walker.hh"
|
||||||
#include "arch/arm/tlb.hh"
|
#include "arch/arm/tlb.hh"
|
||||||
#include "arch/arm/utility.hh"
|
#include "arch/arm/utility.hh"
|
||||||
|
@ -62,10 +63,6 @@
|
||||||
#include "sim/full_system.hh"
|
#include "sim/full_system.hh"
|
||||||
#include "sim/process.hh"
|
#include "sim/process.hh"
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
#include "arch/arm/system.hh"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
using namespace std;
|
using namespace std;
|
||||||
using namespace ArmISA;
|
using namespace ArmISA;
|
||||||
|
|
||||||
|
@ -421,14 +418,14 @@ TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#if !FULL_SYSTEM
|
if (!FullSystem) {
|
||||||
Addr paddr;
|
Addr paddr;
|
||||||
Process *p = tc->getProcessPtr();
|
Process *p = tc->getProcessPtr();
|
||||||
|
|
||||||
if (!p->pTable->translate(vaddr, paddr))
|
if (!p->pTable->translate(vaddr, paddr))
|
||||||
return Fault(new GenericPageTableFault(vaddr));
|
return Fault(new GenericPageTableFault(vaddr));
|
||||||
req->setPaddr(paddr);
|
req->setPaddr(paddr);
|
||||||
#endif
|
}
|
||||||
|
|
||||||
return NoFault;
|
return NoFault;
|
||||||
}
|
}
|
||||||
|
@ -573,11 +570,11 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
if (FullSystem) {
|
||||||
if (!bootUncacheability &&
|
if (!bootUncacheability &&
|
||||||
((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr))
|
((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr))
|
||||||
req->setFlags(Request::UNCACHEABLE);
|
req->setFlags(Request::UNCACHEABLE);
|
||||||
#endif
|
}
|
||||||
|
|
||||||
switch ( (dacr >> (te->domain * 2)) & 0x3) {
|
switch ( (dacr >> (te->domain * 2)) & 0x3) {
|
||||||
case 0:
|
case 0:
|
||||||
|
|
|
@ -40,15 +40,12 @@
|
||||||
|
|
||||||
#include "arch/arm/faults.hh"
|
#include "arch/arm/faults.hh"
|
||||||
#include "arch/arm/isa_traits.hh"
|
#include "arch/arm/isa_traits.hh"
|
||||||
#include "arch/arm/utility.hh"
|
|
||||||
#include "cpu/thread_context.hh"
|
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
#include "arch/arm/vtophys.hh"
|
|
||||||
#include "mem/vport.hh"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#include "arch/arm/tlb.hh"
|
#include "arch/arm/tlb.hh"
|
||||||
|
#include "arch/arm/utility.hh"
|
||||||
|
#include "arch/arm/vtophys.hh"
|
||||||
|
#include "cpu/thread_context.hh"
|
||||||
|
#include "mem/vport.hh"
|
||||||
|
#include "sim/full_system.hh"
|
||||||
|
|
||||||
namespace ArmISA {
|
namespace ArmISA {
|
||||||
|
|
||||||
|
@ -66,20 +63,20 @@ initCPU(ThreadContext *tc, int cpuId)
|
||||||
uint64_t
|
uint64_t
|
||||||
getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
|
getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
|
||||||
{
|
{
|
||||||
#if FULL_SYSTEM
|
if (FullSystem) {
|
||||||
if (size == (uint16_t)(-1))
|
if (size == (uint16_t)(-1))
|
||||||
size = ArmISA::MachineBytes;
|
size = ArmISA::MachineBytes;
|
||||||
if (fp)
|
if (fp)
|
||||||
panic("getArgument(): Floating point arguments not implemented\n");
|
panic("getArgument(): Floating point arguments not implemented\n");
|
||||||
|
|
||||||
if (number < NumArgumentRegs) {
|
if (number < NumArgumentRegs) {
|
||||||
// If the argument is 64 bits, it must be in an even regiser number
|
// If the argument is 64 bits, it must be in an even regiser
|
||||||
// Increment the number here if it isn't even
|
// number. Increment the number here if it isn't even.
|
||||||
if (size == sizeof(uint64_t)) {
|
if (size == sizeof(uint64_t)) {
|
||||||
if ((number % 2) != 0)
|
if ((number % 2) != 0)
|
||||||
number++;
|
number++;
|
||||||
// Read the two halves of the data
|
// Read the two halves of the data. Number is inc here to
|
||||||
// number is inc here to get the second half of the 64 bit reg
|
// get the second half of the 64 bit reg.
|
||||||
uint64_t tmp;
|
uint64_t tmp;
|
||||||
tmp = tc->readIntReg(number++);
|
tmp = tc->readIntReg(number++);
|
||||||
tmp |= tc->readIntReg(number) << 32;
|
tmp |= tc->readIntReg(number) << 32;
|
||||||
|
@ -105,10 +102,10 @@ getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
|
||||||
}
|
}
|
||||||
return arg;
|
return arg;
|
||||||
}
|
}
|
||||||
#else
|
} else {
|
||||||
panic("getArgument() only implemented for FULL_SYSTEM\n");
|
panic("getArgument() only implemented for full system mode.\n");
|
||||||
M5_DUMMY_RETURN
|
M5_DUMMY_RETURN
|
||||||
#endif
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
|
|
Loading…
Reference in a new issue