From f58d85128dde9aebb5b161aa51799309d5c16d67 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 14 Jan 2005 18:34:56 -0500 Subject: [PATCH 01/20] Fixes so m5 compiles on gcc 3.4, which has much stricter syntax. Most changes come from templated code, which is evaluated slightly differently than in previous versions of gcc. arch/alpha/alpha_linux_process.cc: Alphabetize includes. arch/alpha/vptr.hh: Change the constants that are being used for alpha pagebytes to come from the ISA. base/random.hh: cpu/static_inst.cc: sim/param.cc: Fix up template syntax. base/range.hh: Include iostream for << operator. base/res_list.hh: base/statistics.hh: cpu/simple_cpu/simple_cpu.hh: cpu/static_inst.hh: sim/eventq.hh: sim/param.hh: Fixup for templated code to resolve different scope lookup in gcc 3.4. This defers the lookup of the function/variable until actual instantiation time by making it dependent on the templated class/function. base/trace.cc: Fix call to new. base/trace.hh: Fix up #define to have full path. cpu/base_cpu.cc: Fix up call to new. dev/etherlink.hh: dev/ns_gige.hh: dev/sinic.hh: Fixup for friend class/function declaration. g++ 3.4 no longer allows typedefs to be declared as a friend class. dev/pcidev.hh: Fix up re-definition of access level to params. kern/linux/linux_syscalls.hh: kern/tru64/tru64_syscalls.hh: Fix up header. Fix up template syntax. sim/serialize.cc: Include errno.h. sim/startup.cc: Change startupq. queue was getting destructed before all things had called ~StartupCallback(), which lead to a segfault. This puts startupq in global space, and we allocate it ourselves. Other code may be similar to this and may need changing in the future. sim/syscall_emul.hh: Include cpu/exec_context.hh and sim/process.hh, as forward declarations are no longer sufficient. sim/universe.cc: Include errno.h --HG-- extra : convert_revision : e49d08ee89eb06a28351f02bafc028ca6652d5af --- arch/alpha/alpha_linux_process.cc | 20 ++--- arch/alpha/vptr.hh | 11 +-- base/random.hh | 20 ++--- base/range.hh | 1 + base/res_list.hh | 2 +- base/statistics.hh | 128 +++++++++++++++--------------- base/trace.cc | 2 +- base/trace.hh | 6 +- cpu/base_cpu.cc | 4 +- cpu/simple_cpu/simple_cpu.hh | 19 ++--- cpu/static_inst.cc | 2 +- cpu/static_inst.hh | 2 +- dev/etherlink.hh | 10 +-- dev/ns_gige.hh | 8 +- dev/pcidev.hh | 9 ++- dev/sinic.hh | 8 +- kern/linux/linux_syscalls.hh | 7 +- kern/tru64/tru64_syscalls.hh | 7 +- sim/eventq.hh | 34 ++++---- sim/param.cc | 18 ++--- sim/param.hh | 9 ++- sim/serialize.cc | 1 + sim/startup.cc | 24 ++++-- sim/syscall_emul.hh | 84 ++++++++++---------- sim/universe.cc | 1 + 25 files changed, 227 insertions(+), 210 deletions(-) diff --git a/arch/alpha/alpha_linux_process.cc b/arch/alpha/alpha_linux_process.cc index 67bb0ab3b..ba4b1d07e 100644 --- a/arch/alpha/alpha_linux_process.cc +++ b/arch/alpha/alpha_linux_process.cc @@ -26,24 +26,24 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include -#include -#include // for host open() flags -#include -#include -#include // for memset() #include +#include +#include // for host open() flags +#include // for memset() +#include +#include +#include -#include "sim/host.hh" #include "cpu/base_cpu.hh" -#include "mem/functional_mem/functional_memory.hh" -#include "sim/process.hh" #include "cpu/exec_context.hh" +#include "mem/functional_mem/functional_memory.hh" #include "sim/fake_syscall.hh" +#include "sim/host.hh" +#include "sim/process.hh" #include "sim/sim_events.hh" -#include "sim/syscall_emul.hh" #include "arch/alpha/alpha_common_syscall_emul.hh" +#include "sim/syscall_emul.hh" #include "sim/universe.hh" // for curTick & ticksPerSecond #include "arch/alpha/alpha_linux_process.hh" diff --git a/arch/alpha/vptr.hh b/arch/alpha/vptr.hh index cd4bc547b..e955c67cf 100644 --- a/arch/alpha/vptr.hh +++ b/arch/alpha/vptr.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __VPTR_HH__ -#define __VPTR_HH__ +#ifndef __ARCH_ALPHA_VPTR_HH__ +#define __ARCH_ALPHA_VPTR_HH__ #include "arch/alpha/vtophys.hh" @@ -69,14 +69,15 @@ class VPtr const VPtr &operator+=(int offset) { ptr += offset; - assert((ptr & (ALPHA_PGBYTES - 1)) + sizeof(T) < ALPHA_PGBYTES); + assert((ptr & (AlphaISA::PageBytes - 1)) + sizeof(T) + < AlphaISA::PageBytes); return *this; } const VPtr &operator=(Addr p) { - assert((p & (ALPHA_PGBYTES - 1)) + sizeof(T) < ALPHA_PGBYTES); + assert((p & (AlphaISA::PageBytes)) + sizeof(T) < AlphaISA::PageBytes); ptr = p; return *this; @@ -110,4 +111,4 @@ class VPtr } }; -#endif // __VPTR_HH__ +#endif // __ARCH_ALPHA_VPTR_HH__ diff --git a/base/random.hh b/base/random.hh index 0bfed100c..fe93a98a6 100644 --- a/base/random.hh +++ b/base/random.hh @@ -37,61 +37,61 @@ double getDouble(); template struct Random; -struct Random +template<> struct Random { static int8_t get() { return getLong() & (int8_t)-1; } }; -struct Random +template<> struct Random { static uint8_t get() { return getLong() & (uint8_t)-1; } }; -struct Random +template<> struct Random { static int16_t get() { return getLong() & (int16_t)-1; } }; -struct Random +template<> struct Random { static uint16_t get() { return getLong() & (uint16_t)-1; } }; -struct Random +template<> struct Random { static int32_t get() { return (int32_t)getLong(); } }; -struct Random +template<> struct Random { static uint32_t get() { return (uint32_t)getLong(); } }; -struct Random +template<> struct Random { static int64_t get() { return (int64_t)getLong() << 32 || (uint64_t)getLong(); } }; -struct Random +template<> struct Random { static uint64_t get() { return (uint64_t)getLong() << 32 || (uint64_t)getLong(); } }; -struct Random +template<> struct Random { static float get() { return getDouble(); } }; -struct Random +template<> struct Random { static double get() { return getDouble(); } diff --git a/base/range.hh b/base/range.hh index 9289792ea..57b6e6a77 100644 --- a/base/range.hh +++ b/base/range.hh @@ -30,6 +30,7 @@ #define __BASE_RANGE_HH__ #include +#include #include /** diff --git a/base/res_list.hh b/base/res_list.hh index 7080a3ba7..5dc798fed 100644 --- a/base/res_list.hh +++ b/base/res_list.hh @@ -352,7 +352,7 @@ res_list::insert_after(iterator prev, T *d) iterator p; if (!allocate_storage) - panic("Can't copy data... not allocating storage"); + this->panic("Can't copy data... not allocating storage"); p = insert_after(prev); if (p.notnull()) diff --git a/base/statistics.hh b/base/statistics.hh index f3b8a3922..9ec26eb4d 100644 --- a/base/statistics.hh +++ b/base/statistics.hh @@ -407,7 +407,7 @@ class Wrap : public Child public: Wrap() { - map(new Data(*this)); + map(new Data(*this)); } /** @@ -417,10 +417,10 @@ class Wrap : public Child */ Parent &name(const std::string &_name) { - Data *data = statData(); + Data *data = this->statData(); data->name = _name; - setPrint(); - return self(); + this->setPrint(); + return this->self(); } /** @@ -431,8 +431,8 @@ class Wrap : public Child */ Parent &desc(const std::string &_desc) { - statData()->desc = _desc; - return self(); + this->statData()->desc = _desc; + return this->self(); } /** @@ -442,8 +442,8 @@ class Wrap : public Child */ Parent &precision(int _precision) { - statData()->precision = _precision; - return self(); + this->statData()->precision = _precision; + return this->self(); } /** @@ -453,8 +453,8 @@ class Wrap : public Child */ Parent &flags(StatFlags _flags) { - statData()->flags |= _flags; - return self(); + this->statData()->flags |= _flags; + return this->self(); } /** @@ -466,8 +466,8 @@ class Wrap : public Child template Parent &prereq(const Stat &prereq) { - statData()->prereq = prereq.statData(); - return self(); + this->statData()->prereq = prereq.statData(); + return this->self(); } }; @@ -487,11 +487,11 @@ class WrapVec : public Wrap */ Parent &subname(int index, const std::string &name) { - std::vector &subn = statData()->subnames; + std::vector &subn = this->statData()->subnames; if (subn.size() <= index) subn.resize(index + 1); subn[index] = name; - return self(); + return this->self(); } /** @@ -503,12 +503,12 @@ class WrapVec : public Wrap */ Parent &subdesc(int index, const std::string &desc) { - std::vector &subd = statData()->subdescs; + std::vector &subd = this->statData()->subdescs; if (subd.size() <= index) subd.resize(index + 1); subd[index] = desc; - return self(); + return this->self(); } }; @@ -523,19 +523,19 @@ class WrapVec2d : public WrapVec */ Parent &ysubnames(const char **names) { - Data *data = statData(); - data->y_subnames.resize(y); - for (int i = 0; i < y; ++i) + Data *data = this->statData(); + data->y_subnames.resize(this->y); + for (int i = 0; i < this->y; ++i) data->y_subnames[i] = names[i]; - return self(); + return this->self(); } Parent &ysubname(int index, const std::string subname) { - Data *data = statData(); - assert(index < y); - data->y_subnames.resize(y); + Data *data = this->statData(); + assert(index < this->y); + data->y_subnames.resize(this->y); data->y_subnames[index] = subname.c_str(); - return self(); + return this->self(); } }; @@ -711,7 +711,7 @@ class ScalarBase : public DataAccess /** Define the params of the storage class. */ typedef typename Storage::Params params_t; /** Define the bin type. */ - typedef typename Bin::Bin bin_t; + typedef typename Bin::template Bin bin_t; protected: /** The bin of this stat. */ @@ -914,7 +914,7 @@ class VectorBase : public DataAccess /** Define the params of the storage class. */ typedef typename Storage::Params params_t; /** Define the bin type. */ - typedef typename Bin::VectorBin bin_t; + typedef typename Bin::template VectorBin bin_t; protected: /** The bin of this stat. */ @@ -1022,7 +1022,7 @@ class ScalarProxy /** Define the params of the storage class. */ typedef typename Storage::Params params_t; /** Define the bin type. */ - typedef typename Bin::VectorBin bin_t; + typedef typename Bin::template VectorBin bin_t; private: /** Pointer to the bin in the parent VectorBase. */ @@ -1155,7 +1155,7 @@ class ScalarProxy const StatData *statData() const { return getStatData(stat); } std::string str() const { - return csprintf("%s[%d]", statData()->name, index); + return csprintf("%s[%d]", this->statData()->name, index); } }; @@ -1176,7 +1176,7 @@ class Vector2dBase : public DataAccess { public: typedef typename Storage::Params params_t; - typedef typename Bin::VectorBin bin_t; + typedef typename Bin::template VectorBin bin_t; protected: size_t x; @@ -1204,7 +1204,7 @@ class Vector2dBase : public DataAccess data->cvec[i] = this->data(i)->value(params); } - std::string ysubname(int i) const { return (*y_subnames)[i]; } + std::string ysubname(int i) const { return (*this->y_subnames)[i]; } friend class VectorProxy; VectorProxy operator[](int index); @@ -1225,7 +1225,7 @@ class VectorProxy { public: typedef typename Storage::Params params_t; - typedef typename Bin::VectorBin bin_t; + typedef typename Bin::template VectorBin bin_t; private: bin_t *bin; @@ -1622,7 +1622,7 @@ class DistBase : public DataAccess /** Define the params of the storage class. */ typedef typename Storage::Params params_t; /** Define the bin type. */ - typedef typename Bin::Bin bin_t; + typedef typename Bin::template Bin bin_t; protected: /** The bin of this stat. */ @@ -1698,7 +1698,7 @@ class VectorDistBase : public DataAccess { public: typedef typename Storage::Params params_t; - typedef typename Bin::VectorBin bin_t; + typedef typename Bin::template VectorBin bin_t; protected: bin_t bin; @@ -1749,7 +1749,7 @@ class DistProxy { public: typedef typename Storage::Params params_t; - typedef typename Bin::Bin bin_t; + typedef typename Bin::template Bin bin_t; typedef VectorDistBase base_t; private: @@ -2206,7 +2206,7 @@ class Scalar Scalar() { - setInit(); + this->setInit(); } /** @@ -2258,7 +2258,7 @@ class Average Average() { - setInit(); + this->setInit(); } /** @@ -2290,8 +2290,8 @@ class Vector * @return A reference to this stat. */ Vector &init(size_t size) { - bin.init(size, params); - setInit(); + this->bin.init(size, this->params); + this->setInit(); return *this; } @@ -2314,8 +2314,8 @@ class AverageVector * @return A reference to this stat. */ AverageVector &init(size_t size) { - bin.init(size, params); - setInit(); + this->bin.init(size, this->params); + this->setInit(); return *this; } @@ -2333,10 +2333,10 @@ class Vector2d { public: Vector2d &init(size_t _x, size_t _y) { - statData()->x = x = _x; - statData()->y = y = _y; - bin.init(x * y, params); - setInit(); + this->statData()->x = this->x = _x; + this->statData()->y = this->y = _y; + this->bin.init(this->x * this->y, this->params); + this->setInit(); return *this; } @@ -2367,12 +2367,12 @@ class Distribution * @return A reference to this distribution. */ Distribution &init(Counter min, Counter max, Counter bkt) { - params.min = min; - params.max = max; - params.bucket_size = bkt; - params.size = (int)rint((max - min) / bkt + 1.0); - bin.init(params); - setInit(); + this->params.min = min; + this->params.max = max; + this->params.bucket_size = bkt; + this->params.size = (int)rint((max - min) / bkt + 1.0); + this->bin.init(this->params); + this->setInit(); return *this; } @@ -2399,8 +2399,8 @@ class StandardDeviation * Construct and initialize this distribution. */ StandardDeviation() { - bin.init(params); - setInit(); + this->bin.init(this->params); + this->setInit(); } }; @@ -2426,8 +2426,8 @@ class AverageDeviation */ AverageDeviation() { - bin.init(params); - setInit(); + this->bin.init(this->params); + this->setInit(); } }; @@ -2457,12 +2457,12 @@ class VectorDistribution * @return A reference to this distribution. */ VectorDistribution &init(int size, Counter min, Counter max, Counter bkt) { - params.min = min; - params.max = max; - params.bucket_size = bkt; - params.size = (int)rint((max - min) / bkt + 1.0); - bin.init(size, params); - setInit(); + this->params.min = min; + this->params.max = max; + this->params.bucket_size = bkt; + this->params.size = (int)rint((max - min) / bkt + 1.0); + this->bin.init(size, this->params); + this->setInit(); return *this; } @@ -2491,8 +2491,8 @@ class VectorStandardDeviation * @return A reference to this distribution. */ VectorStandardDeviation &init(int size) { - bin.init(size, params); - setInit(); + this->bin.init(size, this->params); + this->setInit(); return *this; } @@ -2521,8 +2521,8 @@ class VectorAverageDeviation * @return A reference to this distribution. */ VectorAverageDeviation &init(int size) { - bin.init(size, params); - setInit(); + this->bin.init(size, this->params); + this->setInit(); return *this; } diff --git a/base/trace.cc b/base/trace.cc index bc6c9aa7a..aa4e7b2af 100644 --- a/base/trace.cc +++ b/base/trace.cc @@ -71,7 +71,7 @@ Log::init(int _size) size = _size; - buffer = new (Record *)[size]; + buffer = new Record *[size]; for (int i = 0; i < size; ++i) { buffer[i] = NULL; diff --git a/base/trace.hh b/base/trace.hh index 5e05d6e5e..054b14546 100644 --- a/base/trace.hh +++ b/base/trace.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __TRACE_HH__ -#define __TRACE_HH__ +#ifndef __BASE_TRACE_HH__ +#define __BASE_TRACE_HH__ #include @@ -228,4 +228,4 @@ do { \ #endif // TRACING_ON -#endif // __TRACE_HH__ +#endif // __BASE_TRACE_HH__ diff --git a/cpu/base_cpu.cc b/cpu/base_cpu.cc index 7605ff3c3..c4bb97ff8 100644 --- a/cpu/base_cpu.cc +++ b/cpu/base_cpu.cc @@ -76,7 +76,7 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg, maxThreadsPerCPU = number_of_threads; // allocate per-thread instruction-based event queues - comInstEventQueue = new (EventQueue *)[number_of_threads]; + comInstEventQueue = new EventQueue *[number_of_threads]; for (int i = 0; i < number_of_threads; ++i) comInstEventQueue[i] = new EventQueue("instruction-based event queue"); @@ -101,7 +101,7 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg, } // allocate per-thread load-based event queues - comLoadEventQueue = new (EventQueue *)[number_of_threads]; + comLoadEventQueue = new EventQueue *[number_of_threads]; for (int i = 0; i < number_of_threads; ++i) comLoadEventQueue[i] = new EventQueue("load-based event queue"); diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh index 341a0da23..9b6e2423b 100644 --- a/cpu/simple_cpu/simple_cpu.hh +++ b/cpu/simple_cpu/simple_cpu.hh @@ -26,15 +26,15 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __SIMPLE_CPU_HH__ -#define __SIMPLE_CPU_HH__ +#ifndef __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__ +#define __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__ -#include "cpu/base_cpu.hh" -#include "sim/eventq.hh" -#include "cpu/pc_event.hh" #include "base/statistics.hh" +#include "cpu/base_cpu.hh" #include "cpu/exec_context.hh" +#include "cpu/pc_event.hh" #include "cpu/static_inst.hh" +#include "sim/eventq.hh" // forward declarations #ifdef FULL_SYSTEM @@ -103,12 +103,7 @@ class SimpleCPU : public BaseCPU private: Trace::InstRecord *traceData; template - void trace_data(T data) { - if (traceData) { - traceData->setData(data); - } - }; - + void trace_data(T data); public: // enum Status { @@ -346,4 +341,4 @@ class SimpleCPU : public BaseCPU ExecContext *xcBase() { return xc; } }; -#endif // __SIMPLE_CPU_HH__ +#endif // __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__ diff --git a/cpu/static_inst.cc b/cpu/static_inst.cc index 4cb45a818..7069d89ec 100644 --- a/cpu/static_inst.cc +++ b/cpu/static_inst.cc @@ -85,4 +85,4 @@ StaticInst::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) // force instantiation of template function(s) above -template StaticInst; +template class StaticInst; diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh index 46b2e4b19..c442ada35 100644 --- a/cpu/static_inst.hh +++ b/cpu/static_inst.hh @@ -456,7 +456,7 @@ class StaticInstPtr : public RefCountingPtr > /// Convert to pointer to StaticInstBase class. operator const StaticInstBasePtr() { - return get(); + return this->get(); } }; diff --git a/dev/etherlink.hh b/dev/etherlink.hh index e998a006f..d5cd7d7c8 100644 --- a/dev/etherlink.hh +++ b/dev/etherlink.hh @@ -30,13 +30,13 @@ * Device module for modelling a fixed bandwidth full duplex ethernet link */ -#ifndef __ETHERLINK_HH__ -#define __ETHERLINK_HH__ +#ifndef __DEV_ETHERLINK_HH__ +#define __DEV_ETHERLINK_HH__ -#include "sim/host.hh" -#include "sim/eventq.hh" #include "dev/etherint.hh" #include "dev/etherpkt.hh" +#include "sim/eventq.hh" +#include "sim/host.hh" #include "sim/sim_object.hh" class EtherDump; @@ -71,7 +71,7 @@ class EtherLink : public SimObject PacketPtr packet; void txDone(); typedef EventWrapper DoneEvent; - friend class DoneEvent; + friend void DoneEvent::process(); DoneEvent doneEvent; friend class LinkDelayEvent; diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh index 8d6016126..697c39cac 100644 --- a/dev/ns_gige.hh +++ b/dev/ns_gige.hh @@ -262,12 +262,12 @@ class NSGigE : public PciDev void rxKick(); Tick rxKickTick; typedef EventWrapper RxKickEvent; - friend class RxKickEvent; + friend void RxKickEvent::process(); void txKick(); Tick txKickTick; typedef EventWrapper TxKickEvent; - friend class TxKickEvent; + friend void TxKickEvent::process(); /** * Retransmit event @@ -280,7 +280,7 @@ class NSGigE : public PciDev txKick(); } typedef EventWrapper TxEvent; - friend class TxEvent; + friend void TxEvent::process(); TxEvent txEvent; void txDump() const; @@ -315,7 +315,7 @@ class NSGigE : public PciDev void cpuIntrClear(); typedef EventWrapper IntrEvent; - friend class IntrEvent; + friend void IntrEvent::process(); IntrEvent *intrEvent; NSGigEInt *interface; diff --git a/dev/pcidev.hh b/dev/pcidev.hh index 4b947b560..14f183e28 100644 --- a/dev/pcidev.hh +++ b/dev/pcidev.hh @@ -78,10 +78,6 @@ class PciConfigData : public SimObject */ class PciDev : public DmaDevice { - protected: - struct Params; - Params *_params; - public: struct Params { @@ -110,6 +106,11 @@ class PciDev : public DmaDevice /** The function number */ uint32_t functionNum; }; + + protected: + Params *_params; + + public: const Params *params() const { return _params; } protected: diff --git a/dev/sinic.hh b/dev/sinic.hh index ef515ffad..9f265b3f6 100644 --- a/dev/sinic.hh +++ b/dev/sinic.hh @@ -59,7 +59,7 @@ class Base : public PciDev void cpuIntrClear(); typedef EventWrapper IntrEvent; - friend class IntrEvent; + friend void IntrEvent::process(); IntrEvent *intrEvent; Interface *interface; @@ -155,12 +155,12 @@ class Device : public Base void rxKick(); Tick rxKickTick; typedef EventWrapper RxKickEvent; - friend class RxKickEvent; + friend void RxKickEvent::process(); void txKick(); Tick txKickTick; typedef EventWrapper TxKickEvent; - friend class TxKickEvent; + friend void TxKickEvent::process(); /** * Retransmit event @@ -173,7 +173,7 @@ class Device : public Base txKick(); } typedef EventWrapper TxEvent; - friend class TxEvent; + friend void TxEvent::process(); TxEvent txEvent; void txDump() const; diff --git a/kern/linux/linux_syscalls.hh b/kern/linux/linux_syscalls.hh index dee7c5fcd..44a038def 100644 --- a/kern/linux/linux_syscalls.hh +++ b/kern/linux/linux_syscalls.hh @@ -26,14 +26,15 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __LINUX_SYSCALLS_HH__ -#define __LINUX_SYSCALLS_HH__ +#ifndef __KERN_LINUX_LINUX_SYSCALLS_HH__ +#define __KERN_LINUX_LINUX_SYSCALLS_HH__ #include "kern/linux/linux.hh" template class SystemCalls; +template <> class SystemCalls { public: @@ -322,4 +323,4 @@ class SystemCalls }; -#endif // __LINUX_SYSCALLS_HH__ +#endif // __KERN_LINUX_LINUX_SYSCALLS_HH__ diff --git a/kern/tru64/tru64_syscalls.hh b/kern/tru64/tru64_syscalls.hh index 7ddc699b1..44e5de250 100644 --- a/kern/tru64/tru64_syscalls.hh +++ b/kern/tru64/tru64_syscalls.hh @@ -26,14 +26,15 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __TRU64_SYSCALLS_HH__ -#define __TRU64_SYSCALLS_HH__ +#ifndef __KERN_TRU64_TRU64_SYSCALLS_HH__ +#define __KERN_TRU64_TRU64_SYSCALLS_HH__ #include "kern/tru64/tru64.hh" template class SystemCalls; +template <> class SystemCalls { public: @@ -355,4 +356,4 @@ class SystemCalls } }; -#endif // __TRU64_SYSCALLS_HH__ +#endif // __KERN_TRU64_TRU64_SYSCALLS_HH__ diff --git a/sim/eventq.hh b/sim/eventq.hh index 304e4b16a..d62e7df10 100644 --- a/sim/eventq.hh +++ b/sim/eventq.hh @@ -30,8 +30,8 @@ * EventQueue interfaces */ -#ifndef __EVENTQ_HH__ -#define __EVENTQ_HH__ +#ifndef __SIM_EVENTQ_HH__ +#define __SIM_EVENTQ_HH__ #include @@ -43,11 +43,24 @@ #include "sim/host.hh" // for Tick #include "base/fast_alloc.hh" -#include "sim/serialize.hh" #include "base/trace.hh" +#include "sim/serialize.hh" class EventQueue; // forward declaration +////////////////////// +// +// Main Event Queue +// +// Events on this queue are processed at the *beginning* of each +// cycle, before the pipeline simulation is performed. +// +// defined in eventq.cc +// +////////////////////// +extern EventQueue mainEventQueue; + + /* * An item on an event queue. The action caused by a given * event is specified by deriving a subclass and overriding the @@ -228,7 +241,7 @@ DelayFunction(Tick when, T *object) public: DelayEvent(Tick when, T *o) : Event(&mainEventQueue), object(o) - { setFlags(AutoDestroy); schedule(when); } + { setFlags(this->AutoDestroy); schedule(when); } void process() { (object->*F)(); } const char *description() { return "delay"; } }; @@ -386,16 +399,5 @@ EventQueue::reschedule(Event *event) } -////////////////////// -// -// Main Event Queue -// -// Events on this queue are processed at the *beginning* of each -// cycle, before the pipeline simulation is performed. -// -// defined in eventq.cc -// -////////////////////// -extern EventQueue mainEventQueue; -#endif // __EVENTQ_HH__ +#endif // __SIM_EVENTQ_HH__ diff --git a/sim/param.cc b/sim/param.cc index d20be8d33..e25daac30 100644 --- a/sim/param.cc +++ b/sim/param.cc @@ -27,21 +27,21 @@ */ #include +#include // for sscanf() #include #include #include -#include // for sscanf() #include -#include "sim/param.hh" -#include "sim/sim_object.hh" #include "base/inifile.hh" -#include "sim/configfile.hh" -#include "sim/config_node.hh" #include "base/misc.hh" #include "base/str.hh" #include "base/trace.hh" +#include "sim/config_node.hh" +#include "sim/configfile.hh" +#include "sim/param.hh" +#include "sim/sim_object.hh" using namespace std; @@ -474,11 +474,11 @@ EnumVectorParam::showType(ostream &os) const showEnumType(os, map, num_values); } -template EnumParam; -template EnumVectorParam; +template class EnumParam; +template class EnumVectorParam; -template EnumParam; -template EnumVectorParam; +template class EnumParam; +template class EnumVectorParam; //////////////////////////////////////////////////////////////////////// // diff --git a/sim/param.hh b/sim/param.hh index ac57afa31..f4b9d3450 100644 --- a/sim/param.hh +++ b/sim/param.hh @@ -26,9 +26,10 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __PARAM_HH__ -#define __PARAM_HH__ +#ifndef __SIM_PARAM_HH__ +#define __SIM_PARAM_HH__ +#include #include #include #include @@ -524,7 +525,7 @@ class MappedEnumParam : public EnumParam { if (!isValid()) die("not found"); - return (ENUM)value[n]; + return (ENUM)value[this->n]; } }; @@ -782,4 +783,4 @@ SimObjectVectorParam::showType(std::ostream &os) const \ template bool parseParam(const std::string &str, T &data); template void showParam(std::ostream &os, const T &data); -#endif // _PARAM_HH +#endif // _SIM_PARAM_HH_ diff --git a/sim/serialize.cc b/sim/serialize.cc index 2a5e3d398..3a073f68d 100644 --- a/sim/serialize.cc +++ b/sim/serialize.cc @@ -29,6 +29,7 @@ #include #include #include +#include #include #include diff --git a/sim/startup.cc b/sim/startup.cc index ebb4c0bc0..7cc0ac8fb 100644 --- a/sim/startup.cc +++ b/sim/startup.cc @@ -29,20 +29,32 @@ #include #include "base/misc.hh" -#include "sim/startup.hh" #include "sim/debug.hh" +#include "sim/startup.hh" typedef std::list startupq_t; -startupq_t &startupq() { static startupq_t queue; return queue; } -StartupCallback::StartupCallback() { startupq().push_back(this); } -StartupCallback::~StartupCallback() { startupq().remove(this); } + +startupq_t *startupq = NULL; + +StartupCallback::StartupCallback() +{ + if (startupq == NULL) + startupq = new startupq_t; + startupq->push_back(this); +} + +StartupCallback::~StartupCallback() +{ + startupq->remove(this); +} + void StartupCallback::startup() { } void SimStartup() { - startupq_t::iterator i = startupq().begin(); - startupq_t::iterator end = startupq().end(); + startupq_t::iterator i = startupq->begin(); + startupq_t::iterator end = startupq->end(); while (i != end) { (*i)->startup(); diff --git a/sim/syscall_emul.hh b/sim/syscall_emul.hh index 77d104449..768bc3700 100644 --- a/sim/syscall_emul.hh +++ b/sim/syscall_emul.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __SYSCALL_EMUL_HH__ -#define __SYSCALL_EMUL_HH__ +#ifndef __SIM_SYSCALL_EMUL_HH__ +#define __SIM_SYSCALL_EMUL_HH__ /// /// @file syscall_emul.hh @@ -35,14 +35,16 @@ /// This file defines objects used to emulate syscalls from the target /// application on the host machine. +#include #include #include "base/intmath.hh" // for RoundUp -#include "targetarch/isa_traits.hh" // for Addr #include "mem/functional_mem/functional_memory.hh" +#include "targetarch/isa_traits.hh" // for Addr -class Process; -class ExecContext; +#include "base/trace.hh" +#include "cpu/exec_context.hh" +#include "sim/process.hh" /// /// System call descriptor. @@ -197,6 +199,36 @@ int unlinkFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc); /// Target rename() handler. int renameFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc); +/// This struct is used to build an target-OS-dependent table that +/// maps the target's open() flags to the host open() flags. +struct OpenFlagTransTable { + int tgtFlag; //!< Target system flag value. + int hostFlag; //!< Corresponding host system flag value. +}; + + + +/// A readable name for 1,000,000, for converting microseconds to seconds. +const int one_million = 1000000; + +/// Approximate seconds since the epoch (1/1/1970). About a billion, +/// by my reckoning. We want to keep this a constant (not use the +/// real-world time) to keep simulations repeatable. +const unsigned seconds_since_epoch = 1000000000; + +/// Helper function to convert current elapsed time to seconds and +/// microseconds. +template +void +getElapsedTime(T1 &sec, T2 &usec) +{ + int cycles_per_usec = ticksPerSecond / one_million; + + int elapsed_usecs = curTick / cycles_per_usec; + sec = elapsed_usecs / one_million; + usec = elapsed_usecs % one_million; +} + ////////////////////////////////////////////////////////////////////// // // The following emulation functions are generic, but need to be @@ -238,14 +270,6 @@ ioctlFunc(SyscallDesc *desc, int callnum, Process *process, } } -/// This struct is used to build an target-OS-dependent table that -/// maps the target's open() flags to the host open() flags. -struct OpenFlagTransTable { - int tgtFlag; //!< Target system flag value. - int hostFlag; //!< Corresponding host system flag value. -}; - - /// Target open() handler. template int @@ -260,7 +284,7 @@ openFunc(SyscallDesc *desc, int callnum, Process *process, if (path == "/dev/sysdev0") { // This is a memory-mapped high-resolution timer device on Alpha. // We don't support it, so just punt. - DCOUT(SyscallWarnings) << "Ignoring open(" << path << ", ...)" << endl; + DCOUT(SyscallWarnings) << "Ignoring open(" << path << ", ...)" << std::endl; return -ENOENT; } @@ -278,7 +302,7 @@ openFunc(SyscallDesc *desc, int callnum, Process *process, // any target flags left? if (tgtFlags != 0) - cerr << "Syscall: open: cannot decode flags: " << tgtFlags << endl; + std::cerr << "Syscall: open: cannot decode flags: " << tgtFlags << std::endl; #ifdef __CYGWIN32__ hostFlags |= O_BINARY; @@ -414,7 +438,7 @@ getrlimitFunc(SyscallDesc *desc, int callnum, Process *process, break; default: - cerr << "getrlimitFunc: unimplemented resource " << resource << endl; + std::cerr << "getrlimitFunc: unimplemented resource " << resource << std::endl; abort(); break; } @@ -423,28 +447,6 @@ getrlimitFunc(SyscallDesc *desc, int callnum, Process *process, return 0; } -/// A readable name for 1,000,000, for converting microseconds to seconds. -const int one_million = 1000000; - -/// Approximate seconds since the epoch (1/1/1970). About a billion, -/// by my reckoning. We want to keep this a constant (not use the -/// real-world time) to keep simulations repeatable. -const unsigned seconds_since_epoch = 1000000000; - -/// Helper function to convert current elapsed time to seconds and -/// microseconds. -template -void -getElapsedTime(T1 &sec, T2 &usec) -{ - int cycles_per_usec = ticksPerSecond / one_million; - - int elapsed_usecs = curTick / cycles_per_usec; - sec = elapsed_usecs / one_million; - usec = elapsed_usecs % one_million; -} - - /// Target gettimeofday() handler. template int @@ -476,7 +478,7 @@ getrusageFunc(SyscallDesc *desc, int callnum, Process *process, // plow ahead DCOUT(SyscallWarnings) << "Warning: getrusage() only supports RUSAGE_SELF." - << " Parameter " << who << " ignored." << endl; + << " Parameter " << who << " ignored." << std::endl; } getElapsedTime(rup->ru_utime.tv_sec, rup->ru_utime.tv_usec); @@ -502,6 +504,4 @@ getrusageFunc(SyscallDesc *desc, int callnum, Process *process, return 0; } - - -#endif // __SYSCALL_EMUL_HH__ +#endif // __SIM_SYSCALL_EMUL_HH__ diff --git a/sim/universe.cc b/sim/universe.cc index 824b985fa..8311b0618 100644 --- a/sim/universe.cc +++ b/sim/universe.cc @@ -28,6 +28,7 @@ #include #include +#include #include #include From f31a27a030d2e93fef2934aa8642609bb38974af Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Tue, 18 Jan 2005 11:43:45 -0500 Subject: [PATCH 02/20] Move trace data function to .cc file. --HG-- extra : convert_revision : 8180068747489978a2bbaa096dc73b0cfd14b052 --- cpu/simple_cpu/simple_cpu.cc | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index d48f93663..e3cce28ae 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -74,6 +74,15 @@ using namespace std; +template +void +SimpleCPU::trace_data(T data) { + if (traceData) { + traceData->setData(data); + } +} + + SimpleCPU::TickEvent::TickEvent(SimpleCPU *c) : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), multiplier(1) { From 7ec713edc8f0a50e05e84b7f6db907eaca7aa345 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 27 Jan 2005 16:01:25 -0500 Subject: [PATCH 07/20] added support for outputing Dot if pydot is installed --HG-- extra : convert_revision : bdb1032cddb2478e999399647f893d320260ef7e --- sim/pyconfig/m5config.py | 56 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/sim/pyconfig/m5config.py b/sim/pyconfig/m5config.py index 4e2a377b0..020cc9f04 100644 --- a/sim/pyconfig/m5config.py +++ b/sim/pyconfig/m5config.py @@ -26,6 +26,11 @@ from __future__ import generators import os, re, sys, types +noDot = False +try: + import pydot +except: + noDot = True env = {} env.update(os.environ) @@ -699,6 +704,48 @@ class Node(object): for c in self.children: c.display() + # print type and parameter values to .ini file + def outputDot(self, dot): + + + label = "{%s|" % self.path + if isSimObject(self.realtype): + label += '%s|' % self.type + + if self.children: + # instantiate children in same order they were added for + # backward compatibility (else we can end up with cpu1 + # before cpu0). + for c in self.children: + dot.add_edge(pydot.Edge(self.path,c.path, style="bold")) + + simobjs = [] + for param in self.params: + try: + if param.value is None: + raise AttributeError, 'Parameter with no value' + + value = param.convert(param.value) + string = param.string(value) + except: + print 'exception in %s:%s' % (self.name, param.name) + raise + ptype = eval(param.ptype) + if isConfigNode(ptype) and string != "Null": + simobjs.append(string) + else: + label += '%s = %s\\n' % (param.name, string) + + for so in simobjs: + label += "|<%s> %s" % (so, so) + dot.add_edge(pydot.Edge("%s:%s" % (self.path, so), so, tailport="w")) + label += '}' + dot.add_node(pydot.Node(self.path,shape="Mrecord",label=label)) + + # recursively dump out children + for c in self.children: + c.outputDot(dot) + def _string(cls, value): if not isinstance(value, Node): raise AttributeError, 'expecting %s got %s' % (Node, value) @@ -1234,6 +1281,15 @@ def instantiate(root): instance = root.instantiate('root') instance.fixup() instance.display() + if not noDot: + dot = pydot.Dot() + instance.outputDot(dot) + dot.orientation = "portrait" + dot.size = "8.5,11" + dot.ranksep="equally" + dot.rank="samerank" + dot.write("config.dot") + dot.write_ps("config.ps") from objects import * From c3aaf43c886b12758e47844eaf3988937e31c42e Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Fri, 28 Jan 2005 15:57:40 -0500 Subject: [PATCH 08/20] make nat runs used vegas congestion avoidance implementation. --HG-- extra : convert_revision : 29d2c4b70c56f13642466bd88c82f36ba849ed9d --- configs/boot/nat-netperf-maerts-client.rcS | 1 + configs/boot/nat-netperf-server.rcS | 1 + configs/boot/nat-netperf-stream-client.rcS | 1 + configs/boot/nat-spec-surge-client.rcS | 1 + configs/boot/nat-spec-surge-server.rcS | 1 + configs/boot/natbox-netperf.rcS | 2 ++ configs/boot/natbox-spec-surge.rcS | 1 + 7 files changed, 8 insertions(+) diff --git a/configs/boot/nat-netperf-maerts-client.rcS b/configs/boot/nat-netperf-maerts-client.rcS index fa3e174e7..ab9fd8c4e 100644 --- a/configs/boot/nat-netperf-maerts-client.rcS +++ b/configs/boot/nat-netperf-maerts-client.rcS @@ -11,6 +11,7 @@ route add default gw 10.0.0.1 echo "0" > /proc/sys/net/ipv4/tcp_timestamps echo "0" > /proc/sys/net/ipv4/tcp_sack +echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem diff --git a/configs/boot/nat-netperf-server.rcS b/configs/boot/nat-netperf-server.rcS index c0646b61c..5b094b790 100644 --- a/configs/boot/nat-netperf-server.rcS +++ b/configs/boot/nat-netperf-server.rcS @@ -9,6 +9,7 @@ ifconfig eth0 $SERVER txqueuelen 1000 echo "0" > /proc/sys/net/ipv4/tcp_timestamps echo "0" > /proc/sys/net/ipv4/tcp_sack +echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem diff --git a/configs/boot/nat-netperf-stream-client.rcS b/configs/boot/nat-netperf-stream-client.rcS index f0f3a23ce..d0213c265 100644 --- a/configs/boot/nat-netperf-stream-client.rcS +++ b/configs/boot/nat-netperf-stream-client.rcS @@ -8,6 +8,7 @@ ifconfig eth0 $CLIENT txqueuelen 1000 echo "0" > /proc/sys/net/ipv4/tcp_timestamps echo "0" > /proc/sys/net/ipv4/tcp_sack +echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem diff --git a/configs/boot/nat-spec-surge-client.rcS b/configs/boot/nat-spec-surge-client.rcS index 2c0b46607..a3bc512db 100644 --- a/configs/boot/nat-spec-surge-client.rcS +++ b/configs/boot/nat-spec-surge-client.rcS @@ -20,6 +20,7 @@ echo "0" > /proc/sys/net/ipv4/tcp_timestamps echo "0" > /proc/sys/net/ipv4/tcp_sack echo "15" > /proc/sys/net/ipv4/tcp_fin_timeout echo "16384" > /proc/sys/net/ipv4/tcp_max_syn_backlog +echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid echo "1024 65535" > /proc/sys/net/ipv4/ip_local_port_range echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_rmem diff --git a/configs/boot/nat-spec-surge-server.rcS b/configs/boot/nat-spec-surge-server.rcS index ed0e96a44..9b5674e63 100755 --- a/configs/boot/nat-spec-surge-server.rcS +++ b/configs/boot/nat-spec-surge-server.rcS @@ -23,6 +23,7 @@ echo "0" > /proc/sys/net/ipv4/tcp_timestamps echo "0" > /proc/sys/net/ipv4/tcp_sack echo "15" > /proc/sys/net/ipv4/tcp_fin_timeout echo "16384" > /proc/sys/net/ipv4/tcp_max_syn_backlog +echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid echo "1024 65535" > /proc/sys/net/ipv4/ip_local_port_range echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_rmem diff --git a/configs/boot/natbox-netperf.rcS b/configs/boot/natbox-netperf.rcS index d665670fe..5ec08c1a2 100644 --- a/configs/boot/natbox-netperf.rcS +++ b/configs/boot/natbox-netperf.rcS @@ -10,6 +10,8 @@ ifconfig eth1 $INTIF txqueuelen 1000 echo "0" > /proc/sys/net/ipv4/tcp_timestamps echo "0" > /proc/sys/net/ipv4/tcp_sack +echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid + echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem diff --git a/configs/boot/natbox-spec-surge.rcS b/configs/boot/natbox-spec-surge.rcS index ed74b71bd..d612424d2 100644 --- a/configs/boot/natbox-spec-surge.rcS +++ b/configs/boot/natbox-spec-surge.rcS @@ -10,6 +10,7 @@ ifconfig eth1 $INTIF txqueuelen 1000 echo "0" > /proc/sys/net/ipv4/tcp_timestamps echo "0" > /proc/sys/net/ipv4/tcp_sack +echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem From da269014dad5dce6136c53914d451ff9e6ef3e62 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Sun, 30 Jan 2005 16:58:39 -0500 Subject: [PATCH 09/20] removed all tsunami dependence on tlaserreg.h (RTC defines) and all but tlaser_node.cc dependence on tlaserreg.h dev/tsunami_io.cc: dev/tsunamireg.h: removed tlaserreg.h --HG-- extra : convert_revision : 148a5d79530e5ed721a49279f684a48041deed2b --- dev/rtcreg.h | 44 ++++++++++++++++++++++++++++++++++++++++++++ dev/tsunami_io.cc | 23 ++++++++++++----------- dev/tsunamireg.h | 17 ----------------- 3 files changed, 56 insertions(+), 28 deletions(-) create mode 100644 dev/rtcreg.h diff --git a/dev/rtcreg.h b/dev/rtcreg.h new file mode 100644 index 000000000..8e1f51bfa --- /dev/null +++ b/dev/rtcreg.h @@ -0,0 +1,44 @@ + +/* + * Copyright (c) 2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#define RTC_SEC 0x00 +#define RTC_SEC_ALRM 0x01 +#define RTC_MIN 0x02 +#define RTC_MIN_ALRM 0x03 +#define RTC_HR 0x04 +#define RTC_HR_ALRM 0x05 +#define RTC_DOW 0x06 +#define RTC_DOM 0x07 +#define RTC_MON 0x08 +#define RTC_YEAR 0x09 +#define RTC_CNTRL_REGA 0x0A +#define RTC_CNTRL_REGB 0x0B +#define RTC_CNTRL_REGC 0x0C +#define RTC_CNTRL_REGD 0x0D + diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc index a223c95c7..94a951d2c 100644 --- a/dev/tsunami_io.cc +++ b/dev/tsunami_io.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2004 The Regents of The University of Michigan + * Copyright (c) 2004-2005 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -45,6 +45,7 @@ #include "sim/builder.hh" #include "dev/tsunami_cchip.hh" #include "dev/tsunamireg.h" +#include "dev/rtcreg.h" #include "mem/functional_mem/memory_control.hh" using namespace std; @@ -217,36 +218,36 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data) return No_Fault; case TSDEV_RTC_DATA: switch(RTCAddress) { - case RTC_CONTROL_REGISTERA: + case RTC_CNTRL_REGA: *(uint8_t*)data = uip << 7 | 0x26; uip = !uip; return No_Fault; - case RTC_CONTROL_REGISTERB: + case RTC_CNTRL_REGB: // DM and 24/12 and UIE *(uint8_t*)data = 0x46; return No_Fault; - case RTC_CONTROL_REGISTERC: + case RTC_CNTRL_REGC: // If we want to support RTC user access in linux // This won't work, but for now it's fine *(uint8_t*)data = 0x00; return No_Fault; - case RTC_CONTROL_REGISTERD: + case RTC_CNTRL_REGD: panic("RTC Control Register D not implemented"); - case RTC_SECOND: + case RTC_SEC: *(uint8_t *)data = tm.tm_sec; return No_Fault; - case RTC_MINUTE: + case RTC_MIN: *(uint8_t *)data = tm.tm_min; return No_Fault; - case RTC_HOUR: + case RTC_HR: *(uint8_t *)data = tm.tm_hour; return No_Fault; - case RTC_DAY_OF_WEEK: + case RTC_DOW: *(uint8_t *)data = tm.tm_wday; return No_Fault; - case RTC_DAY_OF_MONTH: + case RTC_DOM: *(uint8_t *)data = tm.tm_mday; - case RTC_MONTH: + case RTC_MON: *(uint8_t *)data = tm.tm_mon + 1; return No_Fault; case RTC_YEAR: diff --git a/dev/tsunamireg.h b/dev/tsunamireg.h index 3304082a5..290f21a5b 100644 --- a/dev/tsunamireg.h +++ b/dev/tsunamireg.h @@ -122,23 +122,6 @@ #define TSDEV_RTC_ADDR 0x70 #define TSDEV_RTC_DATA 0x71 -// RTC defines -#define RTC_SECOND 0 // second of minute [0..59] -#define RTC_SECOND_ALARM 1 // seconds to alarm -#define RTC_MINUTE 2 // minute of hour [0..59] -#define RTC_MINUTE_ALARM 3 // minutes to alarm -#define RTC_HOUR 4 // hour of day [0..23] -#define RTC_HOUR_ALARM 5 // hours to alarm -#define RTC_DAY_OF_WEEK 6 // day of week [1..7] -#define RTC_DAY_OF_MONTH 7 // day of month [1..31] -#define RTC_MONTH 8 // month of year [1..12] -#define RTC_YEAR 9 // year [00..99] -#define RTC_CONTROL_REGISTERA 10 // control register A -#define RTC_CONTROL_REGISTERB 11 // control register B -#define RTC_CONTROL_REGISTERC 12 // control register C -#define RTC_CONTROL_REGISTERD 13 // control register D -#define RTC_REGNUMBER_RTC_CR1 0x6A // control register 1 - #define PCHIP_PCI0_MEMORY ULL(0x00000000000) #define PCHIP_PCI0_IO ULL(0x001FC000000) #define TSUNAMI_UNCACHABLE_BIT ULL(0x80000000000) From 45bb2bf14d501f4ccab0bb399f53f8b35f8c82e6 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Tue, 1 Feb 2005 17:35:01 -0500 Subject: [PATCH 11/20] some changes for a split lifo in the new python config. objects/BaseCache.mpy: add all the Split parameters to the BaseCache simobj. --HG-- extra : convert_revision : 4fcba3ce730f730ca8628ac7f4aa0fb9476474ab --- objects/BaseCache.mpy | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/objects/BaseCache.mpy b/objects/BaseCache.mpy index 67ca3c04e..5f22a344a 100644 --- a/objects/BaseCache.mpy +++ b/objects/BaseCache.mpy @@ -12,6 +12,8 @@ simobj BaseCache(BaseMem): do_copy = Param.Bool(false, "perform fast copies in the cache") hash_delay = Param.Int(1, "time in cycles of hash access") in_bus = Param.Bus(NULL, "incoming bus object") + lifo = Param.Bool(false, + "whether this NIC partition should use LIFO repl. policy") max_miss_count = Param.Counter(0, "number of misses to handle before calling exit") mshrs = Param.Int("number of MSHRs (max outstanding requests)") @@ -21,10 +23,15 @@ simobj BaseCache(BaseMem): protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use") repl = Param.Repl(NULL, "replacement policy") size = Param.Int("capacity in bytes") + split = Param.Bool(false, "whether or not this cache is split") + split_size = Param.Int(0, + "How many ways of the cache belong to CPU/LRU partition") store_compressed = Param.Bool(false, "Store compressed data in the cache") subblock_size = Param.Int(0, "Size of subblock in IIC used for compression") tgts_per_mshr = Param.Int("max number of accesses per MSHR") trace_addr = Param.Addr(0, "address to trace") + two_queue = Param.Bool(false, + "whether the lifo should have two queue replacement") write_buffers = Param.Int(8, "number of write buffers") From a736a8fab6dd1ae0d5546939bc0c7fc4aec003e8 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 2 Feb 2005 21:13:01 -0500 Subject: [PATCH 12/20] Update config file language to take simobj and no longer use siminst objects/AlphaConsole.mpy: objects/AlphaTLB.mpy: objects/BadDevice.mpy: objects/BaseCPU.mpy: objects/BaseCache.mpy: objects/BaseSystem.mpy: objects/Bus.mpy: objects/CoherenceProtocol.mpy: objects/Device.mpy: objects/DiskImage.mpy: objects/Ethernet.mpy: objects/Ide.mpy: objects/IntrControl.mpy: objects/MemTest.mpy: objects/Pci.mpy: objects/PhysicalMemory.mpy: objects/Platform.mpy: objects/Process.mpy: objects/Repl.mpy: objects/Root.mpy: objects/SimConsole.mpy: objects/SimpleDisk.mpy: objects/Tsunami.mpy: objects/Uart.mpy: simobj now requires a type= line if it is actually intended to be a type sim/pyconfig/SConscript: keep track of the filename of embedded files for better error messages. sim/pyconfig/m5config.py: Add support for the trickery done with the compiler to get the simobj language feature added to the importer. fix the bug that gave objects the wrong name in error messages. test/genini.py: Globals have been fixed and use execfile --HG-- extra : convert_revision : b74495fd6f3479a87ecea7f1234ebb6731279b2b --- objects/AlphaConsole.mpy | 3 ++- objects/AlphaTLB.mpy | 3 +++ objects/BadDevice.mpy | 1 + objects/BaseCPU.mpy | 1 + objects/BaseCache.mpy | 1 + objects/BaseSystem.mpy | 1 + objects/Bus.mpy | 1 + objects/CoherenceProtocol.mpy | 1 + objects/Device.mpy | 6 ++++-- objects/DiskImage.mpy | 4 +++- objects/Ethernet.mpy | 9 +++++++++ objects/Ide.mpy | 2 ++ objects/IntrControl.mpy | 1 + objects/MemTest.mpy | 1 + objects/Pci.mpy | 4 +++- objects/PhysicalMemory.mpy | 1 + objects/Platform.mpy | 1 + objects/Process.mpy | 3 +++ objects/Repl.mpy | 2 ++ objects/Root.mpy | 1 + objects/SimConsole.mpy | 4 +++- objects/SimpleDisk.mpy | 1 + objects/Tsunami.mpy | 6 +++++- objects/Uart.mpy | 1 + sim/pyconfig/SConscript | 15 ++++++++------- sim/pyconfig/m5config.py | 36 +++++++++++++++++++++-------------- test/genini.py | 4 ++-- 27 files changed, 84 insertions(+), 30 deletions(-) diff --git a/objects/AlphaConsole.mpy b/objects/AlphaConsole.mpy index bcb47bf8b..79918a01e 100644 --- a/objects/AlphaConsole.mpy +++ b/objects/AlphaConsole.mpy @@ -1,8 +1,9 @@ from Device import PioDevice simobj AlphaConsole(PioDevice): + type = 'AlphaConsole' cpu = Param.BaseCPU(Super, "Processor") disk = Param.SimpleDisk("Simple Disk") - num_cpus = Param.Int(1, "Number of CPU's") + num_cpus = Param.Int(1, "Number of CPUs") sim_console = Param.SimConsole(Super, "The Simulator Console") system = Param.BaseSystem(Super, "system object") diff --git a/objects/AlphaTLB.mpy b/objects/AlphaTLB.mpy index 571b98374..8e7cd62cc 100644 --- a/objects/AlphaTLB.mpy +++ b/objects/AlphaTLB.mpy @@ -1,9 +1,12 @@ simobj AlphaTLB(SimObject): + type = 'AlphaTLB' abstract = True size = Param.Int("TLB size") simobj AlphaDTB(AlphaTLB): + type = 'AlphaDTB' size = 64 simobj AlphaITB(AlphaTLB): + type = 'AlphaITB' size = 48 diff --git a/objects/BadDevice.mpy b/objects/BadDevice.mpy index 5c56b8036..35a12e0bf 100644 --- a/objects/BadDevice.mpy +++ b/objects/BadDevice.mpy @@ -1,4 +1,5 @@ from Device import PioDevice simobj BadDevice(PioDevice): + type = 'BadDevice' devicename = Param.String("Name of device to error on") diff --git a/objects/BaseCPU.mpy b/objects/BaseCPU.mpy index 2aca9120d..516509c1e 100644 --- a/objects/BaseCPU.mpy +++ b/objects/BaseCPU.mpy @@ -1,4 +1,5 @@ simobj BaseCPU(SimObject): + type = 'BaseCPU' abstract = True icache = Param.BaseMem(NULL, "L1 instruction cache object") dcache = Param.BaseMem(NULL, "L1 data cache object") diff --git a/objects/BaseCache.mpy b/objects/BaseCache.mpy index 5f22a344a..95a7f0b35 100644 --- a/objects/BaseCache.mpy +++ b/objects/BaseCache.mpy @@ -1,6 +1,7 @@ from BaseMem import BaseMem simobj BaseCache(BaseMem): + type = 'BaseCache' adaptive_compression = Param.Bool(false, "Use an adaptive compression scheme") assoc = Param.Int("associativity") diff --git a/objects/BaseSystem.mpy b/objects/BaseSystem.mpy index 2a8b98338..460bce736 100644 --- a/objects/BaseSystem.mpy +++ b/objects/BaseSystem.mpy @@ -1,4 +1,5 @@ simobj BaseSystem(SimObject): + type = 'BaseSystem' abstract = True memctrl = Param.MemoryController(Super, "memory controller") physmem = Param.PhysicalMemory(Super, "phsyical memory") diff --git a/objects/Bus.mpy b/objects/Bus.mpy index 9e112bfe6..025d69785 100644 --- a/objects/Bus.mpy +++ b/objects/Bus.mpy @@ -1,5 +1,6 @@ from BaseHier import BaseHier simobj Bus(BaseHier): + type = 'Bus' clock_ratio = Param.Int("ratio of CPU to bus frequency") width = Param.Int("bus width in bytes") diff --git a/objects/CoherenceProtocol.mpy b/objects/CoherenceProtocol.mpy index a2518bf39..c77348f0a 100644 --- a/objects/CoherenceProtocol.mpy +++ b/objects/CoherenceProtocol.mpy @@ -1,5 +1,6 @@ Coherence = Enum('uni', 'msi', 'mesi', 'mosi', 'moesi') simobj CoherenceProtocol(SimObject): + type = 'CoherenceProtocol' do_upgrades = Param.Bool(true, "use upgrade transactions?") protocol = Param.Coherence("name of coherence protocol") diff --git a/objects/Device.mpy b/objects/Device.mpy index babc8aa9d..47f8db1cb 100644 --- a/objects/Device.mpy +++ b/objects/Device.mpy @@ -11,21 +11,23 @@ from FunctionalMemory import FunctionalMemory # initialization phase at which point all SimObject pointers will be # valid. simobj FooPioDevice(FunctionalMemory): - abstract = True type = 'PioDevice' + abstract = True addr = Param.Addr("Device Address") mmu = Param.MemoryController(Super, "Memory Controller") io_bus = Param.Bus(NULL, "The IO Bus to attach to") pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles") simobj FooDmaDevice(FooPioDevice): - abstract = True type = 'DmaDevice' + abstract = True simobj PioDevice(FooPioDevice): + type = 'PioDevice' abstract = True platform = Param.Platform(Super, "Platform") simobj DmaDevice(PioDevice): + type = 'DmaDevice' abstract = True diff --git a/objects/DiskImage.mpy b/objects/DiskImage.mpy index bea2e56a8..908805ba0 100644 --- a/objects/DiskImage.mpy +++ b/objects/DiskImage.mpy @@ -1,12 +1,14 @@ simobj DiskImage(SimObject): + type = 'DiskImage' abstract = True image_file = Param.String("disk image file") read_only = Param.Bool(false, "read only image") simobj RawDiskImage(DiskImage): - pass + type = 'RawDiskImage' simobj CowDiskImage(DiskImage): + type = 'CowDiskImage' child = Param.DiskImage("child image") table_size = Param.Int(65536, "initial table size") image_file = '' diff --git a/objects/Ethernet.mpy b/objects/Ethernet.mpy index 64eab00a3..f9479a5c2 100644 --- a/objects/Ethernet.mpy +++ b/objects/Ethernet.mpy @@ -2,10 +2,12 @@ from Device import DmaDevice from Pci import PciDevice simobj EtherInt(SimObject): + type = 'EtherInt' abstract = True peer = Param.EtherInt(NULL, "peer interface") simobj EtherLink(SimObject): + type = 'EtherLink' int1 = Param.EtherInt("interface 1") int2 = Param.EtherInt("interface 2") delay = Param.Tick(0, "transmit delay of packets in us") @@ -13,20 +15,24 @@ simobj EtherLink(SimObject): dump = Param.EtherDump(NULL, "dump object") simobj EtherBus(SimObject): + type = 'EtherBus' loopback = Param.Bool(true, "send packet back to the interface from which it came") dump = Param.EtherDump(NULL, "dump object") speed = Param.UInt64(100000000, "bus speed in bits per second") simobj EtherTap(EtherInt): + type = 'EtherTap' bufsz = Param.Int(10000, "tap buffer size") dump = Param.EtherDump(NULL, "dump object") port = Param.UInt16(3500, "tap port") simobj EtherDump(SimObject): + type = 'EtherDump' file = Param.String("dump file") simobj EtherDev(DmaDevice): + type = 'EtherDev' hardware_address = Param.EthernetAddr(NextEthernetAddr, "Ethernet Hardware Address") @@ -47,6 +53,7 @@ simobj EtherDev(DmaDevice): tlaser = Param.Turbolaser(Super, "Turbolaser") simobj NSGigE(PciDevice): + type = 'NSGigE' hardware_address = Param.EthernetAddr(NextEthernetAddr, "Ethernet Hardware Address") @@ -69,9 +76,11 @@ simobj NSGigE(PciDevice): physmem = Param.PhysicalMemory(Super, "Physical Memory") simobj EtherDevInt(EtherInt): + type = 'EtherDevInt' device = Param.EtherDev("Ethernet device of this interface") simobj NSGigEInt(EtherInt): + type = 'NSGigEInt' device = Param.NSGigE("Ethernet device of this interface") diff --git a/objects/Ide.mpy b/objects/Ide.mpy index 816b33c8c..c4aa2aca0 100644 --- a/objects/Ide.mpy +++ b/objects/Ide.mpy @@ -3,10 +3,12 @@ from Pci import PciDevice IdeID = Enum('master', 'slave') simobj IdeDisk(SimObject): + type = 'IdeDisk' delay = Param.Tick(1, "Fixed disk delay in microseconds") driveID = Param.IdeID('master', "Drive ID") image = Param.DiskImage("Disk image") physmem = Param.PhysicalMemory(Super, "Physical memory") simobj IdeController(PciDevice): + type = 'IdeController' disks = VectorParam.IdeDisk("IDE disks attached to this controller") diff --git a/objects/IntrControl.mpy b/objects/IntrControl.mpy index 7c97746ff..1ef5a17ee 100644 --- a/objects/IntrControl.mpy +++ b/objects/IntrControl.mpy @@ -1,2 +1,3 @@ simobj IntrControl(SimObject): + type = 'IntrControl' cpu = Param.BaseCPU(Super, "the cpu") diff --git a/objects/MemTest.mpy b/objects/MemTest.mpy index 49319e163..1ec33a30c 100644 --- a/objects/MemTest.mpy +++ b/objects/MemTest.mpy @@ -1,4 +1,5 @@ simobj MemTest(SimObject): + type = 'MemTest' cache = Param.BaseCache("L1 cache") check_mem = Param.FunctionalMemory("check memory") main_mem = Param.FunctionalMemory("hierarchical memory") diff --git a/objects/Pci.mpy b/objects/Pci.mpy index a7763139f..caa3c52ff 100644 --- a/objects/Pci.mpy +++ b/objects/Pci.mpy @@ -1,6 +1,7 @@ from Device import FooPioDevice, DmaDevice simobj PciConfigData(FooPioDevice): + type = 'PciConfigData' addr = 0xffffffffffffffffL VendorID = Param.UInt16("Vendor ID") DeviceID = Param.UInt16("Device ID") @@ -38,9 +39,10 @@ simobj PciConfigData(FooPioDevice): MinimumGrant = Param.UInt8(0x00, "Minimum Grant") simobj PciConfigAll(FooPioDevice): - pass + type = 'PciConfigAll' simobj PciDevice(DmaDevice): + type = 'PciDevice' abstract = True pci_bus = Param.Int("PCI bus") pci_dev = Param.Int("PCI device number") diff --git a/objects/PhysicalMemory.mpy b/objects/PhysicalMemory.mpy index 9644c503a..d1e4ad4b4 100644 --- a/objects/PhysicalMemory.mpy +++ b/objects/PhysicalMemory.mpy @@ -1,6 +1,7 @@ from FunctionalMemory import FunctionalMemory simobj PhysicalMemory(FunctionalMemory): + type = 'PhysicalMemory' range = Param.AddrRange("Device Address") file = Param.String('', "memory mapped file") mmu = Param.MemoryController(Super, "Memory Controller") diff --git a/objects/Platform.mpy b/objects/Platform.mpy index 870026259..d0510eaf8 100644 --- a/objects/Platform.mpy +++ b/objects/Platform.mpy @@ -1,4 +1,5 @@ simobj Platform(SimObject): + type = 'Platform' abstract = True interrupt_frequency = Param.Tick(1200, "frequency of interrupts") intrctrl = Param.IntrControl(Super, "interrupt controller") diff --git a/objects/Process.mpy b/objects/Process.mpy index 4f5c4a674..6a91c09c2 100644 --- a/objects/Process.mpy +++ b/objects/Process.mpy @@ -1,12 +1,15 @@ simobj Process(SimObject): + type = 'Process' abstract = True output = Param.String('cout', 'filename for stdout/stderr') simobj LiveProcess(Process): + type = 'LiveProcess' cmd = VectorParam.String("command line (executable plus arguments)") env = VectorParam.String('', "environment settings") input = Param.String('cin', "filename for stdin") simobj EioProcess(Process): + type = 'EioProcess' chkpt = Param.String('', "EIO checkpoint file name (optional)") file = Param.String("EIO trace file name") diff --git a/objects/Repl.mpy b/objects/Repl.mpy index 87e7bfb7d..fff5a2a02 100644 --- a/objects/Repl.mpy +++ b/objects/Repl.mpy @@ -1,7 +1,9 @@ simobj Repl(SimObject): + type = 'Repl' abstract = True simobj GenRepl(Repl): + type = 'GenRepl' fresh_res = Param.Int("associativity") num_pools = Param.Int("capacity in bytes") pool_res = Param.Int("block size in bytes") diff --git a/objects/Root.mpy b/objects/Root.mpy index b12771689..5806ec826 100644 --- a/objects/Root.mpy +++ b/objects/Root.mpy @@ -1,5 +1,6 @@ from HierParams import HierParams simobj Root(SimObject): + type = 'Root' frequency = Param.Tick(200000000, "tick frequency") output_dir = Param.String('.', "directory to output data to") output_file = Param.String('cout', "file to dump simulator output to") diff --git a/objects/SimConsole.mpy b/objects/SimConsole.mpy index 0676738f9..1231e81dc 100644 --- a/objects/SimConsole.mpy +++ b/objects/SimConsole.mpy @@ -1,9 +1,11 @@ simobj ConsoleListener(SimObject): + type = 'ConsoleListener' port = Param.UInt16(3456, "listen port") simobj SimConsole(SimObject): + type = 'SimConsole' append_name = Param.Bool(true, "append name() to filename") intr_control = Param.IntrControl(Super, "interrupt controller") listener = Param.ConsoleListener("console listener") number = Param.Int(0, "console number") - output = Param.String("", "file to dump output to") + output = Param.String('', "file to dump output to") diff --git a/objects/SimpleDisk.mpy b/objects/SimpleDisk.mpy index 46bbdb8fd..c4dd5435b 100644 --- a/objects/SimpleDisk.mpy +++ b/objects/SimpleDisk.mpy @@ -1,3 +1,4 @@ simobj SimpleDisk(SimObject): + type = 'SimpleDisk' disk = Param.DiskImage("Disk Image") physmem = Param.PhysicalMemory(Super, "Physical Memory") diff --git a/objects/Tsunami.mpy b/objects/Tsunami.mpy index 6f9555d49..cfe23977e 100644 --- a/objects/Tsunami.mpy +++ b/objects/Tsunami.mpy @@ -2,20 +2,24 @@ from Device import FooPioDevice from Platform import Platform simobj Tsunami(Platform): + type = 'Tsunami' pciconfig = Param.PciConfigAll("PCI configuration") system = Param.BaseSystem(Super, "system") interrupt_frequency = Param.Int(1024, "frequency of interrupts") simobj TsunamiCChip(FooPioDevice): + type = 'TsunamiCChip' tsunami = Param.Tsunami(Super, "Tsunami") simobj TsunamiFake(FooPioDevice): - pass + type = 'TsunamiFake' simobj TsunamiIO(FooPioDevice): + type = 'TsunamiIO' time = Param.UInt64(1136073600, "System time to use (0 for actual time, default is 1/1/06)") tsunami = Param.Tsunami(Super, "Tsunami") simobj TsunamiPChip(FooPioDevice): + type = 'TsunamiPChip' tsunami = Param.Tsunami(Super, "Tsunami") diff --git a/objects/Uart.mpy b/objects/Uart.mpy index a54e19dcd..76ee8805f 100644 --- a/objects/Uart.mpy +++ b/objects/Uart.mpy @@ -1,5 +1,6 @@ from Device import PioDevice simobj Uart(PioDevice): + type = 'Uart' console = Param.SimConsole(Super, "The console") size = Param.Addr(0x8, "Device size") diff --git a/sim/pyconfig/SConscript b/sim/pyconfig/SConscript index 127b0efae..5708ac9a8 100644 --- a/sim/pyconfig/SConscript +++ b/sim/pyconfig/SConscript @@ -28,14 +28,15 @@ import os, os.path, re -def WriteEmbeddedPyFile(target, source, path, name, ext): +def WriteEmbeddedPyFile(target, source, path, name, ext, filename): if isinstance(source, str): source = file(source, 'r') if isinstance(target, str): target = file(target, 'w') - print >>target, "AddModule(%s, %s, %s, '''\\" % (`path`, `name`, `ext`) + print >>target, "AddModule(%s, %s, %s, %s, '''\\" % \ + (`path`, `name`, `ext`, `filename`) for line in source: line = line @@ -105,7 +106,7 @@ def MakeEmbeddedPyFile(target, source, env): name,ext = pyfile.split('.') if name == '__init__': node['.hasinit'] = True - node[pyfile] = (src,name,ext) + node[pyfile] = (src,name,ext,src) done = False while not done: @@ -136,12 +137,12 @@ def MakeEmbeddedPyFile(target, source, env): raise NameError, 'package directory missing __init__.py' populate(entry, path + [ name ]) else: - pyfile,name,ext = entry - files.append((pyfile, path, name, ext)) + pyfile,name,ext,filename = entry + files.append((pyfile, path, name, ext, filename)) populate(tree) - for pyfile, path, name, ext in files: - WriteEmbeddedPyFile(target, pyfile, path, name, ext) + for pyfile, path, name, ext, filename in files: + WriteEmbeddedPyFile(target, pyfile, path, name, ext, filename) CFileCounter = 0 def MakePythonCFile(target, source, env): diff --git a/sim/pyconfig/m5config.py b/sim/pyconfig/m5config.py index 4c5fc3bf9..5ba7542a0 100644 --- a/sim/pyconfig/m5config.py +++ b/sim/pyconfig/m5config.py @@ -221,6 +221,10 @@ def isParamContext(value): return False +class_decorator = '_M5M5_SIMOBJECT_' +expr_decorator = '_M5M5_EXPRESSION_' +dot_decorator = '_M5M5_DOT_' + # The metaclass for ConfigNode (and thus for everything that derives # from ConfigNode, including SimObject). This class controls how new # classes that derive from ConfigNode are instantiated, and provides @@ -230,7 +234,6 @@ def isParamContext(value): class MetaConfigNode(type): keywords = { 'abstract' : types.BooleanType, 'check' : types.FunctionType, - '_init' : types.FunctionType, 'type' : (types.NoneType, types.StringType) } # __new__ is called before __init__, and is where the statements @@ -246,6 +249,11 @@ class MetaConfigNode(type): '_disable' : {} } for key,val in dict.items(): + del dict[key] + + if key.startswith(expr_decorator): + key = key[len(expr_decorator):] + if mcls.keywords.has_key(key): if not isinstance(val, mcls.keywords[key]): raise TypeError, \ @@ -255,11 +263,9 @@ class MetaConfigNode(type): if isinstance(val, types.FunctionType): val = classmethod(val) priv[key] = val - del dict[key] elif key.startswith('_'): priv[key] = val - del dict[key] elif not isNullPointer(val) and isConfigNode(val): dict[key] = val() @@ -267,19 +273,22 @@ class MetaConfigNode(type): elif isSimObjSequence(val): dict[key] = [ v() for v in val ] + else: + dict[key] = val + # If your parent has a value in it that's a config node, clone it. for base in bases: if not isConfigNode(base): continue - for name,value in base._values.iteritems(): - if dict.has_key(name): + for key,value in base._values.iteritems(): + if dict.has_key(key): continue if isConfigNode(value): - priv['_values'][name] = value() + priv['_values'][key] = value() elif isSimObjSequence(value): - priv['_values'][name] = [ val() for val in value ] + priv['_values'][key] = [ val() for val in value ] # entries left in dict will get passed to __init__, where we'll # deal with them as params. @@ -293,12 +302,12 @@ class MetaConfigNode(type): cls._bases = [c for c in cls.__mro__ if isConfigNode(c)] # initialize attributes with values from class definition - for pname,value in dict.iteritems(): - setattr(cls, pname, value) - - if hasattr(cls, '_init'): - cls._init() - del cls._init + for key,value in dict.iteritems(): + key = key.split(dot_decorator) + c = cls + for item in key[:-1]: + c = getattr(c, item) + setattr(c, key[-1], value) def _isvalue(cls, name): for c in cls._bases: @@ -390,7 +399,6 @@ class MetaConfigNode(type): raise AttributeError, \ "object '%s' has no attribute '%s'" % (cls.__name__, cls) - # Set attribute (called on foo.attr = value when foo is an # instance of class cls). def __setattr__(cls, attr, value): diff --git a/test/genini.py b/test/genini.py index e96d7069c..db1a7a5b0 100644 --- a/test/genini.py +++ b/test/genini.py @@ -31,7 +31,7 @@ sys.path.append('..') sys.path.append('../configs/kernel') sys.path.append('../sim/pyconfig') -from importer import mpy_exec, AddToPath +from importer import mpy_exec, mpy_execfile, AddToPath from m5config import * try: @@ -51,7 +51,7 @@ except getopt.GetoptError: for arg in args: AddToPath(os.path.dirname(arg)) - mpy_exec(file(arg, 'r'), globals()) + mpy_execfile(arg) if globals().has_key('root') and isinstance(root, type) \ and issubclass(root, Root): From 936ad584022be7a4e89292c708cc624841198f62 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 3 Feb 2005 14:33:02 -0500 Subject: [PATCH 14/20] small python config related fixes. dev/simconsole.cc: sim/universe.cc: isValid isn't compatible with new python stuff, so whack it. --HG-- extra : convert_revision : 0c50038769a558650479c51122a8be5d92e7d9c4 --- dev/simconsole.cc | 2 +- sim/universe.cc | 10 ++++++---- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/dev/simconsole.cc b/dev/simconsole.cc index d8d890e15..48e5d0201 100644 --- a/dev/simconsole.cc +++ b/dev/simconsole.cc @@ -315,7 +315,7 @@ CREATE_SIM_OBJECT(SimConsole) { string filename; - if (!output.isValid()) { + if (filename.empty()) { filename = getInstanceName(); } else if (append_name) { filename = (string)output + "." + getInstanceName(); diff --git a/sim/universe.cc b/sim/universe.cc index 52353db11..115f6f790 100644 --- a/sim/universe.cc +++ b/sim/universe.cc @@ -143,7 +143,8 @@ CREATE_SIM_OBJECT(Root) __ticksPerNS = freq / 1.0e9; __ticksPerPS = freq / 1.0e12; - if (output_dir.isValid()) { + outputDirectory = output_dir; + if (!outputDirectory.empty()) { outputDirectory = output_dir; // guarantee that directory ends with a '/' @@ -159,9 +160,10 @@ CREATE_SIM_OBJECT(Root) } outputStream = makeOutputStream(output_file); - configStream = config_output_file.isValid() - ? makeOutputStream(config_output_file) - : outputStream; + configStream = outputStream; + string cof = config_output_file; + if (!cof.empty()) + configStream = makeOutputStream(cof); return root; } From 52403a5ddf1e02f53d0624254f41e27e3914df29 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 3 Feb 2005 17:04:54 -0500 Subject: [PATCH 15/20] get rid of defined and just access the env dict directly get rid of the alias for true to True and false to False to keep consistent python syntax. util/stats/info.py: Fix typo --HG-- extra : convert_revision : e69588a8de52424e043315e70008ca3a3ede7d5b --- objects/BaseCPU.mpy | 2 +- objects/BaseCache.mpy | 16 ++++++++-------- objects/BaseSystem.mpy | 2 +- objects/CoherenceProtocol.mpy | 2 +- objects/DiskImage.mpy | 2 +- objects/Ethernet.mpy | 14 +++++++------- objects/Root.mpy | 2 +- objects/SimConsole.mpy | 2 +- sim/pyconfig/m5config.py | 14 +------------- util/stats/info.py | 2 +- 10 files changed, 23 insertions(+), 35 deletions(-) diff --git a/objects/BaseCPU.mpy b/objects/BaseCPU.mpy index 516509c1e..f6e6ff96c 100644 --- a/objects/BaseCPU.mpy +++ b/objects/BaseCPU.mpy @@ -19,7 +19,7 @@ simobj BaseCPU(SimObject): max_loads_any_thread = Param.Counter(0, "terminate when any thread reaches this load count") - defer_registration = Param.Bool(false, + defer_registration = Param.Bool(False, "defer registration with system (for sampling)") def check(self): diff --git a/objects/BaseCache.mpy b/objects/BaseCache.mpy index 95a7f0b35..98a422e30 100644 --- a/objects/BaseCache.mpy +++ b/objects/BaseCache.mpy @@ -2,37 +2,37 @@ from BaseMem import BaseMem simobj BaseCache(BaseMem): type = 'BaseCache' - adaptive_compression = Param.Bool(false, + adaptive_compression = Param.Bool(False, "Use an adaptive compression scheme") assoc = Param.Int("associativity") block_size = Param.Int("block size in bytes") - compressed_bus = Param.Bool(false, + compressed_bus = Param.Bool(False, "This cache connects to a compressed memory") compression_latency = Param.Int(0, "Latency in cycles of compression algorithm") - do_copy = Param.Bool(false, "perform fast copies in the cache") + do_copy = Param.Bool(False, "perform fast copies in the cache") hash_delay = Param.Int(1, "time in cycles of hash access") in_bus = Param.Bus(NULL, "incoming bus object") - lifo = Param.Bool(false, + lifo = Param.Bool(False, "whether this NIC partition should use LIFO repl. policy") max_miss_count = Param.Counter(0, "number of misses to handle before calling exit") mshrs = Param.Int("number of MSHRs (max outstanding requests)") out_bus = Param.Bus("outgoing bus object") - prioritizeRequests = Param.Bool(false, + prioritizeRequests = Param.Bool(False, "always service demand misses first") protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use") repl = Param.Repl(NULL, "replacement policy") size = Param.Int("capacity in bytes") - split = Param.Bool(false, "whether or not this cache is split") + split = Param.Bool(False, "whether or not this cache is split") split_size = Param.Int(0, "How many ways of the cache belong to CPU/LRU partition") - store_compressed = Param.Bool(false, + store_compressed = Param.Bool(False, "Store compressed data in the cache") subblock_size = Param.Int(0, "Size of subblock in IIC used for compression") tgts_per_mshr = Param.Int("max number of accesses per MSHR") trace_addr = Param.Addr(0, "address to trace") - two_queue = Param.Bool(false, + two_queue = Param.Bool(False, "whether the lifo should have two queue replacement") write_buffers = Param.Int(8, "number of write buffers") diff --git a/objects/BaseSystem.mpy b/objects/BaseSystem.mpy index 460bce736..1cbdf4e99 100644 --- a/objects/BaseSystem.mpy +++ b/objects/BaseSystem.mpy @@ -11,5 +11,5 @@ simobj BaseSystem(SimObject): boot_osflags = Param.String("a", "boot flags to pass to the kernel") system_type = Param.UInt64("Type of system we are emulating") system_rev = Param.UInt64("Revision of system we are emulating") - bin = Param.Bool(false, "is this system binned") + bin = Param.Bool(False, "is this system binned") binned_fns = VectorParam.String([], "functions broken down and binned") diff --git a/objects/CoherenceProtocol.mpy b/objects/CoherenceProtocol.mpy index c77348f0a..ae041b638 100644 --- a/objects/CoherenceProtocol.mpy +++ b/objects/CoherenceProtocol.mpy @@ -2,5 +2,5 @@ Coherence = Enum('uni', 'msi', 'mesi', 'mosi', 'moesi') simobj CoherenceProtocol(SimObject): type = 'CoherenceProtocol' - do_upgrades = Param.Bool(true, "use upgrade transactions?") + do_upgrades = Param.Bool(True, "use upgrade transactions?") protocol = Param.Coherence("name of coherence protocol") diff --git a/objects/DiskImage.mpy b/objects/DiskImage.mpy index 908805ba0..80ef7b072 100644 --- a/objects/DiskImage.mpy +++ b/objects/DiskImage.mpy @@ -2,7 +2,7 @@ simobj DiskImage(SimObject): type = 'DiskImage' abstract = True image_file = Param.String("disk image file") - read_only = Param.Bool(false, "read only image") + read_only = Param.Bool(False, "read only image") simobj RawDiskImage(DiskImage): type = 'RawDiskImage' diff --git a/objects/Ethernet.mpy b/objects/Ethernet.mpy index f9479a5c2..088df4b93 100644 --- a/objects/Ethernet.mpy +++ b/objects/Ethernet.mpy @@ -16,7 +16,7 @@ simobj EtherLink(SimObject): simobj EtherBus(SimObject): type = 'EtherBus' - loopback = Param.Bool(true, + loopback = Param.Bool(True, "send packet back to the interface from which it came") dump = Param.EtherDump(NULL, "dump object") speed = Param.UInt64(100000000, "bus speed in bits per second") @@ -36,14 +36,14 @@ simobj EtherDev(DmaDevice): hardware_address = Param.EthernetAddr(NextEthernetAddr, "Ethernet Hardware Address") - dma_data_free = Param.Bool(false, "DMA of Data is free") - dma_desc_free = Param.Bool(false, "DMA of Descriptors is free") + dma_data_free = Param.Bool(False, "DMA of Data is free") + dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") dma_read_delay = Param.Tick(0, "fixed delay for dma reads") dma_read_factor = Param.Tick(0, "multiplier for dma reads") dma_write_delay = Param.Tick(0, "fixed delay for dma writes") dma_write_factor = Param.Tick(0, "multiplier for dma writes") - rx_filter = Param.Bool(true, "Enable Receive Filter") + rx_filter = Param.Bool(True, "Enable Receive Filter") rx_delay = Param.Tick(1000, "Receive Delay") tx_delay = Param.Tick(1000, "Transmit Delay") @@ -57,14 +57,14 @@ simobj NSGigE(PciDevice): hardware_address = Param.EthernetAddr(NextEthernetAddr, "Ethernet Hardware Address") - dma_data_free = Param.Bool(false, "DMA of Data is free") - dma_desc_free = Param.Bool(false, "DMA of Descriptors is free") + dma_data_free = Param.Bool(False, "DMA of Data is free") + dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") dma_read_delay = Param.Tick(0, "fixed delay for dma reads") dma_read_factor = Param.Tick(0, "multiplier for dma reads") dma_write_delay = Param.Tick(0, "fixed delay for dma writes") dma_write_factor = Param.Tick(0, "multiplier for dma writes") - rx_filter = Param.Bool(true, "Enable Receive Filter") + rx_filter = Param.Bool(True, "Enable Receive Filter") rx_delay = Param.Tick(1000, "Receive Delay") tx_delay = Param.Tick(1000, "Transmit Delay") diff --git a/objects/Root.mpy b/objects/Root.mpy index 5806ec826..b21396e36 100644 --- a/objects/Root.mpy +++ b/objects/Root.mpy @@ -7,5 +7,5 @@ simobj Root(SimObject): config_output_file = Param.String('m5config.out', "file to dump simulator config to") full_system = Param.Bool("Full system simulation?") - hier = HierParams(do_data = false, do_events = true) + hier = HierParams(do_data = False, do_events = True) checkpoint = Param.String('', "Checkpoint file") diff --git a/objects/SimConsole.mpy b/objects/SimConsole.mpy index 1231e81dc..ab88db8c6 100644 --- a/objects/SimConsole.mpy +++ b/objects/SimConsole.mpy @@ -4,7 +4,7 @@ simobj ConsoleListener(SimObject): simobj SimConsole(SimObject): type = 'SimConsole' - append_name = Param.Bool(true, "append name() to filename") + append_name = Param.Bool(True, "append name() to filename") intr_control = Param.IntrControl(Super, "interrupt controller") listener = Param.ConsoleListener("console listener") number = Param.Int(0, "console number") diff --git a/sim/pyconfig/m5config.py b/sim/pyconfig/m5config.py index 5ba7542a0..4e3a4103c 100644 --- a/sim/pyconfig/m5config.py +++ b/sim/pyconfig/m5config.py @@ -34,11 +34,6 @@ except: env = {} env.update(os.environ) -def defined(key): - return env.has_key(key) - -def define(key, value = True): - env[key] = value def panic(*args, **kwargs): sys.exit(*args, **kwargs) @@ -64,9 +59,6 @@ class Singleton(type): cls._instance = super(Singleton, cls).__call__(*args, **kwargs) return cls._instance -if os.environ.has_key('FULL_SYSTEM'): - FULL_SYSTEM = True - ##################################################################### # # M5 Python Configuration Utility @@ -670,7 +662,7 @@ class Node(object): % (self.name, ptype, value._path) found, done = obj.find(ptype, value._path) if isinstance(found, Proxy): - done = false + done = False obj = obj.parent return found @@ -1267,10 +1259,6 @@ class Enum(type): # "Constants"... handy aliases for various values. # -# For compatibility with C++ bool constants. -false = False -true = True - # Some memory range specifications use this as a default upper bound. MAX_ADDR = Addr._max MaxTick = Tick._max diff --git a/util/stats/info.py b/util/stats/info.py index fb46a2d55..01d7bdb0f 100644 --- a/util/stats/info.py +++ b/util/stats/info.py @@ -324,7 +324,7 @@ class Vector(Statistic,FormulaStat): def __eq__(self, other): if issequence(self.value) != issequence(other.value): - return false + return False if issequence(self.value): if len(self.value) != len(other.value): From 0aaf8ec6b83c65a60932fd9f9f4b81eca1bcce74 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Thu, 3 Feb 2005 20:47:11 -0500 Subject: [PATCH 16/20] Add support for CPU models to execute the effective address calculation and memory access portions separately. Not currently used by any CPU models, but Kevin says he needs this. Also clean up handling of execution tracing for memory accesses (move it all into isa_desc and out of CPU models). Got rid of some ancient unused code too. arch/alpha/isa_desc: Add execute() methods to EAComp and MemAcc portions of memory access instructions, to allow CPU models to execute the effective address calculation and memory access portions separately. Requires the execution context to remember the effective address across the two invocations. Added setEA() and getEA() methods to execution context to support this. A model that does not use the split execution model can panic if these methods are called. Also added hook to call traceData->setAddr() after EA computation on any load or store operation. arch/isa_parser.py: Call traceData->setData() on memory writes (stores). cpu/simple_cpu/simple_cpu.cc: Get rid of unused code. cpu/simple_cpu/simple_cpu.hh: Add (non-functional) setEA() and getEA() methods for new split memory access execution support. --HG-- extra : convert_revision : bc2d2c758c4ca753812b9fa81f21038e55929ff0 --- arch/alpha/isa_desc | 171 +++++++++++++++++++++-------------- arch/isa_parser.py | 6 +- cpu/simple_cpu/simple_cpu.cc | 8 -- cpu/simple_cpu/simple_cpu.hh | 8 +- 4 files changed, 113 insertions(+), 80 deletions(-) diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 5154d78d1..5602a6ba6 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -790,48 +790,14 @@ output header {{ protected: /// Constructor MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass, - StaticInstPtr _eaCompPtr, - StaticInstPtr _memAccPtr) + StaticInstPtr _eaCompPtr = nullStaticInstPtr, + StaticInstPtr _memAccPtr = nullStaticInstPtr) : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr) { } std::string generateDisassembly(Addr pc, const SymbolTable *symtab); }; - - - /** - * Base class for "fake" effective-address computation - * instructions returnded by eaCompInst(). - */ - class EACompBase : public AlphaStaticInst - { - public: - /// Constructor - EACompBase(MachInst machInst) - : AlphaStaticInst("(eacomp)", machInst, IntAluOp) - { - } - - %(BasicExecDeclare)s - }; - - /** - * Base class for "fake" memory-access instructions returnded by - * memAccInst(). - */ - class MemAccBase : public AlphaStaticInst - { - public: - /// Constructor - MemAccBase(MachInst machInst, OpClass __opClass) - : AlphaStaticInst("(memacc)", machInst, __opClass) - { - } - - %(BasicExecDeclare)s - }; - }}; @@ -850,21 +816,6 @@ output decoder {{ } }}; -output exec {{ - Fault - EACompBase::execute(%(CPU_exec_context)s *, Trace::InstRecord *) - { - panic("attempt to execute eacomp"); - } - - Fault - MemAccBase::execute(%(CPU_exec_context)s *, Trace::InstRecord *) - { - panic("attempt to execute memacc"); - } -}}; - - def format LoadAddress(code) {{ iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code)) header_output = BasicDeclare.subst(iop) @@ -885,21 +836,25 @@ def template LoadStoreDeclare {{ /** * "Fake" effective address computation class for "%(mnemonic)s". */ - class EAComp : public EACompBase + class EAComp : public %(base_class)s { public: /// Constructor EAComp(MachInst machInst); + + %(BasicExecDeclare)s }; /** * "Fake" memory access instruction class for "%(mnemonic)s". */ - class MemAcc : public MemAccBase + class MemAcc : public %(base_class)s { public: /// Constructor MemAcc(MachInst machInst); + + %(BasicExecDeclare)s }; public: @@ -912,14 +867,17 @@ def template LoadStoreDeclare {{ }}; def template LoadStoreConstructor {{ + /** TODO: change op_class to AddrGenOp or something (requires + * creating new member of OpClass enum in op_class.hh, updating + * config files, etc.). */ inline %(class_name)s::EAComp::EAComp(MachInst machInst) - : EACompBase(machInst) + : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp) { %(ea_constructor)s; } inline %(class_name)s::MemAcc::MemAcc(MachInst machInst) - : MemAccBase(machInst, %(op_class)s) + : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s) { %(memacc_constructor)s; } @@ -932,6 +890,64 @@ def template LoadStoreConstructor {{ } }}; + +def template EACompExecute {{ + Fault + %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) + { + Addr EA; + Fault fault = No_Fault; + + %(fp_enable_check)s; + %(op_decl)s; + %(op_rd)s; + %(code)s; + + if (fault == No_Fault) { + %(op_wb)s; + xc->setEA(EA); + } + + return fault; + } +}}; + +def template MemAccExecute {{ + Fault + %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) + { + Addr EA; + Fault fault = No_Fault; + + %(fp_enable_check)s; + %(op_decl)s; + %(op_nonmem_rd)s; + EA = xc->getEA(); + + if (fault == No_Fault) { + %(op_mem_rd)s; + %(code)s; + } + + if (fault == No_Fault) { + %(op_mem_wb)s; + } + + if (fault == No_Fault) { + %(postacc_code)s; + } + + if (fault == No_Fault) { + %(op_nonmem_wb)s; + } + + return fault; + } +}}; + + def template LoadStoreExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) @@ -1022,18 +1038,33 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '', # Would be nice to autogenerate this list, but oh well. valid_mem_flags = ['LOCKED', 'NO_FAULT', 'EVICT_NEXT', 'PF_EXCLUSIVE'] - inst_flags = [] - mem_flags = [] - for f in flags: - if f in valid_mem_flags: - mem_flags.append(f) - else: - inst_flags.append(f) + mem_flags = [f for f in flags if f in valid_mem_flags] + inst_flags = [f for f in flags if f not in valid_mem_flags] + # add hook to get effective addresses into execution trace output. + ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n' + + # generate code block objects ea_cblk = CodeBlock(ea_code) memacc_cblk = CodeBlock(memacc_code) postacc_cblk = CodeBlock(postacc_code) + # Some CPU models execute the memory operation as an atomic unit, + # while others want to separate them into an effective address + # computation and a memory access operation. As a result, we need + # to generate three StaticInst objects. Note that the latter two + # are nested inside the larger "atomic" one. + + # generate InstObjParams for EAComp object + ea_iop = InstObjParams(name, Name, base_class, ea_cblk, inst_flags) + + # generate InstObjParams for MemAcc object + memacc_iop = InstObjParams(name, Name, base_class, memacc_cblk, inst_flags) + # in the split execution model, the MemAcc portion is responsible + # for the post-access code. + memacc_iop.postacc_code = postacc_cblk.code + + # generate InstObjParams for unified execution cblk = CodeBlock(ea_code + memacc_code + postacc_code) iop = InstObjParams(name, Name, base_class, cblk, inst_flags) @@ -1043,13 +1074,17 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '', iop.memacc_code = memacc_cblk.code iop.postacc_code = postacc_cblk.code - mem_flags = string.join(mem_flags, '|') - if mem_flags != '': - iop.constructor += '\n\tmemAccessFlags = ' + mem_flags + ';' + if mem_flags: + s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' + iop.constructor += s + memacc_iop.constructor += s # (header_output, decoder_output, decode_block, exec_output) return (LoadStoreDeclare.subst(iop), LoadStoreConstructor.subst(iop), - decode_template.subst(iop), exec_template.subst(iop)) + decode_template.subst(iop), + EACompExecute.subst(ea_iop) + + MemAccExecute.subst(memacc_iop) + + exec_template.subst(iop)) }}; @@ -1460,8 +1495,8 @@ output header {{ /// Constructor HwLoadStore(const char *mnem, MachInst _machInst, OpClass __opClass, - StaticInstPtr _eaCompPtr, - StaticInstPtr _memAccPtr); + StaticInstPtr _eaCompPtr = nullStaticInstPtr, + StaticInstPtr _memAccPtr = nullStaticInstPtr); std::string generateDisassembly(Addr pc, const SymbolTable *symtab); }; diff --git a/arch/isa_parser.py b/arch/isa_parser.py index c0b5131de..18e4b0a45 100755 --- a/arch/isa_parser.py +++ b/arch/isa_parser.py @@ -1210,10 +1210,12 @@ class MemOperandTraits(OperandTraits): def makeWrite(self, op_desc): (size, type, is_signed) = operandSizeMap[op_desc.eff_ext] eff_type = 'uint%d_t' % size - return 'fault = xc->write((%s&)%s, EA, %s_flags,' \ - ' &%s_write_result);\n' \ + wb = 'fault = xc->write((%s&)%s, EA, %s_flags, &%s_write_result);\n' \ % (eff_type, op_desc.munged_name, op_desc.base_name, op_desc.base_name) + wb += 'if (traceData) { traceData->setData(%s); }' % \ + op_desc.munged_name + return wb class NPCOperandTraits(OperandTraits): def makeConstructor(self, op_desc): diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index e3cce28ae..f292b25a5 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -74,14 +74,6 @@ using namespace std; -template -void -SimpleCPU::trace_data(T data) { - if (traceData) { - traceData->setData(data); - } -} - SimpleCPU::TickEvent::TickEvent(SimpleCPU *c) : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), multiplier(1) diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh index 9b6e2423b..a81d6365b 100644 --- a/cpu/simple_cpu/simple_cpu.hh +++ b/cpu/simple_cpu/simple_cpu.hh @@ -102,8 +102,7 @@ class SimpleCPU : public BaseCPU private: Trace::InstRecord *traceData; - template - void trace_data(T data); + public: // enum Status { @@ -244,6 +243,11 @@ class SimpleCPU : public BaseCPU template Fault write(T data, Addr addr, unsigned flags, uint64_t *res); + // These functions are only used in CPU models that split + // effective address computation from the actual memory access. + void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } + Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } + void prefetch(Addr addr, unsigned flags) { // need to do this... From 06bee6397d2361a025a354c2ef3e75eeac46343a Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Thu, 3 Feb 2005 20:49:14 -0500 Subject: [PATCH 17/20] Minor bug fix/update to tracediff util. util/tracediff: Fix bug (used += instead of .= for string concatenation in Perl... wrong language!). Also updated for new config (s/Universe/root/). --HG-- extra : convert_revision : 0db3f22794037dc51cc29f78a75bd22012a8ecd9 --- util/tracediff | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/tracediff b/util/tracediff index a95ce8b82..402abbe55 100755 --- a/util/tracediff +++ b/util/tracediff @@ -1,5 +1,5 @@ #! /usr/bin/env perl -# Copyright (c) 2003-2004 The Regents of The University of Michigan +# Copyright (c) 2003-2005 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -53,7 +53,7 @@ $simargs = '"' . join('" "', @ARGV) . '"'; # Redirect config output to cout so that gets diffed too (in case # that's the source of the problem). -$simargs += " --Universe:config_output_file=cout"; +$simargs .= " --root:config_output_file=cout"; $cmd1 = "$sim1 $simargs --stats:text_file=tracediff-$$-1.stats 2>&1 |"; $cmd2 = "$sim2 $simargs --stats:text_file=tracediff-$$-2.stats 2>&1 |"; From 7e559f6c50e38272a6f2ab46ea49394413597634 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 3 Feb 2005 23:50:57 -0500 Subject: [PATCH 18/20] Add Monet configuration, update p4 parameters, couple of typo fixes dev/tsunami_cchip.cc: add a fake register to tsunami that we can do 32bit reads to. Warn on access. --HG-- extra : convert_revision : d87860f3b527528151c23431556039bca6e12945 --- configs/boot/devtime.rcS | 8 ++++++++ dev/tsunami_cchip.cc | 7 +++++++ 2 files changed, 15 insertions(+) create mode 100644 configs/boot/devtime.rcS diff --git a/configs/boot/devtime.rcS b/configs/boot/devtime.rcS new file mode 100644 index 000000000..91fddc20d --- /dev/null +++ b/configs/boot/devtime.rcS @@ -0,0 +1,8 @@ +insmod /modules/devtime.ko dataAddr=0x9000004 count=100 +rmmod devtime +insmod /modules/devtime.ko dataAddr=0x1a0000300 count=100 +rmmod devtime +insmod /modules/devtime.ko memTest=1 count=100 +rmmod devtime +m5 exit + diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc index 823d1f118..6bf4d8b57 100644 --- a/dev/tsunami_cchip.cc +++ b/dev/tsunami_cchip.cc @@ -173,6 +173,13 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data) break; case sizeof(uint32_t): + if (regnum == TSDEV_CC_DRIR) { + warn("accessing DRIR with 32 bit read, " + "hopefully your just reading this for timing"); + *(uint64_t*)data = drir; + } else + panic("invalid access size(?) for tsunami register!\n"); + return No_Fault; case sizeof(uint16_t): case sizeof(uint8_t): default: From fc64ab81027b6787d7543a8f94dbc07c270e4ef1 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sat, 5 Feb 2005 13:49:17 -0500 Subject: [PATCH 19/20] Make pbs submission scripts available to all. Fix up configuration scrupts to have better support for running on the simulation pool. --HG-- extra : convert_revision : 0178c8600b193d6c0ca69163fb735a7fa0e70782 --- util/pbs/job.py | 183 ++++++++++++++++++++++++++++++++++++++++++++ util/pbs/jobfile.py | 83 ++++++++++++++++++++ util/pbs/pbs.py | 126 ++++++++++++++++++++++++++++++ util/pbs/send.py | 169 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 561 insertions(+) create mode 100755 util/pbs/job.py create mode 100644 util/pbs/jobfile.py create mode 100755 util/pbs/pbs.py create mode 100755 util/pbs/send.py diff --git a/util/pbs/job.py b/util/pbs/job.py new file mode 100755 index 000000000..5eed0cd75 --- /dev/null +++ b/util/pbs/job.py @@ -0,0 +1,183 @@ +#!/usr/bin/env python +# Copyright (c) 2005 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert +# Steve Reinhardt +# Ali Saidi + +import os, os.path, shutil, signal, socket, sys, time +from os import environ as env +from os.path import join as joinpath, expanduser + +class rsync: + def __init__(self): + self.sudo = False + self.rsync = 'rsync' + self.compress = False + self.archive = True + self.delete = False + self.options = '' + + def do(self, src, dst): + args = [] + if self.sudo: + args.append('sudo') + + args.append(self.rsync) + if (self.archive): + args.append('-a') + if (self.compress): + args.append('-z') + if (self.delete): + args.append('--delete') + if len(self.options): + args.append(self.options) + args.append(src) + args.append(dst) + + return os.spawnvp(os.P_WAIT, args[0], args) + +def cleandir(dir): + for root, dirs, files in os.walk(dir, False): + for name in files: + os.remove(joinpath(root, name)) + for name in dirs: + os.rmdir(joinpath(root, name)) + +def date(): + return time.strftime('%a %b %e %H:%M:%S %Z %Y', time.localtime()) + +def remfile(file): + if os.path.isfile(file): + os.unlink(file) + +def readval(filename): + file = open(filename, 'r') + value = file.readline().strip() + file.close() + return value + +if __name__ == '__main__': + rootdir = env.setdefault('ROOTDIR', os.getcwd()) + jobid = env['PBS_JOBID'] + jobname = env['PBS_JOBNAME'] + jobdir = joinpath(rootdir, jobname) + basedir = joinpath(rootdir, 'Base') + user = env['USER'] + + env['POOLJOB'] = 'True' + env['OUTPUT_DIR'] = jobdir + env['JOBFILE'] = joinpath(basedir, 'test.py') + env['JOBNAME'] = jobname + + def echofile(filename, string): + try: + f = file(joinpath(jobdir, filename), 'w') + print >>f, string + f.flush() + f.close() + except IOError,e: + sys.exit(e) + + if os.path.isdir("/work"): + workbase = "/work" + else: + workbase = "/tmp/" + + workdir = joinpath(workbase, '%s.%s' % (user, jobid)) + + os.umask(0022) + + echofile('.start', date()) + echofile('.jobid', jobid) + echofile('.host', socket.gethostname()) + + if os.path.isdir(workdir): + cleandir(workdir) + else: + os.mkdir(workdir) + + if os.path.isdir('/z/dist'): + sync = rsync() + sync.delete = True + sync.sudo = True + sync.do('poolfs::dist/m5/', '/z/dist/m5/') + + try: + os.chdir(workdir) + except OSError,e: + sys.exit(e) + + os.symlink(joinpath(jobdir, 'output'), 'status.out') + + args = [ joinpath(basedir, 'm5'), joinpath(basedir, 'run.mpy') ] + if not len(args): + sys.exit("no arguments") + + print 'starting job... %s' % date() + print ' '.join(args) + print + sys.stdout.flush() + + childpid = os.fork() + if not childpid: + # Execute command + sys.stdin.close() + fd = os.open(joinpath(jobdir, "output"), + os.O_WRONLY | os.O_CREAT | os.O_TRUNC) + os.dup2(fd, sys.stdout.fileno()) + os.dup2(fd, sys.stderr.fileno()) + os.execvp(args[0], args) + + def handler(signum, frame): + if childpid != 0: + os.kill(childpid, signum) + + signal.signal(signal.SIGHUP, handler) + signal.signal(signal.SIGINT, handler) + signal.signal(signal.SIGQUIT, handler) + signal.signal(signal.SIGTERM, handler) + signal.signal(signal.SIGSTOP, handler) + signal.signal(signal.SIGCONT, handler) + signal.signal(signal.SIGUSR1, handler) + signal.signal(signal.SIGUSR2, handler) + + done = 0 + while not done: + try: + thepid,ec = os.waitpid(childpid, 0) + if ec: + print 'Exit code ', ec + echofile('.failure', date()) + else: + echofile('.success', date()) + done = 1 + except OSError: + pass + + print '\njob complete... %s' % date() + echofile('.stop', date()) diff --git a/util/pbs/jobfile.py b/util/pbs/jobfile.py new file mode 100644 index 000000000..570faa61b --- /dev/null +++ b/util/pbs/jobfile.py @@ -0,0 +1,83 @@ +# Copyright (c) 2005 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from os.path import expanduser +def crossproduct(options): + number = len(options) + indexes = [ 0 ] * number + maxes = [ len(opt) for opt in options ] + def next(): + for i in xrange(number - 1, -1, -1): + indexes[i] += 1 + if indexes[i] < maxes[i]: + return False + + indexes[i] = 0 + return True + + done = False + while not done: + result = [] + for i in xrange(number): + result.append(options[i][indexes[i]]) + yield result + done = next() + +class JobFile(object): + def __init__(self, file): + self.data = {} + execfile(expanduser(file), self.data) + self.options = self.data['options'] + self.environment = self.data['environment'] + self.jobinfo = {} + self.jobs = [] + for job in crossproduct(self.options): + jobname = '.'.join([ id[0] for id in job ]) + self.jobs.append(jobname) + list = [] + for info in job: + for item in info[1:]: + list.append(item) + self.jobinfo[jobname] = list + + def env(self, jobname): + env = {} + for key,val in self.jobinfo[jobname]: + env[key] = val + + for key,val in self.environment: + env[key] = val + return env + + def printinfo(self, jobname): + print '%s:' % jobname + for key,val in self.jobinfo[jobname]: + print ' %s = %s' % (key, val) + + for key,val in self.environment: + print ' %s = %s' % (key, val) diff --git a/util/pbs/pbs.py b/util/pbs/pbs.py new file mode 100755 index 000000000..a71dbbf8e --- /dev/null +++ b/util/pbs/pbs.py @@ -0,0 +1,126 @@ +# Copyright (c) 2005 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +import os, re, sys + +def ssh(host, script, tty = False, user = ''): + args = [ 'ssh', '-x' ] + if user: + args.append('-l' + user) + if tty: + args.append('-t') + args.append(host) + args.append(script) + + return os.spawnvp(os.P_WAIT, args[0], args) + +class qsub: + def __init__(self): + self.hold = False + self.join = False + self.keep_stdout = False + self.keep_stderr = False + self.node_type = '' + self.mail_abort = False + self.mail_begin = False + self.mail_end = False + self.name = '' + self.stdout = '' + self.priority = 0 + self.queue = '' + self.pbshost = '' + self.qsub = 'qsub' + self.env = {} + self.onlyecho = False + self.verbose = False + + def do(self, script, ): + args = [self.qsub] + + if self.env: + arg = '-v' + arg += ','.join([ '%s=%s' % i for i in self.env.iteritems() ]) + args.append(arg) + + if self.hold: + args.append('-h') + + if len(self.stdout): + args.append('-olocalhost:' + self.stdout) + + if self.keep_stdout and self.keep_stderr: + args.append('-koe') + elif self.keep_stdout: + args.append('-ko') + elif self.keep_stderr: + args.append('-ke') + else: + args.append('-kn') + + if self.join: + args.append('-joe') + + if len(self.node_type): + args.append('-lnodes=' + self.node_type) + + if self.mail_abort or self.mail_begin or self.mail_end: + flags = '' + if self.mail_abort: + flags.append('a') + if self.mail_begin: + flags.append('b') + if self.mail_end: + flags.append('e') + if len(flags): + args.append('-m ' + flags) + + if len(self.name): + args.append("-N%s" % self.name) + + if self.priority != 0: + args.append('-p' + self.priority) + + if len(self.queue): + args.append('-q' + self.queue) + + args.append(script) + + if self.verbose or self.onlyecho: + print >>sys.stderr, 'PBS Command: ', ' '.join(args) + + if self.onlyecho: + return 0 + + print >>sys.stderr, 'PBS Jobid: ', + + ec = os.spawnvp(os.P_WAIT, args[0], args) + + if ec != 0 and len(self.pbshost): + ec = ssh(self.pbshost, ' '.join(args)) + + return ec diff --git a/util/pbs/send.py b/util/pbs/send.py new file mode 100755 index 000000000..c0c56d98b --- /dev/null +++ b/util/pbs/send.py @@ -0,0 +1,169 @@ +#!/usr/bin/env python +# Copyright (c) 2005 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ali Saidi +# Nathan Binkert + +import os, os.path, re, sys +from os import environ as env, listdir +from os.path import basename, isdir, isfile, islink, join as joinpath +from filecmp import cmp as filecmp +from shutil import copyfile + +progname = basename(sys.argv[0]) +usage = """\ +Usage: + %(progname)s [-c] [-e] [-f] [-q queue] [-v] + -c clean directory if job can be run + -e only echo pbs command info, don't actually send the job + -f force the job to run regardless of state + -q submit job to the named queue + -v be verbose + + %(progname)s -l [-v] + -l list job names, don't submit + -v be verbose (list job parameters) + + %(progname)s -h + -h display this help +""" % locals() + +try: + import getopt + opts, args = getopt.getopt(sys.argv[1:], '-cefhlq:v') +except getopt.GetoptError: + sys.exit(usage) + +clean = False +onlyecho = False +exprs = [] +force = False +listonly = False +queue = '' +verbose = False +for o,a in opts: + if o == '-c': + clean = True + if o == '-e': + onlyecho = True + if o == '-f': + force = True + if o == '-h': + print usage + sys.exit(0) + if o == '-l': + listonly = True + if o == '-q': + queue = a + if o == '-v': + verbose = True + +for arg in args: + exprs.append(re.compile(arg)) + +if not listonly and not onlyecho and isdir('Link'): + print 'Checking for outdated files in Link directory' + entries = listdir('Link') + for entry in entries: + link = joinpath('Link', entry) + if not islink(link): + continue + + base = joinpath('Base', entry) + if not isfile(base) or not filecmp(link, base): + print '%s is different than source %s...copying' % (base, link) + copyfile(link, base) + +import job, jobfile, pbs + +test = jobfile.JobFile(joinpath('Base', 'test.py')) + +joblist = [] +for jobname in test.jobs: + if not exprs: + joblist.append(jobname) + continue + + for expr in exprs: + if expr.match(jobname): + joblist.append(jobname) + break + +if listonly: + if verbose: + for jobname in joblist: + test.printinfo(jobname) + else: + for jobname in joblist: + print jobname + sys.exit(0) + +if not onlyecho: + jl = [] + for jobname in joblist: + if os.path.exists(jobname): + if not force: + if os.path.isfile(joinpath(jobname, '.success')): + continue + + if os.path.isfile(joinpath(jobname, '.start')) and \ + not os.path.isfile(joinpath(jobname, '.stop')): + continue + + if not clean: + sys.exit('job directory not clean!') + + job.cleandir(jobname) + else: + os.mkdir(jobname) + jl.append(jobname) + joblist = jl + +rootdir = re.sub(r'^/\.automount/', r'/n/', os.getcwd()) +for jobname in joblist: + jobdir = joinpath(rootdir, jobname) + + if not onlyecho and not os.path.isdir(jobdir): + sys.exit('%s is not a directory. Cannot build job' % jobdir) + + print >>sys.stderr, 'Job name: %s' % jobname + print >>sys.stderr, 'Job directory: %s' % jobdir + + qsub = pbs.qsub() + qsub.pbshost = 'simpool.eecs.umich.edu' + qsub.stdout = joinpath(jobdir, 'jobout') + qsub.name = jobname + qsub.join = True + qsub.node_type = 'FAST' + qsub.onlyecho = onlyecho + qsub.env['ROOTDIR'] = rootdir + qsub.verbose = verbose + if len(queue): + qsub.queue = queue + + qsub.do(joinpath('Base', 'job.py')) + print >>sys.stderr, '' From c4089562d5add225cd8275b59456eb7eb559b988 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sat, 5 Feb 2005 13:50:25 -0500 Subject: [PATCH 20/20] Tweak genini. test/genini.py: Make it possible to run genini from a different directory. --HG-- extra : convert_revision : 57cfb010d6114512040bf334ea21c9ed87234be0 --- test/genini.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/test/genini.py b/test/genini.py index db1a7a5b0..0dac0d409 100644 --- a/test/genini.py +++ b/test/genini.py @@ -26,10 +26,12 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import getopt, os, os.path, sys +from os.path import join as joinpath, realpath -sys.path.append('..') -sys.path.append('../configs/kernel') -sys.path.append('../sim/pyconfig') +mypath = sys.path[0] +sys.path.append(joinpath(mypath, '..')) +sys.path.append(joinpath(mypath, '../configs/kernel')) +sys.path.append(joinpath(mypath, '../sim/pyconfig')) from importer import mpy_exec, mpy_execfile, AddToPath from m5config import *