sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

ARM: Warn about and ignore accesses to DCCISW.

Browse source 
This register is supposed to "Clean and invalidate data or unified cache line
by set/way." Since there isn't a good way to do that, we'll just ignore these
and warn about it.
This commit is contained in:
Gabe Black 2010-06-02 12:58:08 -05:00
parent 8c1be04af6
commit 221e0ac523
2 changed files with 6 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
src/arch/arm/isa/formats/misc.isa
View file

@ -94,6 +94,9 @@ def format McrMrc15() {{
return new NopInst(machInst); return new NopInst(machInst);
} else if (miscReg == NUM_MISCREGS) { } else if (miscReg == NUM_MISCREGS) {
return new Unknown(machInst); return new Unknown(machInst);
} else if (miscReg == MISCREG_DCCISW) {
return new WarnUnimplemented(isRead ? "mrc dccisw" : "mcr dcisw",
machInst);
} else { } else {
if (isRead) { if (isRead) {
return new Mrc15(machInst, rt, (IntRegIndex)miscReg); return new Mrc15(machInst, rt, (IntRegIndex)miscReg);

6
src/arch/arm/miscregs.hh
View file

@ -82,6 +82,7 @@ namespace ArmISA
// CP15 registers // CP15 registers
MISCREG_CP15_START, MISCREG_CP15_START,
MISCREG_SCTLR = MISCREG_CP15_START, MISCREG_SCTLR = MISCREG_CP15_START,
MISCREG_DCCISW,
MISCREG_CP15_UNIMP_START, MISCREG_CP15_UNIMP_START,
MISCREG_CTR = MISCREG_CP15_UNIMP_START, MISCREG_CTR = MISCREG_CP15_UNIMP_START,
MISCREG_TCMTR, MISCREG_TCMTR,
@ -136,7 +137,6 @@ namespace ArmISA
MISCREG_CP15DMB, MISCREG_CP15DMB,
MISCREG_DCCMVAU, MISCREG_DCCMVAU,
MISCREG_DCCIMVAC, MISCREG_DCCIMVAC,
MISCREG_DCCISW,
MISCREG_CONTEXTIDR, MISCREG_CONTEXTIDR,
MISCREG_TPIDRURW, MISCREG_TPIDRURW,
MISCREG_TPIDRURO, MISCREG_TPIDRURO,
@ -158,7 +158,7 @@ namespace ArmISA
"cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
"spsr_mon", "spsr_und", "spsr_abt", "spsr_mon", "spsr_und", "spsr_abt",
"fpsr", "fpsid", "fpscr", "fpexc", "fpsr", "fpsid", "fpscr", "fpexc",
"sctlr", "ctr", "tcmtr", "mpuir", "mpidr", "midr", "sctlr", "dccisw", "ctr", "tcmtr", "mpuir", "mpidr", "midr",
"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0", "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3", "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
@ -167,7 +167,7 @@ namespace ArmISA
"drbar", "irbar", "drsr", "irsr", "dracr", "iracr", "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
"rgnr", "icialluis", "bpiallis", "iciallu", "icimvau", "rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",
"cp15isb", "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw", "cp15isb", "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
"cp15dsb", "cp15dmb", "dccmvau", "dccimvac", "dccisw", "cp15dsb", "cp15dmb", "dccmvau", "dccimvac",
"contextidr", "tpidrurw", "tpidruro", "tpidrprw", "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
"nop", "raz" "nop", "raz"
}; };