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Compilation fix after messy merge.

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--HG--
extra : convert_revision : bf650dfe401377ce1b4c952aa8bfe3708c865472
This commit is contained in:
Gabe Black 2006-12-17 10:53:10 -05:00
parent 9d0ca61b7e
commit 220e99a29b
5 changed files with 73 additions and 66 deletions
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2
src/arch/isa_parser.py
View file

@ -1362,7 +1362,7 @@ class ControlRegOperand(Operand):
bit_select = 0 bit_select = 0
if (self.ctype == 'float' or self.ctype == 'double'): if (self.ctype == 'float' or self.ctype == 'double'):
error(0, 'Attempt to read control register as FP') error(0, 'Attempt to read control register as FP')
base = 'xc->readMiscRegOperandWithEffect(%s)' % self.reg_spec base = 'xc->readMiscRegOperandWithEffect(this, %s)' % self.src_reg_idx
if self.size == self.dflt_size: if self.size == self.dflt_size:
return '%s = %s;\n' % (self.base_name, base) return '%s = %s;\n' % (self.base_name, base)
else: else:

2
src/arch/sparc/isa/formats/mem/basicmem.isa
View file

@ -68,7 +68,7 @@ let {{
decode_block = ROrImmDecode.subst(iop) decode_block = ROrImmDecode.subst(iop)
exec_output = doDualSplitExecute(code, addrCalcReg, addrCalcImm, exec_output = doDualSplitExecute(code, addrCalcReg, addrCalcImm,
execute, faultCode, name, name + "Imm", execute, faultCode, name, name + "Imm",
Name, Name + "Imm", opt_flags) Name, Name + "Imm", asi, opt_flags)
return (header_output, decoder_output, exec_output, decode_block) return (header_output, decoder_output, exec_output, decode_block)
}}; }};

119
src/arch/sparc/miscregfile.cc
View file

@ -47,8 +47,15 @@ string SparcISA::getMiscRegName(RegIndex index)
{ {
static::string miscRegName[NumMiscRegs] = static::string miscRegName[NumMiscRegs] =
{/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic", {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
"gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
"stick", "stick_cmpr",
"tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
"pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin", "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
"wstate",*/ "gl", "wstate",*/ "gl",
"hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
"hstick_cmpr",
"fsr"};
return miscRegName[index]; return miscRegName[index];
} }
@ -59,8 +66,8 @@ enum RegMask
void MiscRegFile::clear() void MiscRegFile::clear()
{ {
y = 0; //y = 0;
ccr = 0; //ccr = 0;
asi = 0; asi = 0;
tick = ULL(1) << 63; tick = ULL(1) << 63;
fprs = 0; fprs = 0;
@ -77,11 +84,11 @@ void MiscRegFile::clear()
tl = 0; tl = 0;
pil = 0; pil = 0;
cwp = 0; cwp = 0;
cansave = 0; //cansave = 0;
canrestore = 0; //canrestore = 0;
cleanwin = 0; //cleanwin = 0;
otherwin = 0; //otherwin = 0;
wstate = 0; //wstate = 0;
gl = 0; gl = 0;
//In a T1, bit 11 is apparently always 1 //In a T1, bit 11 is apparently always 1
hpstate = (1 << 11); hpstate = (1 << 11);
@ -143,10 +150,10 @@ MiscReg MiscRegFile::readReg(int miscReg)
(uint64_t)priContext << 32 | (uint64_t)priContext << 32 |
(uint64_t)secContext << 48; (uint64_t)secContext << 48;
case MISCREG_Y: //case MISCREG_Y:
return y; // return y;
case MISCREG_CCR: //case MISCREG_CCR:
return ccr; // return ccr;
case MISCREG_ASI: case MISCREG_ASI:
return asi; return asi;
case MISCREG_FPRS: case MISCREG_FPRS:
@ -189,16 +196,16 @@ MiscReg MiscRegFile::readReg(int miscReg)
return pil; return pil;
case MISCREG_CWP: case MISCREG_CWP:
return cwp; return cwp;
case MISCREG_CANSAVE: //case MISCREG_CANSAVE:
return cansave; // return cansave;
case MISCREG_CANRESTORE: //case MISCREG_CANRESTORE:
return canrestore; // return canrestore;
case MISCREG_CLEANWIN: //case MISCREG_CLEANWIN:
return cleanwin; // return cleanwin;
case MISCREG_OTHERWIN: //case MISCREG_OTHERWIN:
return otherwin; // return otherwin;
case MISCREG_WSTATE: //case MISCREG_WSTATE:
return wstate; // return wstate;
case MISCREG_GL: case MISCREG_GL:
return gl; return gl;
@ -369,12 +376,12 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
void MiscRegFile::setReg(int miscReg, const MiscReg &val) void MiscRegFile::setReg(int miscReg, const MiscReg &val)
{ {
switch (miscReg) { switch (miscReg) {
case MISCREG_Y: // case MISCREG_Y:
y = val; // y = val;
break; // break;
case MISCREG_CCR: // case MISCREG_CCR:
ccr = val; // ccr = val;
break; // break;
case MISCREG_ASI: case MISCREG_ASI:
asi = val; asi = val;
break; break;
@ -436,21 +443,21 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
case MISCREG_CWP: case MISCREG_CWP:
cwp = val; cwp = val;
break; break;
case MISCREG_CANSAVE: // case MISCREG_CANSAVE:
cansave = val; // cansave = val;
break; // break;
case MISCREG_CANRESTORE: // case MISCREG_CANRESTORE:
canrestore = val; // canrestore = val;
break; // break;
case MISCREG_CLEANWIN: // case MISCREG_CLEANWIN:
cleanwin = val; // cleanwin = val;
break; // break;
case MISCREG_OTHERWIN: // case MISCREG_OTHERWIN:
otherwin = val; // otherwin = val;
break; // break;
case MISCREG_WSTATE: // case MISCREG_WSTATE:
wstate = val; // wstate = val;
break; // break;
case MISCREG_GL: case MISCREG_GL:
gl = val; gl = val;
break; break;
@ -666,23 +673,23 @@ void MiscRegFile::serialize(std::ostream & os)
{ {
SERIALIZE_SCALAR(pstate); SERIALIZE_SCALAR(pstate);
SERIALIZE_SCALAR(tba); SERIALIZE_SCALAR(tba);
SERIALIZE_SCALAR(y); // SERIALIZE_SCALAR(y);
SERIALIZE_SCALAR(pil); SERIALIZE_SCALAR(pil);
SERIALIZE_SCALAR(gl); SERIALIZE_SCALAR(gl);
SERIALIZE_SCALAR(cwp); SERIALIZE_SCALAR(cwp);
SERIALIZE_ARRAY(tt, MaxTL); SERIALIZE_ARRAY(tt, MaxTL);
SERIALIZE_SCALAR(ccr); // SERIALIZE_SCALAR(ccr);
SERIALIZE_SCALAR(asi); SERIALIZE_SCALAR(asi);
SERIALIZE_SCALAR(tl); SERIALIZE_SCALAR(tl);
SERIALIZE_ARRAY(tpc, MaxTL); SERIALIZE_ARRAY(tpc, MaxTL);
SERIALIZE_ARRAY(tnpc, MaxTL); SERIALIZE_ARRAY(tnpc, MaxTL);
SERIALIZE_ARRAY(tstate, MaxTL); SERIALIZE_ARRAY(tstate, MaxTL);
SERIALIZE_SCALAR(tick); SERIALIZE_SCALAR(tick);
SERIALIZE_SCALAR(cansave); // SERIALIZE_SCALAR(cansave);
SERIALIZE_SCALAR(canrestore); // SERIALIZE_SCALAR(canrestore);
SERIALIZE_SCALAR(otherwin); // SERIALIZE_SCALAR(otherwin);
SERIALIZE_SCALAR(cleanwin); // SERIALIZE_SCALAR(cleanwin);
SERIALIZE_SCALAR(wstate); // SERIALIZE_SCALAR(wstate);
SERIALIZE_SCALAR(fsr); SERIALIZE_SCALAR(fsr);
SERIALIZE_SCALAR(fprs); SERIALIZE_SCALAR(fprs);
SERIALIZE_SCALAR(hpstate); SERIALIZE_SCALAR(hpstate);
@ -725,23 +732,23 @@ void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
{ {
UNSERIALIZE_SCALAR(pstate); UNSERIALIZE_SCALAR(pstate);
UNSERIALIZE_SCALAR(tba); UNSERIALIZE_SCALAR(tba);
UNSERIALIZE_SCALAR(y); // UNSERIALIZE_SCALAR(y);
UNSERIALIZE_SCALAR(pil); UNSERIALIZE_SCALAR(pil);
UNSERIALIZE_SCALAR(gl); UNSERIALIZE_SCALAR(gl);
UNSERIALIZE_SCALAR(cwp); UNSERIALIZE_SCALAR(cwp);
UNSERIALIZE_ARRAY(tt, MaxTL); UNSERIALIZE_ARRAY(tt, MaxTL);
UNSERIALIZE_SCALAR(ccr); // UNSERIALIZE_SCALAR(ccr);
UNSERIALIZE_SCALAR(asi); UNSERIALIZE_SCALAR(asi);
UNSERIALIZE_SCALAR(tl); UNSERIALIZE_SCALAR(tl);
UNSERIALIZE_ARRAY(tpc, MaxTL); UNSERIALIZE_ARRAY(tpc, MaxTL);
UNSERIALIZE_ARRAY(tnpc, MaxTL); UNSERIALIZE_ARRAY(tnpc, MaxTL);
UNSERIALIZE_ARRAY(tstate, MaxTL); UNSERIALIZE_ARRAY(tstate, MaxTL);
UNSERIALIZE_SCALAR(tick); UNSERIALIZE_SCALAR(tick);
UNSERIALIZE_SCALAR(cansave); // UNSERIALIZE_SCALAR(cansave);
UNSERIALIZE_SCALAR(canrestore); // UNSERIALIZE_SCALAR(canrestore);
UNSERIALIZE_SCALAR(otherwin); // UNSERIALIZE_SCALAR(otherwin);
UNSERIALIZE_SCALAR(cleanwin); // UNSERIALIZE_SCALAR(cleanwin);
UNSERIALIZE_SCALAR(wstate); // UNSERIALIZE_SCALAR(wstate);
UNSERIALIZE_SCALAR(fsr); UNSERIALIZE_SCALAR(fsr);
UNSERIALIZE_SCALAR(fprs); UNSERIALIZE_SCALAR(fprs);
UNSERIALIZE_SCALAR(hpstate); UNSERIALIZE_SCALAR(hpstate);

14
src/arch/sparc/miscregfile.hh
View file

@ -169,8 +169,8 @@ namespace SparcISA
private: private:
/* ASR Registers */ /* ASR Registers */
uint64_t y; // Y (used in obsolete multiplication) //uint64_t y; // Y (used in obsolete multiplication)
uint8_t ccr; // Condition Code Register //uint8_t ccr; // Condition Code Register
uint8_t asi; // Address Space Identifier uint8_t asi; // Address Space Identifier
uint64_t tick; // Hardware clock-tick counter uint64_t tick; // Hardware clock-tick counter
uint8_t fprs; // Floating-Point Register State uint8_t fprs; // Floating-Point Register State
@ -195,11 +195,11 @@ namespace SparcISA
uint8_t tl; // Trap Level uint8_t tl; // Trap Level
uint8_t pil; // Process Interrupt Register uint8_t pil; // Process Interrupt Register
uint8_t cwp; // Current Window Pointer uint8_t cwp; // Current Window Pointer
uint8_t cansave; // Savable windows //uint8_t cansave; // Savable windows
uint8_t canrestore; // Restorable windows //uint8_t canrestore; // Restorable windows
uint8_t cleanwin; // Clean windows //uint8_t cleanwin; // Clean windows
uint8_t otherwin; // Other windows //uint8_t otherwin; // Other windows
uint8_t wstate; // Window State //uint8_t wstate; // Window State
uint8_t gl; // Global level register uint8_t gl; // Global level register
/** Hyperprivileged Registers */ /** Hyperprivileged Registers */

2
src/arch/sparc/tlb.hh
View file

@ -115,7 +115,7 @@ class TLB : public SimObject
void writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, void writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct,
bool se, FaultTypes ft, int asi); bool se, FaultTypes ft, int asi);
void TLB::clearUsedBits(); void clearUsedBits();
void writeTagAccess(ThreadContext *tc, int reg, Addr va, int context); void writeTagAccess(ThreadContext *tc, int reg, Addr va, int context);